[PATCH 0/4] gdb/riscv: analyse a core file without the executable

[PATCH 0/4] gdb/riscv: analyse a core file without the executable

[Farid Khaidari]

A RISC-V core opened without its executable gets an integer-only
target description, because the core does not say how wide the FP
registers are.  Any object with no ISA attribute, a core included, is
also disassembled as plain rv64gc.

This series reads what the core does record.  The size of the
NT_FPREGSET note gives FLEN, and AT_HWCAP gives the single-letter
extensions.  The last patch passes the ISA of the resulting target
description to the disassembler when the object names none.

Patches 3 and 4 need the "arch=" disassembler option, sent to
binutils@sourceware.org as "RISC-V: add an "arch=" disassembler
option".

Vector state from the NT_RISCV_VECTOR note is left out.  GDB can read
the org.gnu.gdb.riscv.vector feature from a target description but
cannot build one, so a vlen read from the core has nowhere to go yet.
The disassembler test loads a vector description from a file instead.

Tested on x86_64-linux with a riscv64-linux-gnu target: the three new
tests give 23 passes and no failures.  The host cannot run RISC-V
binaries, so I did not run the rest of the testsuite.

Farid Khaidari (4):
  gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files
  gdb/riscv: recover core file ISA features from AT_HWCAP
  gdb/riscv: test the "arch=" disassembler option
  gdb/riscv: disassemble an attribute-less object by the description ISA

 gdb/riscv-linux-tdep.c                        | 120 +++++++++++++
 gdb/riscv-tdep.c                              | 167 +++++++++++++++++-
 gdb/riscv-tdep.h                              |  14 ++
 .../gdb.arch/riscv-core-fpregset.core.bz2     | Bin 0 -> 15134 bytes
 .../gdb.arch/riscv-core-fpregset.exp          |  78 ++++++++
 .../gdb.arch/riscv-core-hwcap.core.bz2        | Bin 0 -> 15122 bytes
 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp   |  72 ++++++++
 .../riscv-disasm-arch-option-vector.xml       | 123 +++++++++++++
 .../gdb.arch/riscv-disasm-arch-option.c       |  40 +++++
 .../gdb.arch/riscv-disasm-arch-option.exp     | 124 +++++++++++++
 10 files changed, 732 insertions(+), 6 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp

-- 
2.43.0

[PATCH 1/4] gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files

[Farid Khaidari]

A Linux kernel core has no float ABI in e_flags and no RISC-V
attributes.  Opened without the executable, it gets an integer-only
target description, and "p $fa0" fails with "Invalid register 'fa0'"
even though the core holds the FP state.

The kernel writes 32 FP registers of FLEN bytes plus fcsr into
NT_FPREGSET, so the note size gives FLEN.  Use it when e_flags says
nothing.

The test core is a real kernel dump with a 264-byte NT_FPREGSET,
i.e. FLEN = 8.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 gdb/riscv-tdep.c                              |  89 +++++++++++++++++-
 .../gdb.arch/riscv-core-fpregset.core.bz2     | Bin 0 -> 15134 bytes
 .../gdb.arch/riscv-core-fpregset.exp          |  78 +++++++++++++++
 3 files changed, 164 insertions(+), 3 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.exp

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 68c56fbafb3..1af4be77091 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -56,6 +56,7 @@
 #include "arch/riscv.h"
 #include "record-full.h"
 #include "riscv-ravenscar-thread.h"
+#include "gdbsupport/selftest.h"
 
 #include <vector>
 
@@ -3923,11 +3924,58 @@ static const struct frame_unwind_legacy riscv_frame_unwind (
   /*.prev_arch     =*/ NULL
 );
 
+/* FP register width, in bytes, implied by the D and F extensions.  */
+static constexpr int riscv_flen_d = 8;
+static constexpr int riscv_flen_f = 4;
+
+/* Return the FLEN implied by SIZE, the size of an NT_FPREGSET note, or 0
+   if SIZE matches no known layout.  The note holds 32 FP registers of
+   FLEN bytes each, followed by fcsr, which the kernel pads to 8 bytes on
+   RV64 but leaves at its natural 4 bytes on RV32.  */
+
+static int
+riscv_flen_from_fpregset_size (bfd_size_type size)
+{
+  constexpr bfd_size_type num_fpregs = 32;
+  constexpr bfd_size_type fcsr_slot_padded = 8;
+  constexpr bfd_size_type fcsr_slot = 4;
+
+  if (size == num_fpregs * riscv_flen_d + fcsr_slot_padded)
+    return riscv_flen_d;
+  if (size == num_fpregs * riscv_flen_f + fcsr_slot_padded
+      || size == num_fpregs * riscv_flen_f + fcsr_slot)
+    return riscv_flen_f;
+
+  return 0;
+}
+
+/* A kernel core file carries no float ABI in its e_flags, but the size
+   of its NT_FPREGSET note (the ".reg2" pseudo-section) reveals the FLEN.
+   Return the implied FLEN, or 0 if ABFD has no such note or its size
+   matches no known layout.  */
+
+static int
+riscv_flen_from_core_fpregset (bfd *abfd)
+{
+  auto *fpregs = bfd_get_section_by_name (abfd, ".reg2");
+  if (fpregs == nullptr)
+    return 0;
+
+  auto size = bfd_section_size (fpregs);
+  int flen = riscv_flen_from_fpregset_size (size);
+  if (flen == 0)
+    warning (_ ("unrecognized .reg2 note size %s in core file; "
+		"FLEN left unknown"),
+	     pulongest (size));
+
+  return flen;
+}
+
 /* Extract a set of required target features out of ABFD.  If ABFD is
    nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state.  */
 
 static struct riscv_gdbarch_features
-riscv_features_from_bfd (const bfd *abfd)
+riscv_features_from_bfd (bfd *abfd)
 {
   struct riscv_gdbarch_features features;
 
@@ -3950,9 +3998,14 @@ riscv_features_from_bfd (const bfd *abfd)
 	internal_error (_("unknown ELF header class %d"), eclass);
 
       if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
-	features.flen = 8;
+	features.flen = riscv_flen_d;
       else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
-	features.flen = 4;
+	features.flen = riscv_flen_f;
+
+      /* A core file carries no float ABI in its e_flags; recover the FLEN
+	 from the size of its NT_FPREGSET note instead.  */
+      if (features.flen == 0 && bfd_get_format (abfd) == bfd_core)
+	features.flen = riscv_flen_from_core_fpregset (abfd);
 
       if (e_flags & EF_RISCV_RVE)
 	{
@@ -4784,12 +4837,42 @@ riscv_supply_regset (const struct regset *regset,
     }
 }
 
+#if GDB_SELF_TEST
+namespace selftests
+{
+
+/* Check that an NT_FPREGSET note size maps to the right FLEN.  */
+
+static void
+riscv_flen_from_fpregset_size_test ()
+{
+  /* 32 doubles plus a padded fcsr.  */
+  SELF_CHECK (riscv_flen_from_fpregset_size (32 * 8 + 8) == riscv_flen_d);
+
+  /* 32 floats plus fcsr, padded on RV64 and unpadded on RV32.  */
+  SELF_CHECK (riscv_flen_from_fpregset_size (32 * 4 + 8) == riscv_flen_f);
+  SELF_CHECK (riscv_flen_from_fpregset_size (32 * 4 + 4) == riscv_flen_f);
+
+  /* Anything else leaves the FLEN unknown.  */
+  SELF_CHECK (riscv_flen_from_fpregset_size (0) == 0);
+  SELF_CHECK (riscv_flen_from_fpregset_size (32 * 8) == 0);
+  SELF_CHECK (riscv_flen_from_fpregset_size (32 * 16 + 8) == 0);
+}
+
+} /* namespace selftests */
+#endif /* GDB_SELF_TEST */
+
 INIT_GDB_FILE (riscv_tdep)
 {
   riscv_init_reggroups ();
 
   gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
 
+#if GDB_SELF_TEST
+  selftests::register_test ("riscv-flen-from-fpregset-size",
+			    selftests::riscv_flen_from_fpregset_size_test);
+#endif
+
   /* Add root prefix command for all "set debug riscv" and "show debug
      riscv" commands.  */
   add_setshow_prefix_cmd ("riscv", no_class,
diff --git a/gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2 b/gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2
new file mode 100644
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diff --git a/gdb/testsuite/gdb.arch/riscv-core-fpregset.exp b/gdb/testsuite/gdb.arch/riscv-core-fpregset.exp
new file mode 100644
index 00000000000..16363299a0a
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-core-fpregset.exp
@@ -0,0 +1,78 @@
+# Copyright 2026 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Check that GDB recovers the FP registers from a kernel core file
+# opened without the executable.  A kernel core has no NT_GDB_TDESC
+# note, no .riscv.attributes, and zero e_flags, so the size of the
+# NT_FPREGSET note is the only evidence of the FLEN.  The kernel dumps
+# the FP state in the D layout: 32 doubles plus 8 bytes for fcsr,
+# 264 bytes in total.
+#
+# The bundled core (riscv-core-fpregset.core.bz2) is a real kernel core
+# whose PT_NOTE carries NT_FPREGSET (264 bytes) but neither NT_GDB_TDESC
+# nor any RISC-V attributes, and whose e_flags are zero.  The dumped
+# program never touched the FP unit, so every FP register in the note
+# is zero.
+#
+# The test checks that, with no executable loaded:
+# 1. the FP registers exist in the target description at all, rather
+#    than GDB reporting "Invalid register 'fa0'";
+# 2. their contents are supplied from the note rather than left
+#    <unavailable> ("(raw 0x...)" in the output proves that);
+# 3. the FP registers are 8 bytes wide, i.e. the FLEN really came from
+#    the 264-byte note size.
+#
+# Only the D layout is exercised here, since that is what the bundled
+# core carries.  The size-to-FLEN mapping itself, including the F
+# layout, is covered by the "riscv-flen-from-fpregset-size" selftest.
+#
+# How to regenerate the fixture: run any RV64 program on a Linux system
+# under "ulimit -c unlimited" with kernel.core_pattern=core, make it
+# dump core, and bzip2 the result.  Check with "readelf -n" that the
+# core carries a 264-byte NT_FPREGSET and neither an NT_GDB_TDESC note
+# nor RISC-V attributes.
+
+# The fixture is an ELF64 core and the FLEN assertions are
+# RV64-specific.
+require {istarget "riscv64-*-*"}
+
+if {![istarget *-*-linux*]} {
+    unsupported "linux only"
+    return -1
+}
+
+set core [decompress_bz2 $srcdir/$subdir/riscv-core-fpregset.core.bz2]
+if {$core == ""} {
+    untested "failed to decompress core file"
+    return -1
+}
+set core [gdb_remote_download host $core]
+
+clean_restart
+
+if {![gdb_core_cmd $core "load kernel core without executable"]} {
+    return -1
+}
+
+# The size of the NT_FPREGSET note implies FLEN, hence the FP registers.
+# The value must come from the note: a raw hex dump in the output means
+# the register bytes were supplied, not left <unavailable>.
+gdb_test "info registers \$fa0" \
+    "fa0\[ \t\]+\\{float = 0, double = 0\\}\[ \t\]+\\(raw 0x0+\\)" \
+    "fp register value supplied from fpregset note"
+
+# 264 bytes = 32 doubles + fcsr, so the FLEN must be 8.
+gdb_test "print sizeof (\$fa0)" "= 8" \
+    "flen recovered from fpregset note size"
-- 
2.43.0

[PATCH 2/4] gdb/riscv: recover core file ISA features from AT_HWCAP

[Farid Khaidari]

Add a core_read_description hook for RISC-V Linux.  It reads AT_HWCAP
from the core's auxv and takes FLEN from the F and D bits, on top of
what riscv_features_from_bfd finds (the function is now exported).  A
core with an NT_GDB_TDESC note still uses that note.

The V bit is ignored.  AT_HWCAP gives no vector length, and a guessed
vlenb would give the vector registers the wrong size.

The test core is a real kernel dump with NT_FPREGSET removed, so
AT_HWCAP (0x20112d, rv64imafdcv) is the only source of FP information.
Its V bit also lets the test check that GDB adds no vector registers.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 gdb/riscv-linux-tdep.c                        | 120 ++++++++++++++++++
 gdb/riscv-tdep.c                              |   8 +-
 gdb/riscv-tdep.h                              |   9 ++
 .../gdb.arch/riscv-core-hwcap.core.bz2        | Bin 0 -> 15122 bytes
 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp   |  72 +++++++++++
 5 files changed, 203 insertions(+), 6 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp

diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c
index fcfa5f98ea4..d7cf6fcfd53 100644
--- a/gdb/riscv-linux-tdep.c
+++ b/gdb/riscv-linux-tdep.c
@@ -31,6 +31,8 @@
 #include "linux-record.h"
 #include "riscv-linux-tdep.h"
 #include "inferior.h"
+#include "auxv.h"
+#include "gdbsupport/selftest.h"
 
 extern unsigned int record_debug;
 
@@ -523,6 +525,57 @@ riscv_linux_get_syscall_number (struct gdbarch *gdbarch, thread_info *thread)
   return ret;
 }
 
+/* The AT_HWCAP bit for a single-letter ISA extension (COMPAT_HWCAP_ISA_*
+   in arch/riscv/include/asm/hwcap.h).  */
+
+static constexpr ULONGEST
+riscv_hwcap_isa (char ext)
+{
+  gdb_assert (ext >= 'a' && ext <= 'z');
+  return ULONGEST{ 1 } << (ext - 'a');
+}
+
+/* Refine FEATURES with the F and D bits of the AT_HWCAP mask HWCAP,
+   which imply the FLEN.  Only fields still at their unknown value (0)
+   are filled in, so a width already recovered from the core wins.
+
+   The V bit is deliberately ignored: AT_HWCAP carries no vector
+   length, and a target description with a guessed vlen would
+   misrepresent the vector registers.  The vector state is recovered
+   from the NT_RISCV_VECTOR note instead.  */
+
+static void
+riscv_apply_hwcap (struct riscv_gdbarch_features &features, ULONGEST hwcap)
+{
+  if (features.flen == 0)
+    {
+      if ((hwcap & riscv_hwcap_isa ('d')) != 0)
+	features.flen = riscv_flen_d;
+      else if ((hwcap & riscv_hwcap_isa ('f')) != 0)
+	features.flen = riscv_flen_f;
+    }
+}
+
+/* Implement the "core_read_description" gdbarch method.
+
+   Sources in decreasing order of precedence: an NT_GDB_TDESC note is
+   used by the core target directly and this hook is never consulted;
+   then the ELF header and the notes via riscv_features_from_bfd;
+   finally AT_HWCAP, which only fills in what is still unknown.  */
+
+static const struct target_desc *
+riscv_linux_core_read_description (struct gdbarch *gdbarch,
+				   struct target_ops *target, bfd *abfd)
+{
+  auto features = riscv_features_from_bfd (abfd);
+
+  auto auxv = target_read_auxv_raw (target);
+  auto hwcap = linux_get_hwcap (auxv, target, gdbarch);
+  riscv_apply_hwcap (features, hwcap);
+
+  return riscv_lookup_target_description (features);
+}
+
 /* Initialize RISC-V Linux ABI info.  */
 
 static void
@@ -555,6 +608,9 @@ riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
   set_gdbarch_iterate_over_regset_sections
     (gdbarch, riscv_linux_iterate_over_regset_sections);
 
+  set_gdbarch_core_read_description (gdbarch,
+				     riscv_linux_core_read_description);
+
   tramp_frame_prepend_unwinder (gdbarch, &riscv_linux_sigframe);
 
   tdep->syscall_next_pc = riscv_linux_syscall_next_pc;
@@ -567,10 +623,74 @@ riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
   set_gdbarch_get_syscall_number (gdbarch, riscv_linux_get_syscall_number);
 }
 
+#if GDB_SELF_TEST
+namespace selftests
+{
+
+/* Check that AT_HWCAP bits refine the ISA features as expected.  */
+
+static void
+riscv_apply_hwcap_test ()
+{
+  const ULONGEST hwcap_f = riscv_hwcap_isa ('f');
+  const ULONGEST hwcap_d = riscv_hwcap_isa ('d');
+  const ULONGEST hwcap_v = riscv_hwcap_isa ('v');
+
+  /* The 'd' bit implies double precision, 'f' single precision.  */
+  {
+    riscv_gdbarch_features features;
+    riscv_apply_hwcap (features, hwcap_d);
+    SELF_CHECK (features.flen == riscv_flen_d);
+  }
+  {
+    riscv_gdbarch_features features;
+    riscv_apply_hwcap (features, hwcap_f);
+    SELF_CHECK (features.flen == riscv_flen_f);
+  }
+
+  /* 'd' wins over 'f' when both are set.  */
+  {
+    riscv_gdbarch_features features;
+    riscv_apply_hwcap (features, hwcap_d | hwcap_f);
+    SELF_CHECK (features.flen == riscv_flen_d);
+  }
+
+  /* An flen already recovered from the core is not overwritten.  */
+  {
+    riscv_gdbarch_features features;
+    features.flen = riscv_flen_f;
+    riscv_apply_hwcap (features, hwcap_d);
+    SELF_CHECK (features.flen == riscv_flen_f);
+  }
+
+  /* The 'v' bit is ignored: AT_HWCAP carries no vector length.  */
+  {
+    riscv_gdbarch_features features;
+    riscv_apply_hwcap (features, hwcap_v);
+    SELF_CHECK (features.vlen == 0);
+  }
+
+  /* No relevant bits leaves the features untouched.  */
+  {
+    riscv_gdbarch_features features;
+    riscv_apply_hwcap (features, 0);
+    SELF_CHECK (features.flen == 0);
+    SELF_CHECK (features.vlen == 0);
+  }
+}
+
+} /* namespace selftests */
+#endif /* GDB_SELF_TEST */
+
 /* Initialize RISC-V Linux target support.  */
 
 INIT_GDB_FILE (riscv_linux_tdep)
 {
   gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_LINUX,
 			  riscv_linux_init_abi);
+
+#if GDB_SELF_TEST
+  selftests::register_test ("riscv-apply-hwcap",
+			    selftests::riscv_apply_hwcap_test);
+#endif
 }
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 1af4be77091..1801b042de3 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -3924,9 +3924,6 @@ static const struct frame_unwind_legacy riscv_frame_unwind (
   /*.prev_arch     =*/ NULL
 );
 
-/* FP register width, in bytes, implied by the D and F extensions.  */
-static constexpr int riscv_flen_d = 8;
-static constexpr int riscv_flen_f = 4;
 
 /* Return the FLEN implied by SIZE, the size of an NT_FPREGSET note, or 0
    if SIZE matches no known layout.  The note holds 32 FP registers of
@@ -3971,10 +3968,9 @@ riscv_flen_from_core_fpregset (bfd *abfd)
   return flen;
 }
 
-/* Extract a set of required target features out of ABFD.  If ABFD is
-   nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state.  */
+/* See riscv-tdep.h.  */
 
-static struct riscv_gdbarch_features
+struct riscv_gdbarch_features
 riscv_features_from_bfd (bfd *abfd)
 {
   struct riscv_gdbarch_features features;
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 344a995a680..5fe91b7287c 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -158,6 +158,15 @@ extern int riscv_abi_flen (struct gdbarch *gdbarch);
    argument registers.  */
 extern bool riscv_abi_embedded (struct gdbarch *gdbarch);
 
+/* FP register width, in bytes, implied by the D and F extensions.  */
+constexpr int riscv_flen_d = 8;
+constexpr int riscv_flen_f = 4;
+
+/* Extract a set of required target features out of ABFD.  If ABFD is
+   nullptr then a RISCV_GDBARCH_FEATURES is returned in its default
+   state.  */
+extern struct riscv_gdbarch_features riscv_features_from_bfd (bfd *abfd);
+
 /* Single step based on where the current instruction will take us.  */
 extern std::vector<CORE_ADDR> riscv_software_single_step
   (struct regcache *regcache);
diff --git a/gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2 b/gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
new file mode 100644
index 0000000000000000000000000000000000000000..c557362d69cf483e16c370c0ecd3fe974b882e69
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z;|M~LWFWB_Ili-(vR+OPa(lxQxG<CbnFSb<ccQ7<{33!Zf{+yuf{O(tL<C}@2+0c}
zLn6ouELjMoiU6dHMFkcFSg=r$7>GfPL;zStAr?YJV-f<vKolfdBCH6a$ViNYSqTLI
zStJFL3P~c85k-+?f|4RYSU^w(l6!^(ra+2Cf`mkX2$BjBLMbAVV#xqmA}~aO6jBNh
z5rh>;vMh@tG}=-SRk4IxB?lAp$6Pzw(10(29uyqWxXIn_13+%KRe%a<*%dSLVh6g4
zmr7|<z9Nz_NQi$_rky+>gCGO%KMz!hLnW_=fg7L#iY1{WL<W>vtH$d3JdanIyx61L
z*9D|N#_KqKRUNF4CCQs9^%})H#!@{_&cw!bUIcII&wQ4XI%oeEaz!{$kg^pqa4HyU
AiU0rr

literal 0
HcmV?d00001

diff --git a/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp b/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
new file mode 100644
index 00000000000..84f09c04b3a
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
@@ -0,0 +1,72 @@
+# Copyright 2026 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Check that GDB recovers the ISA features of a core file from the
+# AT_HWCAP entry of the NT_AUXV note: the kernel publishes the
+# single-letter ISA extensions of the machine there, so a kernel core
+# opened without the executable still reveals the F and D extensions.
+#
+# The bundled core (riscv-core-hwcap.core.bz2) is a real kernel core
+# (e_flags = 0, no NT_GDB_TDESC, no RISC-V attributes) whose
+# NT_FPREGSET note has been stripped, leaving AT_HWCAP = 0x20112d
+# (rv64acdfimv) as the only evidence of the FP extension.  The F-only
+# mapping and the precedence rules are covered by the
+# "riscv-apply-hwcap" selftest.
+#
+# How to regenerate the fixture: take the riscv-core-fpregset.core.bz2
+# kernel core and remove the NT_FPREGSET note from PT_NOTE: rewrite the
+# note blob without the CORE/type-2 entry, zero-pad the segment to keep
+# file offsets stable, shrink p_filesz/p_memsz of the PT_NOTE program
+# header accordingly, and bzip2 the result.
+
+# The fixture is an ELF64 core and the FLEN assertions are
+# RV64-specific.
+require {istarget "riscv64-*-*"}
+
+if {![istarget *-*-linux*]} {
+    unsupported "linux only"
+    return -1
+}
+
+set core [decompress_bz2 $srcdir/$subdir/riscv-core-hwcap.core.bz2]
+if {$core == ""} {
+    untested "failed to decompress core file"
+    return -1
+}
+set core [gdb_remote_download host $core]
+
+clean_restart
+
+# Before the core is loaded there is no target, so nothing to prove
+# that the FP and vector registers below really come from the core.
+gdb_test "info registers \$fa0" "The program has no registers now\\." \
+    "no registers before the core is loaded"
+
+if {![gdb_core_cmd $core "load kernel core without executable"]} {
+    return -1
+}
+
+# The D bit of AT_HWCAP gives us the FP registers.
+gdb_test "info registers \$fa0" "fa0\[ \t\]+.*" \
+    "fp registers recovered from hwcap"
+
+# ... and implies FLEN = 8.
+gdb_test "print sizeof (\$fa0)" "= 8" \
+    "flen recovered from hwcap"
+
+# The V bit of AT_HWCAP is deliberately ignored: it carries no vector
+# length, so no vector registers are invented.
+gdb_test "info registers \$v0" "Invalid register .v0." \
+    "no vector registers invented from hwcap"
-- 
2.43.0

[PATCH 3/4] gdb/riscv: test the "arch=" disassembler option

[Farid Khaidari]

The test puts vector instructions into an executable built for rv64gc.
They disassemble as raw .insn words until "arch=" names an ISA with V.
The check is repeated on a copy with the architecture attribute
stripped.

One "disassemble" command uses a single disassembler for the whole
function, so the expected output covers more than the first
instruction: an option lost after it would show there.  Mapping
symbols are left to objdump tests, since GDB cannot exercise them.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 .../gdb.arch/riscv-disasm-arch-option.c       | 40 +++++++++
 .../gdb.arch/riscv-disasm-arch-option.exp     | 84 +++++++++++++++++++
 2 files changed, 124 insertions(+)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp

diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
new file mode 100644
index 00000000000..75857442b7e
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
@@ -0,0 +1,40 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+   Copyright 2026 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* Plant the encodings of two vector instructions in an ordinary
+   function.  The file is compiled without the vector extension, so the
+   ELF carries an rv64gc architecture attribute and the instructions
+   only decode once the disassembler is told about the vector extension
+   through the "arch=" option.  ".insn" is used rather than the
+   mnemonics because assembling those would require the vector
+   extension, which would then appear in the architecture attribute of
+   the ELF and leave the option with nothing to prove.  */
+
+void
+vector_insns (void)
+{
+  /* vsetvli t0,a0,e8,m1,ta,ma */
+  asm volatile (".insn 4, 0x0c0572d7");
+  /* vxor.vv v1,v2,v3 */
+  asm volatile (".insn 4, 0x2e2180d7");
+}
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
new file mode 100644
index 00000000000..1e6698b2e5d
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
@@ -0,0 +1,84 @@
+# Copyright 2026 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Check the "arch=" disassembler option against an executable.  The
+# option names the ISA to disassemble for, in place of the one the
+# object records, so the test needs an object both with and without an
+# architecture attribute.
+#
+# A single "disassemble" prints the whole function through one
+# disassembler, so an ISA that survived only the first instruction would
+# show up from the second on: the expected output names both.
+
+require {istarget "riscv64-*-*"}
+
+standard_testfile
+
+# Compile without the vector extension: the executable carries an rv64gc
+# architecture attribute, and the vector instructions planted in it only
+# decode once the disassembler is told about the vector extension.
+set compile_flags {debug}
+lappend compile_flags "additional_flags=-march=rv64gc"
+
+if {[prepare_for_testing "failed to prepare" $testfile $srcfile $compile_flags]} {
+    return -1
+}
+
+gdb_test "disassemble vector_insns" "\\.insn\[ \t\]+4, 0x0c0572d7.*" \
+    "vector instructions not decoded with the ISA of the object"
+
+gdb_test_no_output "set disassembler-options arch=rv64gcv" \
+    "set the arch to one with vector"
+
+gdb_test "disassemble vector_insns" \
+    "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*" \
+    "arch= overrides the ISA of the object"
+
+# Each "disassemble" builds its own disassembler, so this repetition
+# only checks that the option is still in effect for the next command,
+# not that it survived within one.
+gdb_test "disassemble vector_insns" \
+    "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*" \
+    "arch=rv64gcv still in effect for the next command"
+
+# Clearing the option returns to the ISA of the object.
+gdb_test_no_output "set disassembler-options" "clear disassembler options"
+
+gdb_test "disassemble vector_insns" "\\.insn\[ \t\]+4, 0x0c0572d7.*" \
+    "vector instructions not decoded after clearing the option"
+
+# An object that records no ISA is the case GDB supplies the option for
+# on its own.  Strip the attribute to get one that still has a symbol
+# table, which a core file cannot stand in for.
+set stripped ${testfile}-no-attributes
+set objcopy [gdb_find_objcopy]
+
+if {[run_on_host "strip the architecture attribute" $objcopy \
+	 "--remove-section=.riscv.attributes $binfile \
+	      [standard_output_file $stripped]"]} {
+    return -1
+}
+
+clean_restart $stripped
+
+gdb_test "info symbol vector_insns" "vector_insns in section .*" \
+    "the stripped binary still carries a symbol table"
+
+gdb_test_no_output "set disassembler-options arch=rv64gcv" \
+    "set the arch on an object without an attribute"
+
+gdb_test "disassemble vector_insns" \
+    "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*" \
+    "vector instructions decoded with arch=rv64gcv"
-- 
2.43.0

[PATCH 4/4] gdb/riscv: disassemble an attribute-less object by the description ISA

[Farid Khaidari]

An object without a RISC-V architecture attribute is disassembled as
rv64gc, whatever the target description says.  A core file is such an
object, so its vector instructions print as raw .insn words even when
the description has vector registers.

For such objects, pass the ISA implied by the target description to
the disassembler as "arch=".  An object that records its own ISA keeps
using it.  The test checks both cases: with a vector description
loaded, an rv64gc executable must not decode the planted words as
vector instructions, and the same executable with the attribute
stripped must.

The option is set in print_insn, not through
gdbarch_disassembler_options_implicit as mips-tdep.c does.  A gdbarch
is shared by all objects with matching features, and only print_insn
knows which object it is disassembling.

User options are appended to the string for every instruction.
libopcodes clears disassembler_options after parsing and resets any
option missing from a later string, so they would be lost from the
second instruction on.

The test loads the vector description from a file.  In practice such a
description comes from a core, but a core only matches the executable
that produced it.  Only RV64 is tested; the RV32 ISA string was checked
by reading the code.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 gdb/riscv-tdep.c                              |  76 +++++++++++
 gdb/riscv-tdep.h                              |   5 +
 .../riscv-disasm-arch-option-vector.xml       | 123 ++++++++++++++++++
 .../gdb.arch/riscv-disasm-arch-option.exp     |  42 +++++-
 4 files changed, 245 insertions(+), 1 deletion(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 1801b042de3..a1132b86b43 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -39,6 +39,7 @@
 #include "elf-bfd.h"
 #include "symcat.h"
 #include "dis-asm.h"
+#include "disasm.h"
 #include "frame-unwind.h"
 #include "frame-base.h"
 #include "trad-frame.h"
@@ -4201,6 +4202,44 @@ riscv_gnu_triplet_regexp (struct gdbarch *gdbarch)
   return "riscv(32|64)?";
 }
 
+/* Return true if the object owning the section being disassembled
+   records a RISC-V ISA string attribute.  */
+
+static bool
+riscv_disasm_bfd_has_isa_attribute (struct disassemble_info *info)
+{
+  if (info->section == nullptr)
+    return false;
+
+  auto *abfd = info->section->owner;
+  if (abfd == nullptr || bfd_get_flavour (abfd) != bfd_target_elf_flavour)
+    return false;
+
+  return elf_known_obj_attributes_proc (abfd)[Tag_RISCV_arch].s != nullptr;
+}
+
+/* X register width, in bytes, implied by the RV32 base integer ISA.  */
+constexpr int riscv_xlen_32 = 4;
+
+/* Build an ISA string for the "arch=" disassembler option from
+   FEATURES, the target description of the architecture.  The option
+   replaces the rv64gc default of libopcodes, so the extension set is
+   that same default, widened by V once the target description sizes
+   the vector registers.  Naming the extensions the description does
+   know about instead would decode less than the default it replaces:
+   an ISA without G implies neither Zicsr nor Zifencei, which would
+   drop "csrr" and "fence.i" from a target that merely describes no FP
+   registers.  */
+
+static std::string
+riscv_isa_for_disassembler (const struct riscv_gdbarch_features &features)
+{
+  std::string isa = features.xlen == riscv_xlen_32 ? "rv32gc" : "rv64gc";
+  if (features.vlen > 0)
+    isa += "v";
+  return isa;
+}
+
 /* Implement the "print_insn" gdbarch method.  */
 
 static int
@@ -4212,6 +4251,37 @@ riscv_print_insn (bfd_vma addr, struct disassemble_info *info)
   if (s != nullptr)
     info->section = s->the_bfd_section;
 
+  /* An object that records its own ISA is disassembled according to
+     that ISA.  One that does not, such as a core file loaded without an
+     executable, is disassembled according to the target description;
+     libopcodes would otherwise fall back to plain rv64gc.  ARCH_OPTION
+     must outlive the default_print_insn call below, which parses it.
+
+     The user options are read from the gdbarch and appended here.
+     libopcodes clears INFO->DISASSEMBLER_OPTIONS once it has parsed
+     them, so the string has to be supplied again for the next
+     instruction; each parse first resets every option it does not see
+     back to its default, which is why the user ones have to be
+     repeated rather than parsed once.  They come last and so take
+     precedence.  */
+  std::string arch_option;
+  auto *di = static_cast<gdb_disassemble_info *> (info->application_data);
+  if (di != nullptr && !riscv_disasm_bfd_has_isa_attribute (info))
+    {
+      gdbarch *arch = di->arch ();
+      riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (arch);
+
+      arch_option = tdep->disassembler_options_arch;
+
+      const char *user_options = get_disassembler_options (arch);
+      if (user_options != nullptr && *user_options != '\0')
+	{
+	  arch_option += ',';
+	  arch_option += user_options;
+	}
+      info->disassembler_options = arch_option.c_str ();
+    }
+
   return default_print_insn (addr, info);
 }
 
@@ -4343,6 +4413,12 @@ riscv_gdbarch_init (struct gdbarch_info info,
   tdep->isa_features = features;
   tdep->abi_features = abi_features;
 
+  /* Supplied to the disassembler for an object that records no ISA of
+     its own, such as a core file loaded without an executable, which
+     libopcodes would otherwise disassemble as plain rv64gc.  */
+  std::string isa = riscv_isa_for_disassembler (features);
+  tdep->disassembler_options_arch = "arch=" + isa;
+
   /* Target data types.  */
   set_gdbarch_short_bit (gdbarch, 16);
   set_gdbarch_int_bit (gdbarch, 32);
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 5fe91b7287c..d9a696fccb7 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -94,6 +94,11 @@ struct riscv_gdbarch_tdep : gdbarch_tdep_base
   /* ISA-specific data types.  */
   struct type *riscv_fpreg_d_type = nullptr;
 
+  /* The "arch=" disassembler option naming the ISA of ISA_FEATURES,
+     supplied to the disassembler for an object that records no ISA of
+     its own.  */
+  std::string disassembler_options_arch;
+
   /* The location of these registers, set to -2 by default so we don't
      match against -1 which is frequently used to mean "all registers",
      e.g. in the regcache supply/collect code.  */
diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml
new file mode 100644
index 00000000000..7f514803d51
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml
@@ -0,0 +1,123 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2026 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+  <architecture>riscv</architecture>
+  <feature name="org.gnu.gdb.riscv.cpu">
+    <reg name="zero" bitsize="64" type="int"/>
+    <reg name="ra" bitsize="64" type="code_ptr"/>
+    <reg name="sp" bitsize="64" type="data_ptr"/>
+    <reg name="gp" bitsize="64" type="data_ptr"/>
+    <reg name="tp" bitsize="64" type="data_ptr"/>
+    <reg name="t0" bitsize="64" type="int"/>
+    <reg name="t1" bitsize="64" type="int"/>
+    <reg name="t2" bitsize="64" type="int"/>
+    <reg name="fp" bitsize="64" type="data_ptr"/>
+    <reg name="s1" bitsize="64" type="int"/>
+    <reg name="a0" bitsize="64" type="int"/>
+    <reg name="a1" bitsize="64" type="int"/>
+    <reg name="a2" bitsize="64" type="int"/>
+    <reg name="a3" bitsize="64" type="int"/>
+    <reg name="a4" bitsize="64" type="int"/>
+    <reg name="a5" bitsize="64" type="int"/>
+    <reg name="a6" bitsize="64" type="int"/>
+    <reg name="a7" bitsize="64" type="int"/>
+    <reg name="s2" bitsize="64" type="int"/>
+    <reg name="s3" bitsize="64" type="int"/>
+    <reg name="s4" bitsize="64" type="int"/>
+    <reg name="s5" bitsize="64" type="int"/>
+    <reg name="s6" bitsize="64" type="int"/>
+    <reg name="s7" bitsize="64" type="int"/>
+    <reg name="s8" bitsize="64" type="int"/>
+    <reg name="s9" bitsize="64" type="int"/>
+    <reg name="s10" bitsize="64" type="int"/>
+    <reg name="s11" bitsize="64" type="int"/>
+    <reg name="t3" bitsize="64" type="int"/>
+    <reg name="t4" bitsize="64" type="int"/>
+    <reg name="t5" bitsize="64" type="int"/>
+    <reg name="t6" bitsize="64" type="int"/>
+    <reg name="pc" bitsize="64" type="code_ptr"/>
+  </feature>
+  <feature name="org.gnu.gdb.riscv.fpu">
+
+    <union id="riscv_double">
+      <field name="float" type="ieee_single"/>
+      <field name="double" type="ieee_double"/>
+    </union>
+
+    <reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/>
+    <reg name="ft1" bitsize="64" type="riscv_double"/>
+    <reg name="ft2" bitsize="64" type="riscv_double"/>
+    <reg name="ft3" bitsize="64" type="riscv_double"/>
+    <reg name="ft4" bitsize="64" type="riscv_double"/>
+    <reg name="ft5" bitsize="64" type="riscv_double"/>
+    <reg name="ft6" bitsize="64" type="riscv_double"/>
+    <reg name="ft7" bitsize="64" type="riscv_double"/>
+    <reg name="fs0" bitsize="64" type="riscv_double"/>
+    <reg name="fs1" bitsize="64" type="riscv_double"/>
+    <reg name="fa0" bitsize="64" type="riscv_double"/>
+    <reg name="fa1" bitsize="64" type="riscv_double"/>
+    <reg name="fa2" bitsize="64" type="riscv_double"/>
+    <reg name="fa3" bitsize="64" type="riscv_double"/>
+    <reg name="fa4" bitsize="64" type="riscv_double"/>
+    <reg name="fa5" bitsize="64" type="riscv_double"/>
+    <reg name="fa6" bitsize="64" type="riscv_double"/>
+    <reg name="fa7" bitsize="64" type="riscv_double"/>
+    <reg name="fs2" bitsize="64" type="riscv_double"/>
+    <reg name="fs3" bitsize="64" type="riscv_double"/>
+    <reg name="fs4" bitsize="64" type="riscv_double"/>
+    <reg name="fs5" bitsize="64" type="riscv_double"/>
+    <reg name="fs6" bitsize="64" type="riscv_double"/>
+    <reg name="fs7" bitsize="64" type="riscv_double"/>
+    <reg name="fs8" bitsize="64" type="riscv_double"/>
+    <reg name="fs9" bitsize="64" type="riscv_double"/>
+    <reg name="fs10" bitsize="64" type="riscv_double"/>
+    <reg name="fs11" bitsize="64" type="riscv_double"/>
+    <reg name="ft8" bitsize="64" type="riscv_double"/>
+    <reg name="ft9" bitsize="64" type="riscv_double"/>
+    <reg name="ft10" bitsize="64" type="riscv_double"/>
+    <reg name="ft11" bitsize="64" type="riscv_double"/>
+
+    <reg name="fcsr" bitsize="32" type="int" regnum="68"/>
+  </feature>
+  <feature name="org.gnu.gdb.riscv.vector">
+    <vector id="bytes16" type="uint8" count="16"/>
+    <reg name="v0" bitsize="128" type="bytes16"/>
+    <reg name="v1" bitsize="128" type="bytes16"/>
+    <reg name="v2" bitsize="128" type="bytes16"/>
+    <reg name="v3" bitsize="128" type="bytes16"/>
+    <reg name="v4" bitsize="128" type="bytes16"/>
+    <reg name="v5" bitsize="128" type="bytes16"/>
+    <reg name="v6" bitsize="128" type="bytes16"/>
+    <reg name="v7" bitsize="128" type="bytes16"/>
+    <reg name="v8" bitsize="128" type="bytes16"/>
+    <reg name="v9" bitsize="128" type="bytes16"/>
+    <reg name="v10" bitsize="128" type="bytes16"/>
+    <reg name="v11" bitsize="128" type="bytes16"/>
+    <reg name="v12" bitsize="128" type="bytes16"/>
+    <reg name="v13" bitsize="128" type="bytes16"/>
+    <reg name="v14" bitsize="128" type="bytes16"/>
+    <reg name="v15" bitsize="128" type="bytes16"/>
+    <reg name="v16" bitsize="128" type="bytes16"/>
+    <reg name="v17" bitsize="128" type="bytes16"/>
+    <reg name="v18" bitsize="128" type="bytes16"/>
+    <reg name="v19" bitsize="128" type="bytes16"/>
+    <reg name="v20" bitsize="128" type="bytes16"/>
+    <reg name="v21" bitsize="128" type="bytes16"/>
+    <reg name="v22" bitsize="128" type="bytes16"/>
+    <reg name="v23" bitsize="128" type="bytes16"/>
+    <reg name="v24" bitsize="128" type="bytes16"/>
+    <reg name="v25" bitsize="128" type="bytes16"/>
+    <reg name="v26" bitsize="128" type="bytes16"/>
+    <reg name="v27" bitsize="128" type="bytes16"/>
+    <reg name="v28" bitsize="128" type="bytes16"/>
+    <reg name="v29" bitsize="128" type="bytes16"/>
+    <reg name="v30" bitsize="128" type="bytes16"/>
+    <reg name="v31" bitsize="128" type="bytes16"/>
+  </feature>
+</target>
diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
index 1e6698b2e5d..49500408f72 100644
--- a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
+++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
@@ -16,7 +16,8 @@
 # Check the "arch=" disassembler option against an executable.  The
 # option names the ISA to disassemble for, in place of the one the
 # object records, so the test needs an object both with and without an
-# architecture attribute.
+# architecture attribute.  GDB supplies the option itself for the object
+# that records nothing, which the test checks as well.
 #
 # A single "disassemble" prints the whole function through one
 # disassembler, so an ISA that survived only the first instruction would
@@ -82,3 +83,42 @@ gdb_test_no_output "set disassembler-options arch=rv64gcv" \
 gdb_test "disassemble vector_insns" \
     "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*" \
     "vector instructions decoded with arch=rv64gcv"
+
+# For an object that records no ISA, GDB names one on its own, out of the
+# target description.  In practice a description that sizes the vector
+# registers is the one recovered from a core file, but a core only pairs
+# with the executable it was dumped from, and the instructions of this
+# one would be nowhere in the memory such a core dumped.  A description
+# loaded from a file sizes the registers the same way and pairs with any
+# executable.
+set tdesc_file "${srcdir}/${subdir}/${testfile}-vector.xml"
+
+if {[is_remote host]} {
+    set tdesc_file [remote_download host $tdesc_file]
+}
+
+# Restarting drops the option set above: what decodes the instructions
+# here is the ISA GDB supplies itself.
+clean_restart $stripped
+
+gdb_test_no_output "set tdesc filename $tdesc_file" \
+    "load a description with vector registers, object without an attribute"
+
+gdb_test "disassemble vector_insns" \
+    "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*" \
+    "the description ISA reaches the disassembler on its own"
+
+# The same description against the executable that does record rv64gc:
+# the attribute has to keep winning, so the planted encodings stay raw
+# words.  Were the description supplied here anyway, they would decode as
+# vector instructions.
+clean_restart $testfile
+
+gdb_test_no_output "set tdesc filename $tdesc_file" \
+    "load a description with vector registers"
+
+gdb_test "print sizeof (\$v0)" " = 16" \
+    "the description sizes the vector registers"
+
+gdb_test "disassemble vector_insns" "\\.insn\[ \t\]+4, 0x0c0572d7.*" \
+    "the attribute of the object outranks the description ISA"
-- 
2.43.0

Re: [PATCH 1/4] gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files

[Kevin Buettner]

Hi Farid,

On 10/22/26 8:44 AM, Farid Khaidari wrote:
> A Linux kernel core has no float ABI in e_flags and no RISC-V
> attributes.  Opened without the executable, it gets an integer-only
> target description, and "p $fa0" fails with "Invalid register 'fa0'"
> even though the core holds the FP state.
> 
> The kernel writes 32 FP registers of FLEN bytes plus fcsr into
> NT_FPREGSET, so the note size gives FLEN.  Use it when e_flags says
> nothing.
> 
> The test core is a real kernel dump with a 264-byte NT_FPREGSET,
> i.e. FLEN = 8.
> 
> Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
> ---
>  gdb/riscv-tdep.c                              |  89 +++++++++++++++++-

I don't think that riscv-tdep.c is the correct place to add knowledge
about linux specific features.  It seems to me that much of what you've
done here ought to be placed in gdb/riscv-linux-tdep.c.

If it's not truly linux-specific, but would be of benefit to other riscv
platforms, then this should be explained in the commit log as well as in
the code comments too.

Kevin

Re: [PATCH 0/4] gdb/riscv: analyse a core file without the executable

[Kevin Buettner]

On 10/22/26 8:44 AM, Farid Khaidari wrote:
> A RISC-V core opened without its executable gets an integer-only
> target description, because the core does not say how wide the FP
> registers are.  Any object with no ISA attribute, a core included, is
> also disassembled as plain rv64gc.
> 
> This series reads what the core does record.  The size of the
> NT_FPREGSET note gives FLEN, and AT_HWCAP gives the single-letter
> extensions.  The last patch passes the ISA of the resulting target
> description to the disassembler when the object names none.
> 
> Patches 3 and 4 need the "arch=" disassembler option, sent to
> binutils@sourceware.org as "RISC-V: add an "arch=" disassembler
> option".
> 
> Vector state from the NT_RISCV_VECTOR note is left out.  GDB can read
> the org.gnu.gdb.riscv.vector feature from a target description but
> cannot build one, so a vlen read from the core has nowhere to go yet.
> The disassembler test loads a vector description from a file instead.
> 
> Tested on x86_64-linux with a riscv64-linux-gnu target: the three new
> tests give 23 passes and no failures.  The host cannot run RISC-V
> binaries, so I did not run the rest of the testsuite.
> 
> Farid Khaidari (4):
>   gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files
>   gdb/riscv: recover core file ISA features from AT_HWCAP
>   gdb/riscv: test the "arch=" disassembler option
>   gdb/riscv: disassemble an attribute-less object by the description ISA
> 
>  gdb/riscv-linux-tdep.c                        | 120 +++++++++++++
>  gdb/riscv-tdep.c                              | 167 +++++++++++++++++-
>  gdb/riscv-tdep.h                              |  14 ++
>  .../gdb.arch/riscv-core-fpregset.core.bz2     | Bin 0 -> 15134 bytes
>  .../gdb.arch/riscv-core-fpregset.exp          |  78 ++++++++
>  .../gdb.arch/riscv-core-hwcap.core.bz2        | Bin 0 -> 15122 bytes
>  gdb/testsuite/gdb.arch/riscv-core-hwcap.exp   |  72 ++++++++
>  .../riscv-disasm-arch-option-vector.xml       | 123 +++++++++++++
>  .../gdb.arch/riscv-disasm-arch-option.c       |  40 +++++
>  .../gdb.arch/riscv-disasm-arch-option.exp     | 124 +++++++++++++
>  10 files changed, 732 insertions(+), 6 deletions(-)
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.exp
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp

I ran this series, including the companion changes sent to the binutils
list, through an AI code review which included testing on a RISC-V Linux
machine.  No regressions were found; this series does what it claims.

I am replying to concerns found regarding individual patches.

Kevin

Re: [PATCH 4/4] gdb/riscv: disassemble an attribute-less object by the description ISA

[Kevin Buettner]

Hi Farid,

A nit...

On 10/22/26 8:44 AM, Farid Khaidari wrote:

>  static int
> @@ -4212,6 +4251,37 @@ riscv_print_insn (bfd_vma addr, struct disassemble_info *info)
>    if (s != nullptr)
>      info->section = s->the_bfd_section;
>  
> +  /* An object that records its own ISA is disassembled according to
> +     that ISA.  One that does not, such as a core file loaded without an
> +     executable, is disassembled according to the target description;
> +     libopcodes would otherwise fall back to plain rv64gc.  ARCH_OPTION
> +     must outlive the default_print_insn call below, which parses it.
> +
> +     The user options are read from the gdbarch and appended here.
> +     libopcodes clears INFO->DISASSEMBLER_OPTIONS once it has parsed
> +     them, so the string has to be supplied again for the next
> +     instruction; each parse first resets every option it does not see
> +     back to its default, which is why the user ones have to be
> +     repeated rather than parsed once.  They come last and so take
> +     precedence.  */
> +  std::string arch_option;
> +  auto *di = static_cast<gdb_disassemble_info *> (info->application_data);
> +  if (di != nullptr && !riscv_disasm_bfd_has_isa_attribute (info))
> +    {
> +      gdbarch *arch = di->arch ();
> +      riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (arch);
> +
> +      arch_option = tdep->disassembler_options_arch;
> +
> +      const char *user_options = get_disassembler_options (arch);
> +      if (user_options != nullptr && *user_options != '\0')
> +	{
> +	  arch_option += ',';
> +	  arch_option += user_options;
> +	}
> +      info->disassembler_options = arch_option.c_str ();

This points info->disassembler_options at storage owned by a local
std::string, which is destroyed when riscv_print_insn returns.  It
only works because print_insn_riscv() sets disassembler_options to
NULL after parsing them.  (There is an early return before that, when
riscv_init_disasm_info fails, but that function currently always
returns true.)  Relying on that libopcodes behaviour seems fragile:
if print_insn_riscv ever stops clearing the field, or returns early
before doing so, the next instruction will see a dangling pointer.

Kevin

[PATCH v2 0/4] gdb/riscv: analyse a core file without the executable

[Farid Khaidari]

A RISC-V core opened without its executable gets an integer-only
target description and is disassembled as plain rv64gc.  This series
takes FLEN from the size of the NT_FPREGSET note and the single-letter
extensions from AT_HWCAP, and passes the resulting ISA to the
disassembler when the object names none.  Vector state is left out:
GDB cannot build a vector target description yet.

Patches 3 and 4 need "[PATCH v2] RISC-V: add an "arch=" disassembler
option" on binutils@sourceware.org.

Changes in v2:

- The core file code moves to riscv-linux-tdep.c as a
  core_read_description hook (patches 1 and 2).
- riscv_print_insn restores disassembler_options after each
  instruction (patch 4).
- The test core files were regenerated on a stock Linux 6.8 kernel.

Tested on x86_64-linux with a riscv64-linux-gnu target: 22 passes, no
failures, and each patch builds and passes its tests on its own.

Farid Khaidari (4):
  gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files
  gdb/riscv: recover core file ISA features from AT_HWCAP
  gdb/riscv: test the "arch=" disassembler option
  gdb/riscv: disassemble an attribute-less object by the description ISA

 gdb/riscv-linux-tdep.c                        | 161 +++++++++++++++++-
 gdb/riscv-tdep.c                              |  78 ++++++++-
 gdb/riscv-tdep.h                              |  10 ++
 .../gdb.arch/riscv-core-fpregset.core.bz2     | Bin 0 -> 3204 bytes
 .../gdb.arch/riscv-core-fpregset.exp          |  73 ++++++++
 .../gdb.arch/riscv-core-hwcap.core.bz2        | Bin 0 -> 3229 bytes
 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp   |  67 ++++++++
 .../riscv-disasm-arch-option-vector.xml       | 123 +++++++++++++
 .../gdb.arch/riscv-disasm-arch-option.c       |  40 +++++
 .../gdb.arch/riscv-disasm-arch-option.exp     | 119 +++++++++++++
 10 files changed, 663 insertions(+), 8 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp

-- 
2.43.0

[PATCH v2 1/4] gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files

[Farid Khaidari]

A core dumped by the Linux kernel has no float ABI in e_flags and no
RISC-V attributes.  Opened without the executable, it gets an
integer-only target description, and "p $fa0" fails with "Invalid
register 'fa0'" even though the core holds the FP state.

Add a core_read_description hook for RISC-V Linux.  When e_flags says
nothing, it takes FLEN from the size of the NT_FPREGSET note: 32
registers of FLEN bytes plus fcsr padded to 8 bytes.  The size formula
moves out of riscv_linux_iterate_over_regset_sections into a helper
that both use.  The
layout is Linux-specific (FreeBSD, for one, always uses 16-byte slots),
so the hook lives in riscv-linux-tdep.c.  If the note gives nothing,
the hook returns no description and GDB behaves as before.
riscv_features_from_bfd is exported for it.

The test core is a real Linux core dump with a 264-byte NT_FPREGSET,
i.e. FLEN = 8.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 gdb/riscv-linux-tdep.c                        |  93 +++++++++++++++++-
 gdb/riscv-tdep.c                              |   9 +-
 gdb/riscv-tdep.h                              |  10 ++
 .../gdb.arch/riscv-core-fpregset.core.bz2     | Bin 0 -> 3204 bytes
 .../gdb.arch/riscv-core-fpregset.exp          |  73 ++++++++++++++
 5 files changed, 177 insertions(+), 8 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.exp

diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c
index fcfa5f98ea4..594f6a36f89 100644
--- a/gdb/riscv-linux-tdep.c
+++ b/gdb/riscv-linux-tdep.c
@@ -31,6 +31,7 @@
 #include "linux-record.h"
 #include "riscv-linux-tdep.h"
 #include "inferior.h"
+#include "gdbsupport/selftest.h"
 
 extern unsigned int record_debug;
 
@@ -74,6 +75,16 @@ static const struct regset riscv_linux_fregset =
   riscv_linux_fregmap, riscv_supply_regset, regcache_collect_regset
 };
 
+/* Return the size of the FP register regset for FP registers of FLEN
+   bytes: 32 registers followed by FCSR, which the kernel pads to 8
+   bytes.  */
+
+static constexpr int
+riscv_linux_fregset_size (int flen)
+{
+  return 32 * flen + 8;
+}
+
 /* Define hook for core file support.  */
 
 static void
@@ -84,9 +95,8 @@ riscv_linux_iterate_over_regset_sections (struct gdbarch *gdbarch,
 {
   cb (".reg", (32 * riscv_isa_xlen (gdbarch)), (32 * riscv_isa_xlen (gdbarch)),
       &riscv_linux_gregset, NULL, cb_data);
-  /* The kernel is adding 8 bytes for FCSR.  */
-  cb (".reg2", (32 * riscv_isa_flen (gdbarch)) + 8,
-      (32 * riscv_isa_flen (gdbarch)) + 8,
+  cb (".reg2", riscv_linux_fregset_size (riscv_isa_flen (gdbarch)),
+      riscv_linux_fregset_size (riscv_isa_flen (gdbarch)),
       &riscv_linux_fregset, NULL, cb_data);
 }
 
@@ -523,6 +533,52 @@ riscv_linux_get_syscall_number (struct gdbarch *gdbarch, thread_info *thread)
   return ret;
 }
 
+/* Return the FLEN implied by SIZE, the size of an NT_FPREGSET note, or 0
+   if SIZE matches no known layout.  This inverts
+   riscv_linux_fregset_size.  */
+
+static int
+riscv_linux_flen_from_fpregset_size (bfd_size_type size)
+{
+  for (int flen : { riscv_flen_d, riscv_flen_f })
+    if (size == riscv_linux_fregset_size (flen))
+      return flen;
+
+  return 0;
+}
+
+/* Implement the "core_read_description" gdbarch method.
+
+   A core dumped by the Linux kernel has no float ABI in its e_flags, so
+   if ABFD has an NT_FPREGSET note (the ".reg2" pseudo-section), recover
+   the FLEN from its size.  A core with an NT_GDB_TDESC note never gets
+   here; the core target uses that note directly.  */
+
+static const struct target_desc *
+riscv_linux_core_read_description (struct gdbarch *gdbarch,
+				   struct target_ops *target, bfd *abfd)
+{
+  auto features = riscv_features_from_bfd (abfd);
+
+  asection *fpregs = bfd_get_section_by_name (abfd, ".reg2");
+  if (features.flen == 0 && fpregs != nullptr)
+    {
+      bfd_size_type size = bfd_section_size (fpregs);
+      features.flen = riscv_linux_flen_from_fpregset_size (size);
+      if (features.flen == 0)
+	warning (_("unrecognized .reg2 note size %s in core file; "
+		   "FLEN left unknown"),
+		 pulongest (size));
+    }
+
+  /* Nothing was learnt beyond the ELF header.  Let GDB fall back to its
+     default description, which also takes the executable into account.  */
+  if (features.flen == 0)
+    return nullptr;
+
+  return riscv_lookup_target_description (features);
+}
+
 /* Initialize RISC-V Linux ABI info.  */
 
 static void
@@ -555,6 +611,9 @@ riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
   set_gdbarch_iterate_over_regset_sections
     (gdbarch, riscv_linux_iterate_over_regset_sections);
 
+  set_gdbarch_core_read_description (gdbarch,
+				     riscv_linux_core_read_description);
+
   tramp_frame_prepend_unwinder (gdbarch, &riscv_linux_sigframe);
 
   tdep->syscall_next_pc = riscv_linux_syscall_next_pc;
@@ -567,10 +626,38 @@ riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
   set_gdbarch_get_syscall_number (gdbarch, riscv_linux_get_syscall_number);
 }
 
+#if GDB_SELF_TEST
+namespace selftests
+{
+
+/* Check that an NT_FPREGSET note size maps to the right FLEN.  */
+
+static void
+riscv_linux_flen_from_fpregset_size_test ()
+{
+  for (int flen : { riscv_flen_d, riscv_flen_f })
+    SELF_CHECK (riscv_linux_flen_from_fpregset_size
+		  (riscv_linux_fregset_size (flen)) == flen);
+
+  /* Anything else leaves the FLEN unknown.  */
+  SELF_CHECK (riscv_linux_flen_from_fpregset_size (0) == 0);
+  SELF_CHECK (riscv_linux_flen_from_fpregset_size (32 * 8) == 0);
+  SELF_CHECK (riscv_linux_flen_from_fpregset_size (32 * 16 + 8) == 0);
+}
+
+} /* namespace selftests */
+#endif /* GDB_SELF_TEST */
+
 /* Initialize RISC-V Linux target support.  */
 
 INIT_GDB_FILE (riscv_linux_tdep)
 {
   gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_LINUX,
 			  riscv_linux_init_abi);
+
+#if GDB_SELF_TEST
+  selftests::register_test
+    ("riscv-linux-flen-from-fpregset-size",
+     selftests::riscv_linux_flen_from_fpregset_size_test);
+#endif
 }
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 68c56fbafb3..0a997231abc 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -3923,10 +3923,9 @@ static const struct frame_unwind_legacy riscv_frame_unwind (
   /*.prev_arch     =*/ NULL
 );
 
-/* Extract a set of required target features out of ABFD.  If ABFD is
-   nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state.  */
+/* See riscv-tdep.h.  */
 
-static struct riscv_gdbarch_features
+struct riscv_gdbarch_features
 riscv_features_from_bfd (const bfd *abfd)
 {
   struct riscv_gdbarch_features features;
@@ -3950,9 +3949,9 @@ riscv_features_from_bfd (const bfd *abfd)
 	internal_error (_("unknown ELF header class %d"), eclass);
 
       if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
-	features.flen = 8;
+	features.flen = riscv_flen_d;
       else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
-	features.flen = 4;
+	features.flen = riscv_flen_f;
 
       if (e_flags & EF_RISCV_RVE)
 	{
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 344a995a680..01cb515dfbd 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -158,6 +158,16 @@ extern int riscv_abi_flen (struct gdbarch *gdbarch);
    argument registers.  */
 extern bool riscv_abi_embedded (struct gdbarch *gdbarch);
 
+/* FP register width, in bytes, implied by the D and F extensions.  */
+constexpr int riscv_flen_d = 8;
+constexpr int riscv_flen_f = 4;
+
+/* Extract a set of required target features out of ABFD.  If ABFD is
+   nullptr then a RISCV_GDBARCH_FEATURES is returned in its default
+   state.  */
+extern struct riscv_gdbarch_features riscv_features_from_bfd
+  (const bfd *abfd);
+
 /* Single step based on where the current instruction will take us.  */
 extern std::vector<CORE_ADDR> riscv_software_single_step
   (struct regcache *regcache);
diff --git a/gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2 b/gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2
new file mode 100644
index 0000000000000000000000000000000000000000..497db069ac76a81e74b7ba676b3ddf3e3a64a014
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diff --git a/gdb/testsuite/gdb.arch/riscv-core-fpregset.exp b/gdb/testsuite/gdb.arch/riscv-core-fpregset.exp
new file mode 100644
index 00000000000..57e63756f77
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-core-fpregset.exp
@@ -0,0 +1,73 @@
+# Copyright 2026 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Check that GDB recovers the FP registers from a core file dumped by
+# the Linux kernel and opened without the executable.  Such a core has
+# no NT_GDB_TDESC note, no .riscv.attributes, and zero e_flags, so the
+# size of the NT_FPREGSET note is the only evidence of the FLEN.  The
+# kernel dumps the FP state in the D layout: 32 doubles plus 8 bytes for
+# fcsr, 264 bytes in total.
+#
+# The bundled core (riscv-core-fpregset.core.bz2) was dumped by a stock
+# Linux 6.8 kernel.  Its PT_NOTE carries NT_FPREGSET (264 bytes) but
+# neither NT_GDB_TDESC nor any RISC-V attributes, and its e_flags are
+# zero.  The dumped program never touched the FP unit, so every FP
+# register in the note is zero.
+#
+# The test checks that, with no executable loaded:
+# 1. the FP registers exist in the target description at all, rather
+#    than GDB reporting "Invalid register 'fa0'";
+# 2. their contents are supplied from the note rather than left
+#    <unavailable> ("(raw 0x...)" in the output proves that);
+# 3. the FP registers are 8 bytes wide, i.e. the FLEN really came from
+#    the 264-byte note size.
+#
+# Only the D layout is exercised here, since that is what the bundled
+# core carries.  The size-to-FLEN mapping itself, including the F
+# layout, is covered by the "riscv-linux-flen-from-fpregset-size" selftest.
+#
+# How to regenerate the fixture: run any RV64 program on a Linux system
+# under "ulimit -c unlimited" with kernel.core_pattern=core, make it
+# dump core, and bzip2 the result.  Check with "readelf -n" that the
+# core carries a 264-byte NT_FPREGSET and neither an NT_GDB_TDESC note
+# nor RISC-V attributes.
+
+# The fixture is an ELF64 Linux core and the FLEN assertions are
+# RV64-specific.
+require {istarget "riscv64-*-linux*"}
+
+set core [decompress_bz2 $srcdir/$subdir/riscv-core-fpregset.core.bz2]
+if {$core == ""} {
+    untested "failed to decompress core file"
+    return -1
+}
+set core [gdb_remote_download host $core]
+
+clean_restart
+
+if {[gdb_core_cmd $core "load core without executable"] != 1} {
+    return -1
+}
+
+# The size of the NT_FPREGSET note implies FLEN, hence the FP registers.
+# The value must come from the note: a raw hex dump in the output means
+# the register bytes were supplied, not left <unavailable>.
+gdb_test "info registers \$fa0" \
+    "fa0\[ \t\]+\\{float = 0, double = 0\\}\[ \t\]+\\(raw 0x0+\\)" \
+    "fp register value supplied from fpregset note"
+
+# 264 bytes = 32 doubles + fcsr, so the FLEN must be 8.
+gdb_test "print sizeof (\$fa0)" "= 8" \
+    "flen recovered from fpregset note size"
-- 
2.43.0

[PATCH v2 2/4] gdb/riscv: recover core file ISA features from AT_HWCAP

[Farid Khaidari]

When a core has neither a float ABI in e_flags nor an NT_FPREGSET
note, the RISC-V Linux core_read_description hook now reads AT_HWCAP
from the core's auxv and takes FLEN from the F and D bits.

The V bit is ignored.  AT_HWCAP gives no vector length, and a guessed
vlen would give the vector registers the wrong size.

The test core is a real Linux core dump with NT_FPREGSET removed, so
AT_HWCAP (0x20112d, rv64imafdcv) is the only source of FP information.
Its V bit also lets the test check that GDB adds no vector registers.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 gdb/riscv-linux-tdep.c                        |  72 +++++++++++++++++-
 .../gdb.arch/riscv-core-hwcap.core.bz2        | Bin 0 -> 3229 bytes
 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp   |  67 ++++++++++++++++
 3 files changed, 137 insertions(+), 2 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp

diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c
index 594f6a36f89..707852e8f54 100644
--- a/gdb/riscv-linux-tdep.c
+++ b/gdb/riscv-linux-tdep.c
@@ -31,6 +31,7 @@
 #include "linux-record.h"
 #include "riscv-linux-tdep.h"
 #include "inferior.h"
+#include "auxv.h"
 #include "gdbsupport/selftest.h"
 
 extern unsigned int record_debug;
@@ -547,12 +548,43 @@ riscv_linux_flen_from_fpregset_size (bfd_size_type size)
   return 0;
 }
 
+/* The AT_HWCAP bit for a single-letter ISA extension (COMPAT_HWCAP_ISA_*
+   in arch/riscv/include/asm/hwcap.h).  */
+
+static constexpr ULONGEST
+riscv_hwcap_isa (char ext)
+{
+  gdb_assert (ext >= 'a' && ext <= 'z');
+  return ULONGEST{ 1 } << (ext - 'a');
+}
+
+/* Refine FEATURES with the F and D bits of the AT_HWCAP mask HWCAP,
+   which imply the FLEN.  Only fields still at their unknown value (0)
+   are filled in, so a width already recovered from the core wins.
+
+   The V bit is deliberately ignored: AT_HWCAP carries no vector
+   length, and a target description with a guessed vlen would
+   misrepresent the vector registers.  */
+
+static void
+riscv_apply_hwcap (struct riscv_gdbarch_features &features, ULONGEST hwcap)
+{
+  if (features.flen != 0)
+    return;
+
+  if ((hwcap & riscv_hwcap_isa ('d')) != 0)
+    features.flen = riscv_flen_d;
+  else if ((hwcap & riscv_hwcap_isa ('f')) != 0)
+    features.flen = riscv_flen_f;
+}
+
 /* Implement the "core_read_description" gdbarch method.
 
    A core dumped by the Linux kernel has no float ABI in its e_flags, so
    if ABFD has an NT_FPREGSET note (the ".reg2" pseudo-section), recover
-   the FLEN from its size.  A core with an NT_GDB_TDESC note never gets
-   here; the core target uses that note directly.  */
+   the FLEN from its size; failing that, from AT_HWCAP in the core's
+   auxv.  A core with an NT_GDB_TDESC note never gets here; the core
+   target uses that note directly.  */
 
 static const struct target_desc *
 riscv_linux_core_read_description (struct gdbarch *gdbarch,
@@ -571,6 +603,9 @@ riscv_linux_core_read_description (struct gdbarch *gdbarch,
 		 pulongest (size));
     }
 
+  auto auxv = target_read_auxv_raw (target);
+  riscv_apply_hwcap (features, linux_get_hwcap (auxv, target, gdbarch));
+
   /* Nothing was learnt beyond the ELF header.  Let GDB fall back to its
      default description, which also takes the executable into account.  */
   if (features.flen == 0)
@@ -645,6 +680,37 @@ riscv_linux_flen_from_fpregset_size_test ()
   SELF_CHECK (riscv_linux_flen_from_fpregset_size (32 * 16 + 8) == 0);
 }
 
+/* Check that AT_HWCAP bits refine the ISA features as expected.  */
+
+static void
+riscv_apply_hwcap_test ()
+{
+  const ULONGEST hwcap_f = riscv_hwcap_isa ('f');
+  const ULONGEST hwcap_d = riscv_hwcap_isa ('d');
+  const ULONGEST hwcap_v = riscv_hwcap_isa ('v');
+
+  /* Return features with FLEN set, refined by HWCAP.  */
+  auto apply = [] (ULONGEST hwcap, int flen = 0)
+    {
+      riscv_gdbarch_features features;
+      features.flen = flen;
+      riscv_apply_hwcap (features, hwcap);
+      return features;
+    };
+
+  /* 'd' implies double precision, 'f' single, and 'd' wins.  */
+  SELF_CHECK (apply (hwcap_d).flen == riscv_flen_d);
+  SELF_CHECK (apply (hwcap_f).flen == riscv_flen_f);
+  SELF_CHECK (apply (hwcap_d | hwcap_f).flen == riscv_flen_d);
+  SELF_CHECK (apply (0).flen == 0);
+
+  /* An FLEN already recovered from the core is not overwritten.  */
+  SELF_CHECK (apply (hwcap_d, riscv_flen_f).flen == riscv_flen_f);
+
+  /* The 'v' bit is ignored: AT_HWCAP carries no vector length.  */
+  SELF_CHECK (apply (hwcap_v).vlen == 0);
+}
+
 } /* namespace selftests */
 #endif /* GDB_SELF_TEST */
 
@@ -659,5 +725,7 @@ INIT_GDB_FILE (riscv_linux_tdep)
   selftests::register_test
     ("riscv-linux-flen-from-fpregset-size",
      selftests::riscv_linux_flen_from_fpregset_size_test);
+  selftests::register_test ("riscv-apply-hwcap",
+			    selftests::riscv_apply_hwcap_test);
 #endif
 }
diff --git a/gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2 b/gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
new file mode 100644
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z%0maP)MUlCX1Lar?MbWrsptf)e!1qcKql4)k2BLi8zYWUg_QB;alUTekw`9~y)02z
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zdSqAzF8Zxpwgxau4l2?Rj}jbJuGg-LA9j?A43p67dSZx^t*wNa3yNE>i}ZlYCj}8<
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zg;NdUBzAaV2$u&K?3@QIQO61cDI*yHl@mRx<?Rr)+nT7wa(NL^Yk{YZzH;Y#!)*%S
z^D@f=t!pm{b{5<NO+z7gH3|yJ_KjI&91K&)DBX)^E!KjE7yiTJVdf5SQukc(K@Fgr
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z2lLw<{0fIrnLxpUVl@ELM*Dc_RYan!J+M73-bEOXXiWjeCNXBxr&Ymf@C7`7+!*cT
zca7AXtpM%$^yus}vlC_>$Sh-S>~nAIhx(F&H?&CpV2pTLM%*jY<(~oSRoh9g%c0G<
z56O235*%O0MvC;W?=hd{1x#NH{e(=uhC7-G*}>#%d>~utC;ZuPIGe|hRK!FxaV8Iz
z&qH%HPGr+o{aRAA7~TOyh*d{(z+Ty~@h_%}g@udz+Oq@t6Szd*Sjcg|pVHlZI)~Ma
z(n~0SdS5{krifvws1O~MIX2stBcSW}KhNU2aW%)`@MA>YuKH#V{J@rKXcUo-lp!wn
zHvRJQDy2EQ9hXnH_b>FLCKnU1f|=(t5(Ng@IJqKWVW7_hsZ#T3^Y*qsEes$h?w~-i
zebl)gb+Mq)ZicP(;A~QMotQca#d|7Eb~uMLT@M%s)4B4YSzbLN0D%EXfhfu1{u1vM
zc|oDpY17r?mIo(khf;sxWx$mkm>1byl#=XP$t@7UkSWHisM8coIoZ`ymn{(Gb2%_G
P@BCfK6yZWb9KvM$m8QOX

literal 0
HcmV?d00001

diff --git a/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp b/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
new file mode 100644
index 00000000000..3655cb047a0
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
@@ -0,0 +1,67 @@
+# Copyright 2026 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Check that GDB recovers the ISA features of a core file from the
+# AT_HWCAP entry of the NT_AUXV note: the kernel publishes the
+# single-letter ISA extensions of the machine there, so a core it dumps
+# opened without the executable still reveals the F and D extensions.
+#
+# The bundled core (riscv-core-hwcap.core.bz2) is a real Linux core
+# (e_flags = 0, no NT_GDB_TDESC, no RISC-V attributes) whose
+# NT_FPREGSET note has been stripped, leaving AT_HWCAP = 0x20112d
+# (rv64acdfimv) as the only evidence of the FP extension.  The F-only
+# mapping and the precedence rules are covered by the
+# "riscv-apply-hwcap" selftest.
+#
+# How to regenerate the fixture: take the riscv-core-fpregset.core.bz2
+# core and remove the NT_FPREGSET note from PT_NOTE: rewrite the
+# note blob without the CORE/type-2 entry, zero-pad the segment to keep
+# file offsets stable, shrink p_filesz of the PT_NOTE program
+# header accordingly, and bzip2 the result.
+
+# The fixture is an ELF64 Linux core and the FLEN assertions are
+# RV64-specific.
+require {istarget "riscv64-*-linux*"}
+
+set core [decompress_bz2 $srcdir/$subdir/riscv-core-hwcap.core.bz2]
+if {$core == ""} {
+    untested "failed to decompress core file"
+    return -1
+}
+set core [gdb_remote_download host $core]
+
+clean_restart
+
+# Before the core is loaded there is no target, so nothing to prove
+# that the FP and vector registers below really come from the core.
+gdb_test "info registers \$fa0" "The program has no registers now\\." \
+    "no registers before the core is loaded"
+
+if {[gdb_core_cmd $core "load core without executable"] != 1} {
+    return -1
+}
+
+# The D bit of AT_HWCAP gives us the FP registers.
+gdb_test "info registers \$fa0" "fa0\[ \t\]+.*" \
+    "fp registers recovered from hwcap"
+
+# ... and implies FLEN = 8.
+gdb_test "print sizeof (\$fa0)" "= 8" \
+    "flen recovered from hwcap"
+
+# The V bit of AT_HWCAP is deliberately ignored: it carries no vector
+# length, so no vector registers are invented.
+gdb_test "info registers \$v0" "Invalid register .v0." \
+    "no vector registers invented from hwcap"
-- 
2.43.0

[PATCH v2 3/4] gdb/riscv: test the "arch=" disassembler option

[Farid Khaidari]

The test puts vector instructions into an executable built for rv64gc.
They disassemble as raw .insn words until "arch=" names an ISA with V.
The check is repeated on a copy with the architecture attribute
stripped.

One "disassemble" command uses a single disassembler for the whole
function, so the expected output covers more than the first
instruction: an option lost after it would show there.  Mapping
symbols are left to objdump tests, since GDB cannot exercise them.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 .../gdb.arch/riscv-disasm-arch-option.c       | 40 ++++++++++
 .../gdb.arch/riscv-disasm-arch-option.exp     | 80 +++++++++++++++++++
 2 files changed, 120 insertions(+)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp

diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
new file mode 100644
index 00000000000..75857442b7e
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
@@ -0,0 +1,40 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+   Copyright 2026 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* Plant the encodings of two vector instructions in an ordinary
+   function.  The file is compiled without the vector extension, so the
+   ELF carries an rv64gc architecture attribute and the instructions
+   only decode once the disassembler is told about the vector extension
+   through the "arch=" option.  ".insn" is used rather than the
+   mnemonics because assembling those would require the vector
+   extension, which would then appear in the architecture attribute of
+   the ELF and leave the option with nothing to prove.  */
+
+void
+vector_insns (void)
+{
+  /* vsetvli t0,a0,e8,m1,ta,ma */
+  asm volatile (".insn 4, 0x0c0572d7");
+  /* vxor.vv v1,v2,v3 */
+  asm volatile (".insn 4, 0x2e2180d7");
+}
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
new file mode 100644
index 00000000000..2dd7a998eeb
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
@@ -0,0 +1,80 @@
+# Copyright 2026 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Check the "arch=" disassembler option against an executable.  The
+# option names the ISA to disassemble for, in place of the one the
+# object records, so the test needs an object both with and without an
+# architecture attribute.
+#
+# A single "disassemble" prints the whole function through one
+# disassembler, so an ISA that survived only the first instruction would
+# show up from the second on: the expected output names both.
+
+require {istarget "riscv64-*-*"}
+
+standard_testfile
+
+# Compile without the vector extension: the executable carries an rv64gc
+# architecture attribute, and the vector instructions planted in it only
+# decode once the disassembler is told about the vector extension.
+set compile_flags {debug}
+lappend compile_flags "additional_flags=-march=rv64gc"
+
+if {[prepare_for_testing "failed to prepare" $testfile $srcfile \
+	 $compile_flags]} {
+    return -1
+}
+
+# The planted words decoded as vector instructions, and left raw.
+set vector_re "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*"
+set raw_re "\\.insn\[ \t\]+4, 0x0c0572d7.*"
+
+gdb_test "disassemble vector_insns" $raw_re \
+    "vector instructions not decoded with the ISA of the object"
+
+gdb_test_no_output "set disassembler-options arch=rv64gcv" \
+    "set the arch to one with vector"
+
+gdb_test "disassemble vector_insns" $vector_re \
+    "arch= overrides the ISA of the object"
+
+# Clearing the option returns to the ISA of the object.
+gdb_test_no_output "set disassembler-options" "clear disassembler options"
+
+gdb_test "disassemble vector_insns" $raw_re \
+    "vector instructions not decoded after clearing the option"
+
+# An object that records no ISA is the case GDB supplies the option for
+# on its own.  Strip the attribute to get one that still has a symbol
+# table, which a core file cannot stand in for.
+set stripped ${testfile}-no-attributes
+set objcopy [gdb_find_objcopy]
+
+if {[run_on_host "strip the architecture attribute" $objcopy \
+	 "--remove-section=.riscv.attributes $binfile \
+	      [standard_output_file $stripped]"]} {
+    return -1
+}
+
+clean_restart $stripped
+
+gdb_test "info symbol vector_insns" "vector_insns in section .*" \
+    "the stripped binary still carries a symbol table"
+
+gdb_test_no_output "set disassembler-options arch=rv64gcv" \
+    "set the arch on an object without an attribute"
+
+gdb_test "disassemble vector_insns" $vector_re \
+    "vector instructions decoded with arch=rv64gcv"
-- 
2.43.0

[PATCH v2 4/4] gdb/riscv: disassemble an attribute-less object by the description ISA

[Farid Khaidari]

An object without a RISC-V architecture attribute is disassembled as
rv64gc, whatever the target description says.  A core file is such an
object, so its vector instructions print as raw .insn words even when
the description has vector registers.

For such objects, pass the ISA implied by the target description to
the disassembler as "arch=".  An object that records its own ISA keeps
using it.  The test checks both cases: with a vector description
loaded, an rv64gc executable must not decode the planted words as
vector instructions, and the same executable with the attribute
stripped must.

The option is set in print_insn, not through
gdbarch_disassembler_options_implicit as mips-tdep.c does.  A gdbarch
is shared by all objects with matching features, and only print_insn
knows which object it is disassembling.

User options are appended to the string for every instruction.
libopcodes clears disassembler_options after parsing and resets any
option missing from a later string, so they would be lost from the
second instruction on.  The string is local to print_insn, and the
previous disassembler_options value is restored after the call, so no
pointer to it outlives print_insn.

The test loads the vector description from a file.  In practice such a
description comes from a core, but a core only matches the executable
that produced it.  Only RV64 is tested; the RV32 ISA string was checked
by reading the code.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 gdb/riscv-tdep.c                              |  69 ++++++++++
 .../riscv-disasm-arch-option-vector.xml       | 123 ++++++++++++++++++
 .../gdb.arch/riscv-disasm-arch-option.exp     |  41 +++++-
 3 files changed, 232 insertions(+), 1 deletion(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml

diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 0a997231abc..606bd371676 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -39,6 +39,7 @@
 #include "elf-bfd.h"
 #include "symcat.h"
 #include "dis-asm.h"
+#include "disasm.h"
 #include "frame-unwind.h"
 #include "frame-base.h"
 #include "trad-frame.h"
@@ -56,6 +57,7 @@
 #include "arch/riscv.h"
 #include "record-full.h"
 #include "riscv-ravenscar-thread.h"
+#include "gdbsupport/scope-exit.h"
 
 #include <vector>
 
@@ -4151,6 +4153,45 @@ riscv_gnu_triplet_regexp (struct gdbarch *gdbarch)
   return "riscv(32|64)?";
 }
 
+/* Return true if the object owning the section being disassembled
+   records a RISC-V ISA string attribute.  */
+
+static bool
+riscv_disasm_bfd_has_isa_attribute (struct disassemble_info *info)
+{
+  if (info->section == nullptr)
+    return false;
+
+  auto *abfd = info->section->owner;
+  if (abfd == nullptr || bfd_get_flavour (abfd) != bfd_target_elf_flavour)
+    return false;
+
+  return elf_known_obj_attributes_proc (abfd)[Tag_RISCV_arch].s != nullptr;
+}
+
+/* X register width, in bytes, implied by the RV32 base integer ISA.  */
+constexpr int riscv_xlen_32 = 4;
+
+/* Build an ISA string for the "arch=" disassembler option from
+   FEATURES, the target description of the architecture.  The option
+   replaces the rv64gc default of libopcodes, so the extension set is
+   that same default, widened by V once the target description sizes
+   the vector registers.  Naming the extensions the description does
+   know about instead would decode less than the default it replaces:
+   an ISA without G implies neither Zicsr nor Zifencei, which would
+   drop "csrr" and "fence.i" from a target that merely describes no FP
+   registers.  An RV32E target gets rv32gc for the same reason: E only
+   removes registers, so rv32gc decodes every RV32E instruction.  */
+
+static std::string
+riscv_isa_for_disassembler (const struct riscv_gdbarch_features &features)
+{
+  std::string isa = features.xlen == riscv_xlen_32 ? "rv32gc" : "rv64gc";
+  if (features.vlen > 0)
+    isa += "v";
+  return isa;
+}
+
 /* Implement the "print_insn" gdbarch method.  */
 
 static int
@@ -4162,6 +4203,34 @@ riscv_print_insn (bfd_vma addr, struct disassemble_info *info)
   if (s != nullptr)
     info->section = s->the_bfd_section;
 
+  /* An object that records its own ISA is disassembled according to
+     that ISA.  One that does not, such as a core file loaded without an
+     executable, is disassembled according to the target description;
+     libopcodes would otherwise fall back to plain rv64gc.
+
+     The option is supplied for each instruction, since the object can
+     change between them.  Each parse resets the options it does not
+     see, so the user ones are appended, last so that they win.  INFO
+     points at the local string only for this call.  */
+  auto *di = static_cast<gdb_disassemble_info *> (info->application_data);
+  if (di == nullptr || riscv_disasm_bfd_has_isa_attribute (info))
+    return default_print_insn (addr, info);
+
+  gdbarch *arch = di->arch ();
+  riscv_gdbarch_tdep *tdep = gdbarch_tdep<riscv_gdbarch_tdep> (arch);
+  std::string options
+    = "arch=" + riscv_isa_for_disassembler (tdep->isa_features);
+
+  const char *user_options = get_disassembler_options (arch);
+  if (user_options != nullptr && *user_options != '\0')
+    {
+      options += ',';
+      options += user_options;
+    }
+
+  const char *saved_options = info->disassembler_options;
+  info->disassembler_options = options.c_str ();
+  SCOPE_EXIT { info->disassembler_options = saved_options; };
   return default_print_insn (addr, info);
 }
 
diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml
new file mode 100644
index 00000000000..7f514803d51
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml
@@ -0,0 +1,123 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2026 Free Software Foundation, Inc.
+
+     Copying and distribution of this file, with or without modification,
+     are permitted in any medium without royalty provided the copyright
+     notice and this notice are preserved.  -->
+
+<!DOCTYPE target SYSTEM "gdb-target.dtd">
+<target>
+  <architecture>riscv</architecture>
+  <feature name="org.gnu.gdb.riscv.cpu">
+    <reg name="zero" bitsize="64" type="int"/>
+    <reg name="ra" bitsize="64" type="code_ptr"/>
+    <reg name="sp" bitsize="64" type="data_ptr"/>
+    <reg name="gp" bitsize="64" type="data_ptr"/>
+    <reg name="tp" bitsize="64" type="data_ptr"/>
+    <reg name="t0" bitsize="64" type="int"/>
+    <reg name="t1" bitsize="64" type="int"/>
+    <reg name="t2" bitsize="64" type="int"/>
+    <reg name="fp" bitsize="64" type="data_ptr"/>
+    <reg name="s1" bitsize="64" type="int"/>
+    <reg name="a0" bitsize="64" type="int"/>
+    <reg name="a1" bitsize="64" type="int"/>
+    <reg name="a2" bitsize="64" type="int"/>
+    <reg name="a3" bitsize="64" type="int"/>
+    <reg name="a4" bitsize="64" type="int"/>
+    <reg name="a5" bitsize="64" type="int"/>
+    <reg name="a6" bitsize="64" type="int"/>
+    <reg name="a7" bitsize="64" type="int"/>
+    <reg name="s2" bitsize="64" type="int"/>
+    <reg name="s3" bitsize="64" type="int"/>
+    <reg name="s4" bitsize="64" type="int"/>
+    <reg name="s5" bitsize="64" type="int"/>
+    <reg name="s6" bitsize="64" type="int"/>
+    <reg name="s7" bitsize="64" type="int"/>
+    <reg name="s8" bitsize="64" type="int"/>
+    <reg name="s9" bitsize="64" type="int"/>
+    <reg name="s10" bitsize="64" type="int"/>
+    <reg name="s11" bitsize="64" type="int"/>
+    <reg name="t3" bitsize="64" type="int"/>
+    <reg name="t4" bitsize="64" type="int"/>
+    <reg name="t5" bitsize="64" type="int"/>
+    <reg name="t6" bitsize="64" type="int"/>
+    <reg name="pc" bitsize="64" type="code_ptr"/>
+  </feature>
+  <feature name="org.gnu.gdb.riscv.fpu">
+
+    <union id="riscv_double">
+      <field name="float" type="ieee_single"/>
+      <field name="double" type="ieee_double"/>
+    </union>
+
+    <reg name="ft0" bitsize="64" type="riscv_double" regnum="33"/>
+    <reg name="ft1" bitsize="64" type="riscv_double"/>
+    <reg name="ft2" bitsize="64" type="riscv_double"/>
+    <reg name="ft3" bitsize="64" type="riscv_double"/>
+    <reg name="ft4" bitsize="64" type="riscv_double"/>
+    <reg name="ft5" bitsize="64" type="riscv_double"/>
+    <reg name="ft6" bitsize="64" type="riscv_double"/>
+    <reg name="ft7" bitsize="64" type="riscv_double"/>
+    <reg name="fs0" bitsize="64" type="riscv_double"/>
+    <reg name="fs1" bitsize="64" type="riscv_double"/>
+    <reg name="fa0" bitsize="64" type="riscv_double"/>
+    <reg name="fa1" bitsize="64" type="riscv_double"/>
+    <reg name="fa2" bitsize="64" type="riscv_double"/>
+    <reg name="fa3" bitsize="64" type="riscv_double"/>
+    <reg name="fa4" bitsize="64" type="riscv_double"/>
+    <reg name="fa5" bitsize="64" type="riscv_double"/>
+    <reg name="fa6" bitsize="64" type="riscv_double"/>
+    <reg name="fa7" bitsize="64" type="riscv_double"/>
+    <reg name="fs2" bitsize="64" type="riscv_double"/>
+    <reg name="fs3" bitsize="64" type="riscv_double"/>
+    <reg name="fs4" bitsize="64" type="riscv_double"/>
+    <reg name="fs5" bitsize="64" type="riscv_double"/>
+    <reg name="fs6" bitsize="64" type="riscv_double"/>
+    <reg name="fs7" bitsize="64" type="riscv_double"/>
+    <reg name="fs8" bitsize="64" type="riscv_double"/>
+    <reg name="fs9" bitsize="64" type="riscv_double"/>
+    <reg name="fs10" bitsize="64" type="riscv_double"/>
+    <reg name="fs11" bitsize="64" type="riscv_double"/>
+    <reg name="ft8" bitsize="64" type="riscv_double"/>
+    <reg name="ft9" bitsize="64" type="riscv_double"/>
+    <reg name="ft10" bitsize="64" type="riscv_double"/>
+    <reg name="ft11" bitsize="64" type="riscv_double"/>
+
+    <reg name="fcsr" bitsize="32" type="int" regnum="68"/>
+  </feature>
+  <feature name="org.gnu.gdb.riscv.vector">
+    <vector id="bytes16" type="uint8" count="16"/>
+    <reg name="v0" bitsize="128" type="bytes16"/>
+    <reg name="v1" bitsize="128" type="bytes16"/>
+    <reg name="v2" bitsize="128" type="bytes16"/>
+    <reg name="v3" bitsize="128" type="bytes16"/>
+    <reg name="v4" bitsize="128" type="bytes16"/>
+    <reg name="v5" bitsize="128" type="bytes16"/>
+    <reg name="v6" bitsize="128" type="bytes16"/>
+    <reg name="v7" bitsize="128" type="bytes16"/>
+    <reg name="v8" bitsize="128" type="bytes16"/>
+    <reg name="v9" bitsize="128" type="bytes16"/>
+    <reg name="v10" bitsize="128" type="bytes16"/>
+    <reg name="v11" bitsize="128" type="bytes16"/>
+    <reg name="v12" bitsize="128" type="bytes16"/>
+    <reg name="v13" bitsize="128" type="bytes16"/>
+    <reg name="v14" bitsize="128" type="bytes16"/>
+    <reg name="v15" bitsize="128" type="bytes16"/>
+    <reg name="v16" bitsize="128" type="bytes16"/>
+    <reg name="v17" bitsize="128" type="bytes16"/>
+    <reg name="v18" bitsize="128" type="bytes16"/>
+    <reg name="v19" bitsize="128" type="bytes16"/>
+    <reg name="v20" bitsize="128" type="bytes16"/>
+    <reg name="v21" bitsize="128" type="bytes16"/>
+    <reg name="v22" bitsize="128" type="bytes16"/>
+    <reg name="v23" bitsize="128" type="bytes16"/>
+    <reg name="v24" bitsize="128" type="bytes16"/>
+    <reg name="v25" bitsize="128" type="bytes16"/>
+    <reg name="v26" bitsize="128" type="bytes16"/>
+    <reg name="v27" bitsize="128" type="bytes16"/>
+    <reg name="v28" bitsize="128" type="bytes16"/>
+    <reg name="v29" bitsize="128" type="bytes16"/>
+    <reg name="v30" bitsize="128" type="bytes16"/>
+    <reg name="v31" bitsize="128" type="bytes16"/>
+  </feature>
+</target>
diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
index 2dd7a998eeb..2c7a85bf70c 100644
--- a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
+++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
@@ -16,7 +16,8 @@
 # Check the "arch=" disassembler option against an executable.  The
 # option names the ISA to disassemble for, in place of the one the
 # object records, so the test needs an object both with and without an
-# architecture attribute.
+# architecture attribute.  GDB supplies the option itself for the object
+# that records nothing, which the test checks as well.
 #
 # A single "disassemble" prints the whole function through one
 # disassembler, so an ISA that survived only the first instruction would
@@ -78,3 +79,41 @@ gdb_test_no_output "set disassembler-options arch=rv64gcv" \
 
 gdb_test "disassemble vector_insns" $vector_re \
     "vector instructions decoded with arch=rv64gcv"
+
+# For an object that records no ISA, GDB names one on its own, out of the
+# target description.  In practice a description that sizes the vector
+# registers is the one recovered from a core file, but a core only pairs
+# with the executable it was dumped from, and the instructions of this
+# one would be nowhere in the memory such a core dumped.  A description
+# loaded from a file sizes the registers the same way and pairs with any
+# executable.
+set tdesc_file "${srcdir}/${subdir}/${testfile}-vector.xml"
+
+if {[is_remote host]} {
+    set tdesc_file [remote_download host $tdesc_file]
+}
+
+# Restarting drops the option set above: what decodes the instructions
+# here is the ISA GDB supplies itself.
+clean_restart $stripped
+
+gdb_test_no_output "set tdesc filename $tdesc_file" \
+    "load a description with vector registers, object without an attribute"
+
+gdb_test "disassemble vector_insns" $vector_re \
+    "the description ISA reaches the disassembler on its own"
+
+# The same description against the executable that does record rv64gc:
+# the attribute has to keep winning, so the planted encodings stay raw
+# words.  Were the description supplied here anyway, they would decode as
+# vector instructions.
+clean_restart $testfile
+
+gdb_test_no_output "set tdesc filename $tdesc_file" \
+    "load a description with vector registers"
+
+gdb_test "print sizeof (\$v0)" " = 16" \
+    "the description sizes the vector registers"
+
+gdb_test "disassemble vector_insns" $raw_re \
+    "the attribute of the object outranks the description ISA"
-- 
2.43.0

Re: [PATCH 1/4] gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files

[Farid Khaidari]

Hi Kevin,

On 10/25/26 23:07, Kevin Buettner wrote:
> I don't think that riscv-tdep.c is the correct place to add knowledge
> about linux specific features.  It seems to me that much of what you've
> done here ought to be placed in gdb/riscv-linux-tdep.c.

Thanks for the review.  It is Linux-specific: FreeBSD lays out
NT_FPREGSET in 16-byte slots, so its size says nothing about FLEN
there.  v2 moves the code to riscv-linux-tdep.c as a
core_read_description hook.

Farid

Re: [PATCH 4/4] gdb/riscv: disassemble an attribute-less object by the description ISA

[Farid Khaidari]

Hi Kevin,

On 10/25/26 23:50, Kevin Buettner wrote:
> Relying on that libopcodes behaviour seems fragile:
> if print_insn_riscv ever stops clearing the field, or returns early
> before doing so, the next instruction will see a dangling pointer.

Agreed.  v2 saves disassembler_options and restores it with
SCOPE_EXIT, so no pointer to the local string outlives the call.

Farid

Re: [PATCH v2 0/4] gdb/riscv: analyse a core file without the executable

[Farid Khaidari]

The opcodes "arch=" disassembler option that patches 3/4 and 4/4 depend
on is now in master as commit 6f52aa942cb.  The series applies cleanly
on top of current master.