[PATCH 3/4] gdb/riscv: test the "arch=" disassembler option

[Farid Khaidari <khaidari.fg@gmail.com>]

The test puts vector instructions into an executable built for rv64gc.
They disassemble as raw .insn words until "arch=" names an ISA with V.
The check is repeated on a copy with the architecture attribute
stripped.

One "disassemble" command uses a single disassembler for the whole
function, so the expected output covers more than the first
instruction: an option lost after it would show there.  Mapping
symbols are left to objdump tests, since GDB cannot exercise them.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 .../gdb.arch/riscv-disasm-arch-option.c       | 40 +++++++++
 .../gdb.arch/riscv-disasm-arch-option.exp     | 84 +++++++++++++++++++
 2 files changed, 124 insertions(+)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp

diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
new file mode 100644
index 00000000000..75857442b7e
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
@@ -0,0 +1,40 @@
+/* This testcase is part of GDB, the GNU debugger.
+
+   Copyright 2026 Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
+
+/* Plant the encodings of two vector instructions in an ordinary
+   function.  The file is compiled without the vector extension, so the
+   ELF carries an rv64gc architecture attribute and the instructions
+   only decode once the disassembler is told about the vector extension
+   through the "arch=" option.  ".insn" is used rather than the
+   mnemonics because assembling those would require the vector
+   extension, which would then appear in the architecture attribute of
+   the ELF and leave the option with nothing to prove.  */
+
+void
+vector_insns (void)
+{
+  /* vsetvli t0,a0,e8,m1,ta,ma */
+  asm volatile (".insn 4, 0x0c0572d7");
+  /* vxor.vv v1,v2,v3 */
+  asm volatile (".insn 4, 0x2e2180d7");
+}
+
+int
+main (void)
+{
+  return 0;
+}
diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
new file mode 100644
index 00000000000..1e6698b2e5d
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp
@@ -0,0 +1,84 @@
+# Copyright 2026 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Check the "arch=" disassembler option against an executable.  The
+# option names the ISA to disassemble for, in place of the one the
+# object records, so the test needs an object both with and without an
+# architecture attribute.
+#
+# A single "disassemble" prints the whole function through one
+# disassembler, so an ISA that survived only the first instruction would
+# show up from the second on: the expected output names both.
+
+require {istarget "riscv64-*-*"}
+
+standard_testfile
+
+# Compile without the vector extension: the executable carries an rv64gc
+# architecture attribute, and the vector instructions planted in it only
+# decode once the disassembler is told about the vector extension.
+set compile_flags {debug}
+lappend compile_flags "additional_flags=-march=rv64gc"
+
+if {[prepare_for_testing "failed to prepare" $testfile $srcfile $compile_flags]} {
+    return -1
+}
+
+gdb_test "disassemble vector_insns" "\\.insn\[ \t\]+4, 0x0c0572d7.*" \
+    "vector instructions not decoded with the ISA of the object"
+
+gdb_test_no_output "set disassembler-options arch=rv64gcv" \
+    "set the arch to one with vector"
+
+gdb_test "disassemble vector_insns" \
+    "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*" \
+    "arch= overrides the ISA of the object"
+
+# Each "disassemble" builds its own disassembler, so this repetition
+# only checks that the option is still in effect for the next command,
+# not that it survived within one.
+gdb_test "disassemble vector_insns" \
+    "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*" \
+    "arch=rv64gcv still in effect for the next command"
+
+# Clearing the option returns to the ISA of the object.
+gdb_test_no_output "set disassembler-options" "clear disassembler options"
+
+gdb_test "disassemble vector_insns" "\\.insn\[ \t\]+4, 0x0c0572d7.*" \
+    "vector instructions not decoded after clearing the option"
+
+# An object that records no ISA is the case GDB supplies the option for
+# on its own.  Strip the attribute to get one that still has a symbol
+# table, which a core file cannot stand in for.
+set stripped ${testfile}-no-attributes
+set objcopy [gdb_find_objcopy]
+
+if {[run_on_host "strip the architecture attribute" $objcopy \
+	 "--remove-section=.riscv.attributes $binfile \
+	      [standard_output_file $stripped]"]} {
+    return -1
+}
+
+clean_restart $stripped
+
+gdb_test "info symbol vector_insns" "vector_insns in section .*" \
+    "the stripped binary still carries a symbol table"
+
+gdb_test_no_output "set disassembler-options arch=rv64gcv" \
+    "set the arch on an object without an attribute"
+
+gdb_test "disassemble vector_insns" \
+    "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*" \
+    "vector instructions decoded with arch=rv64gcv"
-- 
2.43.0