[PATCH v2 0/4] gdb/riscv: analyse a core file without the executable

[Farid Khaidari <khaidari.fg@gmail.com>]

A RISC-V core opened without its executable gets an integer-only
target description and is disassembled as plain rv64gc.  This series
takes FLEN from the size of the NT_FPREGSET note and the single-letter
extensions from AT_HWCAP, and passes the resulting ISA to the
disassembler when the object names none.  Vector state is left out:
GDB cannot build a vector target description yet.

Patches 3 and 4 need "[PATCH v2] RISC-V: add an "arch=" disassembler
option" on binutils@sourceware.org.

Changes in v2:

- The core file code moves to riscv-linux-tdep.c as a
  core_read_description hook (patches 1 and 2).
- riscv_print_insn restores disassembler_options after each
  instruction (patch 4).
- The test core files were regenerated on a stock Linux 6.8 kernel.

Tested on x86_64-linux with a riscv64-linux-gnu target: 22 passes, no
failures, and each patch builds and passes its tests on its own.

Farid Khaidari (4):
  gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files
  gdb/riscv: recover core file ISA features from AT_HWCAP
  gdb/riscv: test the "arch=" disassembler option
  gdb/riscv: disassemble an attribute-less object by the description ISA

 gdb/riscv-linux-tdep.c                        | 161 +++++++++++++++++-
 gdb/riscv-tdep.c                              |  78 ++++++++-
 gdb/riscv-tdep.h                              |  10 ++
 .../gdb.arch/riscv-core-fpregset.core.bz2     | Bin 0 -> 3204 bytes
 .../gdb.arch/riscv-core-fpregset.exp          |  73 ++++++++
 .../gdb.arch/riscv-core-hwcap.core.bz2        | Bin 0 -> 3229 bytes
 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp   |  67 ++++++++
 .../riscv-disasm-arch-option-vector.xml       | 123 +++++++++++++
 .../gdb.arch/riscv-disasm-arch-option.c       |  40 +++++
 .../gdb.arch/riscv-disasm-arch-option.exp     | 119 +++++++++++++
 10 files changed, 663 insertions(+), 8 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
 create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp

-- 
2.43.0