Re: [PATCH 0/4] gdb/riscv: analyse a core file without the executable

[Kevin Buettner <kevinb@redhat.com>]

On 10/22/26 8:44 AM, Farid Khaidari wrote:
> A RISC-V core opened without its executable gets an integer-only
> target description, because the core does not say how wide the FP
> registers are.  Any object with no ISA attribute, a core included, is
> also disassembled as plain rv64gc.
> 
> This series reads what the core does record.  The size of the
> NT_FPREGSET note gives FLEN, and AT_HWCAP gives the single-letter
> extensions.  The last patch passes the ISA of the resulting target
> description to the disassembler when the object names none.
> 
> Patches 3 and 4 need the "arch=" disassembler option, sent to
> binutils@sourceware.org as "RISC-V: add an "arch=" disassembler
> option".
> 
> Vector state from the NT_RISCV_VECTOR note is left out.  GDB can read
> the org.gnu.gdb.riscv.vector feature from a target description but
> cannot build one, so a vlen read from the core has nowhere to go yet.
> The disassembler test loads a vector description from a file instead.
> 
> Tested on x86_64-linux with a riscv64-linux-gnu target: the three new
> tests give 23 passes and no failures.  The host cannot run RISC-V
> binaries, so I did not run the rest of the testsuite.
> 
> Farid Khaidari (4):
>   gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files
>   gdb/riscv: recover core file ISA features from AT_HWCAP
>   gdb/riscv: test the "arch=" disassembler option
>   gdb/riscv: disassemble an attribute-less object by the description ISA
> 
>  gdb/riscv-linux-tdep.c                        | 120 +++++++++++++
>  gdb/riscv-tdep.c                              | 167 +++++++++++++++++-
>  gdb/riscv-tdep.h                              |  14 ++
>  .../gdb.arch/riscv-core-fpregset.core.bz2     | Bin 0 -> 15134 bytes
>  .../gdb.arch/riscv-core-fpregset.exp          |  78 ++++++++
>  .../gdb.arch/riscv-core-hwcap.core.bz2        | Bin 0 -> 15122 bytes
>  gdb/testsuite/gdb.arch/riscv-core-hwcap.exp   |  72 ++++++++
>  .../riscv-disasm-arch-option-vector.xml       | 123 +++++++++++++
>  .../gdb.arch/riscv-disasm-arch-option.c       |  40 +++++
>  .../gdb.arch/riscv-disasm-arch-option.exp     | 124 +++++++++++++
>  10 files changed, 732 insertions(+), 6 deletions(-)
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.exp
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c
>  create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp

I ran this series, including the companion changes sent to the binutils
list, through an AI code review which included testing on a RISC-V Linux
machine.  No regressions were found; this series does what it claims.

I am replying to concerns found regarding individual patches.

Kevin