[PATCH 2/4] gdb/riscv: recover core file ISA features from AT_HWCAP

[Farid Khaidari <khaidari.fg@gmail.com>]

Add a core_read_description hook for RISC-V Linux.  It reads AT_HWCAP
from the core's auxv and takes FLEN from the F and D bits, on top of
what riscv_features_from_bfd finds (the function is now exported).  A
core with an NT_GDB_TDESC note still uses that note.

The V bit is ignored.  AT_HWCAP gives no vector length, and a guessed
vlenb would give the vector registers the wrong size.

The test core is a real kernel dump with NT_FPREGSET removed, so
AT_HWCAP (0x20112d, rv64imafdcv) is the only source of FP information.
Its V bit also lets the test check that GDB adds no vector registers.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 gdb/riscv-linux-tdep.c                        | 120 ++++++++++++++++++
 gdb/riscv-tdep.c                              |   8 +-
 gdb/riscv-tdep.h                              |   9 ++
 .../gdb.arch/riscv-core-hwcap.core.bz2        | Bin 0 -> 15122 bytes
 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp   |  72 +++++++++++
 5 files changed, 203 insertions(+), 6 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp

diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c
index fcfa5f98ea4..d7cf6fcfd53 100644
--- a/gdb/riscv-linux-tdep.c
+++ b/gdb/riscv-linux-tdep.c
@@ -31,6 +31,8 @@
 #include "linux-record.h"
 #include "riscv-linux-tdep.h"
 #include "inferior.h"
+#include "auxv.h"
+#include "gdbsupport/selftest.h"
 
 extern unsigned int record_debug;
 
@@ -523,6 +525,57 @@ riscv_linux_get_syscall_number (struct gdbarch *gdbarch, thread_info *thread)
   return ret;
 }
 
+/* The AT_HWCAP bit for a single-letter ISA extension (COMPAT_HWCAP_ISA_*
+   in arch/riscv/include/asm/hwcap.h).  */
+
+static constexpr ULONGEST
+riscv_hwcap_isa (char ext)
+{
+  gdb_assert (ext >= 'a' && ext <= 'z');
+  return ULONGEST{ 1 } << (ext - 'a');
+}
+
+/* Refine FEATURES with the F and D bits of the AT_HWCAP mask HWCAP,
+   which imply the FLEN.  Only fields still at their unknown value (0)
+   are filled in, so a width already recovered from the core wins.
+
+   The V bit is deliberately ignored: AT_HWCAP carries no vector
+   length, and a target description with a guessed vlen would
+   misrepresent the vector registers.  The vector state is recovered
+   from the NT_RISCV_VECTOR note instead.  */
+
+static void
+riscv_apply_hwcap (struct riscv_gdbarch_features &features, ULONGEST hwcap)
+{
+  if (features.flen == 0)
+    {
+      if ((hwcap & riscv_hwcap_isa ('d')) != 0)
+	features.flen = riscv_flen_d;
+      else if ((hwcap & riscv_hwcap_isa ('f')) != 0)
+	features.flen = riscv_flen_f;
+    }
+}
+
+/* Implement the "core_read_description" gdbarch method.
+
+   Sources in decreasing order of precedence: an NT_GDB_TDESC note is
+   used by the core target directly and this hook is never consulted;
+   then the ELF header and the notes via riscv_features_from_bfd;
+   finally AT_HWCAP, which only fills in what is still unknown.  */
+
+static const struct target_desc *
+riscv_linux_core_read_description (struct gdbarch *gdbarch,
+				   struct target_ops *target, bfd *abfd)
+{
+  auto features = riscv_features_from_bfd (abfd);
+
+  auto auxv = target_read_auxv_raw (target);
+  auto hwcap = linux_get_hwcap (auxv, target, gdbarch);
+  riscv_apply_hwcap (features, hwcap);
+
+  return riscv_lookup_target_description (features);
+}
+
 /* Initialize RISC-V Linux ABI info.  */
 
 static void
@@ -555,6 +608,9 @@ riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
   set_gdbarch_iterate_over_regset_sections
     (gdbarch, riscv_linux_iterate_over_regset_sections);
 
+  set_gdbarch_core_read_description (gdbarch,
+				     riscv_linux_core_read_description);
+
   tramp_frame_prepend_unwinder (gdbarch, &riscv_linux_sigframe);
 
   tdep->syscall_next_pc = riscv_linux_syscall_next_pc;
@@ -567,10 +623,74 @@ riscv_linux_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
   set_gdbarch_get_syscall_number (gdbarch, riscv_linux_get_syscall_number);
 }
 
+#if GDB_SELF_TEST
+namespace selftests
+{
+
+/* Check that AT_HWCAP bits refine the ISA features as expected.  */
+
+static void
+riscv_apply_hwcap_test ()
+{
+  const ULONGEST hwcap_f = riscv_hwcap_isa ('f');
+  const ULONGEST hwcap_d = riscv_hwcap_isa ('d');
+  const ULONGEST hwcap_v = riscv_hwcap_isa ('v');
+
+  /* The 'd' bit implies double precision, 'f' single precision.  */
+  {
+    riscv_gdbarch_features features;
+    riscv_apply_hwcap (features, hwcap_d);
+    SELF_CHECK (features.flen == riscv_flen_d);
+  }
+  {
+    riscv_gdbarch_features features;
+    riscv_apply_hwcap (features, hwcap_f);
+    SELF_CHECK (features.flen == riscv_flen_f);
+  }
+
+  /* 'd' wins over 'f' when both are set.  */
+  {
+    riscv_gdbarch_features features;
+    riscv_apply_hwcap (features, hwcap_d | hwcap_f);
+    SELF_CHECK (features.flen == riscv_flen_d);
+  }
+
+  /* An flen already recovered from the core is not overwritten.  */
+  {
+    riscv_gdbarch_features features;
+    features.flen = riscv_flen_f;
+    riscv_apply_hwcap (features, hwcap_d);
+    SELF_CHECK (features.flen == riscv_flen_f);
+  }
+
+  /* The 'v' bit is ignored: AT_HWCAP carries no vector length.  */
+  {
+    riscv_gdbarch_features features;
+    riscv_apply_hwcap (features, hwcap_v);
+    SELF_CHECK (features.vlen == 0);
+  }
+
+  /* No relevant bits leaves the features untouched.  */
+  {
+    riscv_gdbarch_features features;
+    riscv_apply_hwcap (features, 0);
+    SELF_CHECK (features.flen == 0);
+    SELF_CHECK (features.vlen == 0);
+  }
+}
+
+} /* namespace selftests */
+#endif /* GDB_SELF_TEST */
+
 /* Initialize RISC-V Linux target support.  */
 
 INIT_GDB_FILE (riscv_linux_tdep)
 {
   gdbarch_register_osabi (bfd_arch_riscv, 0, GDB_OSABI_LINUX,
 			  riscv_linux_init_abi);
+
+#if GDB_SELF_TEST
+  selftests::register_test ("riscv-apply-hwcap",
+			    selftests::riscv_apply_hwcap_test);
+#endif
 }
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 1af4be77091..1801b042de3 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -3924,9 +3924,6 @@ static const struct frame_unwind_legacy riscv_frame_unwind (
   /*.prev_arch     =*/ NULL
 );
 
-/* FP register width, in bytes, implied by the D and F extensions.  */
-static constexpr int riscv_flen_d = 8;
-static constexpr int riscv_flen_f = 4;
 
 /* Return the FLEN implied by SIZE, the size of an NT_FPREGSET note, or 0
    if SIZE matches no known layout.  The note holds 32 FP registers of
@@ -3971,10 +3968,9 @@ riscv_flen_from_core_fpregset (bfd *abfd)
   return flen;
 }
 
-/* Extract a set of required target features out of ABFD.  If ABFD is
-   nullptr then a RISCV_GDBARCH_FEATURES is returned in its default state.  */
+/* See riscv-tdep.h.  */
 
-static struct riscv_gdbarch_features
+struct riscv_gdbarch_features
 riscv_features_from_bfd (bfd *abfd)
 {
   struct riscv_gdbarch_features features;
diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h
index 344a995a680..5fe91b7287c 100644
--- a/gdb/riscv-tdep.h
+++ b/gdb/riscv-tdep.h
@@ -158,6 +158,15 @@ extern int riscv_abi_flen (struct gdbarch *gdbarch);
    argument registers.  */
 extern bool riscv_abi_embedded (struct gdbarch *gdbarch);
 
+/* FP register width, in bytes, implied by the D and F extensions.  */
+constexpr int riscv_flen_d = 8;
+constexpr int riscv_flen_f = 4;
+
+/* Extract a set of required target features out of ABFD.  If ABFD is
+   nullptr then a RISCV_GDBARCH_FEATURES is returned in its default
+   state.  */
+extern struct riscv_gdbarch_features riscv_features_from_bfd (bfd *abfd);
+
 /* Single step based on where the current instruction will take us.  */
 extern std::vector<CORE_ADDR> riscv_software_single_step
   (struct regcache *regcache);
diff --git a/gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2 b/gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
new file mode 100644
index 0000000000000000000000000000000000000000..c557362d69cf483e16c370c0ecd3fe974b882e69
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diff --git a/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp b/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
new file mode 100644
index 00000000000..84f09c04b3a
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
@@ -0,0 +1,72 @@
+# Copyright 2026 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Check that GDB recovers the ISA features of a core file from the
+# AT_HWCAP entry of the NT_AUXV note: the kernel publishes the
+# single-letter ISA extensions of the machine there, so a kernel core
+# opened without the executable still reveals the F and D extensions.
+#
+# The bundled core (riscv-core-hwcap.core.bz2) is a real kernel core
+# (e_flags = 0, no NT_GDB_TDESC, no RISC-V attributes) whose
+# NT_FPREGSET note has been stripped, leaving AT_HWCAP = 0x20112d
+# (rv64acdfimv) as the only evidence of the FP extension.  The F-only
+# mapping and the precedence rules are covered by the
+# "riscv-apply-hwcap" selftest.
+#
+# How to regenerate the fixture: take the riscv-core-fpregset.core.bz2
+# kernel core and remove the NT_FPREGSET note from PT_NOTE: rewrite the
+# note blob without the CORE/type-2 entry, zero-pad the segment to keep
+# file offsets stable, shrink p_filesz/p_memsz of the PT_NOTE program
+# header accordingly, and bzip2 the result.
+
+# The fixture is an ELF64 core and the FLEN assertions are
+# RV64-specific.
+require {istarget "riscv64-*-*"}
+
+if {![istarget *-*-linux*]} {
+    unsupported "linux only"
+    return -1
+}
+
+set core [decompress_bz2 $srcdir/$subdir/riscv-core-hwcap.core.bz2]
+if {$core == ""} {
+    untested "failed to decompress core file"
+    return -1
+}
+set core [gdb_remote_download host $core]
+
+clean_restart
+
+# Before the core is loaded there is no target, so nothing to prove
+# that the FP and vector registers below really come from the core.
+gdb_test "info registers \$fa0" "The program has no registers now\\." \
+    "no registers before the core is loaded"
+
+if {![gdb_core_cmd $core "load kernel core without executable"]} {
+    return -1
+}
+
+# The D bit of AT_HWCAP gives us the FP registers.
+gdb_test "info registers \$fa0" "fa0\[ \t\]+.*" \
+    "fp registers recovered from hwcap"
+
+# ... and implies FLEN = 8.
+gdb_test "print sizeof (\$fa0)" "= 8" \
+    "flen recovered from hwcap"
+
+# The V bit of AT_HWCAP is deliberately ignored: it carries no vector
+# length, so no vector registers are invented.
+gdb_test "info registers \$v0" "Invalid register .v0." \
+    "no vector registers invented from hwcap"
-- 
2.43.0