[PATCH v2 2/4] gdb/riscv: recover core file ISA features from AT_HWCAP

[Farid Khaidari <khaidari.fg@gmail.com>]

When a core has neither a float ABI in e_flags nor an NT_FPREGSET
note, the RISC-V Linux core_read_description hook now reads AT_HWCAP
from the core's auxv and takes FLEN from the F and D bits.

The V bit is ignored.  AT_HWCAP gives no vector length, and a guessed
vlen would give the vector registers the wrong size.

The test core is a real Linux core dump with NT_FPREGSET removed, so
AT_HWCAP (0x20112d, rv64imafdcv) is the only source of FP information.
Its V bit also lets the test check that GDB adds no vector registers.

Signed-off-by: Farid Khaidari <khaidari.fg@gmail.com>
---
 gdb/riscv-linux-tdep.c                        |  72 +++++++++++++++++-
 .../gdb.arch/riscv-core-hwcap.core.bz2        | Bin 0 -> 3229 bytes
 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp   |  67 ++++++++++++++++
 3 files changed, 137 insertions(+), 2 deletions(-)
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp

diff --git a/gdb/riscv-linux-tdep.c b/gdb/riscv-linux-tdep.c
index 594f6a36f89..707852e8f54 100644
--- a/gdb/riscv-linux-tdep.c
+++ b/gdb/riscv-linux-tdep.c
@@ -31,6 +31,7 @@
 #include "linux-record.h"
 #include "riscv-linux-tdep.h"
 #include "inferior.h"
+#include "auxv.h"
 #include "gdbsupport/selftest.h"
 
 extern unsigned int record_debug;
@@ -547,12 +548,43 @@ riscv_linux_flen_from_fpregset_size (bfd_size_type size)
   return 0;
 }
 
+/* The AT_HWCAP bit for a single-letter ISA extension (COMPAT_HWCAP_ISA_*
+   in arch/riscv/include/asm/hwcap.h).  */
+
+static constexpr ULONGEST
+riscv_hwcap_isa (char ext)
+{
+  gdb_assert (ext >= 'a' && ext <= 'z');
+  return ULONGEST{ 1 } << (ext - 'a');
+}
+
+/* Refine FEATURES with the F and D bits of the AT_HWCAP mask HWCAP,
+   which imply the FLEN.  Only fields still at their unknown value (0)
+   are filled in, so a width already recovered from the core wins.
+
+   The V bit is deliberately ignored: AT_HWCAP carries no vector
+   length, and a target description with a guessed vlen would
+   misrepresent the vector registers.  */
+
+static void
+riscv_apply_hwcap (struct riscv_gdbarch_features &features, ULONGEST hwcap)
+{
+  if (features.flen != 0)
+    return;
+
+  if ((hwcap & riscv_hwcap_isa ('d')) != 0)
+    features.flen = riscv_flen_d;
+  else if ((hwcap & riscv_hwcap_isa ('f')) != 0)
+    features.flen = riscv_flen_f;
+}
+
 /* Implement the "core_read_description" gdbarch method.
 
    A core dumped by the Linux kernel has no float ABI in its e_flags, so
    if ABFD has an NT_FPREGSET note (the ".reg2" pseudo-section), recover
-   the FLEN from its size.  A core with an NT_GDB_TDESC note never gets
-   here; the core target uses that note directly.  */
+   the FLEN from its size; failing that, from AT_HWCAP in the core's
+   auxv.  A core with an NT_GDB_TDESC note never gets here; the core
+   target uses that note directly.  */
 
 static const struct target_desc *
 riscv_linux_core_read_description (struct gdbarch *gdbarch,
@@ -571,6 +603,9 @@ riscv_linux_core_read_description (struct gdbarch *gdbarch,
 		 pulongest (size));
     }
 
+  auto auxv = target_read_auxv_raw (target);
+  riscv_apply_hwcap (features, linux_get_hwcap (auxv, target, gdbarch));
+
   /* Nothing was learnt beyond the ELF header.  Let GDB fall back to its
      default description, which also takes the executable into account.  */
   if (features.flen == 0)
@@ -645,6 +680,37 @@ riscv_linux_flen_from_fpregset_size_test ()
   SELF_CHECK (riscv_linux_flen_from_fpregset_size (32 * 16 + 8) == 0);
 }
 
+/* Check that AT_HWCAP bits refine the ISA features as expected.  */
+
+static void
+riscv_apply_hwcap_test ()
+{
+  const ULONGEST hwcap_f = riscv_hwcap_isa ('f');
+  const ULONGEST hwcap_d = riscv_hwcap_isa ('d');
+  const ULONGEST hwcap_v = riscv_hwcap_isa ('v');
+
+  /* Return features with FLEN set, refined by HWCAP.  */
+  auto apply = [] (ULONGEST hwcap, int flen = 0)
+    {
+      riscv_gdbarch_features features;
+      features.flen = flen;
+      riscv_apply_hwcap (features, hwcap);
+      return features;
+    };
+
+  /* 'd' implies double precision, 'f' single, and 'd' wins.  */
+  SELF_CHECK (apply (hwcap_d).flen == riscv_flen_d);
+  SELF_CHECK (apply (hwcap_f).flen == riscv_flen_f);
+  SELF_CHECK (apply (hwcap_d | hwcap_f).flen == riscv_flen_d);
+  SELF_CHECK (apply (0).flen == 0);
+
+  /* An FLEN already recovered from the core is not overwritten.  */
+  SELF_CHECK (apply (hwcap_d, riscv_flen_f).flen == riscv_flen_f);
+
+  /* The 'v' bit is ignored: AT_HWCAP carries no vector length.  */
+  SELF_CHECK (apply (hwcap_v).vlen == 0);
+}
+
 } /* namespace selftests */
 #endif /* GDB_SELF_TEST */
 
@@ -659,5 +725,7 @@ INIT_GDB_FILE (riscv_linux_tdep)
   selftests::register_test
     ("riscv-linux-flen-from-fpregset-size",
      selftests::riscv_linux_flen_from_fpregset_size_test);
+  selftests::register_test ("riscv-apply-hwcap",
+			    selftests::riscv_apply_hwcap_test);
 #endif
 }
diff --git a/gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2 b/gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2
new file mode 100644
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diff --git a/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp b/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
new file mode 100644
index 00000000000..3655cb047a0
--- /dev/null
+++ b/gdb/testsuite/gdb.arch/riscv-core-hwcap.exp
@@ -0,0 +1,67 @@
+# Copyright 2026 Free Software Foundation, Inc.
+
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+# Check that GDB recovers the ISA features of a core file from the
+# AT_HWCAP entry of the NT_AUXV note: the kernel publishes the
+# single-letter ISA extensions of the machine there, so a core it dumps
+# opened without the executable still reveals the F and D extensions.
+#
+# The bundled core (riscv-core-hwcap.core.bz2) is a real Linux core
+# (e_flags = 0, no NT_GDB_TDESC, no RISC-V attributes) whose
+# NT_FPREGSET note has been stripped, leaving AT_HWCAP = 0x20112d
+# (rv64acdfimv) as the only evidence of the FP extension.  The F-only
+# mapping and the precedence rules are covered by the
+# "riscv-apply-hwcap" selftest.
+#
+# How to regenerate the fixture: take the riscv-core-fpregset.core.bz2
+# core and remove the NT_FPREGSET note from PT_NOTE: rewrite the
+# note blob without the CORE/type-2 entry, zero-pad the segment to keep
+# file offsets stable, shrink p_filesz of the PT_NOTE program
+# header accordingly, and bzip2 the result.
+
+# The fixture is an ELF64 Linux core and the FLEN assertions are
+# RV64-specific.
+require {istarget "riscv64-*-linux*"}
+
+set core [decompress_bz2 $srcdir/$subdir/riscv-core-hwcap.core.bz2]
+if {$core == ""} {
+    untested "failed to decompress core file"
+    return -1
+}
+set core [gdb_remote_download host $core]
+
+clean_restart
+
+# Before the core is loaded there is no target, so nothing to prove
+# that the FP and vector registers below really come from the core.
+gdb_test "info registers \$fa0" "The program has no registers now\\." \
+    "no registers before the core is loaded"
+
+if {[gdb_core_cmd $core "load core without executable"] != 1} {
+    return -1
+}
+
+# The D bit of AT_HWCAP gives us the FP registers.
+gdb_test "info registers \$fa0" "fa0\[ \t\]+.*" \
+    "fp registers recovered from hwcap"
+
+# ... and implies FLEN = 8.
+gdb_test "print sizeof (\$fa0)" "= 8" \
+    "flen recovered from hwcap"
+
+# The V bit of AT_HWCAP is deliberately ignored: it carries no vector
+# length, so no vector registers are invented.
+gdb_test "info registers \$v0" "Invalid register .v0." \
+    "no vector registers invented from hwcap"
-- 
2.43.0