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Sun, 25 Oct 2026 20:17:33 +0000 (UTC) Received: from [100.90.172.125] (headnet04.pony-001.prod.iad2.dc.redhat.com [10.2.32.116]) by mx-prod-int-05.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 99EE11956089; Sun, 25 Oct 2026 20:17:32 +0000 (UTC) Message-ID: <976a7887-b486-47ab-9dec-0e0d53256917@redhat.com> Date: Sun, 25 Oct 2026 13:17:30 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/4] gdb/riscv: analyse a core file without the executable To: Farid Khaidari , gdb-patches@sourceware.org References: <20261022154417.235510-1-khaidari.fg@gmail.com> From: Kevin Buettner In-Reply-To: <20261022154417.235510-1-khaidari.fg@gmail.com> X-Scanned-By: MIMEDefang 3.0 on 10.30.177.17 X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: 6E0iqzemEDl49vM7FzGLamtOu0yObgaksNqNDbtrZ1E_1792959454 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org On 10/22/26 8:44 AM, Farid Khaidari wrote: > A RISC-V core opened without its executable gets an integer-only > target description, because the core does not say how wide the FP > registers are. Any object with no ISA attribute, a core included, is > also disassembled as plain rv64gc. > > This series reads what the core does record. The size of the > NT_FPREGSET note gives FLEN, and AT_HWCAP gives the single-letter > extensions. The last patch passes the ISA of the resulting target > description to the disassembler when the object names none. > > Patches 3 and 4 need the "arch=" disassembler option, sent to > binutils@sourceware.org as "RISC-V: add an "arch=" disassembler > option". > > Vector state from the NT_RISCV_VECTOR note is left out. GDB can read > the org.gnu.gdb.riscv.vector feature from a target description but > cannot build one, so a vlen read from the core has nowhere to go yet. > The disassembler test loads a vector description from a file instead. > > Tested on x86_64-linux with a riscv64-linux-gnu target: the three new > tests give 23 passes and no failures. The host cannot run RISC-V > binaries, so I did not run the rest of the testsuite. > > Farid Khaidari (4): > gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files > gdb/riscv: recover core file ISA features from AT_HWCAP > gdb/riscv: test the "arch=" disassembler option > gdb/riscv: disassemble an attribute-less object by the description ISA > > gdb/riscv-linux-tdep.c | 120 +++++++++++++ > gdb/riscv-tdep.c | 167 +++++++++++++++++- > gdb/riscv-tdep.h | 14 ++ > .../gdb.arch/riscv-core-fpregset.core.bz2 | Bin 0 -> 15134 bytes > .../gdb.arch/riscv-core-fpregset.exp | 78 ++++++++ > .../gdb.arch/riscv-core-hwcap.core.bz2 | Bin 0 -> 15122 bytes > gdb/testsuite/gdb.arch/riscv-core-hwcap.exp | 72 ++++++++ > .../riscv-disasm-arch-option-vector.xml | 123 +++++++++++++ > .../gdb.arch/riscv-disasm-arch-option.c | 40 +++++ > .../gdb.arch/riscv-disasm-arch-option.exp | 124 +++++++++++++ > 10 files changed, 732 insertions(+), 6 deletions(-) > create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2 > create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.exp > create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2 > create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp > create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml > create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c > create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp I ran this series, including the companion changes sent to the binutils list, through an AI code review which included testing on a RISC-V Linux machine. No regressions were found; this series does what it claims. I am replying to concerns found regarding individual patches. Kevin