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Mon, 26 Oct 2026 02:57:04 -0700 (PDT) Received: from localhost.localdomain ([178.64.143.40]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3eb8f387sm15080682f8f.4.2026.10.26.02.57.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 02:57:04 -0700 (PDT) From: Farid Khaidari To: gdb-patches@sourceware.org Cc: Andrew Burgess , Palmer Dabbelt , Timur Golubovich , Kevin Buettner Subject: [PATCH v2 0/4] gdb/riscv: analyse a core file without the executable Date: Mon, 26 Oct 2026 12:56:42 +0300 Message-ID: <20261026095647.3035166-1-khaidari.fg@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261022154417.235510-1-khaidari.fg@gmail.com> References: <20261022154417.235510-1-khaidari.fg@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org A RISC-V core opened without its executable gets an integer-only target description and is disassembled as plain rv64gc. This series takes FLEN from the size of the NT_FPREGSET note and the single-letter extensions from AT_HWCAP, and passes the resulting ISA to the disassembler when the object names none. Vector state is left out: GDB cannot build a vector target description yet. Patches 3 and 4 need "[PATCH v2] RISC-V: add an "arch=" disassembler option" on binutils@sourceware.org. Changes in v2: - The core file code moves to riscv-linux-tdep.c as a core_read_description hook (patches 1 and 2). - riscv_print_insn restores disassembler_options after each instruction (patch 4). - The test core files were regenerated on a stock Linux 6.8 kernel. Tested on x86_64-linux with a riscv64-linux-gnu target: 22 passes, no failures, and each patch builds and passes its tests on its own. Farid Khaidari (4): gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files gdb/riscv: recover core file ISA features from AT_HWCAP gdb/riscv: test the "arch=" disassembler option gdb/riscv: disassemble an attribute-less object by the description ISA gdb/riscv-linux-tdep.c | 161 +++++++++++++++++- gdb/riscv-tdep.c | 78 ++++++++- gdb/riscv-tdep.h | 10 ++ .../gdb.arch/riscv-core-fpregset.core.bz2 | Bin 0 -> 3204 bytes .../gdb.arch/riscv-core-fpregset.exp | 73 ++++++++ .../gdb.arch/riscv-core-hwcap.core.bz2 | Bin 0 -> 3229 bytes gdb/testsuite/gdb.arch/riscv-core-hwcap.exp | 67 ++++++++ .../riscv-disasm-arch-option-vector.xml | 123 +++++++++++++ .../gdb.arch/riscv-disasm-arch-option.c | 40 +++++ .../gdb.arch/riscv-disasm-arch-option.exp | 119 +++++++++++++ 10 files changed, 663 insertions(+), 8 deletions(-) create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.exp create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp -- 2.43.0