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Thu, 22 Oct 2026 08:44:28 -0700 (PDT) Received: from localhost.localdomain ([176.15.140.8]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5bfa11f60d9sm1205912e87.17.2026.10.22.08.44.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2026 08:44:28 -0700 (PDT) From: Farid Khaidari To: gdb-patches@sourceware.org Cc: Farid Khaidari , Andrew Burgess , Palmer Dabbelt , Timur Golubovich Subject: [PATCH 4/4] gdb/riscv: disassemble an attribute-less object by the description ISA Date: Thu, 22 Oct 2026 18:44:17 +0300 Message-ID: <20261022154417.235510-5-khaidari.fg@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261022154417.235510-1-khaidari.fg@gmail.com> References: <20261022154417.235510-1-khaidari.fg@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org An object without a RISC-V architecture attribute is disassembled as rv64gc, whatever the target description says. A core file is such an object, so its vector instructions print as raw .insn words even when the description has vector registers. For such objects, pass the ISA implied by the target description to the disassembler as "arch=". An object that records its own ISA keeps using it. The test checks both cases: with a vector description loaded, an rv64gc executable must not decode the planted words as vector instructions, and the same executable with the attribute stripped must. The option is set in print_insn, not through gdbarch_disassembler_options_implicit as mips-tdep.c does. A gdbarch is shared by all objects with matching features, and only print_insn knows which object it is disassembling. User options are appended to the string for every instruction. libopcodes clears disassembler_options after parsing and resets any option missing from a later string, so they would be lost from the second instruction on. The test loads the vector description from a file. In practice such a description comes from a core, but a core only matches the executable that produced it. Only RV64 is tested; the RV32 ISA string was checked by reading the code. Signed-off-by: Farid Khaidari --- gdb/riscv-tdep.c | 76 +++++++++++ gdb/riscv-tdep.h | 5 + .../riscv-disasm-arch-option-vector.xml | 123 ++++++++++++++++++ .../gdb.arch/riscv-disasm-arch-option.exp | 42 +++++- 4 files changed, 245 insertions(+), 1 deletion(-) create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 1801b042de3..a1132b86b43 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -39,6 +39,7 @@ #include "elf-bfd.h" #include "symcat.h" #include "dis-asm.h" +#include "disasm.h" #include "frame-unwind.h" #include "frame-base.h" #include "trad-frame.h" @@ -4201,6 +4202,44 @@ riscv_gnu_triplet_regexp (struct gdbarch *gdbarch) return "riscv(32|64)?"; } +/* Return true if the object owning the section being disassembled + records a RISC-V ISA string attribute. */ + +static bool +riscv_disasm_bfd_has_isa_attribute (struct disassemble_info *info) +{ + if (info->section == nullptr) + return false; + + auto *abfd = info->section->owner; + if (abfd == nullptr || bfd_get_flavour (abfd) != bfd_target_elf_flavour) + return false; + + return elf_known_obj_attributes_proc (abfd)[Tag_RISCV_arch].s != nullptr; +} + +/* X register width, in bytes, implied by the RV32 base integer ISA. */ +constexpr int riscv_xlen_32 = 4; + +/* Build an ISA string for the "arch=" disassembler option from + FEATURES, the target description of the architecture. The option + replaces the rv64gc default of libopcodes, so the extension set is + that same default, widened by V once the target description sizes + the vector registers. Naming the extensions the description does + know about instead would decode less than the default it replaces: + an ISA without G implies neither Zicsr nor Zifencei, which would + drop "csrr" and "fence.i" from a target that merely describes no FP + registers. */ + +static std::string +riscv_isa_for_disassembler (const struct riscv_gdbarch_features &features) +{ + std::string isa = features.xlen == riscv_xlen_32 ? "rv32gc" : "rv64gc"; + if (features.vlen > 0) + isa += "v"; + return isa; +} + /* Implement the "print_insn" gdbarch method. */ static int @@ -4212,6 +4251,37 @@ riscv_print_insn (bfd_vma addr, struct disassemble_info *info) if (s != nullptr) info->section = s->the_bfd_section; + /* An object that records its own ISA is disassembled according to + that ISA. One that does not, such as a core file loaded without an + executable, is disassembled according to the target description; + libopcodes would otherwise fall back to plain rv64gc. ARCH_OPTION + must outlive the default_print_insn call below, which parses it. + + The user options are read from the gdbarch and appended here. + libopcodes clears INFO->DISASSEMBLER_OPTIONS once it has parsed + them, so the string has to be supplied again for the next + instruction; each parse first resets every option it does not see + back to its default, which is why the user ones have to be + repeated rather than parsed once. They come last and so take + precedence. */ + std::string arch_option; + auto *di = static_cast (info->application_data); + if (di != nullptr && !riscv_disasm_bfd_has_isa_attribute (info)) + { + gdbarch *arch = di->arch (); + riscv_gdbarch_tdep *tdep = gdbarch_tdep (arch); + + arch_option = tdep->disassembler_options_arch; + + const char *user_options = get_disassembler_options (arch); + if (user_options != nullptr && *user_options != '\0') + { + arch_option += ','; + arch_option += user_options; + } + info->disassembler_options = arch_option.c_str (); + } + return default_print_insn (addr, info); } @@ -4343,6 +4413,12 @@ riscv_gdbarch_init (struct gdbarch_info info, tdep->isa_features = features; tdep->abi_features = abi_features; + /* Supplied to the disassembler for an object that records no ISA of + its own, such as a core file loaded without an executable, which + libopcodes would otherwise disassemble as plain rv64gc. */ + std::string isa = riscv_isa_for_disassembler (features); + tdep->disassembler_options_arch = "arch=" + isa; + /* Target data types. */ set_gdbarch_short_bit (gdbarch, 16); set_gdbarch_int_bit (gdbarch, 32); diff --git a/gdb/riscv-tdep.h b/gdb/riscv-tdep.h index 5fe91b7287c..d9a696fccb7 100644 --- a/gdb/riscv-tdep.h +++ b/gdb/riscv-tdep.h @@ -94,6 +94,11 @@ struct riscv_gdbarch_tdep : gdbarch_tdep_base /* ISA-specific data types. */ struct type *riscv_fpreg_d_type = nullptr; + /* The "arch=" disassembler option naming the ISA of ISA_FEATURES, + supplied to the disassembler for an object that records no ISA of + its own. */ + std::string disassembler_options_arch; + /* The location of these registers, set to -2 by default so we don't match against -1 which is frequently used to mean "all registers", e.g. in the regcache supply/collect code. */ diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml new file mode 100644 index 00000000000..7f514803d51 --- /dev/null +++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml @@ -0,0 +1,123 @@ + + + + + + riscv + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp index 1e6698b2e5d..49500408f72 100644 --- a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp +++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp @@ -16,7 +16,8 @@ # Check the "arch=" disassembler option against an executable. The # option names the ISA to disassemble for, in place of the one the # object records, so the test needs an object both with and without an -# architecture attribute. +# architecture attribute. GDB supplies the option itself for the object +# that records nothing, which the test checks as well. # # A single "disassemble" prints the whole function through one # disassembler, so an ISA that survived only the first instruction would @@ -82,3 +83,42 @@ gdb_test_no_output "set disassembler-options arch=rv64gcv" \ gdb_test "disassemble vector_insns" \ "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*" \ "vector instructions decoded with arch=rv64gcv" + +# For an object that records no ISA, GDB names one on its own, out of the +# target description. In practice a description that sizes the vector +# registers is the one recovered from a core file, but a core only pairs +# with the executable it was dumped from, and the instructions of this +# one would be nowhere in the memory such a core dumped. A description +# loaded from a file sizes the registers the same way and pairs with any +# executable. +set tdesc_file "${srcdir}/${subdir}/${testfile}-vector.xml" + +if {[is_remote host]} { + set tdesc_file [remote_download host $tdesc_file] +} + +# Restarting drops the option set above: what decodes the instructions +# here is the ISA GDB supplies itself. +clean_restart $stripped + +gdb_test_no_output "set tdesc filename $tdesc_file" \ + "load a description with vector registers, object without an attribute" + +gdb_test "disassemble vector_insns" \ + "vsetvli\[ \t\]+t0,a0,e8,m1,ta,ma.*vxor\\.vv\[ \t\]+v1,v2,v3.*" \ + "the description ISA reaches the disassembler on its own" + +# The same description against the executable that does record rv64gc: +# the attribute has to keep winning, so the planted encodings stay raw +# words. Were the description supplied here anyway, they would decode as +# vector instructions. +clean_restart $testfile + +gdb_test_no_output "set tdesc filename $tdesc_file" \ + "load a description with vector registers" + +gdb_test "print sizeof (\$v0)" " = 16" \ + "the description sizes the vector registers" + +gdb_test "disassemble vector_insns" "\\.insn\[ \t\]+4, 0x0c0572d7.*" \ + "the attribute of the object outranks the description ISA" -- 2.43.0