From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id IYZKAGok32p6xxsAWB0awg (envelope-from ) for ; Mon, 26 Oct 2026 05:59:06 -0400 Authentication-Results: simark.ca; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20251104 header.b=ZPah9aqD; dkim-atps=neutral Received: by simark.ca (Postfix, from userid 112) id DE859378002; Mon, 26 Oct 2026 05:59:05 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-25) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-5.4 required=5.0 tests=ARC_SIGNED,ARC_VALID,BAYES_00, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FROM,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham autolearn_force=no version=4.0.1 Received: from vm01.sourceware.org (vm01.sourceware.org [IPv6:2620:52:6:3111::32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id C80111E007 for ; Mon, 26 Oct 2026 05:59:01 -0400 (EDT) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CF5254BA23D7 for ; Mon, 26 Oct 2026 09:59:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CF5254BA23D7 Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20251104 header.b=ZPah9aqD Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by sourceware.org (Postfix) with ESMTPS id 3F01B4BA23E5 for ; Mon, 26 Oct 2026 09:57:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 3F01B4BA23E5 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gmail.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 3F01B4BA23E5 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=2a00:1450:4864:20::42d ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1793008631; cv=none; b=MGeoaCGqPg6x75QwAKTzYTJz/U9ADCm/UfB4lNDOsh3bTrDiiGpDaft6+iT3D7OWTmAvov97CR7iZVpZ84jbTaOtR5Wro/pnieUQoLrAU8hylHdyAa53XJ6Yxxeh6BsygTqxFwy4uPRwwrtaCD8ijIUBWLpstGchhyZ1Bal5Bwc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1793008631; c=relaxed/simple; bh=dZeOJy234nVIZuuaKzrvNZVmGdxYJxJD3cDEYxHZhl8=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=s/9rmOkZgcogLyI57SSsC1nEoylZJsPPhwtTf3A7IFWSsVzay0LGZzU3vQWnm1Da9So8eGcir5SOwE+Y3Nk+2H22ItT6nKfweJsYEKT8YEbcqTG0rbt6KIvC/Rpe92Crz0y8LyWAP38OjAAWw3TOa5tN6DVQrHEt3vUodCbs25s= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256 header.s=20251104 header.b=ZPah9aqD DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3F01B4BA23E5 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-48e20ed3b9dso2527007f8f.2 for ; Mon, 26 Oct 2026 02:57:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1793008630; x=1793613430; darn=sourceware.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=UJKjOhIH12/w5pL9ynu1OF5jEF/XhpTDNDkJT5476LE=; b=ZPah9aqDtfR4IjjaD/lOLeAegd8lRkJxZFS277cjetBBP2zNDUwcu59kQOrebsL/Ae +f0UaYIUgcYODkxB+RCPmy6n9aI5UX0qe8EVyKfd7UL11C5VB3KLpCbYu4SAqxzwJ4ph FrDyORYGlYHeiIg0QhQX0lg6AgAdaoYjsCR4IueaLiMsLgAe8y58xquPAb1fpyfpbQZS poWDiawLqLMW4sevFhIGN9qDXHC4mWbQnbXb7VGlOmaiDfZiAwr1s4JhR9CZYDL4+kNA F2aF+cqWZ20Pg/izceVPAHxYE1oU7y4RELp2sYU91bDR89XwXDtJa/7UengY1rmP3YRQ PlYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1793008630; x=1793613430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=UJKjOhIH12/w5pL9ynu1OF5jEF/XhpTDNDkJT5476LE=; b=pD7nO5PhXcZSBhJjBXlTTc7NC3A+slHvXu0I4XD+2J0JtYp3xn9/Iq+mD/tFmjqTZV 3A+2/Ccio0wvZa2acAkhkQCXl2xRGiplGxO/79YSuAra0AfTNvQVry6NTqykopJ6/KuE hnKdCimGqY5IEoUzZeFZc40SAI6IwHq+zoSraa147y5B01AOrmufO3deVGBCgxSVEdoR 5oztnEHmu/75+JosQrA1zHrUJh/XkecQ807Dks+SNAtjBKIeGRIx61AuN2d5W5LQlEaW LT982GsPYAkZR4FFg9op7Au1s7tKD4wsnqI6soofeeeWZNlH5vFfdfIK6mlWJv7gegqO pldw== X-Gm-Message-State: AFq9FYKRq/K5x/cWjLcrNKcomr3XxF1G938i7fF+Qks73tApU0Hk6L3e ejL5W5TFi9ZWb0JgAHvDxZ07CxCfT1OG4y/7Nhlkv/nC5fwwsXnW8Go0huAB3mMlJRpjeHxDdt4 = X-Gm-Gg: AYBFou34+MNPdT4PzUf8l178KClYfNq1QiQCI0Y6+7NeuLoSGVlEMLo3hX2C5+jr+xR mvuds5wfZhTtui9wkaGn9I/R0DJCbcwjx5obn3PqAbhxQ4BpSR7klkbKkZVvCqzhO+DqEja5hZn e05M+amfNyYYnPe4wCFSItIENKIOAg3WP+LguuHakqVR2ae+/LURMAVA/Go2/9NQc6Df4Sif134 NvcoGR/n0hxMupgUeB8BR+Mkc0TbI/4v8In4Z119OJGdR5lFyrz6dki2FhGFNBOmb8KYPO4zd8L LPdmb5pHq+LGInfPl9fxkr01xM+EBYOWYjORxHVaXKI4dUSQF6yw4X2ghKABP/pqBi5wxONMLxI O6MhUPAL4q8p8ur+yGxDg0KsAXQQ961iwYlX6QKVDdxqsFC5A6WKzQXcq/ccosE0ZoKXAZh5Rxc icaR7/0/q16Nc+CxDACn/yda1WAw3TRHn1GmGokcGO9tf3rzV7SFn6pssxCqJP5Nj7+d//lAkdL VpK/hSUMNU5RKBwpHTWSTRZjEP2a3SMtqOouJOMNgTlbLGo0LUtLSNoEOXU6ugLQ9TUiq1LTFMz dr5GPtC7z4A3WgYyFhpDh4ASnmO9Fe7LB1LWlB6/X1QW+Q0AUcpjRPsE8abHZcsdd+vnORkr X-Received: by 2002:a05:6000:25fc:b0:48a:fb1c:c2a1 with SMTP id ffacd0b85a97d-48e3eb946b0mr10712722f8f.47.1793008629945; Mon, 26 Oct 2026 02:57:09 -0700 (PDT) Received: from localhost.localdomain ([178.64.143.40]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3eb8f387sm15080682f8f.4.2026.10.26.02.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 02:57:09 -0700 (PDT) From: Farid Khaidari To: gdb-patches@sourceware.org Cc: Andrew Burgess , Palmer Dabbelt , Timur Golubovich , Kevin Buettner Subject: [PATCH v2 4/4] gdb/riscv: disassemble an attribute-less object by the description ISA Date: Mon, 26 Oct 2026 12:56:46 +0300 Message-ID: <20261026095647.3035166-5-khaidari.fg@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261026095647.3035166-1-khaidari.fg@gmail.com> References: <20261022154417.235510-1-khaidari.fg@gmail.com> <20261026095647.3035166-1-khaidari.fg@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org An object without a RISC-V architecture attribute is disassembled as rv64gc, whatever the target description says. A core file is such an object, so its vector instructions print as raw .insn words even when the description has vector registers. For such objects, pass the ISA implied by the target description to the disassembler as "arch=". An object that records its own ISA keeps using it. The test checks both cases: with a vector description loaded, an rv64gc executable must not decode the planted words as vector instructions, and the same executable with the attribute stripped must. The option is set in print_insn, not through gdbarch_disassembler_options_implicit as mips-tdep.c does. A gdbarch is shared by all objects with matching features, and only print_insn knows which object it is disassembling. User options are appended to the string for every instruction. libopcodes clears disassembler_options after parsing and resets any option missing from a later string, so they would be lost from the second instruction on. The string is local to print_insn, and the previous disassembler_options value is restored after the call, so no pointer to it outlives print_insn. The test loads the vector description from a file. In practice such a description comes from a core, but a core only matches the executable that produced it. Only RV64 is tested; the RV32 ISA string was checked by reading the code. Signed-off-by: Farid Khaidari --- gdb/riscv-tdep.c | 69 ++++++++++ .../riscv-disasm-arch-option-vector.xml | 123 ++++++++++++++++++ .../gdb.arch/riscv-disasm-arch-option.exp | 41 +++++- 3 files changed, 232 insertions(+), 1 deletion(-) create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c index 0a997231abc..606bd371676 100644 --- a/gdb/riscv-tdep.c +++ b/gdb/riscv-tdep.c @@ -39,6 +39,7 @@ #include "elf-bfd.h" #include "symcat.h" #include "dis-asm.h" +#include "disasm.h" #include "frame-unwind.h" #include "frame-base.h" #include "trad-frame.h" @@ -56,6 +57,7 @@ #include "arch/riscv.h" #include "record-full.h" #include "riscv-ravenscar-thread.h" +#include "gdbsupport/scope-exit.h" #include @@ -4151,6 +4153,45 @@ riscv_gnu_triplet_regexp (struct gdbarch *gdbarch) return "riscv(32|64)?"; } +/* Return true if the object owning the section being disassembled + records a RISC-V ISA string attribute. */ + +static bool +riscv_disasm_bfd_has_isa_attribute (struct disassemble_info *info) +{ + if (info->section == nullptr) + return false; + + auto *abfd = info->section->owner; + if (abfd == nullptr || bfd_get_flavour (abfd) != bfd_target_elf_flavour) + return false; + + return elf_known_obj_attributes_proc (abfd)[Tag_RISCV_arch].s != nullptr; +} + +/* X register width, in bytes, implied by the RV32 base integer ISA. */ +constexpr int riscv_xlen_32 = 4; + +/* Build an ISA string for the "arch=" disassembler option from + FEATURES, the target description of the architecture. The option + replaces the rv64gc default of libopcodes, so the extension set is + that same default, widened by V once the target description sizes + the vector registers. Naming the extensions the description does + know about instead would decode less than the default it replaces: + an ISA without G implies neither Zicsr nor Zifencei, which would + drop "csrr" and "fence.i" from a target that merely describes no FP + registers. An RV32E target gets rv32gc for the same reason: E only + removes registers, so rv32gc decodes every RV32E instruction. */ + +static std::string +riscv_isa_for_disassembler (const struct riscv_gdbarch_features &features) +{ + std::string isa = features.xlen == riscv_xlen_32 ? "rv32gc" : "rv64gc"; + if (features.vlen > 0) + isa += "v"; + return isa; +} + /* Implement the "print_insn" gdbarch method. */ static int @@ -4162,6 +4203,34 @@ riscv_print_insn (bfd_vma addr, struct disassemble_info *info) if (s != nullptr) info->section = s->the_bfd_section; + /* An object that records its own ISA is disassembled according to + that ISA. One that does not, such as a core file loaded without an + executable, is disassembled according to the target description; + libopcodes would otherwise fall back to plain rv64gc. + + The option is supplied for each instruction, since the object can + change between them. Each parse resets the options it does not + see, so the user ones are appended, last so that they win. INFO + points at the local string only for this call. */ + auto *di = static_cast (info->application_data); + if (di == nullptr || riscv_disasm_bfd_has_isa_attribute (info)) + return default_print_insn (addr, info); + + gdbarch *arch = di->arch (); + riscv_gdbarch_tdep *tdep = gdbarch_tdep (arch); + std::string options + = "arch=" + riscv_isa_for_disassembler (tdep->isa_features); + + const char *user_options = get_disassembler_options (arch); + if (user_options != nullptr && *user_options != '\0') + { + options += ','; + options += user_options; + } + + const char *saved_options = info->disassembler_options; + info->disassembler_options = options.c_str (); + SCOPE_EXIT { info->disassembler_options = saved_options; }; return default_print_insn (addr, info); } diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml new file mode 100644 index 00000000000..7f514803d51 --- /dev/null +++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml @@ -0,0 +1,123 @@ + + + + + + riscv + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp index 2dd7a998eeb..2c7a85bf70c 100644 --- a/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp +++ b/gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp @@ -16,7 +16,8 @@ # Check the "arch=" disassembler option against an executable. The # option names the ISA to disassemble for, in place of the one the # object records, so the test needs an object both with and without an -# architecture attribute. +# architecture attribute. GDB supplies the option itself for the object +# that records nothing, which the test checks as well. # # A single "disassemble" prints the whole function through one # disassembler, so an ISA that survived only the first instruction would @@ -78,3 +79,41 @@ gdb_test_no_output "set disassembler-options arch=rv64gcv" \ gdb_test "disassemble vector_insns" $vector_re \ "vector instructions decoded with arch=rv64gcv" + +# For an object that records no ISA, GDB names one on its own, out of the +# target description. In practice a description that sizes the vector +# registers is the one recovered from a core file, but a core only pairs +# with the executable it was dumped from, and the instructions of this +# one would be nowhere in the memory such a core dumped. A description +# loaded from a file sizes the registers the same way and pairs with any +# executable. +set tdesc_file "${srcdir}/${subdir}/${testfile}-vector.xml" + +if {[is_remote host]} { + set tdesc_file [remote_download host $tdesc_file] +} + +# Restarting drops the option set above: what decodes the instructions +# here is the ISA GDB supplies itself. +clean_restart $stripped + +gdb_test_no_output "set tdesc filename $tdesc_file" \ + "load a description with vector registers, object without an attribute" + +gdb_test "disassemble vector_insns" $vector_re \ + "the description ISA reaches the disassembler on its own" + +# The same description against the executable that does record rv64gc: +# the attribute has to keep winning, so the planted encodings stay raw +# words. Were the description supplied here anyway, they would decode as +# vector instructions. +clean_restart $testfile + +gdb_test_no_output "set tdesc filename $tdesc_file" \ + "load a description with vector registers" + +gdb_test "print sizeof (\$v0)" " = 16" \ + "the description sizes the vector registers" + +gdb_test "disassemble vector_insns" $raw_re \ + "the attribute of the object outranks the description ISA" -- 2.43.0