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Thu, 22 Oct 2026 08:44:21 -0700 (PDT) Received: from localhost.localdomain ([176.15.140.8]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5bfa11f60d9sm1205912e87.17.2026.10.22.08.44.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 22 Oct 2026 08:44:21 -0700 (PDT) From: Farid Khaidari To: gdb-patches@sourceware.org Cc: Farid Khaidari , Andrew Burgess , Palmer Dabbelt , Timur Golubovich Subject: [PATCH 0/4] gdb/riscv: analyse a core file without the executable Date: Thu, 22 Oct 2026 18:44:13 +0300 Message-ID: <20261022154417.235510-1-khaidari.fg@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org A RISC-V core opened without its executable gets an integer-only target description, because the core does not say how wide the FP registers are. Any object with no ISA attribute, a core included, is also disassembled as plain rv64gc. This series reads what the core does record. The size of the NT_FPREGSET note gives FLEN, and AT_HWCAP gives the single-letter extensions. The last patch passes the ISA of the resulting target description to the disassembler when the object names none. Patches 3 and 4 need the "arch=" disassembler option, sent to binutils@sourceware.org as "RISC-V: add an "arch=" disassembler option". Vector state from the NT_RISCV_VECTOR note is left out. GDB can read the org.gnu.gdb.riscv.vector feature from a target description but cannot build one, so a vlen read from the core has nowhere to go yet. The disassembler test loads a vector description from a file instead. Tested on x86_64-linux with a riscv64-linux-gnu target: the three new tests give 23 passes and no failures. The host cannot run RISC-V binaries, so I did not run the rest of the testsuite. Farid Khaidari (4): gdb/riscv: recover FLEN from the NT_FPREGSET note size in core files gdb/riscv: recover core file ISA features from AT_HWCAP gdb/riscv: test the "arch=" disassembler option gdb/riscv: disassemble an attribute-less object by the description ISA gdb/riscv-linux-tdep.c | 120 +++++++++++++ gdb/riscv-tdep.c | 167 +++++++++++++++++- gdb/riscv-tdep.h | 14 ++ .../gdb.arch/riscv-core-fpregset.core.bz2 | Bin 0 -> 15134 bytes .../gdb.arch/riscv-core-fpregset.exp | 78 ++++++++ .../gdb.arch/riscv-core-hwcap.core.bz2 | Bin 0 -> 15122 bytes gdb/testsuite/gdb.arch/riscv-core-hwcap.exp | 72 ++++++++ .../riscv-disasm-arch-option-vector.xml | 123 +++++++++++++ .../gdb.arch/riscv-disasm-arch-option.c | 40 +++++ .../gdb.arch/riscv-disasm-arch-option.exp | 124 +++++++++++++ 10 files changed, 732 insertions(+), 6 deletions(-) create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.core.bz2 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-fpregset.exp create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.core.bz2 create mode 100644 gdb/testsuite/gdb.arch/riscv-core-hwcap.exp create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option-vector.xml create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.c create mode 100644 gdb/testsuite/gdb.arch/riscv-disasm-arch-option.exp -- 2.43.0