Re: [PATCH 15/24] RISC-V sim: Improve cycle and instret counts.

[Jim Wilson <jimw@sifive.com>]

On Sun, Apr 18, 2021 at 9:25 PM Mike Frysinger <vapier@gentoo.org> wrote:

> On 17 Apr 2021 10:58, Jim Wilson wrote:
> > @@ -2398,6 +2408,10 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int
> mhartid)
> >
> >    cpu->csr.mimpid = 0x8000;
> >    cpu->csr.mhartid = mhartid;
> > +  cpu->csr.cycle = 0;
> > +  cpu->csr.cycleh = 0;
> > +  cpu->csr.instret = 0;
> > +  cpu->csr.instreth = 0;
>
> if this is done so we can re-initialize the CPU and have all the CSR's be
> reset, we should do this with a single memset across all of cpu->csr right
> ?
> are there any that should be preserved ?  if there were, i'd argue that
> cycle
> falls into that bucket too.
>

Yes, we should memset the csrs before we start initializing the non-zero
ones.  And while I'm on the subject, we should memset the fprs too, which
we can do by just running memset on the entire cpu structure instead of
just cpu->regs at the start of initialize_cpu.  I'll have to test this
change to make sure it works.

Jim