From: Jim Wilson <jimw@sifive.com>
To: gdb-patches@sourceware.org
Subject: [PATCH 23/24] RISC-V sim: Add zicsr support.
Date: Sat, 17 Apr 2021 10:58:30 -0700 [thread overview]
Message-ID: <20210417175831.16413-24-jimw@sifive.com> (raw)
In-Reply-To: <20210417175831.16413-1-jimw@sifive.com>
The CSR and f*csr, f*rm, and f*flags instructions are in INSN_CLASS_ZICSR.
Move to a new execute_zicsr function.
sim/riscv/
* sim-main.c (execute_f): Remove CSR instructions.
(execute_i): Likewise.
(execute_zicsr): New function.
(execute_one): Call execute_zicsr.
---
sim/riscv/sim-main.c | 256 ++++++++++++++++++++++++++++-----------------------
1 file changed, 140 insertions(+), 116 deletions(-)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 67ad768..3974f61 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -761,39 +761,6 @@ execute_f (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
break;
}
break;
- case MATCH_FRCSR:
- TRACE_INSN (cpu, "frcsr %s",
- rd_name);
- store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
- break;
- case MATCH_FSCSR:
- TRACE_INSN (cpu, "fscsr %s, %sf",
- rd_name, rs1_name);
- store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
- store_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr, cpu->regs[rs1]);
- break;
- case MATCH_FRRM:
- TRACE_INSN (cpu, "frrm %s",
- rd_name);
- store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FRM, &cpu->csr.frm));
- break;
- case MATCH_FSRM:
- TRACE_INSN (cpu, "fsrm %s, %s",
- rd_name, rs1_name);
- store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm));
- store_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm, cpu->regs[rs1]);
- break;
- case MATCH_FRFLAGS:
- TRACE_INSN (cpu, "frflags %s",
- rd_name);
- store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
- break;
- case MATCH_FSFLAGS:
- TRACE_INSN (cpu, "fsflags %s, %s",
- rd_name, frs1_name);
- store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
- store_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags, cpu->regs[rs1]);
- break;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
@@ -1872,89 +1839,6 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
cpu->regs[rs1] + s_imm, cpu->regs[rs2]);
break;
- case MATCH_CSRRC:
- TRACE_INSN (cpu, "csrrc");
- switch (csr)
- {
-#define DECLARE_CSR(name, num, ...) \
- case num: \
- store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
- store_csr (cpu, #name, num, &cpu->csr.name, \
- cpu->csr.name & !cpu->regs[rs1]); \
- break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
- }
- break;
- case MATCH_CSRRCI:
- TRACE_INSN (cpu, "csrrci");
- switch (csr)
- {
-#define DECLARE_CSR(name, num, ...) \
- case num: \
- store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
- store_csr (cpu, #name, num, &cpu->csr.name, \
- cpu->csr.name & !rs1); \
- break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
- }
- break;
- case MATCH_CSRRS:
- TRACE_INSN (cpu, "csrrs");
- switch (csr)
- {
-#define DECLARE_CSR(name, num, ...) \
- case num: \
- store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
- store_csr (cpu, #name, num, &cpu->csr.name, \
- cpu->csr.name | cpu->regs[rs1]); \
- break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
- }
- break;
- case MATCH_CSRRSI:
- TRACE_INSN (cpu, "csrrsi");
- switch (csr)
- {
-#define DECLARE_CSR(name, num, ...) \
- case num: \
- store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
- store_csr (cpu, #name, num, &cpu->csr.name, \
- cpu->csr.name | rs1); \
- break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
- }
- break;
- case MATCH_CSRRW:
- TRACE_INSN (cpu, "csrrw");
- switch (csr)
- {
-#define DECLARE_CSR(name, num, ...) \
- case num: \
- store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
- store_csr (cpu, #name, num, &cpu->csr.name, cpu->regs[rs1]); \
- break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
- }
- break;
- case MATCH_CSRRWI:
- TRACE_INSN (cpu, "csrrwi");
- switch (csr)
- {
-#define DECLARE_CSR(name, num, ...) \
- case num: \
- store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
- store_csr (cpu, #name, num, &cpu->csr.name, rs1); \
- break;
-#include "opcode/riscv-opc.h"
-#undef DECLARE_CSR
- }
- break;
-
case MATCH_RDCYCLE:
TRACE_INSN (cpu, "rdcycle %s;", rd_name);
store_rd (cpu, rd, fetch_csr (cpu, "cycle", CSR_CYCLE, &cpu->csr.cycle));
@@ -2409,6 +2293,144 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
}
static sim_cia
+execute_zicsr (SIM_CPU *cpu, unsigned_word iw,
+ const struct riscv_opcode *op)
+{
+ SIM_DESC sd = CPU_STATE (cpu);
+ sim_cia pc = cpu->pc + 4;
+ int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+ int rs1 = (iw >> OP_SH_RS1) & OP_MASK_RS1;
+ const char *rd_name = riscv_gpr_names_abi[rd];
+ const char *rs1_name = riscv_gpr_names_abi[rs1];
+ const char *frs1_name = riscv_fpr_names_abi[rs1];
+ unsigned int csr = (iw >> OP_SH_CSR) & OP_MASK_CSR;
+
+ switch (op->match)
+ {
+ case MATCH_CSRRC:
+ TRACE_INSN (cpu, "csrrc");
+ switch (csr)
+ {
+#define DECLARE_CSR(name, num, ...) \
+ case num: \
+ store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+ store_csr (cpu, #name, num, &cpu->csr.name, \
+ cpu->csr.name & !cpu->regs[rs1]); \
+ break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+ }
+ break;
+ case MATCH_CSRRCI:
+ TRACE_INSN (cpu, "csrrci");
+ switch (csr)
+ {
+#define DECLARE_CSR(name, num, ...) \
+ case num: \
+ store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+ store_csr (cpu, #name, num, &cpu->csr.name, \
+ cpu->csr.name & !rs1); \
+ break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+ }
+ break;
+ case MATCH_CSRRS:
+ TRACE_INSN (cpu, "csrrs");
+ switch (csr)
+ {
+#define DECLARE_CSR(name, num, ...) \
+ case num: \
+ store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+ store_csr (cpu, #name, num, &cpu->csr.name, \
+ cpu->csr.name | cpu->regs[rs1]); \
+ break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+ }
+ break;
+ case MATCH_CSRRSI:
+ TRACE_INSN (cpu, "csrrsi");
+ switch (csr)
+ {
+#define DECLARE_CSR(name, num, ...) \
+ case num: \
+ store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+ store_csr (cpu, #name, num, &cpu->csr.name, \
+ cpu->csr.name | rs1); \
+ break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+ }
+ break;
+ case MATCH_CSRRW:
+ TRACE_INSN (cpu, "csrrw");
+ switch (csr)
+ {
+#define DECLARE_CSR(name, num, ...) \
+ case num: \
+ store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+ store_csr (cpu, #name, num, &cpu->csr.name, cpu->regs[rs1]); \
+ break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+ }
+ break;
+ case MATCH_CSRRWI:
+ TRACE_INSN (cpu, "csrrwi");
+ switch (csr)
+ {
+#define DECLARE_CSR(name, num, ...) \
+ case num: \
+ store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+ store_csr (cpu, #name, num, &cpu->csr.name, rs1); \
+ break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+ }
+ break;
+ case MATCH_FRCSR:
+ TRACE_INSN (cpu, "frcsr %s",
+ rd_name);
+ store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
+ break;
+ case MATCH_FSCSR:
+ TRACE_INSN (cpu, "fscsr %s, %sf",
+ rd_name, rs1_name);
+ store_rd (cpu, rd, fetch_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr));
+ store_csr (cpu, "fcsr", CSR_FCSR, &cpu->csr.fcsr, cpu->regs[rs1]);
+ break;
+ case MATCH_FRRM:
+ TRACE_INSN (cpu, "frrm %s",
+ rd_name);
+ store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FRM, &cpu->csr.frm));
+ break;
+ case MATCH_FSRM:
+ TRACE_INSN (cpu, "fsrm %s, %s",
+ rd_name, rs1_name);
+ store_rd (cpu, rd, fetch_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm));
+ store_csr (cpu, "frm", CSR_FCSR, &cpu->csr.frm, cpu->regs[rs1]);
+ break;
+ case MATCH_FRFLAGS:
+ TRACE_INSN (cpu, "frflags %s",
+ rd_name);
+ store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
+ break;
+ case MATCH_FSFLAGS:
+ TRACE_INSN (cpu, "fsflags %s, %s",
+ rd_name, frs1_name);
+ store_rd (cpu, rd, fetch_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags));
+ store_csr (cpu, "fflags", CSR_FFLAGS, &cpu->csr.fflags, cpu->regs[rs1]);
+ break;
+ default:
+ TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+ }
+
+ return pc;
+}
+
+static sim_cia
execute_zifencei (SIM_CPU *cpu, unsigned_word iw,
const struct riscv_opcode *op)
{
@@ -2456,6 +2478,8 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
return execute_f_and_c (cpu, iw, op);
case INSN_CLASS_D_AND_C:
return execute_d_and_c (cpu, iw, op);
+ case INSN_CLASS_ZICSR:
+ return execute_zicsr (cpu, iw, op);
case INSN_CLASS_ZIFENCEI:
return execute_zifencei (cpu, iw, op);
default:
--
2.7.4
next prev parent reply other threads:[~2021-04-17 17:59 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-17 17:58 [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Jim Wilson
2021-04-17 17:58 ` [PATCH 01/24] RISC-V sim: Fix fence.i Jim Wilson
2021-04-17 20:36 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 02/24] RISC-V sim: Fix for jalr Jim Wilson
2021-04-19 3:41 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 03/24] RISC-V sim: Atomic fixes Jim Wilson
2021-04-19 3:56 ` Mike Frysinger via Gdb-patches
2021-04-21 23:00 ` Jim Wilson
2021-04-22 0:09 ` Mike Frysinger via Gdb-patches
2021-04-22 3:12 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 04/24] RISC-V sim: More atomic fixes Jim Wilson
2021-04-19 3:57 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 05/24] RISC-V sim: Fix stack pointer alignment Jim Wilson
2021-04-19 3:58 ` Mike Frysinger via Gdb-patches
2021-04-21 22:39 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 06/24] RISC-V: Add fp support Jim Wilson
2021-04-19 4:08 ` Mike Frysinger via Gdb-patches
2021-04-21 23:34 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 07/24] RISC-V sim: Add link syscall support Jim Wilson
2021-04-19 4:09 ` Mike Frysinger via Gdb-patches
2021-04-21 23:36 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 08/24] RISC-V sim: Add brk syscall Jim Wilson
2021-04-19 5:24 ` Mike Frysinger via Gdb-patches
2021-04-21 23:51 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 09/24] RISC-V sim: Fix syscall fallback Jim Wilson
2021-04-21 23:38 ` Jim Wilson
2021-04-22 3:23 ` Mike Frysinger via Gdb-patches
2021-04-23 20:35 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 10/24] RISC-V sim: Fix ebreak Jim Wilson
2021-04-19 4:20 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 11/24] RISC-V sim: Fix ebreak, part 2 Jim Wilson
2021-04-19 4:20 ` Mike Frysinger via Gdb-patches
2021-04-21 23:41 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 12/24] RISC-V sim: Add compressed support Jim Wilson
2021-04-19 4:13 ` Mike Frysinger via Gdb-patches
2021-04-21 23:42 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 13/24] RISC-V sim: Add gettimeofday Jim Wilson
2021-04-19 4:19 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 14/24] RISC-V sim: Add csrr*i instructions Jim Wilson
2021-04-19 4:26 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 15/24] RISC-V sim: Improve cycle and instret counts Jim Wilson
2021-04-19 4:25 ` Mike Frysinger via Gdb-patches
2021-04-22 2:26 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 16/24] RISC-V sim: Check sbrk argument Jim Wilson
2021-04-19 5:33 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 17/24] RISC-V sim: Fix tracing typo Jim Wilson
2021-04-19 4:26 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 18/24] RISC-V sim: Improve branch tracing Jim Wilson
2021-04-19 4:27 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 19/24] RISC-V sim: Improve tracing for slt* instructions Jim Wilson
2021-04-19 4:27 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 20/24] RISC-V sim: Set brk to _end if possible Jim Wilson
2021-04-19 5:41 ` Mike Frysinger via Gdb-patches
2021-04-22 2:45 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 21/24] RISC-V sim: Fix mingw builds Jim Wilson
2021-04-19 4:12 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 22/24] RISC-V sim: Support compressed FP instructions Jim Wilson
2021-04-19 4:27 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` Jim Wilson [this message]
2021-04-19 5:13 ` [PATCH 23/24] RISC-V sim: Add zicsr support Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 24/24] RISC-V sim: Fix divw and remw Jim Wilson
2021-04-19 5:10 ` Mike Frysinger via Gdb-patches
2021-04-17 20:38 ` [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Mike Frysinger via Gdb-patches
2021-04-19 2:33 ` Jim Wilson
2021-04-19 3:23 ` Mike Frysinger via Gdb-patches
2021-04-19 4:32 ` Jim Wilson
2021-04-19 3:42 ` Mike Frysinger via Gdb-patches
2021-04-19 4:37 ` Jim Wilson
2021-04-21 15:47 ` Andrew Burgess
2021-04-21 17:49 ` Andrew Burgess
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20210417175831.16413-24-jimw@sifive.com \
--to=jimw@sifive.com \
--cc=gdb-patches@sourceware.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox