Re: [PATCH 16/24] RISC-V sim: Check sbrk argument.

[Mike Frysinger via Gdb-patches <gdb-patches@sourceware.org>]

On 17 Apr 2021 10:58, Jim Wilson wrote:
> +		  {
> +		    if (cpu->a0 >= DEFAULT_MEM_SIZE)
> +		      cpu->a0 = -1;
> +		    else
> +		      cpu->endbrk = cpu->a0;
> +		  }

this incorrectly assumes that DEFAULT_MEM_SIZE is always the limit when it's
not: that is simply the default memory size if the user hasn't specified one.
so it could be larger or smaller.  if it were larger, it'd mean the program
would fail w/OOM even if the user had configured the sim specifically to have
more resources.  if it were smaller, it'd return success when the memory isn't
actually available.

your best bet probably is to just probe the memory and see if it exists.  look
at how sim_core_read_buffer is used in riscv/interp.c:sim_open.  it would mean
the code would fail if the user had MMIO at much higher addresses and then the
program passed that address here, but making the code more precise is kind of
hard, especially when you consider the user could just create a bunch of random
memory stripes.
0000-1000: RAM
1000-2000: Nothing
2000-3000: RAM
3000-4000: Nothing
4000-5000: RAM
5000-6000: Nothing
6000-7000: RAM
...

easier to just document this brk behavior and call it a day rather than try to
protect against overtly pathological scenarios.
-mike