[PATCH 04/24] RISC-V sim: More atomic fixes.

[Jim Wilson <jimw@sifive.com>]

Last patch was incomplete, as all amo instructions need fix for when
rd and rs2 are the same register.

	sim/riscv/
	* sim-main.c (execute_a): Use rs2_val instead of cpu->regs[rs2]
	in more cases.
---
 sim/riscv/sim-main.c | 18 ++++++++++--------
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index eaf0da2..b6ae060 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -802,6 +802,8 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
   struct atomic_mem_reserved_list *amo_prev, *amo_curr;
   insn_t aqrl_mask = (OP_MASK_AQ << OP_SH_AQ) | (OP_MASK_RL << OP_SH_RL);
   unsigned_word tmp;
+  /* We need the original value of rs2.  Might change if rd and rs2 are
+     the same register.  */
   unsigned_word rs2_val = cpu->regs[rs2];
   sim_cia pc = cpu->pc + 4;
 
@@ -872,31 +874,31 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
     {
     case MATCH_AMOADD_D:
     case MATCH_AMOADD_W:
-      tmp = tmp + cpu->regs[rs2];
+      tmp = tmp + rs2_val;
       break;
     case MATCH_AMOAND_D:
     case MATCH_AMOAND_W:
-      tmp = tmp & cpu->regs[rs2];
+      tmp = tmp & rs2_val;
       break;
     case MATCH_AMOMAX_D:
     case MATCH_AMOMAX_W:
-      tmp = MAX ((signed_word) tmp, (signed_word) cpu->regs[rs2]);
+      tmp = MAX ((signed_word) tmp, (signed_word) rs2_val);
       break;
     case MATCH_AMOMAXU_D:
     case MATCH_AMOMAXU_W:
-      tmp = MAX ((unsigned_word) tmp, (unsigned_word) cpu->regs[rs2]);
+      tmp = MAX ((unsigned_word) tmp, (unsigned_word) rs2_val);
       break;
     case MATCH_AMOMIN_D:
     case MATCH_AMOMIN_W:
-      tmp = MIN ((signed_word) tmp, (signed_word) cpu->regs[rs2]);
+      tmp = MIN ((signed_word) tmp, (signed_word) rs2_val);
       break;
     case MATCH_AMOMINU_D:
     case MATCH_AMOMINU_W:
-      tmp = MIN ((unsigned_word) tmp, (unsigned_word) cpu->regs[rs2]);
+      tmp = MIN ((unsigned_word) tmp, (unsigned_word) rs2_val);
       break;
     case MATCH_AMOOR_D:
     case MATCH_AMOOR_W:
-      tmp = tmp | cpu->regs[rs2];
+      tmp = tmp | rs2_val;
       break;
     case MATCH_AMOSWAP_D:
     case MATCH_AMOSWAP_W:
@@ -904,7 +906,7 @@ execute_a (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       break;
     case MATCH_AMOXOR_D:
     case MATCH_AMOXOR_W:
-      tmp = tmp ^ cpu->regs[rs2];
+      tmp = tmp ^ rs2_val;
       break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
-- 
2.7.4