[PATCH 07/24] RISC-V sim: Add link syscall support.

[Jim Wilson <jimw@sifive.com>]

From: Kuan-Lin Chen <rufus@andestech.com>

Use callback routines to support more syscalls, add TARGET_SYS_link support.

	sim/riscv/
	* sim-main.c: Include unistd.h.
	(execute_i): In case MATCH_ECALL, Call cb_target_to_host_syscall
	and handle TARGET_sys_link.
---
 sim/riscv/sim-main.c | 37 ++++++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index de76089..03ba79b 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -25,6 +25,7 @@
 
 #include <inttypes.h>
 #include <time.h>
+#include <unistd.h>
 
 #include "sim-main.h"
 #include "sim-fpu.h"
@@ -1245,7 +1246,41 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
       break;
     case MATCH_ECALL:
       TRACE_INSN (cpu, "ecall;");
-      cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0, cpu->a1, cpu->a2, cpu->a3);
+      if (cb_target_to_host_syscall (STATE_CALLBACK (sd), cpu->a7) == -1)
+	{
+	  host_callback *cb = STATE_CALLBACK (sd);
+	  CB_SYSCALL sc;
+
+	  CB_SYSCALL_INIT (&sc);
+
+	  sc.arg1 = cpu->a0;
+	  sc.arg2 = cpu->a1;
+	  sc.arg3 = cpu->a2;
+	  sc.arg4 = cpu->a3;
+	  sc.func = cpu->a7;
+
+	  sc.p1 = (PTR) sd;
+	  sc.p2 = (PTR) cpu;
+	  sc.read_mem = sim_syscall_read_mem;
+	  sc.write_mem = sim_syscall_write_mem;
+
+	  switch (cpu->a7)
+	    {
+	    case TARGET_SYS_link:
+	      {
+		char oldpath[1024], newpath[1024];
+		cb_get_string (cb, &sc, oldpath, sizeof (oldpath), sc.arg1);
+		cb_get_string (cb, &sc, newpath, sizeof (newpath), sc.arg2);
+		cpu->a0 = link (oldpath, newpath);
+		break;
+	      }
+	    default:
+	      cpu->a0 = -1;
+	      break;
+	    }
+	}
+      else
+	cpu->a0 = sim_syscall (cpu, cpu->a7, cpu->a0, cpu->a1, cpu->a2, cpu->a3);
       break;
     default:
       TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
-- 
2.7.4