[PATCH 14/24] RISC-V sim: Add csrr*i instructions.

[Jim Wilson <jimw@sifive.com>]

From: Kito Cheng <kito.cheng@gmail.com>

Implement csrrci, csrrsi, and csrrwi.

	sim/riscv/
	* sim-main.c (execute_i): Handle MATCH_CSRRCI, MATCH_CSRRSI,
	MATCH_CSRRWI.
---
 sim/riscv/sim-main.c | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index f330ef9..42506a9 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1647,6 +1647,20 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 #undef DECLARE_CSR
 	}
       break;
+    case MATCH_CSRRCI:
+      TRACE_INSN (cpu, "csrrci");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, \
+		     cpu->csr.name & !rs1); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
     case MATCH_CSRRS:
       TRACE_INSN (cpu, "csrrs");
       switch (csr)
@@ -1661,6 +1675,20 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 #undef DECLARE_CSR
 	}
       break;
+    case MATCH_CSRRSI:
+      TRACE_INSN (cpu, "csrrsi");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, \
+		     cpu->csr.name | rs1); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
     case MATCH_CSRRW:
       TRACE_INSN (cpu, "csrrw");
       switch (csr)
@@ -1674,6 +1702,19 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 #undef DECLARE_CSR
 	}
       break;
+    case MATCH_CSRRWI:
+      TRACE_INSN (cpu, "csrrwi");
+      switch (csr)
+	{
+#define DECLARE_CSR(name, num, ...) \
+	case num: \
+	  store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
+	  store_csr (cpu, #name, num, &cpu->csr.name, rs1); \
+	  break;
+#include "opcode/riscv-opc.h"
+#undef DECLARE_CSR
+	}
+      break;
 
     case MATCH_RDCYCLE:
       TRACE_INSN (cpu, "rdcycle %s;", rd_name);
-- 
2.7.4