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Date: Sat, 17 Apr 2021 10:58:21 -0700 Message-Id: <20210417175831.16413-15-jimw@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210417175831.16413-1-jimw@sifive.com> References: <20210417175831.16413-1-jimw@sifive.com> X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" From: Kito Cheng Implement csrrci, csrrsi, and csrrwi. sim/riscv/ * sim-main.c (execute_i): Handle MATCH_CSRRCI, MATCH_CSRRSI, MATCH_CSRRWI. --- sim/riscv/sim-main.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index f330ef9..42506a9 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -1647,6 +1647,20 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) #undef DECLARE_CSR } break; + case MATCH_CSRRCI: + TRACE_INSN (cpu, "csrrci"); + switch (csr) + { +#define DECLARE_CSR(name, num, ...) \ + case num: \ + store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ + store_csr (cpu, #name, num, &cpu->csr.name, \ + cpu->csr.name & !rs1); \ + break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + break; case MATCH_CSRRS: TRACE_INSN (cpu, "csrrs"); switch (csr) @@ -1661,6 +1675,20 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) #undef DECLARE_CSR } break; + case MATCH_CSRRSI: + TRACE_INSN (cpu, "csrrsi"); + switch (csr) + { +#define DECLARE_CSR(name, num, ...) \ + case num: \ + store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ + store_csr (cpu, #name, num, &cpu->csr.name, \ + cpu->csr.name | rs1); \ + break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + break; case MATCH_CSRRW: TRACE_INSN (cpu, "csrrw"); switch (csr) @@ -1674,6 +1702,19 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) #undef DECLARE_CSR } break; + case MATCH_CSRRWI: + TRACE_INSN (cpu, "csrrwi"); + switch (csr) + { +#define DECLARE_CSR(name, num, ...) \ + case num: \ + store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \ + store_csr (cpu, #name, num, &cpu->csr.name, rs1); \ + break; +#include "opcode/riscv-opc.h" +#undef DECLARE_CSR + } + break; case MATCH_RDCYCLE: TRACE_INSN (cpu, "rdcycle %s;", rd_name); -- 2.7.4