Re: [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain.

[Andrew Burgess <andrew.burgess@embecosm.com>]

* Andrew Burgess <andrew.burgess@embecosm.com> [2021-04-21 16:47:39 +0100]:

> * Jim Wilson <jimw@sifive.com> [2021-04-17 10:58:07 -0700]:
> 
> > These are mostly patches extracted from riscv-gnu-toolchain with minor
> > changes to apply to current FSF GDB sim.  I was careful to maintain the
> > original author info, and the original commit logs when reasonable.
> 
> Maybe a silly question, but all of these authors do have an FSF
> copyright assignment in place, right?  And they did all agree to pass
> this code over to the FSF, right?
> 
> I don't think we can assume that just because an assignment is in
> place they choose to give this code over to FSF, it would depend upon
> the context in which they originally posted the code.

OK, I realise you actually already addressed this point.  I don't know
how I didn't see this given it was on the very next line.

Apologies for the noise - it's been a long day :(

Thanks,
Andrew


> 
> Thanks,
> Andrew
> 
> 
> 
> 
> > There are also a few extra patches from me added in, as I noticed some
> > problems when reviewing the patches, and debugging issues.  Note that
> > Kito and Monk were at Andes when they wrote these patches, and are now
> > at SiFive.  So this is mostly Andes work, and they should get credit
> > for this work.  I kept their original email addresses even though they
> > won't work anymore.  We will need permission from Andes to merge the
> > patches into FSF GDB.  Hopefully Kuan-Lin can do that for us.  The patches
> > from Palmer and myself were written at SiFive.
> > 
> > I tested this with a gcc make check using riscv-gnu-toolchain and pulling
> > in FSF GDB sim with my patches applied.  I get 13 gcc unexpected failures
> > for rv32imac/ilp32 and 24 gcc unexpected failures for rv64gc/lp64d which
> > matches the old simulator port in riscv-gnu-toolchain.  I did have one
> > problem with the GNUC code in mulhu function producing the wrong result,
> > but I think that is a bug in the Ubuntu 16.04 gcc-4.8 on my server.  If
> > this is still broken with newer gcc versions I will take another look at
> > that.
> > 
> > This code can probably use some cleanup.  I'd like to see the extensions
> > in canonical arch order for instance.  But dealing with this many patches
> > is unwieldy, and I wanted to retain the original authorship for the
> > patches, so I'd rather do cleanup work as follow on patches.
> > 
> > Jim
> > 
> > Jim Wilson (6):
> >   RISC-V sim: Fix fence.i.
> >   RISC-V sim: More atomic fixes.
> >   RISC-V sim: Fix ebreak, part 2.
> >   RISC-V sim: Fix mingw builds.
> >   RISC-V sim: Support compressed FP instructions.
> >   RISC-V sim: Add zicsr support.
> > 
> > Kito Cheng (9):
> >   RISC-V sim: Atomic fixes.
> >   RISC-V sim: Fix syscall fallback.
> >   RISC-V sim: Add csrr*i instructions.
> >   RISC-V sim: Improve cycle and instret counts.
> >   RISC-V sim: Check sbrk argument.
> >   RISC-V sim: Improve branch tracing.
> >   RISC-V sim: Improve tracing for slt* instructions.
> >   RISC-V sim: Set brk to _end if possible.
> >   RISC-V sim: Fix divw and remw.
> > 
> > Kuan-Lin Chen (5):
> >   RISC-V sim: Fix stack pointer alignment.
> >   RISC-V sim: Add link syscall support.
> >   RISC-V sim: Add brk syscall.
> >   RISC-V sim: Add gettimeofday.
> >   RISC-V sim: Fix tracing typo.
> > 
> > Monk Chiang (3):
> >   RISC-V: Add fp support.
> >   RISC-V sim: Fix ebreak.
> >   RISC-V sim: Add compressed support.
> > 
> > Palmer Dabbelt (1):
> >   RISC-V sim: Fix for jalr.
> > 
> >  sim/riscv/interp.c   |   45 ++
> >  sim/riscv/sim-main.c | 1790 ++++++++++++++++++++++++++++++++++++++++++++++----
> >  sim/riscv/sim-main.h |   16 +-
> >  3 files changed, 1733 insertions(+), 118 deletions(-)
> > 
> > -- 
> > 2.7.4
> >