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From: Jim Wilson <jimw@sifive.com>
To: gdb-patches@sourceware.org
Cc: Kuan-Lin Chen <rufus@andestech.com>
Subject: [PATCH 08/24] RISC-V sim: Add brk syscall.
Date: Sat, 17 Apr 2021 10:58:15 -0700	[thread overview]
Message-ID: <20210417175831.16413-9-jimw@sifive.com> (raw)
In-Reply-To: <20210417175831.16413-1-jimw@sifive.com>

From: Kuan-Lin Chen <rufus@andestech.com>

Add endbrk field to cpu struct.  Set it to highest section end address.
Use it for the brk syscall support.

	sim/riscv/
	* interp.c: Include libiberty.h, bfd.h, and elf-bfd.h.
	(sim_create_inferior): New locals phdr, i, phnum.  Use to
	calculate cpu->endbrk.
	* sim-main.c (execute_i): In case MATCH_ECALL, handle
	TARGET_SYS_brk.
	* sim-main.h (struct _sim_cpu): Add endbrk field.
---
 sim/riscv/interp.c   | 15 +++++++++++++++
 sim/riscv/sim-main.c |  9 +++++++++
 sim/riscv/sim-main.h |  1 +
 3 files changed, 25 insertions(+)

diff --git a/sim/riscv/interp.c b/sim/riscv/interp.c
index 1bf60a4..c98f6ab 100644
--- a/sim/riscv/interp.c
+++ b/sim/riscv/interp.c
@@ -20,6 +20,10 @@
 
 #include "config.h"
 
+#include "libiberty.h"
+#include "bfd.h"
+#include "elf-bfd.h"
+
 #include "sim-main.h"
 #include "sim-options.h"
 \f
@@ -129,6 +133,8 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
 {
   SIM_CPU *cpu = STATE_CPU (sd, 0);
   SIM_ADDR addr;
+  Elf_Internal_Phdr *phdr;
+  int i, phnum;
 
   /* Set the PC.  */
   if (abfd != NULL)
@@ -137,6 +143,15 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
     addr = 0;
   sim_pc_set (cpu, addr);
 
+  /* Set endbrk to highest section end address.  */
+  phdr = elf_tdata (abfd)->phdr;
+  phnum = elf_elfheader (abfd)->e_phnum;
+  for (i = 0; i < phnum; i++)
+    {
+      if (phdr[i].p_paddr + phdr[i].p_memsz > cpu->endbrk)
+	cpu->endbrk = phdr[i].p_paddr + phdr[i].p_memsz;
+    }
+
   /* Standalone mode (i.e. `run`) will take care of the argv for us in
      sim_open() -> sim_parse_args().  But in debug mode (i.e. 'target sim'
      with `gdb`), we need to handle it because the user can change the
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 03ba79b..597e9c3 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -1274,6 +1274,15 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
 		cpu->a0 = link (oldpath, newpath);
 		break;
 	      }
+	    case TARGET_SYS_brk:
+	      {
+		/* FIXME: Check the invalid access.  */
+		if (cpu->a0 == 0)
+		  cpu->a0 = cpu->endbrk;
+		else
+		  cpu->endbrk = cpu->a0;
+		break;
+	      }
 	    default:
 	      cpu->a0 = -1;
 	      break;
diff --git a/sim/riscv/sim-main.h b/sim/riscv/sim-main.h
index e53794f..9206b94 100644
--- a/sim/riscv/sim-main.h
+++ b/sim/riscv/sim-main.h
@@ -63,6 +63,7 @@ struct _sim_cpu {
     };
   };
   sim_cia pc;
+  sim_cia endbrk;
 
   struct {
 #define DECLARE_CSR(name, ...) unsigned_word name;
-- 
2.7.4


  parent reply	other threads:[~2021-04-17 17:59 UTC|newest]

Thread overview: 70+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-17 17:58 [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Jim Wilson
2021-04-17 17:58 ` [PATCH 01/24] RISC-V sim: Fix fence.i Jim Wilson
2021-04-17 20:36   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 02/24] RISC-V sim: Fix for jalr Jim Wilson
2021-04-19  3:41   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 03/24] RISC-V sim: Atomic fixes Jim Wilson
2021-04-19  3:56   ` Mike Frysinger via Gdb-patches
2021-04-21 23:00     ` Jim Wilson
2021-04-22  0:09       ` Mike Frysinger via Gdb-patches
2021-04-22  3:12         ` Jim Wilson
2021-04-17 17:58 ` [PATCH 04/24] RISC-V sim: More atomic fixes Jim Wilson
2021-04-19  3:57   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 05/24] RISC-V sim: Fix stack pointer alignment Jim Wilson
2021-04-19  3:58   ` Mike Frysinger via Gdb-patches
2021-04-21 22:39     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 06/24] RISC-V: Add fp support Jim Wilson
2021-04-19  4:08   ` Mike Frysinger via Gdb-patches
2021-04-21 23:34     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 07/24] RISC-V sim: Add link syscall support Jim Wilson
2021-04-19  4:09   ` Mike Frysinger via Gdb-patches
2021-04-21 23:36     ` Jim Wilson
2021-04-17 17:58 ` Jim Wilson [this message]
2021-04-19  5:24   ` [PATCH 08/24] RISC-V sim: Add brk syscall Mike Frysinger via Gdb-patches
2021-04-21 23:51     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 09/24] RISC-V sim: Fix syscall fallback Jim Wilson
2021-04-21 23:38   ` Jim Wilson
2021-04-22  3:23     ` Mike Frysinger via Gdb-patches
2021-04-23 20:35       ` Jim Wilson
2021-04-17 17:58 ` [PATCH 10/24] RISC-V sim: Fix ebreak Jim Wilson
2021-04-19  4:20   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 11/24] RISC-V sim: Fix ebreak, part 2 Jim Wilson
2021-04-19  4:20   ` Mike Frysinger via Gdb-patches
2021-04-21 23:41     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 12/24] RISC-V sim: Add compressed support Jim Wilson
2021-04-19  4:13   ` Mike Frysinger via Gdb-patches
2021-04-21 23:42     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 13/24] RISC-V sim: Add gettimeofday Jim Wilson
2021-04-19  4:19   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 14/24] RISC-V sim: Add csrr*i instructions Jim Wilson
2021-04-19  4:26   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 15/24] RISC-V sim: Improve cycle and instret counts Jim Wilson
2021-04-19  4:25   ` Mike Frysinger via Gdb-patches
2021-04-22  2:26     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 16/24] RISC-V sim: Check sbrk argument Jim Wilson
2021-04-19  5:33   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 17/24] RISC-V sim: Fix tracing typo Jim Wilson
2021-04-19  4:26   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 18/24] RISC-V sim: Improve branch tracing Jim Wilson
2021-04-19  4:27   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 19/24] RISC-V sim: Improve tracing for slt* instructions Jim Wilson
2021-04-19  4:27   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 20/24] RISC-V sim: Set brk to _end if possible Jim Wilson
2021-04-19  5:41   ` Mike Frysinger via Gdb-patches
2021-04-22  2:45     ` Jim Wilson
2021-04-17 17:58 ` [PATCH 21/24] RISC-V sim: Fix mingw builds Jim Wilson
2021-04-19  4:12   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 22/24] RISC-V sim: Support compressed FP instructions Jim Wilson
2021-04-19  4:27   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 23/24] RISC-V sim: Add zicsr support Jim Wilson
2021-04-19  5:13   ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 24/24] RISC-V sim: Fix divw and remw Jim Wilson
2021-04-19  5:10   ` Mike Frysinger via Gdb-patches
2021-04-17 20:38 ` [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Mike Frysinger via Gdb-patches
2021-04-19  2:33   ` Jim Wilson
2021-04-19  3:23     ` Mike Frysinger via Gdb-patches
2021-04-19  4:32       ` Jim Wilson
2021-04-19  3:42 ` Mike Frysinger via Gdb-patches
2021-04-19  4:37   ` Jim Wilson
2021-04-21 15:47 ` Andrew Burgess
2021-04-21 17:49   ` Andrew Burgess

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