From: Jim Wilson <jimw@sifive.com>
To: gdb-patches@sourceware.org
Subject: [PATCH 22/24] RISC-V sim: Support compressed FP instructions.
Date: Sat, 17 Apr 2021 10:58:29 -0700 [thread overview]
Message-ID: <20210417175831.16413-23-jimw@sifive.com> (raw)
In-Reply-To: <20210417175831.16413-1-jimw@sifive.com>
Add functions to handle INSN_CLASS_F_AND_C and INSN_CLASS_D_AND_C. Add
decode errors for insns that can decode to more than one class depending
on XLEN, if decoded in the wrong class.
sim/riscv/
* sim-main.c (execute_c): For F and D compressed instructions,
call sim_engine_halt and report decode error.
(execute_f_and_c, execute_d_and_c): New functions.
(execute_one): Call the new functions.
---
sim/riscv/sim-main.c | 376 +++++++++++++++++++++++++++++++++++++++++----------
1 file changed, 306 insertions(+), 70 deletions(-)
diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 82c8d4e..67ad768 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -914,16 +914,10 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
case MATCH_C_FLD:
if (RISCV_XLEN (cpu) <= 64)
{
- TRACE_INSN (cpu, "c.fld %s, %" PRIiTW "(%s);"
- " // %s = *(%s + %" PRIiTW ")",
- fcrs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), fcrs1s_name,
- fcrs2s_name, fcrs1s_name, EXTRACT_CLTYPE_LD_IMM (iw));
- /* rv32/64, c.fld instruction. */
- store_frd64 (cpu, crs2s,
- sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
- cpu->regs[crs1s]
- + EXTRACT_CLTYPE_LD_IMM (iw)));
- return pc;
+ /* rv32/64, c.fld instruction which is D and C. */
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
}
else
{
@@ -933,17 +927,12 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
sim_signalled, SIM_SIGILL);
}
case MATCH_C_FLW:
- /* rv32: c.flw, rv64: c.ld. */
+ /* rv32: c.flw F and C, rv64: c.ld. */
if (RISCV_XLEN (cpu) == 32)
{
- TRACE_INSN (cpu, "c.flw %s, %" PRIiTW "(%s);"
- " // *(%s + %" PRIiTW ") = %s",
- fcrs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
- crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), fcrs2s_name);
- store_frd (cpu, crs2s, EXTEND32 (
- sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
- cpu->regs[crs1s]
- + EXTRACT_CLTYPE_LW_IMM (iw))));
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
}
else
{
@@ -960,16 +949,10 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
case MATCH_C_FSD:
if (RISCV_XLEN (cpu) <= 64)
{
- /* rv32/64, c.fsd instruction. */
- TRACE_INSN (cpu, "c.fsd %s, %" PRIiTW "(%s);"
- " // *(%s + %" PRIiTW ") = %s",
- fcrs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), crs1s_name,
- crs1s_name, EXTRACT_CLTYPE_LD_IMM (iw), fcrs2s_name);
- sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
- cpu->regs[crs1s]
- + EXTRACT_CLTYPE_LD_IMM (iw),
- cpu->fpregs[crs2s].v[0]);
- return pc;
+ /* rv32/64, c.fsd instruction which is D and C. */
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
}
else
{
@@ -979,17 +962,12 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
sim_signalled, SIM_SIGILL);
}
case MATCH_C_FSW:
- /* rv32: c.fsw, rv64: c.sd. */
+ /* rv32: c.fsw F and C, rv64: c.sd. */
if (RISCV_XLEN (cpu) == 32)
{
- TRACE_INSN (cpu, "c.fsw %s, %" PRIiTW "(%s);"
- " // *(%s + %" PRIiTW ") = %s",
- fcrs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
- crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), fcrs2s_name);
- sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
- cpu->regs[crs1s]
- + EXTRACT_CLTYPE_LW_IMM (iw),
- cpu->fpregs[crs2s].w[0]);
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
}
else
{
@@ -1173,18 +1151,13 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
store_rd (cpu, rd, cpu->regs[rd] + cpu->regs[crs2]);
return pc;
case MATCH_C_FLDSP:
- /* rv32/64: c.fldsp, rv128: c.flqsp. */
+ /* rv32/64: c.fldsp D and C, rv128: c.flqsp. */
if (RISCV_XLEN (cpu) <= 64)
{
- TRACE_INSN (cpu, "c.fldsp %s, %" PRIiTW "(sp);"
- " // %s = *(sp + %" PRIiTW ")",
- frd_name, EXTRACT_CITYPE_LDSP_IMM (iw),
- frd_name, EXTRACT_CITYPE_LDSP_IMM (iw));
- store_frd64 (cpu, rd,
- sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
- cpu->sp
- + EXTRACT_CITYPE_LDSP_IMM (iw)));
- return pc;
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+
}
else
{
@@ -1193,17 +1166,13 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
sim_signalled, SIM_SIGILL);
}
case MATCH_C_FLWSP:
- /* rv32: c.flwsp, rv64: c.ldsp. */
+ /* rv32: c.flwsp F and C, rv64: c.ldsp. */
if (RISCV_XLEN (cpu) == 32)
{
- TRACE_INSN (cpu, "c.flwsp %s, %" PRIiTW "(sp);"
- " // %s = *(sp + %" PRIiTW ")",
- frd_name, EXTRACT_CITYPE_LWSP_IMM (iw),
- frd_name, EXTRACT_CITYPE_LWSP_IMM (iw));
- store_frd (cpu, rd, EXTEND32 (
- sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
- cpu->sp
- + EXTRACT_CITYPE_LWSP_IMM (iw))));
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+
}
else
{
@@ -1218,26 +1187,157 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
}
return pc;
case MATCH_C_FSDSP:
- /* rv32/64: c.fsdsp, rv128: c.fsqsp. */
+ /* rv32/64: c.fsdsp D and C, rv128: c.fsqsp. */
if (RISCV_XLEN (cpu) <= 64)
{
- TRACE_INSN (cpu, "c.fsdsp %s, %" PRIiTW "(sp);"
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+
+ }
+ else
+ {
+ TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+ }
+ case MATCH_C_FSWSP:
+ /* rv32: c.fswsp F and C, rv64: c.sdsp. */
+ if (RISCV_XLEN (cpu) == 32)
+ {
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+ }
+ else
+ {
+ TRACE_INSN (cpu, "c.sdsp %s, %" PRIiTW "(sp);"
" // *(sp + %" PRIiTW ") = %s",
- fcrs2_name, EXTRACT_CSSTYPE_SDSP_IMM (iw),
- EXTRACT_CSSTYPE_SDSP_IMM (iw), fcrs2_name);
+ crs2_name, EXTRACT_CSSTYPE_SDSP_IMM (iw),
+ EXTRACT_CSSTYPE_SDSP_IMM (iw), crs2_name);
sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
cpu->sp + EXTRACT_CSSTYPE_SDSP_IMM (iw),
- cpu->fpregs[crs2].v[0]);
- return pc;
+ cpu->regs[crs2]);
+ }
+ return pc;
+ default:
+ TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+ }
+ default:
+ TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+ }
+
+ return pc;
+}
+
+static sim_cia
+execute_f_and_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
+{
+ SIM_DESC sd = CPU_STATE (cpu);
+ const int mask_group_op = 0x3;
+ const int mask_mv_jr = 0xf003;
+ const int match_mv_jr = 0x8002;
+ const int mask_ebk_jalr_add = 0xf003;
+ const int match_ebk_jalr_add = 0x9002;
+
+ int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+ int crs2 = (iw >> OP_SH_CRS2) & OP_MASK_CRS2;
+ int crs1s = ((iw >> OP_SH_CRS1S) & OP_MASK_CRS1S) | 0x8;
+ int crs2s = ((iw >> OP_SH_CRS2S) & OP_MASK_CRS2S) | 0x8;
+ int ciw_rd = crs2s;
+ unsigned_word rvc_imm = EXTRACT_CITYPE_IMM (iw);
+ unsigned_word tmp;
+ sim_cia pc = cpu->pc + 2;
+
+ const char *rd_name = riscv_gpr_names_abi[rd];
+ const char *crs2_name = riscv_gpr_names_abi[crs2];
+ const char *crs1s_name = riscv_gpr_names_abi[crs1s];
+ const char *crs2s_name = riscv_gpr_names_abi[crs2s];
+ const char *ciw_rd_name = crs2s_name;
+
+ const char *frd_name = riscv_fpr_names_abi[rd];
+ const char *fcrs2_name = riscv_fpr_names_abi[crs2];
+ const char *fcrs1s_name = riscv_fpr_names_abi[crs1s];
+ const char *fcrs2s_name = riscv_fpr_names_abi[crs2s];
+ const char *fciw_rd_name = fcrs2s_name;
+
+ switch (op->match & mask_group_op)
+ {
+ case 0:
+ switch (op->match)
+ {
+ case MATCH_C_FLW:
+ /* rv32: c.flw F and C, rv64: c.ld. */
+ if (RISCV_XLEN (cpu) == 32)
+ {
+ TRACE_INSN (cpu, "c.flw %s, %" PRIiTW "(%s);"
+ " // *(%s + %" PRIiTW ") = %s",
+ fcrs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
+ crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), fcrs2s_name);
+ store_frd (cpu, crs2s, EXTEND32 (
+ sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
+ cpu->regs[crs1s]
+ + EXTRACT_CLTYPE_LW_IMM (iw))));
}
else
{
- TRACE_INSN (cpu, "UNHANDLED RV128 INSN: %s", op->name);
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
sim_engine_halt (sd, cpu, NULL, cpu->pc,
sim_signalled, SIM_SIGILL);
}
+ return pc;
+ case MATCH_C_FSW:
+ /* rv32: c.fsw F and C, rv64: c.sd. */
+ if (RISCV_XLEN (cpu) == 32)
+ {
+ TRACE_INSN (cpu, "c.fsw %s, %" PRIiTW "(%s);"
+ " // *(%s + %" PRIiTW ") = %s",
+ fcrs2s_name, EXTRACT_CLTYPE_LW_IMM (iw), crs1s_name,
+ crs1s_name, EXTRACT_CLTYPE_LW_IMM (iw), fcrs2s_name);
+ sim_core_write_unaligned_4 (cpu, cpu->pc, write_map,
+ cpu->regs[crs1s]
+ + EXTRACT_CLTYPE_LW_IMM (iw),
+ cpu->fpregs[crs2s].w[0]);
+ }
+ else
+ {
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+ }
+ return pc;
+ default:
+ TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+ }
+ case 2:
+ switch (op->match)
+ {
+ case MATCH_C_FLWSP:
+ /* rv32: c.flwsp F and C, rv64: c.ldsp. */
+ if (RISCV_XLEN (cpu) == 32)
+ {
+ TRACE_INSN (cpu, "c.flwsp %s, %" PRIiTW "(sp);"
+ " // %s = *(sp + %" PRIiTW ")",
+ frd_name, EXTRACT_CITYPE_LWSP_IMM (iw),
+ frd_name, EXTRACT_CITYPE_LWSP_IMM (iw));
+ store_frd (cpu, rd, EXTEND32 (
+ sim_core_read_unaligned_4 (cpu, cpu->pc, read_map,
+ cpu->sp
+ + EXTRACT_CITYPE_LWSP_IMM (iw))));
+ }
+ else
+ {
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+
+ }
+ return pc;
case MATCH_C_FSWSP:
- /* rv32: c.fswsp, rv64: c.sdsp. */
+ /* rv32: c.fswsp F and C, rv64: c.sdsp. */
if (RISCV_XLEN (cpu) == 32)
{
TRACE_INSN (cpu, "c.fswsp %s, %" PRIiTW "(sp);"
@@ -1251,15 +1351,147 @@ execute_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
}
else
{
- TRACE_INSN (cpu, "c.sdsp %s, %" PRIiTW "(sp);"
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+
+ }
+ return pc;
+ default:
+ TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+ }
+ default:
+ TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+ }
+
+ return pc;
+}
+
+static sim_cia
+execute_d_and_c (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
+{
+ SIM_DESC sd = CPU_STATE (cpu);
+ const int mask_group_op = 0x3;
+ const int mask_mv_jr = 0xf003;
+ const int match_mv_jr = 0x8002;
+ const int mask_ebk_jalr_add = 0xf003;
+ const int match_ebk_jalr_add = 0x9002;
+
+ int rd = (iw >> OP_SH_RD) & OP_MASK_RD;
+ int crs2 = (iw >> OP_SH_CRS2) & OP_MASK_CRS2;
+ int crs1s = ((iw >> OP_SH_CRS1S) & OP_MASK_CRS1S) | 0x8;
+ int crs2s = ((iw >> OP_SH_CRS2S) & OP_MASK_CRS2S) | 0x8;
+ int ciw_rd = crs2s;
+ unsigned_word rvc_imm = EXTRACT_CITYPE_IMM (iw);
+ unsigned_word tmp;
+ sim_cia pc = cpu->pc + 2;
+
+ const char *rd_name = riscv_gpr_names_abi[rd];
+ const char *crs2_name = riscv_gpr_names_abi[crs2];
+ const char *crs1s_name = riscv_gpr_names_abi[crs1s];
+ const char *crs2s_name = riscv_gpr_names_abi[crs2s];
+ const char *ciw_rd_name = crs2s_name;
+
+ const char *frd_name = riscv_fpr_names_abi[rd];
+ const char *fcrs2_name = riscv_fpr_names_abi[crs2];
+ const char *fcrs1s_name = riscv_fpr_names_abi[crs1s];
+ const char *fcrs2s_name = riscv_fpr_names_abi[crs2s];
+ const char *fciw_rd_name = fcrs2s_name;
+
+ switch (op->match & mask_group_op)
+ {
+ case 0:
+ switch (op->match)
+ {
+ case MATCH_C_FLD:
+ if (RISCV_XLEN (cpu) <= 64)
+ {
+ TRACE_INSN (cpu, "c.fld %s, %" PRIiTW "(%s);"
+ " // %s = *(%s + %" PRIiTW ")",
+ fcrs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), fcrs1s_name,
+ fcrs2s_name, fcrs1s_name, EXTRACT_CLTYPE_LD_IMM (iw));
+ /* rv32/64, c.fld D and C instruction. */
+ store_frd64 (cpu, crs2s,
+ sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
+ cpu->regs[crs1s]
+ + EXTRACT_CLTYPE_LD_IMM (iw)));
+ return pc;
+ }
+ else
+ {
+ /* rv128, c.lq instruction, which is C. */
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+ }
+ case MATCH_C_FSD:
+ if (RISCV_XLEN (cpu) <= 64)
+ {
+ /* rv32/64, c.fsd D and C instruction. */
+ TRACE_INSN (cpu, "c.fsd %s, %" PRIiTW "(%s);"
+ " // *(%s + %" PRIiTW ") = %s",
+ fcrs2s_name, EXTRACT_CLTYPE_LD_IMM (iw), crs1s_name,
+ crs1s_name, EXTRACT_CLTYPE_LD_IMM (iw), fcrs2s_name);
+ sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
+ cpu->regs[crs1s]
+ + EXTRACT_CLTYPE_LD_IMM (iw),
+ cpu->fpregs[crs2s].v[0]);
+ return pc;
+ }
+ else
+ {
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+ }
+ default:
+ TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
+ }
+ case 2:
+ switch (op->match)
+ {
+ case MATCH_C_FLDSP:
+ /* rv32/64: c.fldsp D and C, rv128: c.flqsp. */
+ if (RISCV_XLEN (cpu) <= 64)
+ {
+ TRACE_INSN (cpu, "c.fldsp %s, %" PRIiTW "(sp);"
+ " // %s = *(sp + %" PRIiTW ")",
+ frd_name, EXTRACT_CITYPE_LDSP_IMM (iw),
+ frd_name, EXTRACT_CITYPE_LDSP_IMM (iw));
+ store_frd64 (cpu, rd,
+ sim_core_read_unaligned_8 (cpu, cpu->pc, read_map,
+ cpu->sp
+ + EXTRACT_CITYPE_LDSP_IMM (iw)));
+ return pc;
+ }
+ else
+ {
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
+ }
+ case MATCH_C_FSDSP:
+ /* rv32/64: c.fsdsp D and C, rv128: c.fsqsp. */
+ if (RISCV_XLEN (cpu) <= 64)
+ {
+ TRACE_INSN (cpu, "c.fsdsp %s, %" PRIiTW "(sp);"
" // *(sp + %" PRIiTW ") = %s",
- crs2_name, EXTRACT_CSSTYPE_SDSP_IMM (iw),
- EXTRACT_CSSTYPE_SDSP_IMM (iw), crs2_name);
+ fcrs2_name, EXTRACT_CSSTYPE_SDSP_IMM (iw),
+ EXTRACT_CSSTYPE_SDSP_IMM (iw), fcrs2_name);
sim_core_write_unaligned_8 (cpu, cpu->pc, write_map,
cpu->sp + EXTRACT_CSSTYPE_SDSP_IMM (iw),
- cpu->regs[crs2]);
+ cpu->fpregs[crs2].v[0]);
+ return pc;
+ }
+ else
+ {
+ TRACE_INSN (cpu, "DECODE ERROR WITH INSN: %s", op->name);
+ sim_engine_halt (sd, cpu, NULL, cpu->pc,
+ sim_signalled, SIM_SIGILL);
}
- return pc;
default:
TRACE_INSN (cpu, "UNHANDLED INSN: %s", op->name);
sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL);
@@ -2220,6 +2452,10 @@ execute_one (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op)
return execute_f (cpu, iw, op);
case INSN_CLASS_C:
return execute_c (cpu, iw, op);
+ case INSN_CLASS_F_AND_C:
+ return execute_f_and_c (cpu, iw, op);
+ case INSN_CLASS_D_AND_C:
+ return execute_d_and_c (cpu, iw, op);
case INSN_CLASS_ZIFENCEI:
return execute_zifencei (cpu, iw, op);
default:
--
2.7.4
next prev parent reply other threads:[~2021-04-17 17:59 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-17 17:58 [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Jim Wilson
2021-04-17 17:58 ` [PATCH 01/24] RISC-V sim: Fix fence.i Jim Wilson
2021-04-17 20:36 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 02/24] RISC-V sim: Fix for jalr Jim Wilson
2021-04-19 3:41 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 03/24] RISC-V sim: Atomic fixes Jim Wilson
2021-04-19 3:56 ` Mike Frysinger via Gdb-patches
2021-04-21 23:00 ` Jim Wilson
2021-04-22 0:09 ` Mike Frysinger via Gdb-patches
2021-04-22 3:12 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 04/24] RISC-V sim: More atomic fixes Jim Wilson
2021-04-19 3:57 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 05/24] RISC-V sim: Fix stack pointer alignment Jim Wilson
2021-04-19 3:58 ` Mike Frysinger via Gdb-patches
2021-04-21 22:39 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 06/24] RISC-V: Add fp support Jim Wilson
2021-04-19 4:08 ` Mike Frysinger via Gdb-patches
2021-04-21 23:34 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 07/24] RISC-V sim: Add link syscall support Jim Wilson
2021-04-19 4:09 ` Mike Frysinger via Gdb-patches
2021-04-21 23:36 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 08/24] RISC-V sim: Add brk syscall Jim Wilson
2021-04-19 5:24 ` Mike Frysinger via Gdb-patches
2021-04-21 23:51 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 09/24] RISC-V sim: Fix syscall fallback Jim Wilson
2021-04-21 23:38 ` Jim Wilson
2021-04-22 3:23 ` Mike Frysinger via Gdb-patches
2021-04-23 20:35 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 10/24] RISC-V sim: Fix ebreak Jim Wilson
2021-04-19 4:20 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 11/24] RISC-V sim: Fix ebreak, part 2 Jim Wilson
2021-04-19 4:20 ` Mike Frysinger via Gdb-patches
2021-04-21 23:41 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 12/24] RISC-V sim: Add compressed support Jim Wilson
2021-04-19 4:13 ` Mike Frysinger via Gdb-patches
2021-04-21 23:42 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 13/24] RISC-V sim: Add gettimeofday Jim Wilson
2021-04-19 4:19 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 14/24] RISC-V sim: Add csrr*i instructions Jim Wilson
2021-04-19 4:26 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 15/24] RISC-V sim: Improve cycle and instret counts Jim Wilson
2021-04-19 4:25 ` Mike Frysinger via Gdb-patches
2021-04-22 2:26 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 16/24] RISC-V sim: Check sbrk argument Jim Wilson
2021-04-19 5:33 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 17/24] RISC-V sim: Fix tracing typo Jim Wilson
2021-04-19 4:26 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 18/24] RISC-V sim: Improve branch tracing Jim Wilson
2021-04-19 4:27 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 19/24] RISC-V sim: Improve tracing for slt* instructions Jim Wilson
2021-04-19 4:27 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 20/24] RISC-V sim: Set brk to _end if possible Jim Wilson
2021-04-19 5:41 ` Mike Frysinger via Gdb-patches
2021-04-22 2:45 ` Jim Wilson
2021-04-17 17:58 ` [PATCH 21/24] RISC-V sim: Fix mingw builds Jim Wilson
2021-04-19 4:12 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` Jim Wilson [this message]
2021-04-19 4:27 ` [PATCH 22/24] RISC-V sim: Support compressed FP instructions Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 23/24] RISC-V sim: Add zicsr support Jim Wilson
2021-04-19 5:13 ` Mike Frysinger via Gdb-patches
2021-04-17 17:58 ` [PATCH 24/24] RISC-V sim: Fix divw and remw Jim Wilson
2021-04-19 5:10 ` Mike Frysinger via Gdb-patches
2021-04-17 20:38 ` [PATCH 00/24] RISC-V sim: Update from riscv-gnu-toolchain Mike Frysinger via Gdb-patches
2021-04-19 2:33 ` Jim Wilson
2021-04-19 3:23 ` Mike Frysinger via Gdb-patches
2021-04-19 4:32 ` Jim Wilson
2021-04-19 3:42 ` Mike Frysinger via Gdb-patches
2021-04-19 4:37 ` Jim Wilson
2021-04-21 15:47 ` Andrew Burgess
2021-04-21 17:49 ` Andrew Burgess
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