[PATCH 15/24] RISC-V sim: Improve cycle and instret counts.

[Jim Wilson <jimw@sifive.com>]

From: Kito Cheng <kito.cheng@gmail.com>

Update cycleh and instreth in step_once.

	sim/riscv/
	* sim-main.c (step_once): For rv32, handle cycle and instret
	overflow into cycleh and instreth.
---
 sim/riscv/sim-main.c | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c
index 42506a9..4275ee2 100644
--- a/sim/riscv/sim-main.c
+++ b/sim/riscv/sim-main.c
@@ -2261,10 +2261,20 @@ void step_once (SIM_CPU *cpu)
       break;
     }
 
-  /* TODO: Handle overflow into high 32 bits.  */
   /* TODO: Try to use a common counter and only update on demand (reads).  */
-  ++cpu->csr.cycle;
-  ++cpu->csr.instret;
+  if (RISCV_XLEN (cpu) == 32)
+    {
+      unsigned_word old_cycle = cpu->csr.cycle++;
+
+      /* Increase cycleh if cycle is overflowed.  */
+      if (old_cycle > cpu->csr.cycle)
+	cpu->csr.cycleh++;
+    }
+  else
+    ++cpu->csr.cycle;
+
+  cpu->csr.instret = cpu->csr.cycle;
+  cpu->csr.instreth = cpu->csr.cycleh;
 
   cpu->pc = pc;
 }
@@ -2398,6 +2408,10 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int mhartid)
 
   cpu->csr.mimpid = 0x8000;
   cpu->csr.mhartid = mhartid;
+  cpu->csr.cycle = 0;
+  cpu->csr.cycleh = 0;
+  cpu->csr.instret = 0;
+  cpu->csr.instreth = 0;
 }
 \f
 /* Some utils don't like having a NULL environ.  */
-- 
2.7.4