From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id 7707McvegGDvSgAAWB0awg (envelope-from ) for ; Wed, 21 Apr 2021 22:26:19 -0400 Received: by simark.ca (Postfix, from userid 112) id BC5CA1F104; Wed, 21 Apr 2021 22:26:19 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED, MAILING_LIST_MULTI,T_DKIM_INVALID,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.2 Received: from sourceware.org (server2.sourceware.org [8.43.85.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id D98C71E54D for ; Wed, 21 Apr 2021 22:26:18 -0400 (EDT) Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 519BD3857C71; Thu, 22 Apr 2021 02:26:18 +0000 (GMT) Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by sourceware.org (Postfix) with ESMTPS id 5E0973857C71 for ; Thu, 22 Apr 2021 02:26:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 5E0973857C71 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=jimw@sifive.com Received: by mail-ej1-x630.google.com with SMTP id r9so66385724ejj.3 for ; Wed, 21 Apr 2021 19:26:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to; bh=/ZaDB01nC6qdHmcUYfIiXkKGqMHoNJsUHXgiTKYZdCw=; b=ZaFMpSq9Kr2u1fX5Rj3Gva+EJEomlaTFybVCaOxjnRN7I5Bw4hLhMVluenZ3O17nrs x3US6eZFvuh7PQPZFz4J+bEh23Rsz5bb3IwYezuPrXaZw91yB+P87AXO2Cc69c8NZVmM y2snP1m++MU7/6ldE0foEQFcgJOMkztApXnagL44niguSMgY0gRx7yMInaCwIGreBBIa Rclk7on84lt5bSah8Mm3vYlKuMbY5HOVnCuOQhkxKMqWXvUTuUUdD+GSf0N4Wv+fmbHa r6qu9u+nqWRnhLRD3G2mnsW9coyXSRZNMOmLua8s5bhf23/kVcZ92I6MNaXYyihkZSop ALDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to; bh=/ZaDB01nC6qdHmcUYfIiXkKGqMHoNJsUHXgiTKYZdCw=; b=G6OqikkJx0z4rSRo4SDDN8wWAhayr6fEgMU1DJ0j2Y1DqiEWDnpZAD0xg9Nt2HS+U5 2Xgig54iYQkvq+X7lvP3dSVXsHS5nei7wgLSS7kEzdzAf9NtQreLXMPBTYeUVe25DK4C vosQp/Qxn9TYVQ9ZvP7+OijFs9c0Dhr+/HV1IoOdgCulEoW0b7fXLoSRNWJPX7ixJdCc NAb7G26BMPlvcrJHL9UppNuCG2jIYNbnlRtIHziB0+BkVM08SqbGP0P0VuI74yrGktur W4WIMfBwS/jcZ1yIiNExmSW+aO1q6gmsA4HFtNQ1zQcUR+8qlgjpU5ncTryTQi2DMALC Cxig== X-Gm-Message-State: AOAM533ltw8MkUOlKfwrH/aSBCfcVBntRYiB0uBvqFdnnY1TarsuKYSb n3C5PpreWR3MUb2dmsIAGY3o8aWJjv/xejyPJBPv9EZ98l0= X-Google-Smtp-Source: ABdhPJymjdUFA4HwLA5hPyUWW3L4zqkaTxlKqTzikTKUs1EoQpPEAU3A6sqX2S8FnBhpWi9/AeCe/bVScAwxZi7XgQ8= X-Received: by 2002:a17:906:d922:: with SMTP id rn2mr870976ejb.165.1619058374434; Wed, 21 Apr 2021 19:26:14 -0700 (PDT) MIME-Version: 1.0 References: <20210417175831.16413-1-jimw@sifive.com> <20210417175831.16413-16-jimw@sifive.com> In-Reply-To: From: Jim Wilson Date: Wed, 21 Apr 2021 19:26:03 -0700 Message-ID: Subject: Re: [PATCH 15/24] RISC-V sim: Improve cycle and instret counts. To: Jim Wilson , gdb-patches@sourceware.org, Kito Cheng Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces@sourceware.org Sender: "Gdb-patches" On Sun, Apr 18, 2021 at 9:25 PM Mike Frysinger wrote: > On 17 Apr 2021 10:58, Jim Wilson wrote: > > @@ -2398,6 +2408,10 @@ initialize_cpu (SIM_DESC sd, SIM_CPU *cpu, int > mhartid) > > > > cpu->csr.mimpid = 0x8000; > > cpu->csr.mhartid = mhartid; > > + cpu->csr.cycle = 0; > > + cpu->csr.cycleh = 0; > > + cpu->csr.instret = 0; > > + cpu->csr.instreth = 0; > > if this is done so we can re-initialize the CPU and have all the CSR's be > reset, we should do this with a single memset across all of cpu->csr right > ? > are there any that should be preserved ? if there were, i'd argue that > cycle > falls into that bucket too. > Yes, we should memset the csrs before we start initializing the non-zero ones. And while I'm on the subject, we should memset the fprs too, which we can do by just running memset on the entire cpu structure instead of just cpu->regs at the start of initialize_cpu. I'll have to test this change to make sure it works. Jim