* [PATCH 1/4] Change field separator in gdbarch.sh
2017-04-16 14:14 [PATCH 0/4] Remove VEC (CORE_ADDR) Simon Marchi
2017-04-16 14:14 ` [PATCH 3/4] Use std::vector in solib-target lm_info Simon Marchi
2017-04-16 14:14 ` [PATCH 4/4] Remove definition of VEC (CORE_ADDR) Simon Marchi
@ 2017-04-16 14:14 ` Simon Marchi
2017-04-18 20:17 ` Pedro Alves
2017-04-18 20:20 ` Pedro Alves
2017-04-16 14:15 ` [PATCH 2/4] Change return type of gdbarch_software_single_step to vector<CORE_ADDR> Simon Marchi
2017-05-02 17:35 ` [PATCH 0/4] Remove VEC (CORE_ADDR) Simon Marchi
4 siblings, 2 replies; 24+ messages in thread
From: Simon Marchi @ 2017-04-16 14:14 UTC (permalink / raw)
To: gdb-patches; +Cc: Simon Marchi
The fields in the description of the gdbarch interface are separated
using colons. That becomes a problem if we want to use things like
std::vector in it. This patch changes the field separator to use
semicolons instead.
I think there's very little chance we'll ever want to use a semicolon in
one of the fields, but if you think another character would be more
appropriate, let me know.
gdb/ChangeLog:
* gdbarch.sh: Use semi-colon as field separator instead of colon.
* gdbarch.h: Re-generate.
---
gdb/gdbarch.h | 2 +-
gdb/gdbarch.sh | 384 ++++++++++++++++++++++++++++-----------------------------
2 files changed, 193 insertions(+), 193 deletions(-)
diff --git a/gdb/gdbarch.h b/gdb/gdbarch.h
index 4845f239d1..7168e34b9b 100644
--- a/gdb/gdbarch.h
+++ b/gdb/gdbarch.h
@@ -129,7 +129,7 @@ extern void set_gdbarch_bits_big_endian (struct gdbarch *gdbarch, int bits_big_e
/* Number of bits in a char or unsigned char for the target machine.
Just like CHAR_BIT in <limits.h> but describes the target machine.
- v:TARGET_CHAR_BIT:int:char_bit::::8 * sizeof (char):8::0:
+ v;TARGET_CHAR_BIT;int;char_bit;;;;8 * sizeof (char);8;;0;
Number of bits in a short or unsigned short for the target machine. */
diff --git a/gdb/gdbarch.sh b/gdb/gdbarch.sh
index a42dc43774..31bee666b6 100755
--- a/gdb/gdbarch.sh
+++ b/gdb/gdbarch.sh
@@ -65,11 +65,11 @@ ${line}"
else
# The semantics of IFS varies between different SH's. Some
- # treat ``::' as three fields while some treat it as just too.
- # Work around this by eliminating ``::'' ....
- line="`echo "${line}" | sed -e 's/::/: :/g' -e 's/::/: :/g'`"
+ # treat ``;;' as three fields while some treat it as just two.
+ # Work around this by eliminating ``;;'' ....
+ line="`echo "${line}" | sed -e 's/;;/; ;/g' -e 's/;;/; ;/g'`"
- OFS="${IFS}" ; IFS="[:]"
+ OFS="${IFS}" ; IFS="[;]"
eval read ${read} <<EOF
${line}
EOF
@@ -338,35 +338,35 @@ function_list ()
{
# See below (DOCO) for description of each field
cat <<EOF
-i:const struct bfd_arch_info *:bfd_arch_info:::&bfd_default_arch_struct::::gdbarch_bfd_arch_info (gdbarch)->printable_name
+i;const struct bfd_arch_info *;bfd_arch_info;;;&bfd_default_arch_struct;;;;gdbarch_bfd_arch_info (gdbarch)->printable_name
#
-i:enum bfd_endian:byte_order:::BFD_ENDIAN_BIG
-i:enum bfd_endian:byte_order_for_code:::BFD_ENDIAN_BIG
+i;enum bfd_endian;byte_order;;;BFD_ENDIAN_BIG
+i;enum bfd_endian;byte_order_for_code;;;BFD_ENDIAN_BIG
#
-i:enum gdb_osabi:osabi:::GDB_OSABI_UNKNOWN
+i;enum gdb_osabi;osabi;;;GDB_OSABI_UNKNOWN
#
-i:const struct target_desc *:target_desc:::::::host_address_to_string (gdbarch->target_desc)
+i;const struct target_desc *;target_desc;;;;;;;host_address_to_string (gdbarch->target_desc)
# The bit byte-order has to do just with numbering of bits in debugging symbols
# and such. Conceptually, it's quite separate from byte/word byte order.
-v:int:bits_big_endian:::1:(gdbarch->byte_order == BFD_ENDIAN_BIG)::0
+v;int;bits_big_endian;;;1;(gdbarch->byte_order == BFD_ENDIAN_BIG);;0
# Number of bits in a char or unsigned char for the target machine.
# Just like CHAR_BIT in <limits.h> but describes the target machine.
-# v:TARGET_CHAR_BIT:int:char_bit::::8 * sizeof (char):8::0:
+# v;TARGET_CHAR_BIT;int;char_bit;;;;8 * sizeof (char);8;;0;
#
# Number of bits in a short or unsigned short for the target machine.
-v:int:short_bit:::8 * sizeof (short):2*TARGET_CHAR_BIT::0
+v;int;short_bit;;;8 * sizeof (short);2*TARGET_CHAR_BIT;;0
# Number of bits in an int or unsigned int for the target machine.
-v:int:int_bit:::8 * sizeof (int):4*TARGET_CHAR_BIT::0
+v;int;int_bit;;;8 * sizeof (int);4*TARGET_CHAR_BIT;;0
# Number of bits in a long or unsigned long for the target machine.
-v:int:long_bit:::8 * sizeof (long):4*TARGET_CHAR_BIT::0
+v;int;long_bit;;;8 * sizeof (long);4*TARGET_CHAR_BIT;;0
# Number of bits in a long long or unsigned long long for the target
# machine.
-v:int:long_long_bit:::8 * sizeof (LONGEST):2*gdbarch->long_bit::0
+v;int;long_long_bit;;;8 * sizeof (LONGEST);2*gdbarch->long_bit;;0
# Alignment of a long long or unsigned long long for the target
# machine.
-v:int:long_long_align_bit:::8 * sizeof (LONGEST):2*gdbarch->long_bit::0
+v;int;long_long_align_bit;;;8 * sizeof (LONGEST);2*gdbarch->long_bit;;0
# The ABI default bit-size and format for "half", "float", "double", and
# "long double". These bit/format pairs should eventually be combined
@@ -374,25 +374,25 @@ v:int:long_long_align_bit:::8 * sizeof (LONGEST):2*gdbarch->long_bit::0
# Each format describes both the big and little endian layouts (if
# useful).
-v:int:half_bit:::16:2*TARGET_CHAR_BIT::0
-v:const struct floatformat **:half_format:::::floatformats_ieee_half::pformat (gdbarch->half_format)
-v:int:float_bit:::8 * sizeof (float):4*TARGET_CHAR_BIT::0
-v:const struct floatformat **:float_format:::::floatformats_ieee_single::pformat (gdbarch->float_format)
-v:int:double_bit:::8 * sizeof (double):8*TARGET_CHAR_BIT::0
-v:const struct floatformat **:double_format:::::floatformats_ieee_double::pformat (gdbarch->double_format)
-v:int:long_double_bit:::8 * sizeof (long double):8*TARGET_CHAR_BIT::0
-v:const struct floatformat **:long_double_format:::::floatformats_ieee_double::pformat (gdbarch->long_double_format)
+v;int;half_bit;;;16;2*TARGET_CHAR_BIT;;0
+v;const struct floatformat **;half_format;;;;;floatformats_ieee_half;;pformat (gdbarch->half_format)
+v;int;float_bit;;;8 * sizeof (float);4*TARGET_CHAR_BIT;;0
+v;const struct floatformat **;float_format;;;;;floatformats_ieee_single;;pformat (gdbarch->float_format)
+v;int;double_bit;;;8 * sizeof (double);8*TARGET_CHAR_BIT;;0
+v;const struct floatformat **;double_format;;;;;floatformats_ieee_double;;pformat (gdbarch->double_format)
+v;int;long_double_bit;;;8 * sizeof (long double);8*TARGET_CHAR_BIT;;0
+v;const struct floatformat **;long_double_format;;;;;floatformats_ieee_double;;pformat (gdbarch->long_double_format)
# The ABI default bit-size for "wchar_t". wchar_t is a built-in type
# starting with C++11.
-v:int:wchar_bit:::8 * sizeof (wchar_t):4*TARGET_CHAR_BIT::0
+v;int;wchar_bit;;;8 * sizeof (wchar_t);4*TARGET_CHAR_BIT;;0
# One if \`wchar_t' is signed, zero if unsigned.
-v:int:wchar_signed:::1:-1:1
+v;int;wchar_signed;;;1;-1;1
# Returns the floating-point format to be used for values of length LENGTH.
# NAME, if non-NULL, is the type name, which may be used to distinguish
# different target formats of the same length.
-m:const struct floatformat **:floatformat_for_type:const char *name, int length:name, length:0:default_floatformat_for_type::0
+m;const struct floatformat **;floatformat_for_type;const char *name, int length;name, length;0;default_floatformat_for_type;;0
# For most targets, a pointer on the target and its representation as an
# address in GDB have the same size and "look the same". For such a
@@ -404,9 +404,9 @@ m:const struct floatformat **:floatformat_for_type:const char *name, int length:
# gdbarch_address_to_pointer as well.
#
# ptr_bit is the size of a pointer on the target
-v:int:ptr_bit:::8 * sizeof (void*):gdbarch->int_bit::0
+v;int;ptr_bit;;;8 * sizeof (void*);gdbarch->int_bit;;0
# addr_bit is the size of a target address as represented in gdb
-v:int:addr_bit:::8 * sizeof (void*):0:gdbarch_ptr_bit (gdbarch):
+v;int;addr_bit;;;8 * sizeof (void*);0;gdbarch_ptr_bit (gdbarch);
#
# dwarf2_addr_size is the target address size as used in the Dwarf debug
# info. For .debug_frame FDEs, this is supposed to be the target address
@@ -421,114 +421,114 @@ v:int:addr_bit:::8 * sizeof (void*):0:gdbarch_ptr_bit (gdbarch):
# Note that dwarf2_addr_size only needs to be redefined by a target if the
# GCC back-end defines a DWARF2_ADDR_SIZE other than the target pointer size,
# and if Dwarf versions < 4 need to be supported.
-v:int:dwarf2_addr_size:::sizeof (void*):0:gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT:
+v;int;dwarf2_addr_size;;;sizeof (void*);0;gdbarch_ptr_bit (gdbarch) / TARGET_CHAR_BIT;
#
# One if \`char' acts like \`signed char', zero if \`unsigned char'.
-v:int:char_signed:::1:-1:1
+v;int;char_signed;;;1;-1;1
#
-F:CORE_ADDR:read_pc:struct regcache *regcache:regcache
-F:void:write_pc:struct regcache *regcache, CORE_ADDR val:regcache, val
+F;CORE_ADDR;read_pc;struct regcache *regcache;regcache
+F;void;write_pc;struct regcache *regcache, CORE_ADDR val;regcache, val
# Function for getting target's idea of a frame pointer. FIXME: GDB's
# whole scheme for dealing with "frames" and "frame pointers" needs a
# serious shakedown.
-m:void:virtual_frame_pointer:CORE_ADDR pc, int *frame_regnum, LONGEST *frame_offset:pc, frame_regnum, frame_offset:0:legacy_virtual_frame_pointer::0
+m;void;virtual_frame_pointer;CORE_ADDR pc, int *frame_regnum, LONGEST *frame_offset;pc, frame_regnum, frame_offset;0;legacy_virtual_frame_pointer;;0
#
-M:enum register_status:pseudo_register_read:struct regcache *regcache, int cookednum, gdb_byte *buf:regcache, cookednum, buf
+M;enum register_status;pseudo_register_read;struct regcache *regcache, int cookednum, gdb_byte *buf;regcache, cookednum, buf
# Read a register into a new struct value. If the register is wholly
# or partly unavailable, this should call mark_value_bytes_unavailable
# as appropriate. If this is defined, then pseudo_register_read will
# never be called.
-M:struct value *:pseudo_register_read_value:struct regcache *regcache, int cookednum:regcache, cookednum
-M:void:pseudo_register_write:struct regcache *regcache, int cookednum, const gdb_byte *buf:regcache, cookednum, buf
+M;struct value *;pseudo_register_read_value;struct regcache *regcache, int cookednum;regcache, cookednum
+M;void;pseudo_register_write;struct regcache *regcache, int cookednum, const gdb_byte *buf;regcache, cookednum, buf
#
-v:int:num_regs:::0:-1
+v;int;num_regs;;;0;-1
# This macro gives the number of pseudo-registers that live in the
# register namespace but do not get fetched or stored on the target.
# These pseudo-registers may be aliases for other registers,
# combinations of other registers, or they may be computed by GDB.
-v:int:num_pseudo_regs:::0:0::0
+v;int;num_pseudo_regs;;;0;0;;0
# Assemble agent expression bytecode to collect pseudo-register REG.
# Return -1 if something goes wrong, 0 otherwise.
-M:int:ax_pseudo_register_collect:struct agent_expr *ax, int reg:ax, reg
+M;int;ax_pseudo_register_collect;struct agent_expr *ax, int reg;ax, reg
# Assemble agent expression bytecode to push the value of pseudo-register
# REG on the interpreter stack.
# Return -1 if something goes wrong, 0 otherwise.
-M:int:ax_pseudo_register_push_stack:struct agent_expr *ax, int reg:ax, reg
+M;int;ax_pseudo_register_push_stack;struct agent_expr *ax, int reg;ax, reg
# Some targets/architectures can do extra processing/display of
# segmentation faults. E.g., Intel MPX boundary faults.
# Call the architecture dependent function to handle the fault.
# UIOUT is the output stream where the handler will place information.
-M:void:handle_segmentation_fault:struct ui_out *uiout:uiout
+M;void;handle_segmentation_fault;struct ui_out *uiout;uiout
# GDB's standard (or well known) register numbers. These can map onto
# a real register or a pseudo (computed) register or not be defined at
# all (-1).
# gdbarch_sp_regnum will hopefully be replaced by UNWIND_SP.
-v:int:sp_regnum:::-1:-1::0
-v:int:pc_regnum:::-1:-1::0
-v:int:ps_regnum:::-1:-1::0
-v:int:fp0_regnum:::0:-1::0
+v;int;sp_regnum;;;-1;-1;;0
+v;int;pc_regnum;;;-1;-1;;0
+v;int;ps_regnum;;;-1;-1;;0
+v;int;fp0_regnum;;;0;-1;;0
# Convert stab register number (from \`r\' declaration) to a gdb REGNUM.
-m:int:stab_reg_to_regnum:int stab_regnr:stab_regnr::no_op_reg_to_regnum::0
+m;int;stab_reg_to_regnum;int stab_regnr;stab_regnr;;no_op_reg_to_regnum;;0
# Provide a default mapping from a ecoff register number to a gdb REGNUM.
-m:int:ecoff_reg_to_regnum:int ecoff_regnr:ecoff_regnr::no_op_reg_to_regnum::0
+m;int;ecoff_reg_to_regnum;int ecoff_regnr;ecoff_regnr;;no_op_reg_to_regnum;;0
# Convert from an sdb register number to an internal gdb register number.
-m:int:sdb_reg_to_regnum:int sdb_regnr:sdb_regnr::no_op_reg_to_regnum::0
+m;int;sdb_reg_to_regnum;int sdb_regnr;sdb_regnr;;no_op_reg_to_regnum;;0
# Provide a default mapping from a DWARF2 register number to a gdb REGNUM.
# Return -1 for bad REGNUM. Note: Several targets get this wrong.
-m:int:dwarf2_reg_to_regnum:int dwarf2_regnr:dwarf2_regnr::no_op_reg_to_regnum::0
-m:const char *:register_name:int regnr:regnr::0
+m;int;dwarf2_reg_to_regnum;int dwarf2_regnr;dwarf2_regnr;;no_op_reg_to_regnum;;0
+m;const char *;register_name;int regnr;regnr;;0
# Return the type of a register specified by the architecture. Only
# the register cache should call this function directly; others should
# use "register_type".
-M:struct type *:register_type:int reg_nr:reg_nr
+M;struct type *;register_type;int reg_nr;reg_nr
-M:struct frame_id:dummy_id:struct frame_info *this_frame:this_frame
+M;struct frame_id;dummy_id;struct frame_info *this_frame;this_frame
# Implement DUMMY_ID and PUSH_DUMMY_CALL, then delete
# deprecated_fp_regnum.
-v:int:deprecated_fp_regnum:::-1:-1::0
+v;int;deprecated_fp_regnum;;;-1;-1;;0
-M:CORE_ADDR:push_dummy_call:struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr:function, regcache, bp_addr, nargs, args, sp, struct_return, struct_addr
-v:int:call_dummy_location::::AT_ENTRY_POINT::0
-M:CORE_ADDR:push_dummy_code:CORE_ADDR sp, CORE_ADDR funaddr, struct value **args, int nargs, struct type *value_type, CORE_ADDR *real_pc, CORE_ADDR *bp_addr, struct regcache *regcache:sp, funaddr, args, nargs, value_type, real_pc, bp_addr, regcache
+M;CORE_ADDR;push_dummy_call;struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, int nargs, struct value **args, CORE_ADDR sp, int struct_return, CORE_ADDR struct_addr;function, regcache, bp_addr, nargs, args, sp, struct_return, struct_addr
+v;int;call_dummy_location;;;;AT_ENTRY_POINT;;0
+M;CORE_ADDR;push_dummy_code;CORE_ADDR sp, CORE_ADDR funaddr, struct value **args, int nargs, struct type *value_type, CORE_ADDR *real_pc, CORE_ADDR *bp_addr, struct regcache *regcache;sp, funaddr, args, nargs, value_type, real_pc, bp_addr, regcache
# Return true if the code of FRAME is writable.
-m:int:code_of_frame_writable:struct frame_info *frame:frame::default_code_of_frame_writable::0
+m;int;code_of_frame_writable;struct frame_info *frame;frame;;default_code_of_frame_writable;;0
-m:void:print_registers_info:struct ui_file *file, struct frame_info *frame, int regnum, int all:file, frame, regnum, all::default_print_registers_info::0
-m:void:print_float_info:struct ui_file *file, struct frame_info *frame, const char *args:file, frame, args::default_print_float_info::0
-M:void:print_vector_info:struct ui_file *file, struct frame_info *frame, const char *args:file, frame, args
+m;void;print_registers_info;struct ui_file *file, struct frame_info *frame, int regnum, int all;file, frame, regnum, all;;default_print_registers_info;;0
+m;void;print_float_info;struct ui_file *file, struct frame_info *frame, const char *args;file, frame, args;;default_print_float_info;;0
+M;void;print_vector_info;struct ui_file *file, struct frame_info *frame, const char *args;file, frame, args
# MAP a GDB RAW register number onto a simulator register number. See
# also include/...-sim.h.
-m:int:register_sim_regno:int reg_nr:reg_nr::legacy_register_sim_regno::0
-m:int:cannot_fetch_register:int regnum:regnum::cannot_register_not::0
-m:int:cannot_store_register:int regnum:regnum::cannot_register_not::0
+m;int;register_sim_regno;int reg_nr;reg_nr;;legacy_register_sim_regno;;0
+m;int;cannot_fetch_register;int regnum;regnum;;cannot_register_not;;0
+m;int;cannot_store_register;int regnum;regnum;;cannot_register_not;;0
# Determine the address where a longjmp will land and save this address
# in PC. Return nonzero on success.
#
# FRAME corresponds to the longjmp frame.
-F:int:get_longjmp_target:struct frame_info *frame, CORE_ADDR *pc:frame, pc
+F;int;get_longjmp_target;struct frame_info *frame, CORE_ADDR *pc;frame, pc
#
-v:int:believe_pcc_promotion:::::::
+v;int;believe_pcc_promotion;;;;;;;
#
-m:int:convert_register_p:int regnum, struct type *type:regnum, type:0:generic_convert_register_p::0
-f:int:register_to_value:struct frame_info *frame, int regnum, struct type *type, gdb_byte *buf, int *optimizedp, int *unavailablep:frame, regnum, type, buf, optimizedp, unavailablep:0
-f:void:value_to_register:struct frame_info *frame, int regnum, struct type *type, const gdb_byte *buf:frame, regnum, type, buf:0
+m;int;convert_register_p;int regnum, struct type *type;regnum, type;0;generic_convert_register_p;;0
+f;int;register_to_value;struct frame_info *frame, int regnum, struct type *type, gdb_byte *buf, int *optimizedp, int *unavailablep;frame, regnum, type, buf, optimizedp, unavailablep;0
+f;void;value_to_register;struct frame_info *frame, int regnum, struct type *type, const gdb_byte *buf;frame, regnum, type, buf;0
# Construct a value representing the contents of register REGNUM in
# frame FRAME_ID, interpreted as type TYPE. The routine needs to
# allocate and return a struct value with all value attributes
# (but not the value contents) filled in.
-m:struct value *:value_from_register:struct type *type, int regnum, struct frame_id frame_id:type, regnum, frame_id::default_value_from_register::0
+m;struct value *;value_from_register;struct type *type, int regnum, struct frame_id frame_id;type, regnum, frame_id;;default_value_from_register;;0
#
-m:CORE_ADDR:pointer_to_address:struct type *type, const gdb_byte *buf:type, buf::unsigned_pointer_to_address::0
-m:void:address_to_pointer:struct type *type, gdb_byte *buf, CORE_ADDR addr:type, buf, addr::unsigned_address_to_pointer::0
-M:CORE_ADDR:integer_to_address:struct type *type, const gdb_byte *buf:type, buf
+m;CORE_ADDR;pointer_to_address;struct type *type, const gdb_byte *buf;type, buf;;unsigned_pointer_to_address;;0
+m;void;address_to_pointer;struct type *type, gdb_byte *buf, CORE_ADDR addr;type, buf, addr;;unsigned_address_to_pointer;;0
+M;CORE_ADDR;integer_to_address;struct type *type, const gdb_byte *buf;type, buf
# Return the return-value convention that will be used by FUNCTION
# to return a value of type VALTYPE. FUNCTION may be NULL in which
@@ -540,17 +540,17 @@ M:CORE_ADDR:integer_to_address:struct type *type, const gdb_byte *buf:type, buf
# stored into the appropriate register. This can be used when we want
# to force the value returned by a function (see the "return" command
# for instance).
-M:enum return_value_convention:return_value:struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf:function, valtype, regcache, readbuf, writebuf
+M;enum return_value_convention;return_value;struct value *function, struct type *valtype, struct regcache *regcache, gdb_byte *readbuf, const gdb_byte *writebuf;function, valtype, regcache, readbuf, writebuf
# Return true if the return value of function is stored in the first hidden
# parameter. In theory, this feature should be language-dependent, specified
# by language and its ABI, such as C++. Unfortunately, compiler may
# implement it to a target-dependent feature. So that we need such hook here
# to be aware of this in GDB.
-m:int:return_in_first_hidden_param_p:struct type *type:type::default_return_in_first_hidden_param_p::0
+m;int;return_in_first_hidden_param_p;struct type *type;type;;default_return_in_first_hidden_param_p;;0
-m:CORE_ADDR:skip_prologue:CORE_ADDR ip:ip:0:0
-M:CORE_ADDR:skip_main_prologue:CORE_ADDR ip:ip
+m;CORE_ADDR;skip_prologue;CORE_ADDR ip;ip;0;0
+M;CORE_ADDR;skip_main_prologue;CORE_ADDR ip;ip
# On some platforms, a single function may provide multiple entry points,
# e.g. one that is used for function-pointer calls and a different one
# that is used for direct function calls.
@@ -562,28 +562,28 @@ M:CORE_ADDR:skip_main_prologue:CORE_ADDR ip:ip
# actual breakpoint needs to be set. Note that skip_entrypoint is used
# by GDB common code even when debugging optimized code, where skip_prologue
# is not used.
-M:CORE_ADDR:skip_entrypoint:CORE_ADDR ip:ip
+M;CORE_ADDR;skip_entrypoint;CORE_ADDR ip;ip
-f:int:inner_than:CORE_ADDR lhs, CORE_ADDR rhs:lhs, rhs:0:0
-m:const gdb_byte *:breakpoint_from_pc:CORE_ADDR *pcptr, int *lenptr:pcptr, lenptr:0:default_breakpoint_from_pc::0
+f;int;inner_than;CORE_ADDR lhs, CORE_ADDR rhs;lhs, rhs;0;0
+m;const gdb_byte *;breakpoint_from_pc;CORE_ADDR *pcptr, int *lenptr;pcptr, lenptr;0;default_breakpoint_from_pc;;0
# Return the breakpoint kind for this target based on *PCPTR.
-m:int:breakpoint_kind_from_pc:CORE_ADDR *pcptr:pcptr::0:
+m;int;breakpoint_kind_from_pc;CORE_ADDR *pcptr;pcptr;;0;
# Return the software breakpoint from KIND. KIND can have target
# specific meaning like the Z0 kind parameter.
# SIZE is set to the software breakpoint's length in memory.
-m:const gdb_byte *:sw_breakpoint_from_kind:int kind, int *size:kind, size::NULL::0
+m;const gdb_byte *;sw_breakpoint_from_kind;int kind, int *size;kind, size;;NULL;;0
# Return the breakpoint kind for this target based on the current
# processor state (e.g. the current instruction mode on ARM) and the
# *PCPTR. In default, it is gdbarch->breakpoint_kind_from_pc.
-m:int:breakpoint_kind_from_current_state:struct regcache *regcache, CORE_ADDR *pcptr:regcache, pcptr:0:default_breakpoint_kind_from_current_state::0
+m;int;breakpoint_kind_from_current_state;struct regcache *regcache, CORE_ADDR *pcptr;regcache, pcptr;0;default_breakpoint_kind_from_current_state;;0
-M:CORE_ADDR:adjust_breakpoint_address:CORE_ADDR bpaddr:bpaddr
-m:int:memory_insert_breakpoint:struct bp_target_info *bp_tgt:bp_tgt:0:default_memory_insert_breakpoint::0
-m:int:memory_remove_breakpoint:struct bp_target_info *bp_tgt:bp_tgt:0:default_memory_remove_breakpoint::0
-v:CORE_ADDR:decr_pc_after_break:::0:::0
+M;CORE_ADDR;adjust_breakpoint_address;CORE_ADDR bpaddr;bpaddr
+m;int;memory_insert_breakpoint;struct bp_target_info *bp_tgt;bp_tgt;0;default_memory_insert_breakpoint;;0
+m;int;memory_remove_breakpoint;struct bp_target_info *bp_tgt;bp_tgt;0;default_memory_remove_breakpoint;;0
+v;CORE_ADDR;decr_pc_after_break;;;0;;;0
# A function can be addressed by either it's "pointer" (possibly a
# descriptor address) or "entry point" (first executable instruction).
@@ -593,27 +593,27 @@ v:CORE_ADDR:decr_pc_after_break:::0:::0
# corresponds to the "function pointer" and the function's start
# corresponds to the "function entry point" - and hence is redundant.
-v:CORE_ADDR:deprecated_function_start_offset:::0:::0
+v;CORE_ADDR;deprecated_function_start_offset;;;0;;;0
# Return the remote protocol register number associated with this
# register. Normally the identity mapping.
-m:int:remote_register_number:int regno:regno::default_remote_register_number::0
+m;int;remote_register_number;int regno;regno;;default_remote_register_number;;0
# Fetch the target specific address used to represent a load module.
-F:CORE_ADDR:fetch_tls_load_module_address:struct objfile *objfile:objfile
+F;CORE_ADDR;fetch_tls_load_module_address;struct objfile *objfile;objfile
#
-v:CORE_ADDR:frame_args_skip:::0:::0
-M:CORE_ADDR:unwind_pc:struct frame_info *next_frame:next_frame
-M:CORE_ADDR:unwind_sp:struct frame_info *next_frame:next_frame
+v;CORE_ADDR;frame_args_skip;;;0;;;0
+M;CORE_ADDR;unwind_pc;struct frame_info *next_frame;next_frame
+M;CORE_ADDR;unwind_sp;struct frame_info *next_frame;next_frame
# DEPRECATED_FRAME_LOCALS_ADDRESS as been replaced by the per-frame
# frame-base. Enable frame-base before frame-unwind.
-F:int:frame_num_args:struct frame_info *frame:frame
+F;int;frame_num_args;struct frame_info *frame;frame
#
-M:CORE_ADDR:frame_align:CORE_ADDR address:address
-m:int:stabs_argument_has_addr:struct type *type:type::default_stabs_argument_has_addr::0
-v:int:frame_red_zone_size
+M;CORE_ADDR;frame_align;CORE_ADDR address;address
+m;int;stabs_argument_has_addr;struct type *type;type;;default_stabs_argument_has_addr;;0
+v;int;frame_red_zone_size
#
-m:CORE_ADDR:convert_from_func_ptr_addr:CORE_ADDR addr, struct target_ops *targ:addr, targ::convert_from_func_ptr_addr_identity::0
+m;CORE_ADDR;convert_from_func_ptr_addr;CORE_ADDR addr, struct target_ops *targ;addr, targ;;convert_from_func_ptr_addr_identity;;0
# On some machines there are bits in addresses which are not really
# part of the address, but are used by the kernel, the hardware, etc.
# for special purposes. gdbarch_addr_bits_remove takes out any such bits so
@@ -623,7 +623,7 @@ m:CORE_ADDR:convert_from_func_ptr_addr:CORE_ADDR addr, struct target_ops *targ:a
# being a few stray bits in the PC which would mislead us, not as some
# sort of generic thing to handle alignment or segmentation (it's
# possible it should be in TARGET_READ_PC instead).
-m:CORE_ADDR:addr_bits_remove:CORE_ADDR addr:addr::core_addr_identity::0
+m;CORE_ADDR;addr_bits_remove;CORE_ADDR addr;addr;;core_addr_identity;;0
# FIXME/cagney/2001-01-18: This should be split in two. A target method that
# indicates if the target needs software single step. An ISA method to
@@ -640,23 +640,23 @@ m:CORE_ADDR:addr_bits_remove:CORE_ADDR addr:addr::core_addr_identity::0
# the condition and only put the breakpoint at the branch destination if
# the condition is true, so that we ensure forward progress when stepping
# past a conditional branch to self.
-F:VEC (CORE_ADDR) *:software_single_step:struct regcache *regcache:regcache
+F;VEC (CORE_ADDR) *;software_single_step;struct regcache *regcache;regcache
# Return non-zero if the processor is executing a delay slot and a
# further single-step is needed before the instruction finishes.
-M:int:single_step_through_delay:struct frame_info *frame:frame
+M;int;single_step_through_delay;struct frame_info *frame;frame
# FIXME: cagney/2003-08-28: Need to find a better way of selecting the
# disassembler. Perhaps objdump can handle it?
-f:int:print_insn:bfd_vma vma, struct disassemble_info *info:vma, info::0:
-f:CORE_ADDR:skip_trampoline_code:struct frame_info *frame, CORE_ADDR pc:frame, pc::generic_skip_trampoline_code::0
+f;int;print_insn;bfd_vma vma, struct disassemble_info *info;vma, info;;0;
+f;CORE_ADDR;skip_trampoline_code;struct frame_info *frame, CORE_ADDR pc;frame, pc;;generic_skip_trampoline_code;;0
# If in_solib_dynsym_resolve_code() returns true, and SKIP_SOLIB_RESOLVER
# evaluates non-zero, this is the address where the debugger will place
# a step-resume breakpoint to get us past the dynamic linker.
-m:CORE_ADDR:skip_solib_resolver:CORE_ADDR pc:pc::generic_skip_solib_resolver::0
+m;CORE_ADDR;skip_solib_resolver;CORE_ADDR pc;pc;;generic_skip_solib_resolver;;0
# Some systems also have trampoline code for returning from shared libs.
-m:int:in_solib_return_trampoline:CORE_ADDR pc, const char *name:pc, name::generic_in_solib_return_trampoline::0
+m;int;in_solib_return_trampoline;CORE_ADDR pc, const char *name;pc, name;;generic_in_solib_return_trampoline;;0
# A target might have problems with watchpoints as soon as the stack
# frame of the current function has been destroyed. This mostly happens
@@ -667,7 +667,7 @@ m:int:in_solib_return_trampoline:CORE_ADDR pc, const char *name:pc, name::generi
# already been invalidated regardless of the value of addr. Targets
# which don't suffer from that problem could just let this functionality
# untouched.
-m:int:stack_frame_destroyed_p:CORE_ADDR addr:addr:0:generic_stack_frame_destroyed_p::0
+m;int;stack_frame_destroyed_p;CORE_ADDR addr;addr;0;generic_stack_frame_destroyed_p;;0
# Process an ELF symbol in the minimal symbol table in a backend-specific
# way. Normally this hook is supposed to do nothing, however if required,
# then this hook can be used to apply tranformations to symbols that are
@@ -675,8 +675,8 @@ m:int:stack_frame_destroyed_p:CORE_ADDR addr:addr:0:generic_stack_frame_destroye
# to interpret \`st_other' information to mark compressed code symbols so
# that they can be treated in the appropriate manner in the processing of
# the main symbol table and DWARF-2 records.
-F:void:elf_make_msymbol_special:asymbol *sym, struct minimal_symbol *msym:sym, msym
-f:void:coff_make_msymbol_special:int val, struct minimal_symbol *msym:val, msym::default_coff_make_msymbol_special::0
+F;void;elf_make_msymbol_special;asymbol *sym, struct minimal_symbol *msym;sym, msym
+f;void;coff_make_msymbol_special;int val, struct minimal_symbol *msym;val, msym;;default_coff_make_msymbol_special;;0
# Process a symbol in the main symbol table in a backend-specific way.
# Normally this hook is supposed to do nothing, however if required,
# then this hook can be used to apply tranformations to symbols that
@@ -685,7 +685,7 @@ f:void:coff_make_msymbol_special:int val, struct minimal_symbol *msym:val, msym:
# set. This in turn is needed for symbol values seen in GDB to match
# the values used at the runtime by the program itself, for function
# and label references.
-f:void:make_symbol_special:struct symbol *sym, struct objfile *objfile:sym, objfile::default_make_symbol_special::0
+f;void;make_symbol_special;struct symbol *sym, struct objfile *objfile;sym, objfile;;default_make_symbol_special;;0
# Adjust the address retrieved from a DWARF-2 record other than a line
# entry in a backend-specific way. Normally this hook is supposed to
# return the address passed unchanged, however if that is incorrect for
@@ -694,7 +694,7 @@ f:void:make_symbol_special:struct symbol *sym, struct objfile *objfile:sym, objf
# sure addresses in FDE, range records, etc. referring to compressed
# code have the ISA bit set, matching line information and the symbol
# table.
-f:CORE_ADDR:adjust_dwarf2_addr:CORE_ADDR pc:pc::default_adjust_dwarf2_addr::0
+f;CORE_ADDR;adjust_dwarf2_addr;CORE_ADDR pc;pc;;default_adjust_dwarf2_addr;;0
# Adjust the address updated by a line entry in a backend-specific way.
# Normally this hook is supposed to return the address passed unchanged,
# however in the case of inconsistencies in these records, this hook can
@@ -703,20 +703,20 @@ f:CORE_ADDR:adjust_dwarf2_addr:CORE_ADDR pc:pc::default_adjust_dwarf2_addr::0
# are presented with the ISA bit set, which is not always the case. This
# in turn ensures breakpoint addresses are correctly matched against the
# stop PC.
-f:CORE_ADDR:adjust_dwarf2_line:CORE_ADDR addr, int rel:addr, rel::default_adjust_dwarf2_line::0
-v:int:cannot_step_breakpoint:::0:0::0
-v:int:have_nonsteppable_watchpoint:::0:0::0
-F:int:address_class_type_flags:int byte_size, int dwarf2_addr_class:byte_size, dwarf2_addr_class
-M:const char *:address_class_type_flags_to_name:int type_flags:type_flags
+f;CORE_ADDR;adjust_dwarf2_line;CORE_ADDR addr, int rel;addr, rel;;default_adjust_dwarf2_line;;0
+v;int;cannot_step_breakpoint;;;0;0;;0
+v;int;have_nonsteppable_watchpoint;;;0;0;;0
+F;int;address_class_type_flags;int byte_size, int dwarf2_addr_class;byte_size, dwarf2_addr_class
+M;const char *;address_class_type_flags_to_name;int type_flags;type_flags
# Return the appropriate type_flags for the supplied address class.
# This function should return 1 if the address class was recognized and
# type_flags was set, zero otherwise.
-M:int:address_class_name_to_type_flags:const char *name, int *type_flags_ptr:name, type_flags_ptr
+M;int;address_class_name_to_type_flags;const char *name, int *type_flags_ptr;name, type_flags_ptr
# Is a register in a group
-m:int:register_reggroup_p:int regnum, struct reggroup *reggroup:regnum, reggroup::default_register_reggroup_p::0
+m;int;register_reggroup_p;int regnum, struct reggroup *reggroup;regnum, reggroup;;default_register_reggroup_p;;0
# Fetch the pointer to the ith function argument.
-F:CORE_ADDR:fetch_pointer_argument:struct frame_info *frame, int argi, struct type *type:frame, argi, type
+F;CORE_ADDR;fetch_pointer_argument;struct frame_info *frame, int argi, struct type *type;frame, argi, type
# Iterate over all supported register notes in a core file. For each
# supported register note section, the iterator must call CB and pass
@@ -724,55 +724,55 @@ F:CORE_ADDR:fetch_pointer_argument:struct frame_info *frame, int argi, struct ty
# the supported register note sections based on the current register
# values. Otherwise it should enumerate all supported register note
# sections.
-M:void:iterate_over_regset_sections:iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache:cb, cb_data, regcache
+M;void;iterate_over_regset_sections;iterate_over_regset_sections_cb *cb, void *cb_data, const struct regcache *regcache;cb, cb_data, regcache
# Create core file notes
-M:char *:make_corefile_notes:bfd *obfd, int *note_size:obfd, note_size
+M;char *;make_corefile_notes;bfd *obfd, int *note_size;obfd, note_size
# The elfcore writer hook to use to write Linux prpsinfo notes to core
# files. Most Linux architectures use the same prpsinfo32 or
# prpsinfo64 layouts, and so won't need to provide this hook, as we
# call the Linux generic routines in bfd to write prpsinfo notes by
# default.
-F:char *:elfcore_write_linux_prpsinfo:bfd *obfd, char *note_data, int *note_size, const struct elf_internal_linux_prpsinfo *info:obfd, note_data, note_size, info
+F;char *;elfcore_write_linux_prpsinfo;bfd *obfd, char *note_data, int *note_size, const struct elf_internal_linux_prpsinfo *info;obfd, note_data, note_size, info
# Find core file memory regions
-M:int:find_memory_regions:find_memory_region_ftype func, void *data:func, data
+M;int;find_memory_regions;find_memory_region_ftype func, void *data;func, data
# Read offset OFFSET of TARGET_OBJECT_LIBRARIES formatted shared libraries list from
# core file into buffer READBUF with length LEN. Return the number of bytes read
# (zero indicates failure).
# failed, otherwise, return the red length of READBUF.
-M:ULONGEST:core_xfer_shared_libraries:gdb_byte *readbuf, ULONGEST offset, ULONGEST len:readbuf, offset, len
+M;ULONGEST;core_xfer_shared_libraries;gdb_byte *readbuf, ULONGEST offset, ULONGEST len;readbuf, offset, len
# Read offset OFFSET of TARGET_OBJECT_LIBRARIES_AIX formatted shared
# libraries list from core file into buffer READBUF with length LEN.
# Return the number of bytes read (zero indicates failure).
-M:ULONGEST:core_xfer_shared_libraries_aix:gdb_byte *readbuf, ULONGEST offset, ULONGEST len:readbuf, offset, len
+M;ULONGEST;core_xfer_shared_libraries_aix;gdb_byte *readbuf, ULONGEST offset, ULONGEST len;readbuf, offset, len
# How the core target converts a PTID from a core file to a string.
-M:const char *:core_pid_to_str:ptid_t ptid:ptid
+M;const char *;core_pid_to_str;ptid_t ptid;ptid
# How the core target extracts the name of a thread from a core file.
-M:const char *:core_thread_name:struct thread_info *thr:thr
+M;const char *;core_thread_name;struct thread_info *thr;thr
# BFD target to use when generating a core file.
-V:const char *:gcore_bfd_target:::0:0:::pstring (gdbarch->gcore_bfd_target)
+V;const char *;gcore_bfd_target;;;0;0;;;pstring (gdbarch->gcore_bfd_target)
# If the elements of C++ vtables are in-place function descriptors rather
# than normal function pointers (which may point to code or a descriptor),
# set this to one.
-v:int:vtable_function_descriptors:::0:0::0
+v;int;vtable_function_descriptors;;;0;0;;0
# Set if the least significant bit of the delta is used instead of the least
# significant bit of the pfn for pointers to virtual member functions.
-v:int:vbit_in_delta:::0:0::0
+v;int;vbit_in_delta;;;0;0;;0
# Advance PC to next instruction in order to skip a permanent breakpoint.
-f:void:skip_permanent_breakpoint:struct regcache *regcache:regcache:default_skip_permanent_breakpoint:default_skip_permanent_breakpoint::0
+f;void;skip_permanent_breakpoint;struct regcache *regcache;regcache;default_skip_permanent_breakpoint;default_skip_permanent_breakpoint;;0
# The maximum length of an instruction on this architecture in bytes.
-V:ULONGEST:max_insn_length:::0:0
+V;ULONGEST;max_insn_length;;;0;0
# Copy the instruction at FROM to TO, and make any adjustments
# necessary to single-step it at that address.
@@ -803,7 +803,7 @@ V:ULONGEST:max_insn_length:::0:0
# If the instruction cannot execute out of line, return NULL. The
# core falls back to stepping past the instruction in-line instead in
# that case.
-M:struct displaced_step_closure *:displaced_step_copy_insn:CORE_ADDR from, CORE_ADDR to, struct regcache *regs:from, to, regs
+M;struct displaced_step_closure *;displaced_step_copy_insn;CORE_ADDR from, CORE_ADDR to, struct regcache *regs;from, to, regs
# Return true if GDB should use hardware single-stepping to execute
# the displaced instruction identified by CLOSURE. If false,
@@ -814,7 +814,7 @@ M:struct displaced_step_closure *:displaced_step_copy_insn:CORE_ADDR from, CORE_
#
# The default implementation returns false on all targets that
# provide a gdbarch_software_single_step routine, and true otherwise.
-m:int:displaced_step_hw_singlestep:struct displaced_step_closure *closure:closure::default_displaced_step_hw_singlestep::0
+m;int;displaced_step_hw_singlestep;struct displaced_step_closure *closure;closure;;default_displaced_step_hw_singlestep;;0
# Fix up the state resulting from successfully single-stepping a
# displaced instruction, to give the result we would have gotten from
@@ -832,7 +832,7 @@ m:int:displaced_step_hw_singlestep:struct displaced_step_closure *closure:closur
#
# For a general explanation of displaced stepping and how GDB uses it,
# see the comments in infrun.c.
-M:void:displaced_step_fixup:struct displaced_step_closure *closure, CORE_ADDR from, CORE_ADDR to, struct regcache *regs:closure, from, to, regs::NULL
+M;void;displaced_step_fixup;struct displaced_step_closure *closure, CORE_ADDR from, CORE_ADDR to, struct regcache *regs;closure, from, to, regs;;NULL
# Free a closure returned by gdbarch_displaced_step_copy_insn.
#
@@ -844,7 +844,7 @@ M:void:displaced_step_fixup:struct displaced_step_closure *closure, CORE_ADDR fr
#
# For a general explanation of displaced stepping and how GDB uses it,
# see the comments in infrun.c.
-m:void:displaced_step_free_closure:struct displaced_step_closure *closure:closure::NULL::(! gdbarch->displaced_step_free_closure) != (! gdbarch->displaced_step_copy_insn)
+m;void;displaced_step_free_closure;struct displaced_step_closure *closure;closure;;NULL;;(! gdbarch->displaced_step_free_closure) != (! gdbarch->displaced_step_copy_insn)
# Return the address of an appropriate place to put displaced
# instructions while we step over them. There need only be one such
@@ -853,7 +853,7 @@ m:void:displaced_step_free_closure:struct displaced_step_closure *closure:closur
#
# For a general explanation of displaced stepping and how GDB uses it,
# see the comments in infrun.c.
-m:CORE_ADDR:displaced_step_location:void:::NULL::(! gdbarch->displaced_step_location) != (! gdbarch->displaced_step_copy_insn)
+m;CORE_ADDR;displaced_step_location;void;;;NULL;;(! gdbarch->displaced_step_location) != (! gdbarch->displaced_step_copy_insn)
# Relocate an instruction to execute at a different address. OLDLOC
# is the address in the inferior memory where the instruction to
@@ -866,27 +866,27 @@ m:CORE_ADDR:displaced_step_location:void:::NULL::(! gdbarch->displaced_step_loca
# should be adjusted to return to the instruction after OLDLOC;
# relative branches, and other PC-relative instructions need the
# offset adjusted; etc.
-M:void:relocate_instruction:CORE_ADDR *to, CORE_ADDR from:to, from::NULL
+M;void;relocate_instruction;CORE_ADDR *to, CORE_ADDR from;to, from;;NULL
# Refresh overlay mapped state for section OSECT.
-F:void:overlay_update:struct obj_section *osect:osect
+F;void;overlay_update;struct obj_section *osect;osect
-M:const struct target_desc *:core_read_description:struct target_ops *target, bfd *abfd:target, abfd
+M;const struct target_desc *;core_read_description;struct target_ops *target, bfd *abfd;target, abfd
# Handle special encoding of static variables in stabs debug info.
-F:const char *:static_transform_name:const char *name:name
+F;const char *;static_transform_name;const char *name;name
# Set if the address in N_SO or N_FUN stabs may be zero.
-v:int:sofun_address_maybe_missing:::0:0::0
+v;int;sofun_address_maybe_missing;;;0;0;;0
# Parse the instruction at ADDR storing in the record execution log
# the registers REGCACHE and memory ranges that will be affected when
# the instruction executes, along with their current values.
# Return -1 if something goes wrong, 0 otherwise.
-M:int:process_record:struct regcache *regcache, CORE_ADDR addr:regcache, addr
+M;int;process_record;struct regcache *regcache, CORE_ADDR addr;regcache, addr
# Save process state after a signal.
# Return -1 if something goes wrong, 0 otherwise.
-M:int:process_record_signal:struct regcache *regcache, enum gdb_signal signal:regcache, signal
+M;int;process_record_signal;struct regcache *regcache, enum gdb_signal signal;regcache, signal
# Signal translation: translate inferior's signal (target's) number
# into GDB's representation. The implementation of this method must
@@ -895,7 +895,7 @@ M:int:process_record_signal:struct regcache *regcache, enum gdb_signal signal:re
# headers. This is mainly used when cross-debugging core files ---
# "Live" targets hide the translation behind the target interface
# (target_wait, target_resume, etc.).
-M:enum gdb_signal:gdb_signal_from_target:int signo:signo
+M;enum gdb_signal;gdb_signal_from_target;int signo;signo
# Signal translation: translate the GDB's internal signal number into
# the inferior's signal (target's) representation. The implementation
@@ -904,26 +904,26 @@ M:enum gdb_signal:gdb_signal_from_target:int signo:signo
# header, or similar headers.
# Return the target signal number if found, or -1 if the GDB internal
# signal number is invalid.
-M:int:gdb_signal_to_target:enum gdb_signal signal:signal
+M;int;gdb_signal_to_target;enum gdb_signal signal;signal
# Extra signal info inspection.
#
# Return a type suitable to inspect extra signal information.
-M:struct type *:get_siginfo_type:void:
+M;struct type *;get_siginfo_type;void;
# Record architecture-specific information from the symbol table.
-M:void:record_special_symbol:struct objfile *objfile, asymbol *sym:objfile, sym
+M;void;record_special_symbol;struct objfile *objfile, asymbol *sym;objfile, sym
# Function for the 'catch syscall' feature.
# Get architecture-specific system calls information from registers.
-M:LONGEST:get_syscall_number:ptid_t ptid:ptid
+M;LONGEST;get_syscall_number;ptid_t ptid;ptid
# The filename of the XML syscall for this architecture.
-v:const char *:xml_syscall_file:::0:0::0:pstring (gdbarch->xml_syscall_file)
+v;const char *;xml_syscall_file;;;0;0;;0;pstring (gdbarch->xml_syscall_file)
# Information about system calls from this architecture
-v:struct syscalls_info *:syscalls_info:::0:0::0:host_address_to_string (gdbarch->syscalls_info)
+v;struct syscalls_info *;syscalls_info;;;0;0;;0;host_address_to_string (gdbarch->syscalls_info)
# SystemTap related fields and functions.
@@ -934,11 +934,11 @@ v:struct syscalls_info *:syscalls_info:::0:0::0:host_address_to_string (gdbarch-
# \$10 ;; integer constant 10
#
# in this case, this prefix would be the character \`\$\'.
-v:const char *const *:stap_integer_prefixes:::0:0::0:pstring_list (gdbarch->stap_integer_prefixes)
+v;const char *const *;stap_integer_prefixes;;;0;0;;0;pstring_list (gdbarch->stap_integer_prefixes)
# A NULL-terminated array of suffixes used to mark an integer constant
# on the architecture's assembly.
-v:const char *const *:stap_integer_suffixes:::0:0::0:pstring_list (gdbarch->stap_integer_suffixes)
+v;const char *const *;stap_integer_suffixes;;;0;0;;0;pstring_list (gdbarch->stap_integer_suffixes)
# A NULL-terminated array of prefixes used to mark a register name on
# the architecture's assembly.
@@ -947,11 +947,11 @@ v:const char *const *:stap_integer_suffixes:::0:0::0:pstring_list (gdbarch->stap
# \%eax ;; register eax
#
# in this case, this prefix would be the character \`\%\'.
-v:const char *const *:stap_register_prefixes:::0:0::0:pstring_list (gdbarch->stap_register_prefixes)
+v;const char *const *;stap_register_prefixes;;;0;0;;0;pstring_list (gdbarch->stap_register_prefixes)
# A NULL-terminated array of suffixes used to mark a register name on
# the architecture's assembly.
-v:const char *const *:stap_register_suffixes:::0:0::0:pstring_list (gdbarch->stap_register_suffixes)
+v;const char *const *;stap_register_suffixes;;;0;0;;0;pstring_list (gdbarch->stap_register_suffixes)
# A NULL-terminated array of prefixes used to mark a register
# indirection on the architecture's assembly.
@@ -963,7 +963,7 @@ v:const char *const *:stap_register_suffixes:::0:0::0:pstring_list (gdbarch->sta
#
# Please note that we use the indirection prefix also for register
# displacement, e.g., \`4\(\%eax\)\' on x86.
-v:const char *const *:stap_register_indirection_prefixes:::0:0::0:pstring_list (gdbarch->stap_register_indirection_prefixes)
+v;const char *const *;stap_register_indirection_prefixes;;;0;0;;0;pstring_list (gdbarch->stap_register_indirection_prefixes)
# A NULL-terminated array of suffixes used to mark a register
# indirection on the architecture's assembly.
@@ -975,7 +975,7 @@ v:const char *const *:stap_register_indirection_prefixes:::0:0::0:pstring_list (
#
# Please note that we use the indirection suffix also for register
# displacement, e.g., \`4\(\%eax\)\' on x86.
-v:const char *const *:stap_register_indirection_suffixes:::0:0::0:pstring_list (gdbarch->stap_register_indirection_suffixes)
+v;const char *const *;stap_register_indirection_suffixes;;;0;0;;0;pstring_list (gdbarch->stap_register_indirection_suffixes)
# Prefix(es) used to name a register using GDB's nomenclature.
#
@@ -983,10 +983,10 @@ v:const char *const *:stap_register_indirection_suffixes:::0:0::0:pstring_list (
# language (e.g., \`10\' is the 10th general-purpose register). However,
# inside GDB this same register has an \`r\' appended to its name, so the 10th
# register would be represented as \`r10\' internally.
-v:const char *:stap_gdb_register_prefix:::0:0::0:pstring (gdbarch->stap_gdb_register_prefix)
+v;const char *;stap_gdb_register_prefix;;;0;0;;0;pstring (gdbarch->stap_gdb_register_prefix)
# Suffix used to name a register using GDB's nomenclature.
-v:const char *:stap_gdb_register_suffix:::0:0::0:pstring (gdbarch->stap_gdb_register_suffix)
+v;const char *;stap_gdb_register_suffix;;;0;0;;0;pstring (gdbarch->stap_gdb_register_suffix)
# Check if S is a single operand.
#
@@ -1000,7 +1000,7 @@ v:const char *:stap_gdb_register_suffix:::0:0::0:pstring (gdbarch->stap_gdb_regi
# and return 1 if some were found, or zero otherwise. Please try to match
# as much info as you can from the string, i.e., if you have to match
# something like \`\(\%\', do not match just the \`\(\'.
-M:int:stap_is_single_operand:const char *s:s
+M;int;stap_is_single_operand;const char *s;s
# Function used to handle a "special case" in the parser.
#
@@ -1023,53 +1023,53 @@ M:int:stap_is_single_operand:const char *s:s
# if the token was not recognized as a special token (in this case, returning
# zero means that the special parser is deferring the parsing to the generic
# parser), and should advance the buffer pointer (p->arg).
-M:int:stap_parse_special_token:struct stap_parse_info *p:p
+M;int;stap_parse_special_token;struct stap_parse_info *p;p
# DTrace related functions.
# The expression to compute the NARTGth+1 argument to a DTrace USDT probe.
# NARG must be >= 0.
-M:void:dtrace_parse_probe_argument:struct parser_state *pstate, int narg:pstate, narg
+M;void;dtrace_parse_probe_argument;struct parser_state *pstate, int narg;pstate, narg
# True if the given ADDR does not contain the instruction sequence
# corresponding to a disabled DTrace is-enabled probe.
-M:int:dtrace_probe_is_enabled:CORE_ADDR addr:addr
+M;int;dtrace_probe_is_enabled;CORE_ADDR addr;addr
# Enable a DTrace is-enabled probe at ADDR.
-M:void:dtrace_enable_probe:CORE_ADDR addr:addr
+M;void;dtrace_enable_probe;CORE_ADDR addr;addr
# Disable a DTrace is-enabled probe at ADDR.
-M:void:dtrace_disable_probe:CORE_ADDR addr:addr
+M;void;dtrace_disable_probe;CORE_ADDR addr;addr
# True if the list of shared libraries is one and only for all
# processes, as opposed to a list of shared libraries per inferior.
# This usually means that all processes, although may or may not share
# an address space, will see the same set of symbols at the same
# addresses.
-v:int:has_global_solist:::0:0::0
+v;int;has_global_solist;;;0;0;;0
# On some targets, even though each inferior has its own private
# address space, the debug interface takes care of making breakpoints
# visible to all address spaces automatically. For such cases,
# this property should be set to true.
-v:int:has_global_breakpoints:::0:0::0
+v;int;has_global_breakpoints;;;0;0;;0
# True if inferiors share an address space (e.g., uClinux).
-m:int:has_shared_address_space:void:::default_has_shared_address_space::0
+m;int;has_shared_address_space;void;;;default_has_shared_address_space;;0
# True if a fast tracepoint can be set at an address.
-m:int:fast_tracepoint_valid_at:CORE_ADDR addr, char **msg:addr, msg::default_fast_tracepoint_valid_at::0
+m;int;fast_tracepoint_valid_at;CORE_ADDR addr, char **msg;addr, msg;;default_fast_tracepoint_valid_at;;0
# Guess register state based on tracepoint location. Used for tracepoints
# where no registers have been collected, but there's only one location,
# allowing us to guess the PC value, and perhaps some other registers.
# On entry, regcache has all registers marked as unavailable.
-m:void:guess_tracepoint_registers:struct regcache *regcache, CORE_ADDR addr:regcache, addr::default_guess_tracepoint_registers::0
+m;void;guess_tracepoint_registers;struct regcache *regcache, CORE_ADDR addr;regcache, addr;;default_guess_tracepoint_registers;;0
# Return the "auto" target charset.
-f:const char *:auto_charset:void::default_auto_charset:default_auto_charset::0
+f;const char *;auto_charset;void;;default_auto_charset;default_auto_charset;;0
# Return the "auto" target wide charset.
-f:const char *:auto_wide_charset:void::default_auto_wide_charset:default_auto_wide_charset::0
+f;const char *;auto_wide_charset;void;;default_auto_wide_charset;default_auto_wide_charset;;0
# If non-empty, this is a file extension that will be opened in place
# of the file extension reported by the shared library list.
@@ -1077,27 +1077,27 @@ f:const char *:auto_wide_charset:void::default_auto_wide_charset:default_auto_wi
# This is most useful for toolchains that use a post-linker tool,
# where the names of the files run on the target differ in extension
# compared to the names of the files GDB should load for debug info.
-v:const char *:solib_symbols_extension:::::::pstring (gdbarch->solib_symbols_extension)
+v;const char *;solib_symbols_extension;;;;;;;pstring (gdbarch->solib_symbols_extension)
# If true, the target OS has DOS-based file system semantics. That
# is, absolute paths include a drive name, and the backslash is
# considered a directory separator.
-v:int:has_dos_based_file_system:::0:0::0
+v;int;has_dos_based_file_system;;;0;0;;0
# Generate bytecodes to collect the return address in a frame.
# Since the bytecodes run on the target, possibly with GDB not even
# connected, the full unwinding machinery is not available, and
# typically this function will issue bytecodes for one or more likely
# places that the return address may be found.
-m:void:gen_return_address:struct agent_expr *ax, struct axs_value *value, CORE_ADDR scope:ax, value, scope::default_gen_return_address::0
+m;void;gen_return_address;struct agent_expr *ax, struct axs_value *value, CORE_ADDR scope;ax, value, scope;;default_gen_return_address;;0
# Implement the "info proc" command.
-M:void:info_proc:const char *args, enum info_proc_what what:args, what
+M;void;info_proc;const char *args, enum info_proc_what what;args, what
# Implement the "info proc" command for core files. Noe that there
# are two "info_proc"-like methods on gdbarch -- one for core files,
# one for live targets.
-M:void:core_info_proc:const char *args, enum info_proc_what what:args, what
+M;void;core_info_proc;const char *args, enum info_proc_what what;args, what
# Iterate over all objfiles in the order that makes the most sense
# for the architecture to make global symbol searches.
@@ -1112,66 +1112,66 @@ M:void:core_info_proc:const char *args, enum info_proc_what what:args, what
#
# If not NULL, CURRENT_OBJFILE corresponds to the objfile being
# inspected when the symbol search was requested.
-m:void:iterate_over_objfiles_in_search_order:iterate_over_objfiles_in_search_order_cb_ftype *cb, void *cb_data, struct objfile *current_objfile:cb, cb_data, current_objfile:0:default_iterate_over_objfiles_in_search_order::0
+m;void;iterate_over_objfiles_in_search_order;iterate_over_objfiles_in_search_order_cb_ftype *cb, void *cb_data, struct objfile *current_objfile;cb, cb_data, current_objfile;0;default_iterate_over_objfiles_in_search_order;;0
# Ravenscar arch-dependent ops.
-v:struct ravenscar_arch_ops *:ravenscar_ops:::NULL:NULL::0:host_address_to_string (gdbarch->ravenscar_ops)
+v;struct ravenscar_arch_ops *;ravenscar_ops;;;NULL;NULL;;0;host_address_to_string (gdbarch->ravenscar_ops)
# Return non-zero if the instruction at ADDR is a call; zero otherwise.
-m:int:insn_is_call:CORE_ADDR addr:addr::default_insn_is_call::0
+m;int;insn_is_call;CORE_ADDR addr;addr;;default_insn_is_call;;0
# Return non-zero if the instruction at ADDR is a return; zero otherwise.
-m:int:insn_is_ret:CORE_ADDR addr:addr::default_insn_is_ret::0
+m;int;insn_is_ret;CORE_ADDR addr;addr;;default_insn_is_ret;;0
# Return non-zero if the instruction at ADDR is a jump; zero otherwise.
-m:int:insn_is_jump:CORE_ADDR addr:addr::default_insn_is_jump::0
+m;int;insn_is_jump;CORE_ADDR addr;addr;;default_insn_is_jump;;0
# Read one auxv entry from *READPTR, not reading locations >= ENDPTR.
# Return 0 if *READPTR is already at the end of the buffer.
# Return -1 if there is insufficient buffer for a whole entry.
# Return 1 if an entry was read into *TYPEP and *VALP.
-M:int:auxv_parse:gdb_byte **readptr, gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp:readptr, endptr, typep, valp
+M;int;auxv_parse;gdb_byte **readptr, gdb_byte *endptr, CORE_ADDR *typep, CORE_ADDR *valp;readptr, endptr, typep, valp
# Print the description of a single auxv entry described by TYPE and VAL
# to FILE.
-m:void:print_auxv_entry:struct ui_file *file, CORE_ADDR type, CORE_ADDR val:file, type, val::default_print_auxv_entry::0
+m;void;print_auxv_entry;struct ui_file *file, CORE_ADDR type, CORE_ADDR val;file, type, val;;default_print_auxv_entry;;0
# Find the address range of the current inferior's vsyscall/vDSO, and
# write it to *RANGE. If the vsyscall's length can't be determined, a
# range with zero length is returned. Returns true if the vsyscall is
# found, false otherwise.
-m:int:vsyscall_range:struct mem_range *range:range::default_vsyscall_range::0
+m;int;vsyscall_range;struct mem_range *range;range;;default_vsyscall_range;;0
# Allocate SIZE bytes of PROT protected page aligned memory in inferior.
# PROT has GDB_MMAP_PROT_* bitmask format.
# Throw an error if it is not possible. Returned address is always valid.
-f:CORE_ADDR:infcall_mmap:CORE_ADDR size, unsigned prot:size, prot::default_infcall_mmap::0
+f;CORE_ADDR;infcall_mmap;CORE_ADDR size, unsigned prot;size, prot;;default_infcall_mmap;;0
# Deallocate SIZE bytes of memory at ADDR in inferior from gdbarch_infcall_mmap.
# Print a warning if it is not possible.
-f:void:infcall_munmap:CORE_ADDR addr, CORE_ADDR size:addr, size::default_infcall_munmap::0
+f;void;infcall_munmap;CORE_ADDR addr, CORE_ADDR size;addr, size;;default_infcall_munmap;;0
# Return string (caller has to use xfree for it) with options for GCC
# to produce code for this target, typically "-m64", "-m32" or "-m31".
# These options are put before CU's DW_AT_producer compilation options so that
# they can override it. Method may also return NULL.
-m:char *:gcc_target_options:void:::default_gcc_target_options::0
+m;char *;gcc_target_options;void;;;default_gcc_target_options;;0
# Return a regular expression that matches names used by this
# architecture in GNU configury triplets. The result is statically
# allocated and must not be freed. The default implementation simply
# returns the BFD architecture name, which is correct in nearly every
# case.
-m:const char *:gnu_triplet_regexp:void:::default_gnu_triplet_regexp::0
+m;const char *;gnu_triplet_regexp;void;;;default_gnu_triplet_regexp;;0
# Return the size in 8-bit bytes of an addressable memory unit on this
# architecture. This corresponds to the number of 8-bit bytes associated to
# each address in memory.
-m:int:addressable_memory_unit_size:void:::default_addressable_memory_unit_size::0
+m;int;addressable_memory_unit_size;void;;;default_addressable_memory_unit_size;;0
# Functions for allowing a target to modify its disassembler options.
-v:char **:disassembler_options:::0:0::0:pstring_ptr (gdbarch->disassembler_options)
-v:const disasm_options_t *:valid_disassembler_options:::0:0::0:host_address_to_string (gdbarch->valid_disassembler_options)
+v;char **;disassembler_options;;;0;0;;0;pstring_ptr (gdbarch->disassembler_options)
+v;const disasm_options_t *;valid_disassembler_options;;;0;0;;0;host_address_to_string (gdbarch->valid_disassembler_options)
EOF
}
@@ -1963,7 +1963,7 @@ gdbarch_dump (struct gdbarch *gdbarch, struct ui_file *file)
"gdbarch_dump: GDB_NM_FILE = %s\\n",
gdb_nm_file);
EOF
-function_list | sort -t: -k 3 | while do_read
+function_list | sort '-t;' -k 3 | while do_read
do
# First the predicate
if class_is_predicate_p
--
2.12.2
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 2/4] Change return type of gdbarch_software_single_step to vector<CORE_ADDR>
2017-04-16 14:14 [PATCH 0/4] Remove VEC (CORE_ADDR) Simon Marchi
` (2 preceding siblings ...)
2017-04-16 14:14 ` [PATCH 1/4] Change field separator in gdbarch.sh Simon Marchi
@ 2017-04-16 14:15 ` Simon Marchi
2017-04-18 20:17 ` Pedro Alves
2017-05-02 17:35 ` [PATCH 0/4] Remove VEC (CORE_ADDR) Simon Marchi
4 siblings, 1 reply; 24+ messages in thread
From: Simon Marchi @ 2017-04-16 14:15 UTC (permalink / raw)
To: gdb-patches; +Cc: Simon Marchi
This is a relatively straightforward patch that changes
gdbarch_software_single_step so it returns an std::vector<CORE_ADDR>
instead of a VEC (CORE_ADDR).
gdb/ChangeLog:
* gdbarch.sh (software_single_step): Change return type to
std::vector<CORE_ADDR>.
* gdbarch.c, gdbarch.h: Re-generate.
* arch/arm-get-next-pcs.c (thumb_deal_with_atomic_sequence_raw):
Adjust.
(arm_deal_with_atomic_sequence_raw): Adjust.
(thumb_get_next_pcs_raw): Adjust.
(arm_get_next_pcs_raw): Adjust.
(arm_get_next_pcs): Adjust.
* arch/arm-get-next-pcs.h (arm_get_next_pcs): Adjust.
* aarch64-tdep.c (aarch64_software_single_step): Adjust.
* alpha-tdep.c (alpha_deal_with_atomic_sequence): Adjust.
(alpha_software_single_step): Adjust.
* alpha-tdep.h (alpha_software_single_step): Adjust.
* arm-linux-tdep.c (arm_linux_software_single_step): Adjust.
* arm-tdep.c (arm_software_single_step): Adjust.
(arm_breakpoint_kind_from_current_state): Adjust.
* arm-tdep.h (arm_software_single_step): Adjust.
* breakpoint.c (insert_single_step_breakpoint): Adjust.
* cris-tdep.c (cris_software_single_step): Adjust.
* mips-tdep.c (mips_deal_with_atomic_sequence): Adjust.
(micromips_deal_with_atomic_sequence): Adjust.
(deal_with_atomic_sequence): Adjust.
(mips_software_single_step): Adjust.
* mips-tdep.h (mips_software_single_step): Adjust.
* moxie-tdep.c (moxie_software_single_step): Adjust.
* nios2-tdep.c (nios2_software_single_step): Adjust.
* ppc-tdep.h (ppc_deal_with_atomic_sequence): Adjust.
* rs6000-aix-tdep.c (rs6000_software_single_step): Adjust.
* rs6000-tdep.c (ppc_deal_with_atomic_sequence): Adjust.
* s390-linux-tdep.c (s390_software_single_step): Adjust.
* sparc-tdep.c (sparc_software_single_step): Adjust.
* spu-tdep.c (spu_software_single_step): Adjust.
* tic6x-tdep.c (tic6x_software_single_step): Adjust.
gdb/gdbserver/ChangeLog:
* linux-arm-low.c (arm_gdbserver_get_next_pcs): Adjust to
software_single_step change of return type to
std::vector<CORE_ADDR>.
* linux-low.c (install_software_single_step_breakpoints):
Likewise.
* linux-low.h (install_software_single_step_breakpoints):
Likewise.
---
gdb/aarch64-tdep.c | 17 +++++----
gdb/alpha-tdep.c | 23 ++++++-----
gdb/alpha-tdep.h | 3 +-
gdb/arch/arm-get-next-pcs.c | 89 +++++++++++++++++++++----------------------
gdb/arch/arm-get-next-pcs.h | 5 ++-
gdb/arm-linux-tdep.c | 21 +++-------
gdb/arm-tdep.c | 30 +++------------
gdb/arm-tdep.h | 4 +-
gdb/breakpoint.c | 10 ++---
gdb/cris-tdep.c | 8 ++--
gdb/gdbarch.c | 2 +-
gdb/gdbarch.h | 5 ++-
gdb/gdbarch.sh | 3 +-
gdb/gdbserver/linux-arm-low.c | 7 +---
gdb/gdbserver/linux-low.c | 9 +----
gdb/gdbserver/linux-low.h | 2 +-
gdb/mips-tdep.c | 57 +++++++++++++--------------
gdb/mips-tdep.h | 3 +-
gdb/moxie-tdep.c | 26 ++++++-------
gdb/nios2-tdep.c | 7 +---
gdb/ppc-tdep.h | 3 +-
gdb/rs6000-aix-tdep.c | 10 ++---
gdb/rs6000-tdep.c | 15 ++++----
gdb/s390-linux-tdep.c | 15 +++-----
gdb/sparc-tdep.c | 8 ++--
gdb/spu-tdep.c | 9 ++---
gdb/tic6x-tdep.c | 7 +---
27 files changed, 176 insertions(+), 222 deletions(-)
diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c
index 28c2573d18..ff5bc04ea2 100644
--- a/gdb/aarch64-tdep.c
+++ b/gdb/aarch64-tdep.c
@@ -2417,7 +2417,7 @@ value_of_aarch64_user_reg (struct frame_info *frame, const void *baton)
/* Implement the "software_single_step" gdbarch method, needed to
single step through atomic sequences on AArch64. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
aarch64_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
@@ -2435,14 +2435,13 @@ aarch64_software_single_step (struct regcache *regcache)
int bc_insn_count = 0; /* Conditional branch instruction count. */
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
aarch64_inst inst;
- VEC (CORE_ADDR) *next_pcs = NULL;
if (aarch64_decode_insn (insn, &inst, 1) != 0)
- return NULL;
+ return {};
/* Look for a Load Exclusive instruction which begins the sequence. */
if (inst.opcode->iclass != ldstexcl || bit (insn, 22) == 0)
- return NULL;
+ return {};
for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
{
@@ -2451,14 +2450,14 @@ aarch64_software_single_step (struct regcache *regcache)
byte_order_for_code);
if (aarch64_decode_insn (insn, &inst, 1) != 0)
- return NULL;
+ return {};
/* Check if the instruction is a conditional branch. */
if (inst.opcode->iclass == condbranch)
{
gdb_assert (inst.operands[0].type == AARCH64_OPND_ADDR_PCREL19);
if (bc_insn_count >= 1)
- return NULL;
+ return {};
/* It is, so we'll try to set a breakpoint at the destination. */
breaks[1] = loc + inst.operands[0].imm.value;
@@ -2477,7 +2476,7 @@ aarch64_software_single_step (struct regcache *regcache)
/* We didn't find a closing Store Exclusive instruction, fall back. */
if (!closing_insn)
- return NULL;
+ return {};
/* Insert breakpoint after the end of the atomic sequence. */
breaks[0] = loc + insn_size;
@@ -2489,10 +2488,12 @@ aarch64_software_single_step (struct regcache *regcache)
|| (breaks[1] >= pc && breaks[1] <= closing_insn)))
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
/* Insert the breakpoint at the end of the sequence, and one at the
destination of the conditional branch, if it exists. */
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+ next_pcs.push_back (breaks[index]);
return next_pcs;
}
diff --git a/gdb/alpha-tdep.c b/gdb/alpha-tdep.c
index 7c521db24c..d62566c4b0 100644
--- a/gdb/alpha-tdep.c
+++ b/gdb/alpha-tdep.c
@@ -765,7 +765,7 @@ static const int stq_c_opcode = 0x2f;
is found, attempt to step through it. A breakpoint is placed at the end of
the sequence. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
alpha_deal_with_atomic_sequence (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
@@ -779,12 +779,11 @@ alpha_deal_with_atomic_sequence (struct regcache *regcache)
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
const int atomic_sequence_length = 16; /* Instruction sequence length. */
int bc_insn_count = 0; /* Conditional branch instruction count. */
- VEC (CORE_ADDR) *next_pcs = NULL;
/* Assume all atomic sequences start with a LDL_L/LDQ_L instruction. */
if (INSN_OPCODE (insn) != ldl_l_opcode
&& INSN_OPCODE (insn) != ldq_l_opcode)
- return NULL;
+ return {};
/* Assume that no atomic sequence is longer than "atomic_sequence_length"
instructions. */
@@ -803,8 +802,8 @@ alpha_deal_with_atomic_sequence (struct regcache *regcache)
immediate = (immediate ^ 0x400000) - 0x400000;
if (bc_insn_count >= 1)
- return NULL; /* More than one branch found, fallback
- to the standard single-step code. */
+ return {}; /* More than one branch found, fallback
+ to the standard single-step code. */
breaks[1] = loc + ALPHA_INSN_SIZE + immediate;
@@ -820,7 +819,7 @@ alpha_deal_with_atomic_sequence (struct regcache *regcache)
/* Assume that the atomic sequence ends with a STL_C/STQ_C instruction. */
if (INSN_OPCODE (insn) != stl_c_opcode
&& INSN_OPCODE (insn) != stq_c_opcode)
- return NULL;
+ return {};
closing_insn = loc;
loc += ALPHA_INSN_SIZE;
@@ -835,8 +834,10 @@ alpha_deal_with_atomic_sequence (struct regcache *regcache)
|| (breaks[1] >= pc && breaks[1] <= closing_insn)))
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+ next_pcs.push_back (breaks[index]);
return next_pcs;
}
@@ -1717,17 +1718,15 @@ alpha_next_pc (struct regcache *regcache, CORE_ADDR pc)
return (pc + ALPHA_INSN_SIZE);
}
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
alpha_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
CORE_ADDR pc;
- VEC (CORE_ADDR) *next_pcs = NULL;
- pc = regcache_read_pc (regcache);
+ pc = alpha_next_pc (regcache, regcache_read_pc (regcache));
- VEC_safe_push (CORE_ADDR, next_pcs, alpha_next_pc (regcache, pc));
- return next_pcs;
+ return {pc};
}
\f
diff --git a/gdb/alpha-tdep.h b/gdb/alpha-tdep.h
index ab46ba56be..5f1d103273 100644
--- a/gdb/alpha-tdep.h
+++ b/gdb/alpha-tdep.h
@@ -103,7 +103,8 @@ struct gdbarch_tdep
};
extern unsigned int alpha_read_insn (struct gdbarch *gdbarch, CORE_ADDR pc);
-extern VEC (CORE_ADDR) *alpha_software_single_step (struct regcache *regcache);
+extern std::vector<CORE_ADDR> alpha_software_single_step
+ (struct regcache *regcache);
extern CORE_ADDR alpha_after_prologue (CORE_ADDR pc);
extern void alpha_mdebug_init_abi (struct gdbarch_info, struct gdbarch *);
diff --git a/gdb/arch/arm-get-next-pcs.c b/gdb/arch/arm-get-next-pcs.c
index 398dd59ac7..4e5234cb77 100644
--- a/gdb/arch/arm-get-next-pcs.c
+++ b/gdb/arch/arm-get-next-pcs.c
@@ -45,7 +45,7 @@ arm_get_next_pcs_ctor (struct arm_get_next_pcs *self,
is found, attempt to step through it. The end of the sequence address is
added to the next_pcs list. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
{
int byte_order_for_code = self->byte_order_for_code;
@@ -58,27 +58,26 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
const int atomic_sequence_length = 16; /* Instruction sequence length. */
ULONGEST status, itstate;
- VEC (CORE_ADDR) *next_pcs = NULL;
/* We currently do not support atomic sequences within an IT block. */
status = regcache_raw_get_unsigned (self->regcache, ARM_PS_REGNUM);
itstate = ((status >> 8) & 0xfc) | ((status >> 25) & 0x3);
if (itstate & 0x0f)
- return NULL;
+ return {};
/* Assume all atomic sequences start with a ldrex{,b,h,d} instruction. */
insn1 = self->ops->read_mem_uint (loc, 2, byte_order_for_code);
loc += 2;
if (thumb_insn_size (insn1) != 4)
- return NULL;
+ return {};
insn2 = self->ops->read_mem_uint (loc, 2, byte_order_for_code);
loc += 2;
if (!((insn1 & 0xfff0) == 0xe850
|| ((insn1 & 0xfff0) == 0xe8d0 && (insn2 & 0x00c0) == 0x0040)))
- return NULL;
+ return {};
/* Assume that no atomic sequence is longer than "atomic_sequence_length"
instructions. */
@@ -95,8 +94,8 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
if ((insn1 & 0xf000) == 0xd000 && bits (insn1, 8, 11) != 0x0f)
{
if (last_breakpoint > 0)
- return NULL; /* More than one conditional branch found,
- fallback to the standard code. */
+ return {}; /* More than one conditional branch found,
+ fallback to the standard code. */
breaks[1] = loc + 2 + (sbits (insn1, 0, 7) << 1);
last_breakpoint++;
@@ -107,7 +106,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
Fall back to standard code to avoid losing control of
execution. */
else if (thumb_instruction_changes_pc (insn1))
- return NULL;
+ return {};
}
else
{
@@ -135,8 +134,8 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
offset += (imm1 << 12) + (imm2 << 1);
if (last_breakpoint > 0)
- return 0; /* More than one conditional branch found,
- fallback to the standard code. */
+ return {}; /* More than one conditional branch found,
+ fallback to the standard code. */
breaks[1] = loc + offset;
last_breakpoint++;
@@ -147,7 +146,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
Fall back to standard code to avoid losing control of
execution. */
else if (thumb2_instruction_changes_pc (insn1, insn2))
- return NULL;
+ return {};
/* If we find a strex{,b,h,d}, we're done. */
if ((insn1 & 0xfff0) == 0xe840
@@ -158,7 +157,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
/* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
if (insn_count == atomic_sequence_length)
- return NULL;
+ return {};
/* Insert a breakpoint right after the end of the atomic sequence. */
breaks[0] = loc;
@@ -170,9 +169,11 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
|| (breaks[1] >= pc && breaks[1] < loc)))
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
/* Adds the breakpoints to the list to be inserted. */
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, MAKE_THUMB_ADDR (breaks[index]));
+ next_pcs.push_back (MAKE_THUMB_ADDR (breaks[index]));
return next_pcs;
}
@@ -182,7 +183,7 @@ thumb_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
is found, attempt to step through it. The end of the sequence address is
added to the next_pcs list. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
{
int byte_order_for_code = self->byte_order_for_code;
@@ -194,7 +195,6 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
int index;
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
const int atomic_sequence_length = 16; /* Instruction sequence length. */
- VEC (CORE_ADDR) *next_pcs = NULL;
/* Assume all atomic sequences start with a ldrex{,b,h,d} instruction.
Note that we do not currently support conditionally executed atomic
@@ -203,7 +203,7 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
loc += 4;
if ((insn & 0xff9000f0) != 0xe1900090)
- return NULL;
+ return {};
/* Assume that no atomic sequence is longer than "atomic_sequence_length"
instructions. */
@@ -219,8 +219,8 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
if (bits (insn, 24, 27) == 0xa)
{
if (last_breakpoint > 0)
- return NULL; /* More than one conditional branch found, fallback
- to the standard single-step code. */
+ return {}; /* More than one conditional branch found, fallback
+ to the standard single-step code. */
breaks[1] = BranchDest (loc - 4, insn);
last_breakpoint++;
@@ -230,7 +230,7 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
but conditional branches to change the PC. Fall back to standard
code to avoid losing control of execution. */
else if (arm_instruction_changes_pc (insn))
- return NULL;
+ return {};
/* If we find a strex{,b,h,d}, we're done. */
if ((insn & 0xff9000f0) == 0xe1800090)
@@ -239,7 +239,7 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
/* If we didn't find the strex{,b,h,d}, we cannot handle the sequence. */
if (insn_count == atomic_sequence_length)
- return NULL;
+ return {};
/* Insert a breakpoint right after the end of the atomic sequence. */
breaks[0] = loc;
@@ -251,16 +251,18 @@ arm_deal_with_atomic_sequence_raw (struct arm_get_next_pcs *self)
|| (breaks[1] >= pc && breaks[1] < loc)))
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
/* Adds the breakpoints to the list to be inserted. */
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+ next_pcs.push_back (breaks[index]);
return next_pcs;
}
/* Find the next possible PCs for thumb mode. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
{
int byte_order = self->byte_order;
@@ -272,7 +274,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
unsigned long offset;
ULONGEST status, itstate;
struct regcache *regcache = self->regcache;
- VEC (CORE_ADDR) * next_pcs = NULL;
+ std::vector<CORE_ADDR> next_pcs;
nextpc = MAKE_THUMB_ADDR (nextpc);
pc_val = MAKE_THUMB_ADDR (pc_val);
@@ -315,7 +317,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
itstate = thumb_advance_itstate (itstate);
}
- VEC_safe_push (CORE_ADDR, next_pcs, MAKE_THUMB_ADDR (pc));
+ next_pcs.push_back (MAKE_THUMB_ADDR (pc));
return next_pcs;
}
else if (itstate != 0)
@@ -335,7 +337,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
itstate = thumb_advance_itstate (itstate);
}
- VEC_safe_push (CORE_ADDR, next_pcs, MAKE_THUMB_ADDR (pc));
+ next_pcs.push_back (MAKE_THUMB_ADDR (pc));
return next_pcs;
}
else if ((itstate & 0x0f) == 0x08)
@@ -361,7 +363,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
/* Set a breakpoint on the following instruction. */
gdb_assert ((itstate & 0x0f) != 0);
- VEC_safe_push (CORE_ADDR, next_pcs, MAKE_THUMB_ADDR (pc));
+ next_pcs.push_back (MAKE_THUMB_ADDR (pc));
cond_negated = (itstate >> 4) & 1;
@@ -378,7 +380,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
}
while (itstate != 0 && ((itstate >> 4) & 1) == cond_negated);
- VEC_safe_push (CORE_ADDR, next_pcs, MAKE_THUMB_ADDR (pc));
+ next_pcs.push_back (MAKE_THUMB_ADDR (pc));
return next_pcs;
}
@@ -393,8 +395,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
{
/* Advance to the next instruction. All the 32-bit
instructions share a common prefix. */
- VEC_safe_push (CORE_ADDR, next_pcs,
- MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1)));
+ next_pcs.push_back (MAKE_THUMB_ADDR (pc + thumb_insn_size (inst1)));
}
return next_pcs;
@@ -628,7 +629,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
nextpc = pc_val + imm;
}
- VEC_safe_push (CORE_ADDR, next_pcs, nextpc);
+ next_pcs.push_back (nextpc);
return next_pcs;
}
@@ -641,7 +642,7 @@ thumb_get_next_pcs_raw (struct arm_get_next_pcs *self)
in Thumb-State, and gdbarch_addr_bits_remove () to get the plain memory
address in GDB and arm_addr_bits_remove in GDBServer. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
{
int byte_order = self->byte_order;
@@ -652,7 +653,7 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
CORE_ADDR nextpc;
struct regcache *regcache = self->regcache;
CORE_ADDR pc = regcache_read_pc (self->regcache);
- VEC (CORE_ADDR) *next_pcs = NULL;
+ std::vector<CORE_ADDR> next_pcs;
pc_val = (unsigned long) pc;
this_instr = self->ops->read_mem_uint (pc, 4, byte_order_for_code);
@@ -709,7 +710,7 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
? (pc_val + 8)
: regcache_raw_get_unsigned (regcache, rn));
- VEC_safe_push (CORE_ADDR, next_pcs, nextpc);
+ next_pcs.push_back (nextpc);
return next_pcs;
}
@@ -899,40 +900,36 @@ arm_get_next_pcs_raw (struct arm_get_next_pcs *self)
}
}
- VEC_safe_push (CORE_ADDR, next_pcs, nextpc);
+ next_pcs.push_back (nextpc);
+
return next_pcs;
}
/* See arm-get-next-pcs.h. */
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
arm_get_next_pcs (struct arm_get_next_pcs *self)
{
- VEC (CORE_ADDR) *next_pcs = NULL;
+ std::vector<CORE_ADDR> next_pcs;
if (self->ops->is_thumb (self))
{
next_pcs = thumb_deal_with_atomic_sequence_raw (self);
- if (next_pcs == NULL)
+ if (next_pcs.empty ())
next_pcs = thumb_get_next_pcs_raw (self);
}
else
{
next_pcs = arm_deal_with_atomic_sequence_raw (self);
- if (next_pcs == NULL)
+ if (next_pcs.empty ())
next_pcs = arm_get_next_pcs_raw (self);
}
if (self->ops->fixup != NULL)
{
- CORE_ADDR nextpc;
- int i;
-
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, nextpc); i++)
- {
- nextpc = self->ops->fixup (self, nextpc);
- VEC_replace (CORE_ADDR, next_pcs, i, nextpc);
- }
+ for (CORE_ADDR &pc_ref : next_pcs)
+ pc_ref = self->ops->fixup (self, pc_ref);
}
+
return next_pcs;
}
diff --git a/gdb/arch/arm-get-next-pcs.h b/gdb/arch/arm-get-next-pcs.h
index 2300ac1d7b..c6723be838 100644
--- a/gdb/arch/arm-get-next-pcs.h
+++ b/gdb/arch/arm-get-next-pcs.h
@@ -19,7 +19,8 @@
#ifndef ARM_GET_NEXT_PCS_H
#define ARM_GET_NEXT_PCS_H 1
-#include "gdb_vecs.h"
+
+#include <vector>
/* Forward declaration. */
struct arm_get_next_pcs;
@@ -61,6 +62,6 @@ void arm_get_next_pcs_ctor (struct arm_get_next_pcs *self,
struct regcache *regcache);
/* Find the next possible PCs after the current instruction executes. */
-VEC (CORE_ADDR) *arm_get_next_pcs (struct arm_get_next_pcs *self);
+std::vector<CORE_ADDR> arm_get_next_pcs (struct arm_get_next_pcs *self);
#endif /* ARM_GET_NEXT_PCS_H */
diff --git a/gdb/arm-linux-tdep.c b/gdb/arm-linux-tdep.c
index e1eab209df..094ed72757 100644
--- a/gdb/arm-linux-tdep.c
+++ b/gdb/arm-linux-tdep.c
@@ -921,22 +921,16 @@ arm_linux_get_next_pcs_syscall_next_pc (struct arm_get_next_pcs *self)
/* Insert a single step breakpoint at the next executed instruction. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
arm_linux_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct arm_get_next_pcs next_pcs_ctx;
- CORE_ADDR pc;
- int i;
- VEC (CORE_ADDR) *next_pcs = NULL;
- struct cleanup *old_chain;
/* If the target does have hardware single step, GDB doesn't have
to bother software single step. */
if (target_can_do_single_step () == 1)
- return NULL;
-
- old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
+ return {};
arm_get_next_pcs_ctor (&next_pcs_ctx,
&arm_linux_get_next_pcs_ops,
@@ -945,15 +939,10 @@ arm_linux_software_single_step (struct regcache *regcache)
1,
regcache);
- next_pcs = arm_get_next_pcs (&next_pcs_ctx);
-
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
- {
- pc = gdbarch_addr_bits_remove (gdbarch, pc);
- VEC_replace (CORE_ADDR, next_pcs, i, pc);
- }
+ std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
- discard_cleanups (old_chain);
+ for (CORE_ADDR &pc_ref : next_pcs)
+ pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref);
return next_pcs;
}
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c
index c8fabfb31e..24b575be17 100644
--- a/gdb/arm-tdep.c
+++ b/gdb/arm-tdep.c
@@ -6295,15 +6295,11 @@ arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self)
single-step support. We find the target of the coming instructions
and breakpoint them. */
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
arm_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
struct arm_get_next_pcs next_pcs_ctx;
- CORE_ADDR pc;
- int i;
- VEC (CORE_ADDR) *next_pcs = NULL;
- struct cleanup *old_chain = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
arm_get_next_pcs_ctor (&next_pcs_ctx,
&arm_get_next_pcs_ops,
@@ -6312,15 +6308,10 @@ arm_software_single_step (struct regcache *regcache)
0,
regcache);
- next_pcs = arm_get_next_pcs (&next_pcs_ctx);
-
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
- {
- pc = gdbarch_addr_bits_remove (gdbarch, pc);
- VEC_replace (CORE_ADDR, next_pcs, i, pc);
- }
+ std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
- discard_cleanups (old_chain);
+ for (CORE_ADDR &pc_ref : next_pcs)
+ pc_ref = gdbarch_addr_bits_remove (gdbarch, pc_ref);
return next_pcs;
}
@@ -7898,11 +7889,6 @@ arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch,
if (target_read_memory (regcache_read_pc (regcache), buf, 4) == 0)
{
struct arm_get_next_pcs next_pcs_ctx;
- CORE_ADDR pc;
- int i;
- VEC (CORE_ADDR) *next_pcs = NULL;
- struct cleanup *old_chain
- = make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
arm_get_next_pcs_ctor (&next_pcs_ctx,
&arm_get_next_pcs_ops,
@@ -7911,17 +7897,15 @@ arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch,
0,
regcache);
- next_pcs = arm_get_next_pcs (&next_pcs_ctx);
+ std::vector<CORE_ADDR> next_pcs = arm_get_next_pcs (&next_pcs_ctx);
/* If MEMADDR is the next instruction of current pc, do the
software single step computation, and get the thumb mode by
the destination address. */
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
+ for (CORE_ADDR pc : next_pcs)
{
if (UNMAKE_THUMB_ADDR (pc) == *pcptr)
{
- do_cleanups (old_chain);
-
if (IS_THUMB_ADDR (pc))
{
*pcptr = MAKE_THUMB_ADDR (*pcptr);
@@ -7931,8 +7915,6 @@ arm_breakpoint_kind_from_current_state (struct gdbarch *gdbarch,
return ARM_BP_KIND_ARM;
}
}
-
- do_cleanups (old_chain);
}
return arm_breakpoint_kind_from_pc (gdbarch, pcptr);
diff --git a/gdb/arm-tdep.h b/gdb/arm-tdep.h
index 8125226362..132978235b 100644
--- a/gdb/arm-tdep.h
+++ b/gdb/arm-tdep.h
@@ -29,6 +29,8 @@ struct gdb_get_next_pcs;
#include "arch/arm.h"
+#include <vector>
+
/* Say how long FP registers are. Used for documentation purposes and
code readability in this header. IEEE extended doubles are 80
bits. DWORD aligned they use 96 bits. */
@@ -259,7 +261,7 @@ CORE_ADDR arm_get_next_pcs_addr_bits_remove (struct arm_get_next_pcs *self,
int arm_get_next_pcs_is_thumb (struct arm_get_next_pcs *self);
-VEC (CORE_ADDR) *arm_software_single_step (struct regcache *);
+std::vector<CORE_ADDR> arm_software_single_step (struct regcache *);
int arm_is_thumb (struct regcache *regcache);
int arm_frame_is_thumb (struct frame_info *frame);
diff --git a/gdb/breakpoint.c b/gdb/breakpoint.c
index 4940ec271b..ba974c8cf0 100644
--- a/gdb/breakpoint.c
+++ b/gdb/breakpoint.c
@@ -15114,22 +15114,18 @@ int
insert_single_step_breakpoints (struct gdbarch *gdbarch)
{
struct regcache *regcache = get_current_regcache ();
- VEC (CORE_ADDR) * next_pcs;
+ std::vector<CORE_ADDR> next_pcs;
next_pcs = gdbarch_software_single_step (gdbarch, regcache);
- if (next_pcs != NULL)
+ if (!next_pcs.empty ())
{
- int i;
- CORE_ADDR pc;
struct frame_info *frame = get_current_frame ();
struct address_space *aspace = get_frame_address_space (frame);
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); i++)
+ for (CORE_ADDR pc : next_pcs)
insert_single_step_breakpoint (gdbarch, aspace, pc);
- VEC_free (CORE_ADDR, next_pcs);
-
return 1;
}
else
diff --git a/gdb/cris-tdep.c b/gdb/cris-tdep.c
index a46356ff8b..eb397725a7 100644
--- a/gdb/cris-tdep.c
+++ b/gdb/cris-tdep.c
@@ -2060,12 +2060,12 @@ find_step_target (struct regcache *regcache, inst_env_type *inst_env)
digs through the opcodes in order to find all possible targets.
Either one ordinary target or two targets for branches may be found. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
cris_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
inst_env_type inst_env;
- VEC (CORE_ADDR) *next_pcs = NULL;
+ std::vector<CORE_ADDR> next_pcs;
/* Analyse the present instruction environment and insert
breakpoints. */
@@ -2083,14 +2083,14 @@ cris_software_single_step (struct regcache *regcache)
CORE_ADDR next_pc
= (CORE_ADDR) inst_env.reg[gdbarch_pc_regnum (gdbarch)];
- VEC_safe_push (CORE_ADDR, next_pcs, next_pc);
+ next_pcs.push_back (next_pc);
if (inst_env.branch_found
&& (CORE_ADDR) inst_env.branch_break_address != next_pc)
{
CORE_ADDR branch_target_address
= (CORE_ADDR) inst_env.branch_break_address;
- VEC_safe_push (CORE_ADDR, next_pcs, branch_target_address);
+ next_pcs.push_back (branch_target_address);
}
}
diff --git a/gdb/gdbarch.c b/gdb/gdbarch.c
index 56643256da..f085c36deb 100644
--- a/gdb/gdbarch.c
+++ b/gdb/gdbarch.c
@@ -3223,7 +3223,7 @@ gdbarch_software_single_step_p (struct gdbarch *gdbarch)
return gdbarch->software_single_step != NULL;
}
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
gdbarch_software_single_step (struct gdbarch *gdbarch, struct regcache *regcache)
{
gdb_assert (gdbarch != NULL);
diff --git a/gdb/gdbarch.h b/gdb/gdbarch.h
index 7168e34b9b..2eed6b5b6d 100644
--- a/gdb/gdbarch.h
+++ b/gdb/gdbarch.h
@@ -35,6 +35,7 @@
#ifndef GDBARCH_H
#define GDBARCH_H
+#include <vector>
#include "frame.h"
#include "dis-asm.h"
@@ -700,8 +701,8 @@ extern void set_gdbarch_addr_bits_remove (struct gdbarch *gdbarch, gdbarch_addr_
extern int gdbarch_software_single_step_p (struct gdbarch *gdbarch);
-typedef VEC (CORE_ADDR) * (gdbarch_software_single_step_ftype) (struct regcache *regcache);
-extern VEC (CORE_ADDR) * gdbarch_software_single_step (struct gdbarch *gdbarch, struct regcache *regcache);
+typedef std::vector<CORE_ADDR> (gdbarch_software_single_step_ftype) (struct regcache *regcache);
+extern std::vector<CORE_ADDR> gdbarch_software_single_step (struct gdbarch *gdbarch, struct regcache *regcache);
extern void set_gdbarch_software_single_step (struct gdbarch *gdbarch, gdbarch_software_single_step_ftype *software_single_step);
/* Return non-zero if the processor is executing a delay slot and a
diff --git a/gdb/gdbarch.sh b/gdb/gdbarch.sh
index 31bee666b6..b91dc9c12e 100755
--- a/gdb/gdbarch.sh
+++ b/gdb/gdbarch.sh
@@ -640,7 +640,7 @@ m;CORE_ADDR;addr_bits_remove;CORE_ADDR addr;addr;;core_addr_identity;;0
# the condition and only put the breakpoint at the branch destination if
# the condition is true, so that we ensure forward progress when stepping
# past a conditional branch to self.
-F;VEC (CORE_ADDR) *;software_single_step;struct regcache *regcache;regcache
+F;std::vector<CORE_ADDR>;software_single_step;struct regcache *regcache;regcache
# Return non-zero if the processor is executing a delay slot and a
# further single-step is needed before the instruction finishes.
@@ -1268,6 +1268,7 @@ cat <<EOF
#ifndef GDBARCH_H
#define GDBARCH_H
+#include <vector>
#include "frame.h"
#include "dis-asm.h"
diff --git a/gdb/gdbserver/linux-arm-low.c b/gdb/gdbserver/linux-arm-low.c
index fc2b34870a..5a3f465dee 100644
--- a/gdb/gdbserver/linux-arm-low.c
+++ b/gdb/gdbserver/linux-arm-low.c
@@ -925,11 +925,10 @@ arm_arch_setup (void)
/* Fetch the next possible PCs after the current instruction executes. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
arm_gdbserver_get_next_pcs (struct regcache *regcache)
{
struct arm_get_next_pcs next_pcs_ctx;
- VEC (CORE_ADDR) *next_pcs = NULL;
arm_get_next_pcs_ctor (&next_pcs_ctx,
&get_next_pcs_ops,
@@ -939,9 +938,7 @@ arm_gdbserver_get_next_pcs (struct regcache *regcache)
1,
regcache);
- next_pcs = arm_get_next_pcs (&next_pcs_ctx);
-
- return next_pcs;
+ return arm_get_next_pcs (&next_pcs_ctx);
}
/* Support for hardware single step. */
diff --git a/gdb/gdbserver/linux-low.c b/gdb/gdbserver/linux-low.c
index e27cbf825a..ea3c81b847 100644
--- a/gdb/gdbserver/linux-low.c
+++ b/gdb/gdbserver/linux-low.c
@@ -4317,19 +4317,14 @@ enqueue_pending_signal (struct lwp_info *lwp, int signal, siginfo_t *info)
static void
install_software_single_step_breakpoints (struct lwp_info *lwp)
{
- int i;
- CORE_ADDR pc;
struct thread_info *thread = get_lwp_thread (lwp);
struct regcache *regcache = get_thread_regcache (thread, 1);
- VEC (CORE_ADDR) *next_pcs = NULL;
struct cleanup *old_chain = make_cleanup_restore_current_thread ();
- make_cleanup (VEC_cleanup (CORE_ADDR), &next_pcs);
-
current_thread = thread;
- next_pcs = (*the_low_target.get_next_pcs) (regcache);
+ std::vector<CORE_ADDR> next_pcs = the_low_target.get_next_pcs (regcache);
- for (i = 0; VEC_iterate (CORE_ADDR, next_pcs, i, pc); ++i)
+ for (CORE_ADDR pc : next_pcs)
set_single_step_breakpoint (pc, current_ptid);
do_cleanups (old_chain);
diff --git a/gdb/gdbserver/linux-low.h b/gdb/gdbserver/linux-low.h
index 7dcbfcfca4..6328da03ed 100644
--- a/gdb/gdbserver/linux-low.h
+++ b/gdb/gdbserver/linux-low.h
@@ -154,7 +154,7 @@ struct linux_target_ops
const gdb_byte *(*sw_breakpoint_from_kind) (int kind, int *size);
/* Find the next possible PCs after the current instruction executes. */
- VEC (CORE_ADDR) *(*get_next_pcs) (struct regcache *regcache);
+ std::vector<CORE_ADDR> (*get_next_pcs) (struct regcache *regcache);
int decr_pc_after_break;
int (*breakpoint_at) (CORE_ADDR pc);
diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c
index 45d1d731b0..d38cc225dd 100644
--- a/gdb/mips-tdep.c
+++ b/gdb/mips-tdep.c
@@ -3879,7 +3879,7 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
#define SC_OPCODE 0x38
#define SCD_OPCODE 0x3c
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
{
CORE_ADDR breaks[2] = {-1, -1};
@@ -3890,12 +3890,11 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
int index;
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
const int atomic_sequence_length = 16; /* Instruction sequence length. */
- VEC (CORE_ADDR) *next_pcs = NULL;
insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
/* Assume all atomic sequences start with a ll/lld instruction. */
if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
- return NULL;
+ return {};
/* Assume that no atomic sequence is longer than "atomic_sequence_length"
instructions. */
@@ -3912,7 +3911,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
{
case 0: /* SPECIAL */
if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */
- return 0; /* fallback to the standard single-step code. */
+ return {}; /* fallback to the standard single-step code. */
break;
case 1: /* REGIMM */
is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */
@@ -3921,7 +3920,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
break;
case 2: /* J */
case 3: /* JAL */
- return 0; /* fallback to the standard single-step code. */
+ return {}; /* fallback to the standard single-step code. */
case 4: /* BEQ */
case 5: /* BNE */
case 6: /* BLEZ */
@@ -3947,8 +3946,8 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
{
branch_bp = loc + mips32_relative_offset (insn) + 4;
if (last_breakpoint >= 1)
- return 0; /* More than one branch found, fallback to the
- standard single-step code. */
+ return {}; /* More than one branch found, fallback to the
+ standard single-step code. */
breaks[1] = branch_bp;
last_breakpoint++;
}
@@ -3959,7 +3958,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
/* Assume that the atomic sequence ends with a sc/scd instruction. */
if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
- return NULL;
+ return {};
loc += MIPS_INSN32_SIZE;
@@ -3971,14 +3970,16 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
/* Effectively inserts the breakpoints. */
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+ next_pcs.push_back (breaks[index]);
return next_pcs;
}
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
CORE_ADDR pc)
{
@@ -3992,17 +3993,16 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
ULONGEST insn;
int insn_count;
int index;
- VEC (CORE_ADDR) *next_pcs = NULL;
/* Assume all atomic sequences start with a ll/lld instruction. */
insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */
- return NULL;
+ return {};
loc += MIPS_INSN16_SIZE;
insn <<= 16;
insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
- return NULL;
+ return {};
loc += MIPS_INSN16_SIZE;
/* Assume all atomic sequences end with an sc/scd instruction. Assume
@@ -4072,7 +4072,7 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
case 0x35: /* J: bits 110101 */
case 0x3d: /* JAL: bits 111101 */
case 0x3c: /* JALX: bits 111100 */
- return 0; /* Fall back to the standard single-step code. */
+ return {}; /* Fall back to the standard single-step code. */
case 0x18: /* POOL32C: bits 011000 */
if ((b12s4_op (insn) & 0xb) == 0xb)
@@ -4099,24 +4099,24 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
&& b5s5_op (insn) != 0x18)
/* JRADDIUSP: bits 010001 11000 */
break;
- return NULL; /* Fall back to the standard single-step code. */
+ return {}; /* Fall back to the standard single-step code. */
case 0x33: /* B16: bits 110011 */
- return NULL; /* Fall back to the standard single-step code. */
+ return {}; /* Fall back to the standard single-step code. */
}
break;
}
if (is_branch)
{
if (last_breakpoint >= 1)
- return NULL; /* More than one branch found, fallback to the
- standard single-step code. */
+ return {}; /* More than one branch found, fallback to the
+ standard single-step code. */
breaks[1] = branch_bp;
last_breakpoint++;
}
}
if (!sc_found)
- return NULL;
+ return {};
/* Insert a breakpoint right after the end of the atomic sequence. */
breaks[0] = loc;
@@ -4126,14 +4126,16 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
if (last_breakpoint && pc <= breaks[1] && breaks[1] <= breaks[0])
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
/* Effectively inserts the breakpoints. */
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+ next_pcs.push_back (breaks[index]);
return next_pcs;
}
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
{
if (mips_pc_is_mips (pc))
@@ -4141,7 +4143,7 @@ deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
else if (mips_pc_is_micromips (gdbarch, pc))
return micromips_deal_with_atomic_sequence (gdbarch, pc);
else
- return NULL;
+ return {};
}
/* mips_software_single_step() is called just before we want to resume
@@ -4149,22 +4151,21 @@ deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
or kernel single-step support (MIPS on GNU/Linux for example). We find
the target of the coming instruction and breakpoint it. */
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
mips_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
CORE_ADDR pc, next_pc;
- VEC (CORE_ADDR) *next_pcs;
pc = regcache_read_pc (regcache);
- next_pcs = deal_with_atomic_sequence (gdbarch, pc);
- if (next_pcs != NULL)
+ std::vector<CORE_ADDR> next_pcs = deal_with_atomic_sequence (gdbarch, pc);
+
+ if (!next_pcs.empty ())
return next_pcs;
next_pc = mips_next_pc (regcache, pc);
- VEC_safe_push (CORE_ADDR, next_pcs, next_pc);
- return next_pcs;
+ return {next_pc};
}
/* Test whether the PC points to the return instruction at the
diff --git a/gdb/mips-tdep.h b/gdb/mips-tdep.h
index ce168cc49c..541a275f30 100644
--- a/gdb/mips-tdep.h
+++ b/gdb/mips-tdep.h
@@ -154,7 +154,8 @@ enum
};
/* Single step based on where the current instruction will take us. */
-extern VEC (CORE_ADDR) *mips_software_single_step (struct regcache *regcache);
+extern std::vector<CORE_ADDR> mips_software_single_step
+ (struct regcache *regcache);
/* Strip the ISA (compression) bit off from ADDR. */
extern CORE_ADDR mips_unmake_compact_addr (CORE_ADDR addr);
diff --git a/gdb/moxie-tdep.c b/gdb/moxie-tdep.c
index dd7a6f4bfb..2972d5248e 100644
--- a/gdb/moxie-tdep.c
+++ b/gdb/moxie-tdep.c
@@ -299,7 +299,7 @@ moxie_process_readu (CORE_ADDR addr, gdb_byte *buf,
/* Insert a single step breakpoint. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
moxie_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
@@ -309,7 +309,7 @@ moxie_software_single_step (struct regcache *regcache)
uint32_t tmpu32;
ULONGEST fp;
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
- VEC (CORE_ADDR) *next_pcs = NULL;
+ std::vector<CORE_ADDR> next_pcs;
addr = regcache_read_pc (regcache);
@@ -337,9 +337,8 @@ moxie_software_single_step (struct regcache *regcache)
case 0x09: /* bleu */
/* Insert breaks on both branches, because we can't currently tell
which way things will go. */
- VEC_safe_push (CORE_ADDR, next_pcs, addr + 2);
- VEC_safe_push (CORE_ADDR, next_pcs,
- addr + 2 + INST2OFFSET(inst));
+ next_pcs.push_back (addr + 2);
+ next_pcs.push_back (addr + 2 + INST2OFFSET(inst));
break;
default:
{
@@ -351,7 +350,7 @@ moxie_software_single_step (struct regcache *regcache)
else
{
/* This is a Form 2 instruction. They are all 16 bits. */
- VEC_safe_push (CORE_ADDR, next_pcs, addr + 2);
+ next_pcs.push_back (addr + 2);
}
}
else
@@ -398,7 +397,7 @@ moxie_software_single_step (struct regcache *regcache)
case 0x32: /* udiv.l */
case 0x33: /* mod.l */
case 0x34: /* umod.l */
- VEC_safe_push (CORE_ADDR, next_pcs, addr + 2);
+ next_pcs.push_back (addr + 2);
break;
/* 32-bit instructions. */
@@ -408,7 +407,7 @@ moxie_software_single_step (struct regcache *regcache)
case 0x37: /* sto.b */
case 0x38: /* ldo.s */
case 0x39: /* sto.s */
- VEC_safe_push (CORE_ADDR, next_pcs, addr + 4);
+ next_pcs.push_back (addr + 4);
break;
/* 48-bit instructions. */
@@ -421,27 +420,26 @@ moxie_software_single_step (struct regcache *regcache)
case 0x20: /* ldi.s (immediate) */
case 0x22: /* lda.s */
case 0x24: /* sta.s */
- VEC_safe_push (CORE_ADDR, next_pcs, addr + 6);
+ next_pcs.push_back (addr + 6);
break;
/* Control flow instructions. */
case 0x03: /* jsra */
case 0x1a: /* jmpa */
- VEC_safe_push (CORE_ADDR, next_pcs,
- moxie_process_readu (addr + 2, buf, 4, byte_order));
+ next_pcs.push_back (moxie_process_readu (addr + 2, buf, 4,
+ byte_order));
break;
case 0x04: /* ret */
regcache_cooked_read_unsigned (regcache, MOXIE_FP_REGNUM, &fp);
- VEC_safe_push (CORE_ADDR, next_pcs,
- moxie_process_readu (fp + 4, buf, 4, byte_order));
+ next_pcs.push_back (moxie_process_readu (fp + 4, buf, 4, byte_order));
break;
case 0x19: /* jsr */
case 0x25: /* jmp */
regcache_raw_read (regcache,
(inst >> 4) & 0xf, (gdb_byte *) & tmpu32);
- VEC_safe_push (CORE_ADDR, next_pcs, tmpu32);
+ next_pcs.push_back (tmpu32);
break;
case 0x30: /* swi */
diff --git a/gdb/nios2-tdep.c b/gdb/nios2-tdep.c
index 3d39451804..c214078921 100644
--- a/gdb/nios2-tdep.c
+++ b/gdb/nios2-tdep.c
@@ -2219,16 +2219,13 @@ nios2_get_next_pc (struct regcache *regcache, CORE_ADDR pc)
/* Implement the software_single_step gdbarch method. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
nios2_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
CORE_ADDR next_pc = nios2_get_next_pc (regcache, regcache_read_pc (regcache));
- VEC (CORE_ADDR) *next_pcs = NULL;
- VEC_safe_push (CORE_ADDR, next_pcs, next_pc);
-
- return next_pcs;
+ return {next_pc};
}
/* Implement the get_longjump_target gdbarch method. */
diff --git a/gdb/ppc-tdep.h b/gdb/ppc-tdep.h
index 875ad93b18..8d15ace214 100644
--- a/gdb/ppc-tdep.h
+++ b/gdb/ppc-tdep.h
@@ -76,7 +76,8 @@ int ppc_altivec_support_p (struct gdbarch *gdbarch);
/* Return non-zero if the architecture described by GDBARCH has
VSX registers (vsr0 --- vsr63). */
int vsx_support_p (struct gdbarch *gdbarch);
-VEC (CORE_ADDR) *ppc_deal_with_atomic_sequence (struct regcache *regcache);
+std::vector<CORE_ADDR> ppc_deal_with_atomic_sequence
+ (struct regcache *regcache);
/* Register set description. */
diff --git a/gdb/rs6000-aix-tdep.c b/gdb/rs6000-aix-tdep.c
index a14e93c66a..7d817bee1d 100644
--- a/gdb/rs6000-aix-tdep.c
+++ b/gdb/rs6000-aix-tdep.c
@@ -673,7 +673,7 @@ branch_dest (struct regcache *regcache, int opcode, int instr,
/* AIX does not support PT_STEP. Simulate it. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
rs6000_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
@@ -682,14 +682,13 @@ rs6000_software_single_step (struct regcache *regcache)
CORE_ADDR loc;
CORE_ADDR breaks[2];
int opcode;
- VEC (CORE_ADDR) *next_pcs;
loc = regcache_read_pc (regcache);
insn = read_memory_integer (loc, 4, byte_order);
- next_pcs = ppc_deal_with_atomic_sequence (regcache);
- if (next_pcs != NULL)
+ std::vector<CORE_ADDR> next_pcs = ppc_deal_with_atomic_sequence (regcache);
+ if (!next_pcs.empty ())
return next_pcs;
breaks[0] = loc + PPC_INSN_SIZE;
@@ -705,7 +704,8 @@ rs6000_software_single_step (struct regcache *regcache)
/* ignore invalid breakpoint. */
if (breaks[ii] == -1)
continue;
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[ii]);
+
+ next_pcs.push_back (breaks[ii]);
}
errno = 0; /* FIXME, don't ignore errors! */
diff --git a/gdb/rs6000-tdep.c b/gdb/rs6000-tdep.c
index eb784c562f..4072464558 100644
--- a/gdb/rs6000-tdep.c
+++ b/gdb/rs6000-tdep.c
@@ -1165,7 +1165,7 @@ ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
Load And Reserve instruction and ending with a Store Conditional
instruction. If such a sequence is found, attempt to step through it.
A breakpoint is placed at the end of the sequence. */
-VEC (CORE_ADDR) *
+std::vector<CORE_ADDR>
ppc_deal_with_atomic_sequence (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
@@ -1180,11 +1180,10 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
const int atomic_sequence_length = 16; /* Instruction sequence length. */
int bc_insn_count = 0; /* Conditional branch instruction count. */
- VEC (CORE_ADDR) *next_pcs = NULL;
/* Assume all atomic sequences start with a Load And Reserve instruction. */
if (!IS_LOAD_AND_RESERVE_INSN (insn))
- return NULL;
+ return {};
/* Assume that no atomic sequence is longer than "atomic_sequence_length"
instructions. */
@@ -1202,8 +1201,8 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
int absolute = insn & 2;
if (bc_insn_count >= 1)
- return 0; /* More than one conditional branch found, fallback
- to the standard single-step code. */
+ return {}; /* More than one conditional branch found, fallback
+ to the standard single-step code. */
if (absolute)
breaks[1] = immediate;
@@ -1221,7 +1220,7 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
/* Assume that the atomic sequence ends with a Store Conditional
instruction. */
if (!IS_STORE_CONDITIONAL_INSN (insn))
- return NULL;
+ return {};
closing_insn = loc;
loc += PPC_INSN_SIZE;
@@ -1237,8 +1236,10 @@ ppc_deal_with_atomic_sequence (struct regcache *regcache)
|| (breaks[1] >= pc && breaks[1] <= closing_insn)))
last_breakpoint = 0;
+ std::vector<CORE_ADDR> next_pcs;
+
for (index = 0; index <= last_breakpoint; index++)
- VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
+ next_pcs.push_back (breaks[index]);
return next_pcs;
}
diff --git a/gdb/s390-linux-tdep.c b/gdb/s390-linux-tdep.c
index 55129d81f4..8139d817d9 100644
--- a/gdb/s390-linux-tdep.c
+++ b/gdb/s390-linux-tdep.c
@@ -725,7 +725,7 @@ s390_is_partial_instruction (struct gdbarch *gdbarch, CORE_ADDR loc, int *len)
process about 4kiB of it each time, leading to O(n**2) memory and time
complexity. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
s390_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
@@ -733,33 +733,30 @@ s390_software_single_step (struct regcache *regcache)
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
int len;
uint16_t insn;
- VEC (CORE_ADDR) *next_pcs = NULL;
/* Special handling only if recording. */
if (!record_full_is_used ())
- return NULL;
+ return {};
/* First, match a partial instruction. */
if (!s390_is_partial_instruction (gdbarch, loc, &len))
- return NULL;
+ return {};
loc += len;
/* Second, look for a branch back to it. */
insn = read_memory_integer (loc, 2, byte_order);
if (insn != 0xa714) /* BRC with mask 1 */
- return NULL;
+ return {};
insn = read_memory_integer (loc + 2, 2, byte_order);
if (insn != (uint16_t) -(len / 2))
- return NULL;
+ return {};
loc += 4;
/* Found it, step past the whole thing. */
- VEC_safe_push (CORE_ADDR, next_pcs, loc);
-
- return next_pcs;
+ return {loc};
}
static int
diff --git a/gdb/sparc-tdep.c b/gdb/sparc-tdep.c
index 078907a5d4..14d9fc97bc 100644
--- a/gdb/sparc-tdep.c
+++ b/gdb/sparc-tdep.c
@@ -1643,7 +1643,7 @@ sparc_step_trap (struct frame_info *frame, unsigned long insn)
return 0;
}
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
sparc_software_single_step (struct regcache *regcache)
{
struct gdbarch *arch = get_regcache_arch (regcache);
@@ -1651,7 +1651,7 @@ sparc_software_single_step (struct regcache *regcache)
CORE_ADDR npc, nnpc;
CORE_ADDR pc, orig_npc;
- VEC (CORE_ADDR) *next_pcs = NULL;
+ std::vector<CORE_ADDR> next_pcs;
pc = regcache_raw_get_unsigned (regcache, tdep->pc_regnum);
orig_npc = npc = regcache_raw_get_unsigned (regcache, tdep->npc_regnum);
@@ -1659,10 +1659,10 @@ sparc_software_single_step (struct regcache *regcache)
/* Analyze the instruction at PC. */
nnpc = sparc_analyze_control_transfer (regcache, pc, &npc);
if (npc != 0)
- VEC_safe_push (CORE_ADDR, next_pcs, npc);
+ next_pcs.push_back (npc);
if (nnpc != 0)
- VEC_safe_push (CORE_ADDR, next_pcs, nnpc);
+ next_pcs.push_back (nnpc);
/* Assert that we have set at least one breakpoint, and that
they're not set at the same spot - unless we're going
diff --git a/gdb/spu-tdep.c b/gdb/spu-tdep.c
index 91b1a0e4d6..08ab19418f 100644
--- a/gdb/spu-tdep.c
+++ b/gdb/spu-tdep.c
@@ -1612,7 +1612,7 @@ spu_memory_remove_breakpoint (struct gdbarch *gdbarch,
/* Software single-stepping support. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
spu_software_single_step (struct regcache *regcache)
{
struct gdbarch *gdbarch = get_regcache_arch (regcache);
@@ -1622,7 +1622,7 @@ spu_software_single_step (struct regcache *regcache)
int offset, reg;
gdb_byte buf[4];
ULONGEST lslr;
- VEC (CORE_ADDR) *next_pcs = NULL;
+ std::vector<CORE_ADDR> next_pcs;
pc = regcache_read_pc (regcache);
@@ -1645,7 +1645,7 @@ spu_software_single_step (struct regcache *regcache)
else
next_pc = (SPUADDR_ADDR (pc) + 4) & lslr;
- VEC_safe_push (CORE_ADDR, next_pcs, SPUADDR (SPUADDR_SPU (pc), next_pc));
+ next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), next_pc));
if (is_branch (insn, &offset, ®))
{
@@ -1658,8 +1658,7 @@ spu_software_single_step (struct regcache *regcache)
target = target & lslr;
if (target != next_pc)
- VEC_safe_push (CORE_ADDR, next_pcs, SPUADDR (SPUADDR_SPU (pc),
- target));
+ next_pcs.push_back (SPUADDR (SPUADDR_SPU (pc), target));
}
return next_pcs;
diff --git a/gdb/tic6x-tdep.c b/gdb/tic6x-tdep.c
index 23b7b280f6..012b749389 100644
--- a/gdb/tic6x-tdep.c
+++ b/gdb/tic6x-tdep.c
@@ -699,15 +699,12 @@ tic6x_get_next_pc (struct regcache *regcache, CORE_ADDR pc)
/* This is the implementation of gdbarch method software_single_step. */
-static VEC (CORE_ADDR) *
+static std::vector<CORE_ADDR>
tic6x_software_single_step (struct regcache *regcache)
{
CORE_ADDR next_pc = tic6x_get_next_pc (regcache, regcache_read_pc (regcache));
- VEC (CORE_ADDR) *next_pcs = NULL;
- VEC_safe_push (CORE_ADDR, next_pcs, next_pc);
-
- return next_pcs;
+ return {next_pc};
}
/* This is the implementation of gdbarch method frame_align. */
--
2.12.2
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