* [PATCH 05/21] Add microMIPSR6 support
2024-12-13 15:53 [PATCH 0/21] Integrate MIPS-Specific Support into Official binutils-gdb Milica Matic
` (4 preceding siblings ...)
2024-12-13 15:53 ` [PATCH 04/21] Instruction mapping support (pre-R6 to R6) Milica Matic
@ 2024-12-13 15:53 ` Milica Matic
2024-12-13 15:53 ` [PATCH 06/21] Update branch relaxation Milica Matic
` (17 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Milica Matic @ 2024-12-13 15:53 UTC (permalink / raw)
To: gdb-patches
Cc: milica.matic, simark, cfu, aburgess, kevinb, macro,
djordje.todorovic, Andrew Bennett, Faraz Shahbazker
From: Andrew Bennett <andrew.bennett@imgtec.com>
New relocation types, such as R_MICROMIPS_21_PCREL_S1 and
R_MICROMIPS_26_PCREL_S1, have been introduced to enable more efficient
branching and addressing within the microMIPS R6 architecture. Macro
definitions and functionalities have been added to recognize and convert
microMIPS instructions. Mechanisms for handling new PC-relative
relocations and their specific constraints, such as compact branch
processing, have been implemented. New instructions and operand codes
specific to microMIPS R6 have been defined. Structures and macros have
been updated to support the processing of these new instructions.
Cherry-picked b679f51
from https://github.com/MIPS/binutils-gdb
Signed-off-by: Andrew Bennett <andrew.bennett@imgtec.com>
Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Milica Matic <milica.matic@htecgroup.com>
bfd/
* elfxx-mips.c (LA25_LUI_MICROMIPS): Update for R6.
(LA25_BC_MICROMIPS): New macro.
(STUB_LUI_MICROMIPS): Update for R6.
(STUB_JALRC_MICROMIPS, STUB_JALRC32_MICROMIPS): New macro.
(micromipsr6_o32_exec_plt0_entry): New static variable.
(micromipsr6_insn32_o32_exec_plt0_entry): Likewise.
(micromipsr6_o32_exec_plt_entry): Likewise.
(micromipsr6_insn32_o32_exec_plt_entry): Likewise.
(hi16_reloc_p): Include R_MICROMIPS_PCHI16.
(lo16_reloc_p): Include R_MICROMIPS_PCLO16.
(b_reloc_p): Include R_MICROMIPS_PC26_S1, R_MICROMIPS_PC21_S1.
(aligned_pcrel_reloc_p): Include R_MICROMIPS_PC18_S3,
R_MICROMIPS_PC19_S2.
(micromips_branch_reloc_p): Include R_MICROMIPS_PC21_S1,
R_MICROMIPS_PC26_S1.
(mips_elf_relocation_needs_la25_stub): Add new branch relocs.
(mips_elf_calculate_relocation): Update R_MIPS_PC21_S2 and
R_MIPS_PC26_S2 for cross-mode jump checks. Add
R_MICROMIPS_PC18_S3, R_MICROMIPS_PC19_S2, R_MICROMIPS_PCHI16,
R_MICROMIPS_PCLO16, R_MICROMIPS_PC21_S1, R_MICROMIPS_PC26_S1
cases. Report that JALX is removed in R6.
(mips_elf_add_lo16_rel_addend): Support R_MICROMIPS_PCHI16.
(_bfd_mips_elf_check_relocs): Support R_MICROMIPS_PC21_S1,
R_MICROMIPS_PC26_S1.
(_bfd_mips_elf_relocate_section): Defer warnings for R6
cross mode jumpts to mips_elf_perform_relocation.
(mips_elf_create_la25_stub): Update for microMIPS R6
compact branch/jumps.
(_bfd_mips_elf_finish_dynamic_symbol): Update PLT and STUBS
for microMIPS R6 compact branch/jumps.
(mips_finish_exec_plt): Update PLT0 for the same.
(_bfd_mips_elf_relax_section): Disable for MIPSR6.
(_bfd_mips_elf_get_synthetic_symtab): Handle difference in
ADDIUPC range for microMIPS R6.
gas/
* gas/config/tc-mips.c (mips_ases): Enable dspr3 for microMIPS R6.
(mips_check_options): Update ISA restrictions for microMIPS R6.
(micromips_reloc_p): Include BFD_RELOC_MICROMIPS_18_PCREL_S3,
BFD_RELOC_MICROMIPS_19_PCREL_S2, BFD_RELOC_MICROMIPS_21_PCREL_S1,
BFD_RELOC_MICROMIPS_26_PCREL_S1, BFD_RELOC_MICROMIPS_HI16_S_PCREL,
BFD_RELOC_MICROMIPS_LO16_PCREL.
(b_reloc_p): Include BFD_RELOC_MICROMIPS_26_PCREL_S1,
BFD_RELOC_MICROMIPS_21_PCREL_S1.
(limited_pcrel_reloc_p): Include BFD_RELOC_MICROMIPS_18_PCREL_S3,
BFD_RELOC_MICROMIPS_19_PCREL_S2, BFD_RELOC_MICROMIPS_21_PCREL_S1,
BFD_RELOC_MICROMIPS_26_PCREL_S1, BFD_RELOC_MICROMIPS_HI16_S_PCREL,
BFD_RELOC_MICROMIPS_LO16_PCREL.
(find_altered_opcode): Check opcodes are valid as well as match.
(micromips_map_reloc): Add mappings for BFD_RELOC_HI16_S_PCREL,
BFD_RELOC_LO16_PCREL, BFD_RELOC_MIPS_21_PCREL_S2,
BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MIPS_18_PCREL_S3,
BFD_RELOC_MIPS_19_PCREL_S2.
(append_insn): Mark BFD_RELOC_16_PCREL_S2,
BFD_RELOC_MIPS_21_PCREL_S2 and BFD_RELOC_MIPS_26_PCREL_S2
as complete if the reloc is applied.
Include BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MIPS_26_PCREL_S2
in microMIPS relaxations.
(cop12_r6fmt): New static variable.
(mm_jalr_fmt): Likewise.
(mm_jal_fmt): Likewise.
(COP2_FMT): Update for microMIPS R6 format.
(LUI_FMT): Likewise.
(LL_SC_FMT): Likewise.
(LL_SC_PAIRED_FMT): New macro.
(MM_JALR_FMT): New macro.
(MM_JAL_FMT): New macro.
(macro_build): Handle +" and +' branch operands.
(macro_build_jalr): Update for microMIPS R6 JALRC.
(macro_build_branch_rs): Update for microMIPS R6 compact branches.
(macro_build_branch_rsrt): Likewise.
(macro): Updates for microMIPS R6. M_ABS uses BGEZC. M_JAL_2
uses JALRC. M_JAL_A uses BC. M_LWC2_AB, M_LDC2_AB, M_SWC2_AB,
M_SDC2_AB, M_LL_AB, M_LLWPE_AB, M_LLWP_AB, M_LLDP_AB, M_LLD_AB,
M_SWC2_AB, M_SC_AB, M_SCD_AB, M_SCWPE_AB, M_SCWP_AB, M_SCDP_AB,
M_CACHE_AB, M_PREF_AB use new formats. M_JRADDIUSP uses JRC.
(md_pcrel_from): Add BFD_RELOC_MICROMIPS_21_PCREL_S1,
BFD_RELOC_MICROMIPS_26_PCREL_S1.
(mips_force_relocation): Add BFD_RELOC_MICROMIPS_21_PCREL_S1,
BFD_RELOC_MICROMIPS_26_PCREL_S1, BFD_RELOC_MICROMIPS_18_PCREL_S3,
BFD_RELOC_MICROMIPS_19_PCREL_S2, BFD_RELOC_MICROMIPS_HI16_S_PCREL,
BFD_RELOC_MICROMIPS_LO16_PCREL.
(fix_bad_cross_mode_branch_p): Handle
BFD_RELOC_MICROMIPS_21_PCREL_S1, BFD_RELOC_MICROMIPS_26_PCREL_S1.
(calculate_reloc): Handle BFD_RELOC_MICROMIPS_HI16_S_PCREL,
BFD_RELOC_MICROMIPS_LO16_PCREL.
(md_apply_fix): Recognize new microMIPS R6 PCREL relocs. Handle
BFD_RELOC_MICROMIPS_18_PCREL_S3, BFD_RELOC_MICROMIPS_19_PCREL_S2
and update error checks.
(relaxed_branch_length): Note that microMIPS R6 branches are
not always 16-bit.
(relaxed_micromips_32bit_branch_length): Assume branches without
symbols are out of range.
(relaxed_micromips_16bit_branch_length): Likewise.
(tc_gen_reloc): Handle new microMIPS R6 PCREL relocs.
(md_convert_frag): Select BFD_RELOC_MICROMIPS_21_PCREL_S1 or
BFD_RELOC_MICROMIPS_26_PCREL_S1 for relaxing microMIPS R6
branches. Disable relaxing 32-bit branches for microMIPS R6.
* testsuite/gas/mips/mips.exp (run_dump_test_arch): Add
micromips fallback for micromipsr6.
(run_list_test_arch): Likewise.
(micromipsr6): Add new arch.
Update throughout for new tests and micromipsr6 interactions.
* testsuite/gas/mips/abs.s: Ensure NOPs at end of test.
BGEU $0, <reg> == BC.
* testsuite/gas/mips/branch-local-ignore-3.d: Update to match.
* testsuite/gas/mips/branch-local-ignore-n32-3.d: Likewise.
* testsuite/gas/mips/branch-local-ignore-n64-3.d: Likewise.
* testsuite/gas/mips/llpscp-32-micromips.d: New file.
* testsuite/gas/mips/llpscp-64-micromips.d: Likewise.
* testsuite/gas/mips/micromips-compact.d: Use MIPS64R2.
* testsuite/gas/mips/micromips-noinsn32.d: Likewise.
* testsuite/gas/mips/micromips-trap.d: Likewise.
* testsuite/gas/mips/micromips-insn32.d: Remove specific ISA.
* testsuite/gas/mips/micromips.d: Likewise.
* testsuite/gas/mips/micromips.s: Update for microMIPS R6.
* testsuite/gas/mips/micromips.l: Update to match.
* testsuite/gas/mips/micromips-warn.l: Likewise.
* testsuite/gas/mips/micromips@mips32-cp2.s: Update for
microMIPS R6.
* testsuite/gas/mips/mips32r2.d: Update for delay slot NOPs.
* testsuite/gas/mips/mips32r2.s: Likewise.
* testsuite/gas/mips/mipsr6@mips32r2.d: Likewise.
* testsuite/gas/mips/micromips@mips32r2.d: Likewise.
* testsuite/gas/mips/pcrel-reloc-4.s: Update for compact
branches.
* testsuite/gas/mips/pcrel-reloc-4-r6.d: Remove ISA options.
* testsuite/gas/mips/ur6-64-removed.l: New file.
* testsuite/gas/mips/ur6-64-removed.s: Likewise.
* testsuite/gas/mips/ur6-ctc-err.l: Likewise.
* testsuite/gas/mips/ur6-ctc-err.s: Likewise.
* testsuite/gas/mips/ur6-ctc.d: Likewise.
* testsuite/gas/mips/ur6-ctc.s: Likewise.
* testsuite/gas/mips/ur6-removed.l: Likewise.
* testsuite/gas/mips/ur6-removed.s: Likewise.
* testsuite/gas/mips/ur6.d: Likewise.
* testsuite/gas/mips/ur6.s: Likewise.
* testsuite/gas/mips/micromipsr6@pcrel-reloc-4-r6.d: Likewise.
* testsuite/gas/mips/micromipsr6@24k-branch-delay-1.d: Likewise.
* testsuite/gas/mips/micromipsr6@24k-triple-stores-1.d: Likewise.
* testsuite/gas/mips/micromipsr6@24k-triple-stores-2-llsc.d:
Likewise.
* testsuite/gas/mips/micromipsr6@24k-triple-stores-2.d: Likewise.
* testsuite/gas/mips/micromipsr6@24k-triple-stores-3.d: Likewise.
* testsuite/gas/mips/micromipsr6@24k-triple-stores-4.d: Likewise.
* testsuite/gas/mips/micromipsr6@24k-triple-stores-5.d: Likewise.
* testsuite/gas/mips/micromipsr6@24k-triple-stores-6.d: Likewise.
* testsuite/gas/mips/micromipsr6@24k-triple-stores-7.d: Likewise.
* testsuite/gas/mips/micromipsr6@24k-triple-stores-8.d: Likewise.
* testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msingle-float.l:
New file.
* testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msingle-float.s:
Likewise.
* testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msoft-float.l:
Likewise.
* testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msoft-float.s:
Likewise.
* testsuite/gas/mips/micromipsr6@abs.d: Likewise.
* testsuite/gas/mips/micromipsr6@add.d: Likewise.
* testsuite/gas/mips/micromipsr6@and.d: Likewise.
* testsuite/gas/mips/micromipsr6@beq.d: Likewise.
* testsuite/gas/mips/micromipsr6@bge.d: Likewise.
* testsuite/gas/mips/micromipsr6@bgeu.d: Likewise.
* testsuite/gas/mips/micromipsr6@blt.d: Likewise.
* testsuite/gas/mips/micromipsr6@bltu.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-1.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-2-64.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-2.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-2pic-64.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-2pic.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-4-64.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-4.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-5-64.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-5.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-5pic-64.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-misc-5pic.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-swap-3.d: Likewise.
* testsuite/gas/mips/micromipsr6@branch-swap-4.d: Likewise.
* testsuite/gas/mips/micromipsr6@cache.d: Likewise.
* testsuite/gas/mips/micromipsr6@dli.d: Likewise.
* testsuite/gas/mips/micromipsr6@elf-rel29.d: Likewise.
* testsuite/gas/mips/micromipsr6@eva.d: Likewise.
* testsuite/gas/mips/micromipsr6@jal-mask-11.d: Likewise.
* testsuite/gas/mips/micromipsr6@jal-mask-12.d: Likewise.
* testsuite/gas/mips/micromipsr6@jal-range.l: Likewise.
* testsuite/gas/mips/micromipsr6@jal-range.s: Likewise.
* testsuite/gas/mips/micromipsr6@jal-svr4pic-local-n32.d: Likewise.
* testsuite/gas/mips/micromipsr6@jal-svr4pic-local-n64.d: Likewise.
* testsuite/gas/mips/micromipsr6@jal-svr4pic-local.d: Likewise.
* testsuite/gas/mips/micromipsr6@jal-svr4pic-noreorder.d: Likewise.
* testsuite/gas/mips/micromipsr6@jal-svr4pic.d: Likewise.
* testsuite/gas/mips/micromipsr6@jal.d: Likewise.
* testsuite/gas/mips/micromipsr6@lb-svr4pic-ilocks.d: Likewise.
* testsuite/gas/mips/micromipsr6@ld-zero-2.d: Likewise.
* testsuite/gas/mips/micromipsr6@ld-zero-3.d: Likewise.
* testsuite/gas/mips/micromipsr6@ldpc-unalign.l: Likewise.
* testsuite/gas/mips/micromipsr6@ldpc-unalign.s: Likewise.
* testsuite/gas/mips/micromipsr6@li.d: Likewise.
* testsuite/gas/mips/micromipsr6@lui.d: Likewise.
* testsuite/gas/mips/micromipsr6@mcu.d: Likewise.
* testsuite/gas/mips/micromipsr6@micromips-insn32.d: Likewise.
* testsuite/gas/mips/micromipsr6@micromips.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips32-cp2.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips32-dsp.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips32-dspr2.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips32-dspr3.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips32-sf32.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips32.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips32r2.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips4-fp.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips4-fp.s: Likewise.
* testsuite/gas/mips/micromipsr6@mips4.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips5-fp.d: Likewise.
* testsuite/gas/mips/micromipsr6@mips5-fp.s: Likewise.
* testsuite/gas/mips/micromipsr6@pref.d: Likewise.
* testsuite/gas/mips/micromipsr6@r5.d: Likewise.
* testsuite/gas/mips/micromipsr6@r6-branch-constraints.l: Likewise.
* testsuite/gas/mips/micromipsr6@r6-branch-constraints.s: Likewise.
* testsuite/gas/mips/micromipsr6@relax-swap3.d: Likewise.
include/
* opcode/mips.h (struct mips_operand): Add size_top, lsb_top
fields.
(mips_insert_operand): Handle size_top, lsb_top logic.
(mips_extract_operand): Likewise.
(microMIPS R6): Document new operand codes.
ld/
* testsuite/ld-mips-elf/compressed-plt-1-o32-r6.od: New file.
* testsuite/ld-mips-elf/compressed-plt-1-o32-r6.rd: Likewise.
* testsuite/ld-mips-elf/compressed-plt-1-o32-umips-insn32-only.od:
Likewise.
* testsuite/ld-mips-elf/compressed-plt-1-o32-umips-insn32-only.rd:
Likewise.
* testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-insn32-only.od:
Likewise.
* testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-insn32-only.rd:
Likewise.
* testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-only.od:
Likewise.
* testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-only.rd:
Likewise.
* testsuite/ld-mips-elf/compressed-plt-1-umipsr6.ld: Likewise.
* testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6-rel.dd:
Likewise.
* testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6-rel.nd:
Likewise.
* testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6.nd: Likewise.
* testsuite/ld-mips-elf/pic-and-nonpic-1a-micromipsr6.s: Likewise.
* testsuite/ld-mips-elf/undefweak-overflow-r6.d
* testsuite/ld-mips-elf/undefweak-overflow-r6.s
* testsuite/ld-mips-elf/undefweak-overflow.s: Change to pre R6
only.
* testsuite/ld-mips-elf/undefweak-overflow.d: Update to match.
* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d: Force
MIPS64R6, update errors.
* testsuite/ld-mips-elf/unaligned-branch-r6-1.d: Likewise.
* testsuite/ld-mips-elf/compressed-plt-1a.s: Update for microMIPS
R6 branches.
* testsuite/ld-mips-elf/mips-elf.exp: Add new tests.
opcodes/
* micromips-opc.c (decode_micromips_operand): Handle new microMIPS
R6 operands.
(CTC): New macro.
(I37): Likewise.
(I69): Likewise.
(D34): Likewise.
(EVAR6): Likewise.
(micromips_opcodes): Add new instructions.
* mips-dis.c (print_insn_micromips): Check for ISA membership and
ignore special converted to compact entries.
* mips-formats.h (INT_BIAS): Initialise new fields.
(BIT): Likewise.
(MAPPED_INT): Likewise.
(MSB): Likewise.
(REG): Likewise.
(OPTIONAL_REG): Likewise.
(MAPPED_REG): Likewise.
(OPTIONAL_MAPPED_REG): Likewise.
(REG_PAIR): Likewise.
(PCREL): Likewise.
(SPECIAL): Likewise.
(PREV_CHECK): Likewise.
(SPLIT_MAPPED_REG): New macro.
* mips-opc.c (mips_vu0_channel_mask): Initialise new fields.
---
bfd/elfxx-mips.c | 365 +-
gas/config/tc-mips.c | 419 +-
gas/testsuite/gas/mips/abs.s | 1 +
gas/testsuite/gas/mips/bgeu.s | 2 +
gas/testsuite/gas/mips/bltu.s | 2 +
.../gas/mips/branch-local-ignore-3.d | 2 +-
.../gas/mips/branch-local-ignore-n32-3.d | 2 +-
.../gas/mips/branch-local-ignore-n64-3.d | 2 +-
gas/testsuite/gas/mips/llpscp-32-micromips.d | 45 +
gas/testsuite/gas/mips/llpscp-64-micromips.d | 45 +
gas/testsuite/gas/mips/micromips-compact.d | 58 +-
gas/testsuite/gas/mips/micromips-insn32.d | 58 +-
gas/testsuite/gas/mips/micromips-noinsn32.d | 58 +-
gas/testsuite/gas/mips/micromips-trap.d | 58 +-
gas/testsuite/gas/mips/micromips-warn.l | 52 +-
gas/testsuite/gas/mips/micromips.d | 60 +-
gas/testsuite/gas/mips/micromips.l | 212 +-
gas/testsuite/gas/mips/micromips.s | 196 +-
gas/testsuite/gas/mips/micromips@mips32-cp2.s | 4 +
gas/testsuite/gas/mips/micromips@mips32r2.d | 3 +
.../gas/mips/micromipsr6@24k-branch-delay-1.d | 22 +
.../mips/micromipsr6@24k-triple-stores-1.d | 52 +
.../micromipsr6@24k-triple-stores-2-llsc.d | 16 +
.../mips/micromipsr6@24k-triple-stores-2.d | 24 +
.../mips/micromipsr6@24k-triple-stores-3.d | 52 +
.../mips/micromipsr6@24k-triple-stores-4.d | 59 +
.../mips/micromipsr6@24k-triple-stores-5.d | 35 +
.../mips/micromipsr6@24k-triple-stores-6.d | 19 +
.../mips/micromipsr6@24k-triple-stores-7.d | 75 +
.../mips/micromipsr6@24k-triple-stores-8.d | 59 +
gas/testsuite/gas/mips/micromipsr6@abs.d | 19 +
gas/testsuite/gas/mips/micromipsr6@add.d | 25 +
gas/testsuite/gas/mips/micromipsr6@and.d | 36 +
.../micromipsr6@attr-gnu-4-1-msingle-float.l | 3 +
.../micromipsr6@attr-gnu-4-1-msingle-float.s | 1 +
.../micromipsr6@attr-gnu-4-1-msoft-float.l | 3 +
.../micromipsr6@attr-gnu-4-1-msoft-float.s | 1 +
gas/testsuite/gas/mips/micromipsr6@beq.d | 37 +
gas/testsuite/gas/mips/micromipsr6@bge.d | 56 +
gas/testsuite/gas/mips/micromipsr6@bgeu.d | 48 +
gas/testsuite/gas/mips/micromipsr6@blt.d | 56 +
gas/testsuite/gas/mips/micromipsr6@bltu.d | 48 +
.../gas/mips/micromipsr6@branch-misc-1.d | 29 +
.../gas/mips/micromipsr6@branch-misc-2-64.d | 41 +
.../gas/mips/micromipsr6@branch-misc-2.d | 29 +
.../mips/micromipsr6@branch-misc-2pic-64.d | 41 +
.../gas/mips/micromipsr6@branch-misc-2pic.d | 29 +
.../gas/mips/micromipsr6@branch-misc-4-64.d | 31 +
.../gas/mips/micromipsr6@branch-misc-4.d | 23 +
.../gas/mips/micromipsr6@branch-misc-5-64.d | 24 +
.../gas/mips/micromipsr6@branch-misc-5.d | 18 +
.../mips/micromipsr6@branch-misc-5pic-64.d | 24 +
.../gas/mips/micromipsr6@branch-misc-5pic.d | 18 +
.../gas/mips/micromipsr6@branch-swap-3.d | 38 +
.../gas/mips/micromipsr6@branch-swap-4.d | 5 +
gas/testsuite/gas/mips/micromipsr6@c0.d | 5 +
gas/testsuite/gas/mips/micromipsr6@c0.l | 257 +
gas/testsuite/gas/mips/micromipsr6@c1.d | 5 +
gas/testsuite/gas/mips/micromipsr6@c1.l | 257 +
gas/testsuite/gas/mips/micromipsr6@c2.d | 5 +
gas/testsuite/gas/mips/micromipsr6@c2.l | 193 +
gas/testsuite/gas/mips/micromipsr6@c3.d | 5 +
gas/testsuite/gas/mips/micromipsr6@c3.l | 257 +
gas/testsuite/gas/mips/micromipsr6@cache.d | 13 +
gas/testsuite/gas/mips/micromipsr6@cp0b.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp0b.l | 3 +
gas/testsuite/gas/mips/micromipsr6@cp0bl.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp0bl.l | 3 +
gas/testsuite/gas/mips/micromipsr6@cp0c.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp0c.l | 65 +
gas/testsuite/gas/mips/micromipsr6@cp0m.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp0m.l | 65 +
gas/testsuite/gas/mips/micromipsr6@cp2b.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp2b.l | 3 +
gas/testsuite/gas/mips/micromipsr6@cp2bl.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp2bl.l | 3 +
gas/testsuite/gas/mips/micromipsr6@cp3.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp3.l | 129 +
gas/testsuite/gas/mips/micromipsr6@cp3b.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp3b.l | 3 +
gas/testsuite/gas/mips/micromipsr6@cp3bl.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp3bl.l | 3 +
gas/testsuite/gas/mips/micromipsr6@cp3d.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp3d.l | 65 +
gas/testsuite/gas/mips/micromipsr6@cp3m.d | 5 +
gas/testsuite/gas/mips/micromipsr6@cp3m.l | 65 +
gas/testsuite/gas/mips/micromipsr6@dadd.d | 5 +
gas/testsuite/gas/mips/micromipsr6@dadd.l | 5 +
gas/testsuite/gas/mips/micromipsr6@dli.d | 116 +
.../gas/mips/micromipsr6@elf-rel29.d | 18 +
gas/testsuite/gas/mips/micromipsr6@eva.d | 950 ++++
.../gas/mips/micromipsr6@jal-mask-11.d | 19 +
.../gas/mips/micromipsr6@jal-mask-12.d | 19 +
.../gas/mips/micromipsr6@jal-range.l | 8 +
.../gas/mips/micromipsr6@jal-range.s | 8 +
.../mips/micromipsr6@jal-svr4pic-local-n32.d | 32 +
.../mips/micromipsr6@jal-svr4pic-local-n64.d | 36 +
.../gas/mips/micromipsr6@jal-svr4pic-local.d | 31 +
.../mips/micromipsr6@jal-svr4pic-noreorder.d | 41 +
.../gas/mips/micromipsr6@jal-svr4pic.d | 41 +
gas/testsuite/gas/mips/micromipsr6@jal.d | 22 +
.../gas/mips/micromipsr6@lb-svr4pic-ilocks.d | 155 +
.../gas/mips/micromipsr6@ld-zero-2.d | 13 +
.../gas/mips/micromipsr6@ld-zero-3.d | 21 +
.../gas/mips/micromipsr6@ldpc-unalign.l | 9 +
.../gas/mips/micromipsr6@ldpc-unalign.s | 18 +
gas/testsuite/gas/mips/micromipsr6@li.d | 18 +
gas/testsuite/gas/mips/micromipsr6@lui.d | 25 +
gas/testsuite/gas/mips/micromipsr6@mcu.d | 110 +
.../gas/mips/micromipsr6@micromips-insn32.d | 4448 ++++++++++++++++
.../gas/mips/micromipsr6@micromips.d | 4495 +++++++++++++++++
.../gas/mips/micromipsr6@mips32-cp2.d | 16 +
.../gas/mips/micromipsr6@mips32-dsp.d | 148 +
.../gas/mips/micromipsr6@mips32-dspr2.d | 74 +
.../gas/mips/micromipsr6@mips32-dspr3.d | 23 +
.../gas/mips/micromipsr6@mips32-sf32.d | 20 +
gas/testsuite/gas/mips/micromipsr6@mips32.d | 32 +
gas/testsuite/gas/mips/micromipsr6@mips32r2.d | 49 +
gas/testsuite/gas/mips/micromipsr6@mips4-fp.d | 13 +
gas/testsuite/gas/mips/micromipsr6@mips4-fp.s | 11 +
gas/testsuite/gas/mips/micromipsr6@mips4.d | 11 +
gas/testsuite/gas/mips/micromipsr6@mips5-fp.d | 11 +
gas/testsuite/gas/mips/micromipsr6@mips5-fp.s | 8 +
.../gas/mips/micromipsr6@pcrel-reloc-4-r6.d | 69 +
gas/testsuite/gas/mips/micromipsr6@pref.d | 13 +
gas/testsuite/gas/mips/micromipsr6@r5.d | 9 +
.../mips/micromipsr6@r6-branch-constraints.l | 21 +
.../mips/micromipsr6@r6-branch-constraints.s | 21 +
.../gas/mips/micromipsr6@relax-swap3.d | 20 +
gas/testsuite/gas/mips/micromipsr6@rfe.d | 5 +
gas/testsuite/gas/mips/micromipsr6@rfe.l | 2 +
gas/testsuite/gas/mips/mips.exp | 113 +-
gas/testsuite/gas/mips/mips32r2.d | 63 +-
gas/testsuite/gas/mips/mips32r2.s | 5 +
gas/testsuite/gas/mips/mipsr6@mips32r2.d | 63 +-
gas/testsuite/gas/mips/pcrel-reloc-4-r6.d | 4 +-
gas/testsuite/gas/mips/pcrel-reloc-4.s | 2 +
gas/testsuite/gas/mips/ur6-64-removed.l | 8 +
gas/testsuite/gas/mips/ur6-64-removed.s | 10 +
gas/testsuite/gas/mips/ur6-ctc-err.l | 63 +
gas/testsuite/gas/mips/ur6-ctc-err.s | 179 +
gas/testsuite/gas/mips/ur6-ctc.d | 193 +
gas/testsuite/gas/mips/ur6-ctc.s | 157 +
gas/testsuite/gas/mips/ur6-removed.l | 186 +
gas/testsuite/gas/mips/ur6-removed.s | 192 +
gas/testsuite/gas/mips/ur6.d | 419 ++
gas/testsuite/gas/mips/ur6.s | 306 ++
include/opcode/mips.h | 109 +-
.../ld-mips-elf/compressed-plt-1-o32-r6.od | 103 +
.../ld-mips-elf/compressed-plt-1-o32-r6.rd | 79 +
.../compressed-plt-1-o32-umips-insn32-only.od | 105 +
.../compressed-plt-1-o32-umips-insn32-only.rd | 81 +
...ompressed-plt-1-o32-umipsr6-insn32-only.od | 96 +
...ompressed-plt-1-o32-umipsr6-insn32-only.rd | 81 +
.../compressed-plt-1-o32-umipsr6-only.od | 103 +
.../compressed-plt-1-o32-umipsr6-only.rd | 81 +
.../ld-mips-elf/compressed-plt-1-umipsr6.ld | 40 +
ld/testsuite/ld-mips-elf/compressed-plt-1a.s | 9 +-
ld/testsuite/ld-mips-elf/mips-elf.exp | 39 +-
.../pic-and-nonpic-1-micromipsr6-rel.dd | 39 +
.../pic-and-nonpic-1-micromipsr6-rel.nd | 5 +
.../pic-and-nonpic-1-micromipsr6.dd | 45 +
.../pic-and-nonpic-1-micromipsr6.nd | 8 +
.../pic-and-nonpic-1a-micromipsr6.s | 30 +
.../unaligned-branch-ignore-r6-1.d | 15 +-
.../ld-mips-elf/unaligned-branch-r6-1.d | 13 +-
.../ld-mips-elf/undefweak-overflow-r6.d | 30 +
.../ld-mips-elf/undefweak-overflow-r6.s | 34 +
ld/testsuite/ld-mips-elf/undefweak-overflow.d | 22 +-
ld/testsuite/ld-mips-elf/undefweak-overflow.s | 10 +-
opcodes/micromips-opc.c | 1136 +++--
opcodes/mips-dis.c | 4 +
opcodes/mips-formats.h | 34 +-
opcodes/mips-opc.c | 2 +-
174 files changed, 18719 insertions(+), 1035 deletions(-)
create mode 100644 gas/testsuite/gas/mips/llpscp-32-micromips.d
create mode 100644 gas/testsuite/gas/mips/llpscp-64-micromips.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@24k-branch-delay-1.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-1.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-2-llsc.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-2.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-3.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-4.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-5.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-6.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-7.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-8.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@abs.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@add.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@and.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msingle-float.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msingle-float.s
create mode 100644 gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msoft-float.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msoft-float.s
create mode 100644 gas/testsuite/gas/mips/micromipsr6@beq.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@bge.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@bgeu.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@blt.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@bltu.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-1.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-2-64.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-2.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-2pic-64.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-2pic.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-4-64.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-4.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-5-64.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-5.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-5pic-64.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-misc-5pic.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-swap-3.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@branch-swap-4.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@c0.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@c0.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@c1.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@c1.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@c2.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@c2.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@c3.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@c3.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cache.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp0b.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp0b.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp0bl.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp0bl.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp0c.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp0c.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp0m.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp0m.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp2b.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp2b.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp2bl.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp2bl.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp3.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp3.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp3b.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp3b.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp3bl.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp3bl.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp3d.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp3d.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp3m.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@cp3m.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@dadd.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@dadd.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@dli.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@elf-rel29.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@eva.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@jal-mask-11.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@jal-mask-12.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@jal-range.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@jal-range.s
create mode 100644 gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local-n32.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local-n64.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-noreorder.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@jal-svr4pic.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@jal.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@lb-svr4pic-ilocks.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@ld-zero-2.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@ld-zero-3.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@ldpc-unalign.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@ldpc-unalign.s
create mode 100644 gas/testsuite/gas/mips/micromipsr6@li.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@lui.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mcu.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@micromips-insn32.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@micromips.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips32-cp2.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips32-dsp.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips32-dspr2.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips32-dspr3.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips32-sf32.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips32.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips32r2.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips4-fp.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips4-fp.s
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips4.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips5-fp.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@mips5-fp.s
create mode 100644 gas/testsuite/gas/mips/micromipsr6@pcrel-reloc-4-r6.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@pref.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@r5.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@r6-branch-constraints.l
create mode 100644 gas/testsuite/gas/mips/micromipsr6@r6-branch-constraints.s
create mode 100644 gas/testsuite/gas/mips/micromipsr6@relax-swap3.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@rfe.d
create mode 100644 gas/testsuite/gas/mips/micromipsr6@rfe.l
create mode 100644 gas/testsuite/gas/mips/ur6-64-removed.l
create mode 100644 gas/testsuite/gas/mips/ur6-64-removed.s
create mode 100644 gas/testsuite/gas/mips/ur6-ctc-err.l
create mode 100644 gas/testsuite/gas/mips/ur6-ctc-err.s
create mode 100644 gas/testsuite/gas/mips/ur6-ctc.d
create mode 100644 gas/testsuite/gas/mips/ur6-ctc.s
create mode 100644 gas/testsuite/gas/mips/ur6-removed.l
create mode 100644 gas/testsuite/gas/mips/ur6-removed.s
create mode 100644 gas/testsuite/gas/mips/ur6.d
create mode 100644 gas/testsuite/gas/mips/ur6.s
create mode 100644 ld/testsuite/ld-mips-elf/compressed-plt-1-o32-r6.od
create mode 100644 ld/testsuite/ld-mips-elf/compressed-plt-1-o32-r6.rd
create mode 100644 ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-insn32-only.od
create mode 100644 ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-insn32-only.rd
create mode 100644 ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-insn32-only.od
create mode 100644 ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-insn32-only.rd
create mode 100644 ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-only.od
create mode 100644 ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-only.rd
create mode 100644 ld/testsuite/ld-mips-elf/compressed-plt-1-umipsr6.ld
create mode 100644 ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6-rel.dd
create mode 100644 ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6-rel.nd
create mode 100644 ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6.dd
create mode 100644 ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6.nd
create mode 100644 ld/testsuite/ld-mips-elf/pic-and-nonpic-1a-micromipsr6.s
create mode 100644 ld/testsuite/ld-mips-elf/undefweak-overflow-r6.d
create mode 100644 ld/testsuite/ld-mips-elf/undefweak-overflow-r6.s
diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index 59444b063a4..1dfd877b210 100644
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -295,10 +295,12 @@ struct mips_elf_la25_stub {
#define LA25_J(VAL) (0x08000000 | (((VAL) >> 2) & 0x3ffffff)) /* j VAL */
#define LA25_BC(VAL) (0xc8000000 | (((VAL) >> 2) & 0x3ffffff)) /* bc VAL */
#define LA25_ADDIU(VAL) (0x27390000 | (VAL)) /* addiu t9,t9,VAL */
-#define LA25_LUI_MICROMIPS(VAL) \
- (0x41b90000 | (VAL)) /* lui t9,VAL */
+#define LA25_LUI_MICROMIPS(ABFD,VAL) /* lui t9,VAL */ \
+ (MIPSR6_P (ABFD) ? (0x13200000 | (VAL)) : (0x41b90000 | (VAL)))
#define LA25_J_MICROMIPS(VAL) \
(0xd4000000 | (((VAL) >> 1) & 0x3ffffff)) /* j VAL */
+#define LA25_BC_MICROMIPS(VAL) \
+ (0x94000000 | (((VAL) >> 1) & 0x3ffffff)) /* bc VAL */
#define LA25_ADDIU_MICROMIPS(VAL) \
(0x33390000 | (VAL)) /* addiu t9,t9,VAL */
@@ -462,6 +464,9 @@ struct mips_elf_link_hash_table
/* True if we are targetting R6 compact branches. */
bool compact_branches;
+ /* True if we're generating code for VxWorks. */
+ bool is_vxworks;
+
/* True if we already reported the small-data section overflow. */
bool small_data_overflow_reported;
@@ -527,6 +532,9 @@ struct mips_elf_link_hash_table
returns null. */
asection *(*add_stub_section) (const char *, asection *, asection *);
+ /* Small local sym cache. */
+ struct sym_cache sym_cache;
+
/* Is the PLT header compressed? */
unsigned int plt_header_is_comp : 1;
};
@@ -960,10 +968,12 @@ static bfd *reldyn_sorting_bfd;
: 0xff3c8010) /* lw t9,0x8010(gp) */
#define STUB_MOVE_MICROMIPS 0x0dff /* move t7,ra */
#define STUB_MOVE32_MICROMIPS 0x001f7a90 /* or t7,ra,zero */
-#define STUB_LUI_MICROMIPS(VAL) \
- (0x41b80000 + (VAL)) /* lui t8,VAL */
+#define STUB_LUI_MICROMIPS(abfd, VAL) /* lui t8,VAL */ \
+ (MIPSR6_P (abfd) ? 0x13000000 + (VAL) : 0x41b80000 + (VAL))
#define STUB_JALR_MICROMIPS 0x45d9 /* jalr t9 */
+#define STUB_JALRC_MICROMIPS 0x472b /* jalrc t9 */
#define STUB_JALR32_MICROMIPS 0x03f90f3c /* jalr ra,t9 */
+#define STUB_JALRC32_MICROMIPS 0x03f90f3c /* jalrc ra,t9 */
#define STUB_ORI_MICROMIPS(VAL) \
(0x53180000 + (VAL)) /* ori t8,t8,VAL */
#define STUB_LI16U_MICROMIPS(VAL) \
@@ -1154,6 +1164,20 @@ static const bfd_vma micromips_o32_exec_plt0_entry[] =
0x0c00 /* nop */
};
+/* The format of the microMIPSR6 first PLT entry in an O32 executable. */
+static const bfd_vma micromipsr6_o32_exec_plt0_entry[] =
+{
+ 0x7860, 0x0000, /* addiupc $3, (&GOTPLT[0]) - . */
+ 0xff23, 0x0000, /* lw $25, 0($3) */
+ 0x0535, /* subu $2, $2, $3 */
+ 0x2525, /* srl $2, $2, 2 */
+ 0x3302, 0xfffe, /* subu $24, $2, 2 */
+ 0x0dff, /* move $15, $31 */
+ 0x0f83, /* move $28, $3 */
+ 0x472b, /* jalrc $25 */
+ 0x0c00 /* nop */
+};
+
/* The format of the microMIPS first PLT entry in an O32 executable
in the insn32 mode. */
static const bfd_vma micromips_insn32_o32_exec_plt0_entry[] =
@@ -1168,6 +1192,20 @@ static const bfd_vma micromips_insn32_o32_exec_plt0_entry[] =
0x3318, 0xfffe /* subu $24, $24, 2 */
};
+/* The format of the microMIPSR6 first PLT entry in an O32 executable
+ in the insn32 mode. */
+static const bfd_vma micromipsr6_insn32_o32_exec_plt0_entry[] =
+{
+ 0x1380, 0x0000, /* lui $28, %hi(&GOTPLT[0]) */
+ 0xff3c, 0x0000, /* lw $25, %lo(&GOTPLT[0])($28) */
+ 0x339c, 0x0000, /* addiu $28, $28, %lo(&GOTPLT[0]) */
+ 0x0398, 0xc1d0, /* subu $24, $24, $28 */
+ 0x001f, 0x7a90, /* move $15, $31 */
+ 0x0318, 0x1040, /* srl $24, $24, 2 */
+ 0x3318, 0xfffe, /* subu $24, $24, 2 */
+ 0x03f9, 0x0f3c /* jalrc $25 */
+};
+
/* The format of subsequent standard PLT entries. */
static const bfd_vma mips_exec_plt_entry[] =
{
@@ -1217,6 +1255,16 @@ static const bfd_vma micromips_o32_exec_plt_entry[] =
0x0f02 /* move $24, $2 */
};
+/* The format of subsequent microMIPSR6 o32 PLT entries. We use v0 ($2)
+ as a temporary because t8 ($24) is not addressable with ADDIUPC. */
+static const bfd_vma micromipsr6_o32_exec_plt_entry[] =
+{
+ 0x7840, 0x0000, /* addiupc $2, (.got.plt entry) - . */
+ 0xff22, 0x0000, /* lw $25, 0($2) */
+ 0x0f02, /* move $24, $2 */
+ 0x4723 /* jrc $25 */
+};
+
/* The format of subsequent microMIPS o32 PLT entries in the insn32 mode. */
static const bfd_vma micromips_insn32_o32_exec_plt_entry[] =
{
@@ -1226,6 +1274,15 @@ static const bfd_vma micromips_insn32_o32_exec_plt_entry[] =
0x330f, 0x0000 /* addiu $24, $15, %lo(.got.plt entry) */
};
+/* The format of subsequent microMIPS o32 PLT entries in the insn32 mode. */
+static const bfd_vma micromipsr6_insn32_o32_exec_plt_entry[] =
+{
+ 0x11e0, 0x0000, /* lui $15, %hi(.got.plt entry) */
+ 0xff2f, 0x0000, /* lw $25, %lo(.got.plt entry)($15) */
+ 0x330f, 0x0000, /* addiu $24, $15, %lo(.got.plt entry) */
+ 0x8019, 0x0000 /* jic $25,0 */
+};
+
/* The format of the first PLT entry in a VxWorks executable. */
static const bfd_vma mips_vxworks_exec_plt0_entry[] =
{
@@ -2288,7 +2345,8 @@ hi16_reloc_p (int r_type)
return (r_type == R_MIPS_HI16
|| r_type == R_MIPS16_HI16
|| r_type == R_MICROMIPS_HI16
- || r_type == R_MIPS_PCHI16);
+ || r_type == R_MIPS_PCHI16
+ || r_type == R_MICROMIPS_PCHI16);
}
static inline bool
@@ -2297,7 +2355,8 @@ lo16_reloc_p (int r_type)
return (r_type == R_MIPS_LO16
|| r_type == R_MIPS16_LO16
|| r_type == R_MICROMIPS_LO16
- || r_type == R_MIPS_PCLO16);
+ || r_type == R_MIPS_PCLO16
+ || r_type == R_MICROMIPS_PCLO16);
}
static inline bool
@@ -2322,6 +2381,8 @@ b_reloc_p (int r_type)
|| r_type == R_MIPS_PC16
|| r_type == R_MIPS_GNU_REL16_S2
|| r_type == R_MIPS16_PC16_S1
+ || r_type == R_MICROMIPS_PC26_S1
+ || r_type == R_MICROMIPS_PC21_S1
|| r_type == R_MICROMIPS_PC16_S1
|| r_type == R_MICROMIPS_PC10_S1
|| r_type == R_MICROMIPS_PC7_S1);
@@ -2331,7 +2392,9 @@ static inline bool
aligned_pcrel_reloc_p (int r_type)
{
return (r_type == R_MIPS_PC18_S3
- || r_type == R_MIPS_PC19_S2);
+ || r_type == R_MIPS_PC19_S2
+ || r_type == R_MICROMIPS_PC18_S3
+ || r_type == R_MICROMIPS_PC19_S2);
}
static inline bool
@@ -2356,6 +2419,8 @@ micromips_branch_reloc_p (int r_type)
{
return (r_type == R_MICROMIPS_26_S1
|| r_type == R_MICROMIPS_PC16_S1
+ || r_type == R_MICROMIPS_PC21_S1
+ || r_type == R_MICROMIPS_PC26_S1
|| r_type == R_MICROMIPS_PC10_S1
|| r_type == R_MICROMIPS_PC7_S1);
}
@@ -2522,6 +2587,11 @@ _bfd_mips_elf_gprel16_with_gp (bfd *abfd, asymbol *symbol,
return bfd_reloc_ok;
}
+
+/* FIXME: This should not be a static variable. */
+
+static struct mips_hi16 *mips_hi16_list;
+
/* A howto special_function for REL *HI16 relocations. We can only
calculate the correct value once we've seen the partnering
*LO16 relocation, so just save the information for later.
@@ -5372,6 +5442,8 @@ mips_elf_relocation_needs_la25_stub (bfd *input_bfd, int r_type,
case R_MICROMIPS_PC7_S1:
case R_MICROMIPS_PC10_S1:
case R_MICROMIPS_PC16_S1:
+ case R_MICROMIPS_PC21_S1:
+ case R_MICROMIPS_PC26_S1:
case R_MICROMIPS_PC23_S2:
return true;
@@ -6360,7 +6432,12 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
if (howto->partial_inplace)
addend = _bfd_mips_elf_sign_extend (addend, 23);
- if ((symbol + addend) & 3)
+ /* No need to exclude weak undefined symbols here as they resolve
+ to 0 and never set `*cross_mode_jump_p', so this alignment check
+ will never trigger for them. */
+ if (*cross_mode_jump_p
+ ? ((symbol + addend) & 1) != 1
+ : ((symbol + addend) & 3) != 0)
return bfd_reloc_outofrange;
value = symbol + addend - p;
@@ -6374,7 +6451,12 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
if (howto->partial_inplace)
addend = _bfd_mips_elf_sign_extend (addend, 28);
- if ((symbol + addend) & 3)
+ /* No need to exclude weak undefined symbols here as they resolve
+ to 0 and never set `*cross_mode_jump_p', so this alignment check
+ will never trigger for them. */
+ if (*cross_mode_jump_p
+ ? ((symbol + addend) & 1) != 1
+ : ((symbol + addend) & 3) != 0)
return bfd_reloc_outofrange;
value = symbol + addend - p;
@@ -6385,9 +6467,16 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
break;
case R_MIPS_PC18_S3:
+ case R_MICROMIPS_PC18_S3:
if (howto->partial_inplace)
addend = _bfd_mips_elf_sign_extend (addend, 21);
+ /* If the user targetted a code label instead of data then
+ we mask the LSB. For data labels then we do a full alignment
+ check. */
+ if (target_is_micromips_code_p)
+ symbol = (symbol | 1) ^ 1;
+
if ((symbol + addend) & 7)
return bfd_reloc_outofrange;
@@ -6399,13 +6488,20 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
break;
case R_MIPS_PC19_S2:
+ case R_MICROMIPS_PC19_S2:
if (howto->partial_inplace)
addend = _bfd_mips_elf_sign_extend (addend, 21);
+ /* If the user targetted a code label instead of data then
+ we mask the LSB. For data labels then we do a full alignment
+ check. */
+ if (target_is_micromips_code_p)
+ symbol = (symbol | 1) ^ 1;
+
if ((symbol + addend) & 3)
return bfd_reloc_outofrange;
- value = symbol + addend - p;
+ value = symbol + addend - ((p | 3) ^ 3);
if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
overflowed_p = mips_elf_overflow_p (value, 21);
value >>= howto->rightshift;
@@ -6413,11 +6509,13 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
break;
case R_MIPS_PCHI16:
+ case R_MICROMIPS_PCHI16:
value = mips_elf_high (symbol + addend - p);
value &= howto->dst_mask;
break;
case R_MIPS_PCLO16:
+ case R_MICROMIPS_PCLO16:
if (howto->partial_inplace)
addend = _bfd_mips_elf_sign_extend (addend, 16);
value = symbol + addend - p;
@@ -6475,6 +6573,40 @@ mips_elf_calculate_relocation (bfd *abfd, bfd *input_bfd,
value &= howto->dst_mask;
break;
+ case R_MICROMIPS_PC21_S1:
+ if (howto->partial_inplace)
+ addend = _bfd_mips_elf_sign_extend (addend, 22);
+
+ if ((was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ && (*cross_mode_jump_p
+ ? ((symbol + addend) & 3) != 0
+ : ((symbol + addend) & 1) == 0))
+ return bfd_reloc_outofrange;
+
+ value = symbol + addend - p;
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 22);
+ value >>= howto->rightshift;
+ value &= howto->dst_mask;
+ break;
+
+ case R_MICROMIPS_PC26_S1:
+ if (howto->partial_inplace)
+ addend = _bfd_mips_elf_sign_extend (addend, 27);
+
+ if ((was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ && (*cross_mode_jump_p
+ ? ((symbol + addend) & 3) != 0
+ : ((symbol + addend) & 1) == 0))
+ return bfd_reloc_outofrange;
+
+ value = symbol + addend - p;
+ if (was_local_p || h->root.root.type != bfd_link_hash_undefweak)
+ overflowed_p = mips_elf_overflow_p (value, 27);
+ value >>= howto->rightshift;
+ value &= howto->dst_mask;
+ break;
+
case R_MICROMIPS_PC23_S2:
if (howto->partial_inplace)
addend = _bfd_mips_elf_sign_extend (addend, 25);
@@ -6598,6 +6730,7 @@ mips_elf_perform_relocation (struct bfd_link_info *info,
bfd_vma x;
bfd_byte *location;
int r_type = ELF_R_TYPE (input_bfd, relocation->r_info);
+ unsigned int size;
/* Figure out where the relocation is occurring. */
location = contents + relocation->r_offset;
@@ -6628,7 +6761,16 @@ mips_elf_perform_relocation (struct bfd_link_info *info,
return true;
}
}
- if (cross_mode_jump_p && jal_reloc_p (r_type))
+ /* JALX has been removed in MIPSR6. */
+ if (cross_mode_jump_p && MIPSR6_P (input_bfd))
+ {
+ info->callbacks->einfo
+ (_("%X%H: unsupported branch or jump between ISA modes; " \
+ "MIPS R6 does not support the JALX instruction\n"),
+ input_bfd, input_section, relocation->r_offset);
+ return true;
+ }
+ else if (cross_mode_jump_p && jal_reloc_p (r_type))
{
bool ok;
bfd_vma opcode = x >> 26;
@@ -8292,6 +8434,8 @@ mips_elf_add_lo16_rel_addend (bfd *abfd,
r_type = ELF_R_TYPE (abfd, rel->r_info);
if (mips16_reloc_p (r_type))
lo16_type = R_MIPS16_LO16;
+ else if (r_type == R_MICROMIPS_PCHI16)
+ lo16_type = R_MICROMIPS_PCLO16;
else if (micromips_reloc_p (r_type))
lo16_type = R_MICROMIPS_LO16;
else if (r_type == R_MIPS_PCHI16)
@@ -8800,8 +8944,8 @@ _bfd_mips_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
/* Fall through. */
case R_MIPS_GOT_HI16:
- case R_MIPS_GOT_OFST:
- case R_MIPS_TLS_GOTTPREL:
+ case R_MIPS_GOT_OFST:
+ case R_MIPS_TLS_GOTTPREL:
case R_MIPS_TLS_GD:
case R_MIPS_TLS_LDM:
case R_MIPS16_TLS_GOTTPREL:
@@ -8886,6 +9030,8 @@ _bfd_mips_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
case R_MICROMIPS_PC7_S1:
case R_MICROMIPS_PC10_S1:
case R_MICROMIPS_PC16_S1:
+ case R_MICROMIPS_PC21_S1:
+ case R_MICROMIPS_PC26_S1:
case R_MICROMIPS_PC23_S2:
call_reloc_p = true;
break;
@@ -10691,17 +10837,33 @@ _bfd_mips_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info,
case bfd_reloc_outofrange:
msg = NULL;
if (jal_reloc_p (howto->type))
- msg = (cross_mode_jump_p
- ? _("cannot convert a jump to JALX "
- "for a non-word-aligned address")
- : (howto->type == R_MIPS16_26
- ? _("jump to a non-word-aligned address")
- : _("jump to a non-instruction-aligned address")));
+ {
+ msg = (cross_mode_jump_p
+ ? (MIPSR6_P (input_bfd)
+ ? NULL
+ : _("cannot convert a jump to JALX "
+ "for a non-word-aligned address"))
+ : (howto->type == R_MIPS16_26
+ ? _("jump to a non-word-aligned address")
+ : _("jump to a non-instruction-aligned address")));
+ /* Defer to mips_elf_perform_relocation to raise an error for
+ MIPSR6 cross mode jumps. */
+ if (!msg)
+ break;
+ }
else if (b_reloc_p (howto->type))
- msg = (cross_mode_jump_p
- ? _("cannot convert a branch to JALX "
- "for a non-word-aligned address")
- : _("branch to a non-instruction-aligned address"));
+ {
+ msg = (cross_mode_jump_p
+ ? (MIPSR6_P (input_bfd)
+ ? NULL
+ : _("cannot convert a branch to JALX "
+ "for a non-word-aligned address"))
+ : _("branch to a non-instruction-aligned address"));
+ /* Defer to mips_elf_perform_relocation to raise an error for
+ MIPSR6 cross mode jumps. */
+ if (!msg)
+ break;
+ }
else if (aligned_pcrel_reloc_p (howto->type))
msg = _("PC-relative load from unaligned address");
if (msg)
@@ -10845,7 +11007,7 @@ mips_elf_create_la25_stub (void **slot, void *data)
if (ELF_ST_IS_MICROMIPS (stub->h->root.other))
{
bfd_put_micromips_32 (hti->output_bfd,
- LA25_LUI_MICROMIPS (target_high),
+ LA25_LUI_MICROMIPS (hti->output_bfd, target_high),
loc);
bfd_put_micromips_32 (hti->output_bfd,
LA25_ADDIU_MICROMIPS (target_low),
@@ -10864,11 +11026,22 @@ mips_elf_create_la25_stub (void **slot, void *data)
if (ELF_ST_IS_MICROMIPS (stub->h->root.other))
{
bfd_put_micromips_32 (hti->output_bfd,
- LA25_LUI_MICROMIPS (target_high), loc);
- bfd_put_micromips_32 (hti->output_bfd,
- LA25_J_MICROMIPS (target), loc + 4);
- bfd_put_micromips_32 (hti->output_bfd,
- LA25_ADDIU_MICROMIPS (target_low), loc + 8);
+ LA25_LUI_MICROMIPS (hti->output_bfd,
+ target_high), loc);
+ if (MIPSR6_P (hti->output_bfd))
+ {
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_ADDIU_MICROMIPS (target_low), loc + 4);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_BC_MICROMIPS (pcrel_offset), loc + 8);
+ }
+ else
+ {
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_J_MICROMIPS (target), loc + 4);
+ bfd_put_micromips_32 (hti->output_bfd,
+ LA25_ADDIU_MICROMIPS (target_low), loc + 8);
+ }
bfd_put_32 (hti->output_bfd, 0, loc + 12);
}
else
@@ -11090,31 +11263,60 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
}
else if (htab->insn32)
{
- const bfd_vma *plt_entry = micromips_insn32_o32_exec_plt_entry;
+ const bfd_vma *plt_entry;
+
+ if (MIPSR6_P (output_bfd))
+ plt_entry = micromipsr6_insn32_o32_exec_plt_entry;
+ else
+ plt_entry = micromips_insn32_o32_exec_plt_entry;
bfd_put_16 (output_bfd, plt_entry[0], loc);
bfd_put_16 (output_bfd, got_address_high, loc + 2);
bfd_put_16 (output_bfd, plt_entry[2], loc + 4);
bfd_put_16 (output_bfd, got_address_low, loc + 6);
- bfd_put_16 (output_bfd, plt_entry[4], loc + 8);
- bfd_put_16 (output_bfd, plt_entry[5], loc + 10);
- bfd_put_16 (output_bfd, plt_entry[6], loc + 12);
- bfd_put_16 (output_bfd, got_address_low, loc + 14);
+
+ if (MIPSR6_P (output_bfd))
+ {
+ bfd_put_16 (output_bfd, plt_entry[4], loc + 8);
+ bfd_put_16 (output_bfd, got_address_low, loc + 10);
+ bfd_put_16 (output_bfd, plt_entry[6], loc + 12);
+ bfd_put_16 (output_bfd, plt_entry[7], loc + 14);
+ }
+ else
+ {
+ bfd_put_16 (output_bfd, plt_entry[4], loc + 8);
+ bfd_put_16 (output_bfd, plt_entry[5], loc + 10);
+ bfd_put_16 (output_bfd, plt_entry[6], loc + 12);
+ bfd_put_16 (output_bfd, got_address_low, loc + 14);
+ }
}
else
{
const bfd_vma *plt_entry = micromips_o32_exec_plt_entry;
bfd_signed_vma gotpc_offset;
+ bfd_signed_vma addiupc_range;
bfd_vma loc_address;
+ if (MIPSR6_P (output_bfd))
+ plt_entry = micromipsr6_o32_exec_plt_entry;
+ else
+ plt_entry = micromips_o32_exec_plt_entry;
+
BFD_ASSERT (got_address % 4 == 0);
loc_address = (htab->root.splt->output_section->vma
+ htab->root.splt->output_offset + plt_offset);
gotpc_offset = got_address - ((loc_address | 3) ^ 3);
- /* ADDIUPC has a span of +/-16MB, check we're in range. */
- if (gotpc_offset + 0x1000000 >= 0x2000000)
+ if (MIPSR6_P (output_bfd))
+ /* ADDIUPC has a span of +/-1MB. */
+ addiupc_range = 0x100000;
+ else
+ /* ADDIUPC has a span of +/-16MB. */
+ addiupc_range = 0x1000000;
+
+ /* Check we're in range. */
+ if (gotpc_offset + addiupc_range >= addiupc_range * 2)
{
_bfd_error_handler
/* xgettext:c-format */
@@ -11127,8 +11329,12 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
bfd_set_error (bfd_error_no_error);
return false;
}
- bfd_put_16 (output_bfd,
- plt_entry[0] | ((gotpc_offset >> 18) & 0x7f), loc);
+ if (MIPSR6_P (output_bfd))
+ bfd_put_16 (output_bfd,
+ plt_entry[0] | ((gotpc_offset >> 18) & 0x7), loc);
+ else
+ bfd_put_16 (output_bfd,
+ plt_entry[0] | ((gotpc_offset >> 18) & 0x7f), loc);
bfd_put_16 (output_bfd, (gotpc_offset >> 2) & 0xffff, loc + 2);
bfd_put_16 (output_bfd, plt_entry[2], loc + 4);
bfd_put_16 (output_bfd, plt_entry[3], loc + 6);
@@ -11214,20 +11420,24 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
long dynindx_hi = (h->dynindx >> 16) & 0x7fff;
bfd_put_micromips_32 (output_bfd,
- STUB_LUI_MICROMIPS (dynindx_hi),
- stub + idx);
- idx += 4;
- }
- if (htab->insn32)
- {
- bfd_put_micromips_32 (output_bfd, STUB_JALR32_MICROMIPS,
+ STUB_LUI_MICROMIPS (output_bfd, dynindx_hi),
stub + idx);
idx += 4;
}
- else
+
+ if (!MIPSR6_P (output_bfd))
{
- bfd_put_16 (output_bfd, STUB_JALR_MICROMIPS, stub + idx);
- idx += 2;
+ if (htab->insn32)
+ {
+ bfd_put_micromips_32 (output_bfd, STUB_JALR32_MICROMIPS,
+ stub + idx);
+ idx += 4;
+ }
+ else
+ {
+ bfd_put_16 (output_bfd, STUB_JALR_MICROMIPS, stub + idx);
+ idx += 2;
+ }
}
/* If a large stub is not required and sign extension is not a
@@ -11245,6 +11455,16 @@ _bfd_mips_elf_finish_dynamic_symbol (bfd *output_bfd,
STUB_LI16S_MICROMIPS (output_bfd,
h->dynindx),
stub + idx);
+ idx += 4;
+
+ if (MIPSR6_P (output_bfd))
+ {
+ if (htab->insn32)
+ bfd_put_micromips_32 (output_bfd, STUB_JALRC32_MICROMIPS,
+ stub + idx);
+ else
+ bfd_put_16 (output_bfd, STUB_JALRC_MICROMIPS, stub + idx);
+ }
}
else
{
@@ -11666,9 +11886,11 @@ mips_finish_exec_plt (bfd *output_bfd, struct bfd_link_info *info)
? mipsr6_o32_exec_plt0_entry_compact
: mips_o32_exec_plt0_entry);
else if (htab->insn32)
- plt_entry = micromips_insn32_o32_exec_plt0_entry;
+ plt_entry = MIPSR6_P (output_bfd) ? micromipsr6_insn32_o32_exec_plt0_entry
+ : micromips_insn32_o32_exec_plt0_entry;
else
- plt_entry = micromips_o32_exec_plt0_entry;
+ plt_entry = MIPSR6_P (output_bfd) ? micromipsr6_o32_exec_plt0_entry
+ : micromips_o32_exec_plt0_entry;
/* Calculate the value of .got.plt. */
gotplt_value = (htab->root.sgotplt->output_section->vma
@@ -11694,9 +11916,11 @@ mips_finish_exec_plt (bfd *output_bfd, struct bfd_link_info *info)
/* Install the PLT header. */
loc = htab->root.splt->contents;
- if (plt_entry == micromips_o32_exec_plt0_entry)
+ if (plt_entry == micromips_o32_exec_plt0_entry
+ || plt_entry == micromipsr6_o32_exec_plt0_entry)
{
bfd_vma gotpc_offset;
+ bfd_vma addiupc_range;
bfd_vma loc_address;
size_t i;
@@ -11706,8 +11930,15 @@ mips_finish_exec_plt (bfd *output_bfd, struct bfd_link_info *info)
+ htab->root.splt->output_offset);
gotpc_offset = gotplt_value - ((loc_address | 3) ^ 3);
- /* ADDIUPC has a span of +/-16MB, check we're in range. */
- if (gotpc_offset + 0x1000000 >= 0x2000000)
+ if (MIPSR6_P (output_bfd))
+ /* ADDIUPC has a span of +/-1MB. */
+ addiupc_range = 0x100000;
+ else
+ /* ADDIUPC has a span of +/-16MB. */
+ addiupc_range = 0x1000000;
+
+ /* Check we're in range. */
+ if (gotpc_offset + addiupc_range >= addiupc_range * 2)
{
_bfd_error_handler
/* xgettext:c-format */
@@ -11720,13 +11951,18 @@ mips_finish_exec_plt (bfd *output_bfd, struct bfd_link_info *info)
bfd_set_error (bfd_error_no_error);
return false;
}
- bfd_put_16 (output_bfd,
- plt_entry[0] | ((gotpc_offset >> 18) & 0x7f), loc);
+ if (MIPSR6_P (output_bfd))
+ bfd_put_16 (output_bfd,
+ plt_entry[0] | ((gotpc_offset >> 18) & 0x7), loc);
+ else
+ bfd_put_16 (output_bfd,
+ plt_entry[0] | ((gotpc_offset >> 18) & 0x7f), loc);
bfd_put_16 (output_bfd, (gotpc_offset >> 2) & 0xffff, loc + 2);
for (i = 2; i < ARRAY_SIZE (micromips_o32_exec_plt0_entry); i++)
bfd_put_16 (output_bfd, plt_entry[i], loc + (i * 2));
}
- else if (plt_entry == micromips_insn32_o32_exec_plt0_entry)
+ else if (plt_entry == micromips_insn32_o32_exec_plt0_entry
+ || plt_entry == micromipsr6_insn32_o32_exec_plt0_entry)
{
size_t i;
@@ -13996,8 +14232,9 @@ _bfd_mips_elf_relax_section (bfd *abfd, asection *sec,
code section. */
if (bfd_link_relocatable (link_info)
- || sec->reloc_count == 0
+ || MIPSR6_P (abfd)
|| (sec->flags & SEC_RELOC) == 0
+ || sec->reloc_count == 0
|| (sec->flags & SEC_HAS_CONTENTS) == 0
|| (sec->flags & SEC_CODE) == 0)
return true;
@@ -16707,9 +16944,19 @@ _bfd_mips_elf_get_synthetic_symtab (bfd *abfd,
{
if (!micromips_p)
return -1;
- gotplt_hi = bfd_get_16 (abfd, plt_data + plt_offset) & 0x7f;
+
+ if (MIPSR6_P (abfd))
+ {
+ gotplt_hi = bfd_get_16 (abfd, plt_data + plt_offset) & 0x7;
+ gotplt_hi = ((gotplt_hi ^ 0x4) - 0x4) << 18;
+ }
+ else
+ {
+ gotplt_hi = bfd_get_16 (abfd, plt_data + plt_offset) & 0x7f;
+ gotplt_hi = ((gotplt_hi ^ 0x40) - 0x40) << 18;
+ }
+
gotplt_lo = bfd_get_16 (abfd, plt_data + plt_offset + 2) & 0xffff;
- gotplt_hi = ((gotplt_hi ^ 0x40) - 0x40) << 18;
gotplt_lo <<= 2;
gotplt_addr = gotplt_hi + gotplt_lo;
gotplt_addr += ((plt->vma + plt_offset) | 3) ^ 3;
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index ddaa0bd5efc..4eba79b7146 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -1787,7 +1787,7 @@ static const struct mips_ase mips_ases[] = {
{ "dspr3", ASE_DSP | ASE_DSPR2 | ASE_DSPR3, 0,
OPTION_DSPR3, OPTION_NO_DSPR3,
- 6, 6, -1, -1,
+ 6, 6, 6, 6,
-1 },
{ "eva", ASE_EVA, 0,
@@ -3644,6 +3644,7 @@ validate_micromips_insn (const struct mips_opcode *opc,
unsigned long insn_bits;
unsigned long major;
unsigned int length;
+ bfd_boolean bad_length = FALSE;
if (opc->pinfo == INSN_MACRO)
return validate_mips_insn (opc, 0xffffffff, decode_micromips_operand,
@@ -3657,8 +3658,18 @@ validate_micromips_insn (const struct mips_opcode *opc,
return 0;
}
major = opc->match >> (10 + 8 * (length - 2));
- if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
- || (length == 4 && (major & 7) != 0 && (major & 4) != 4))
+ if (!ISA_IS_R6 (mips_opts.isa) && length == 2)
+ bad_length = (major & 7) != 1 && (major & 6) != 2;
+ else if (!ISA_IS_R6 (mips_opts.isa) && length == 4)
+ bad_length = (major & 7) != 0 && (major & 4) != 4;
+ else if (length == 2)
+ bad_length = ((major & 7) != 1 || (major & 0x60) == 0x60) && (major & 6) != 2;
+ else if (length == 4)
+ bad_length = (major & 7) != 0 && (major & 4) != 4 && (major & 0x37) != 0x31;
+
+ gas_assert (length == 2 || length == 4);
+
+ if (bad_length)
{
as_bad (_("internal error: bad microMIPS opcode "
"(opcode/length mismatch): %s %s"), opc->name, opc->args);
@@ -4077,15 +4088,27 @@ mips_check_options (struct mips_set_options *opts, bool abi_checks)
if (opts->micromips == 1 && opts->mips16 == 1)
as_bad (_("`%s' cannot be used with `%s'"), "mips16", "micromips");
else if (ISA_IS_R6 (opts->isa)
- && (opts->micromips == 1
- || opts->mips16 == 1))
- as_fatal (_("`%s' cannot be used with `%s'"),
- opts->micromips ? "micromips" : "mips16",
+ && opts->mips16 == 1)
+ as_fatal (_("`%s' cannot be used with `%s'"), "mips16",
mips_cpu_info_from_isa (opts->isa)->name);
if (ISA_IS_R6 (opts->isa) && mips_relax_branch)
as_fatal (_("branch relaxation is not supported in `%s'"),
mips_cpu_info_from_isa (opts->isa)->name);
+
+ if (ISA_IS_R6 (opts->isa)
+ && opts->micromips
+ && opts->ase & ASE_MSA)
+ as_fatal (_("`%s' is not supported for `%s' and `%s'"), "msa", "micromips", "mips32r6");
+
+ if (ISA_IS_R6 (opts->isa)
+ && opts->micromips
+ && ((opts->ase & ASE_DSP)
+ || (opts->ase & ASE_DSPR2))
+ && (!(opts->ase & ASE_DSPR3)))
+ as_fatal (_("`%s' and `%s' are not supported for `%s' and `%s' please "
+ "use `%s' instead"),
+ "dsp", "dspr2", "micromips", "mips32r6", "dspr3");
}
/* Perform consistency checks on the module level options exactly once.
@@ -4274,6 +4297,10 @@ micromips_reloc_p (bfd_reloc_code_real_type reloc)
case BFD_RELOC_MICROMIPS_7_PCREL_S1:
case BFD_RELOC_MICROMIPS_10_PCREL_S1:
case BFD_RELOC_MICROMIPS_16_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_18_PCREL_S3:
+ case BFD_RELOC_MICROMIPS_19_PCREL_S2:
+ case BFD_RELOC_MICROMIPS_21_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_26_PCREL_S1:
case BFD_RELOC_MICROMIPS_GPREL16:
case BFD_RELOC_MICROMIPS_JMP:
case BFD_RELOC_MICROMIPS_HI16:
@@ -4294,6 +4321,8 @@ micromips_reloc_p (bfd_reloc_code_real_type reloc)
case BFD_RELOC_MICROMIPS_HIGHER:
case BFD_RELOC_MICROMIPS_SCN_DISP:
case BFD_RELOC_MICROMIPS_JALR:
+ case BFD_RELOC_MICROMIPS_HI16_S_PCREL:
+ case BFD_RELOC_MICROMIPS_LO16_PCREL:
return true;
default:
@@ -4314,6 +4343,8 @@ b_reloc_p (bfd_reloc_code_real_type reloc)
|| reloc == BFD_RELOC_MIPS_21_PCREL_S2
|| reloc == BFD_RELOC_16_PCREL_S2
|| reloc == BFD_RELOC_MIPS16_16_PCREL_S1
+ || reloc == BFD_RELOC_MICROMIPS_26_PCREL_S1
+ || reloc == BFD_RELOC_MICROMIPS_21_PCREL_S1
|| reloc == BFD_RELOC_MICROMIPS_16_PCREL_S1
|| reloc == BFD_RELOC_MICROMIPS_10_PCREL_S1
|| reloc == BFD_RELOC_MICROMIPS_7_PCREL_S1);
@@ -4366,6 +4397,10 @@ limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
case BFD_RELOC_MICROMIPS_7_PCREL_S1:
case BFD_RELOC_MICROMIPS_10_PCREL_S1:
case BFD_RELOC_MICROMIPS_16_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_21_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_26_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_18_PCREL_S3:
+ case BFD_RELOC_MICROMIPS_19_PCREL_S2:
case BFD_RELOC_MIPS_21_PCREL_S2:
case BFD_RELOC_MIPS_26_PCREL_S2:
case BFD_RELOC_MIPS_18_PCREL_S3:
@@ -4373,6 +4408,8 @@ limited_pcrel_reloc_p (bfd_reloc_code_real_type reloc)
return true;
case BFD_RELOC_32_PCREL:
+ case BFD_RELOC_MICROMIPS_HI16_S_PCREL:
+ case BFD_RELOC_MICROMIPS_LO16_PCREL:
case BFD_RELOC_HI16_S_PCREL:
case BFD_RELOC_LO16_PCREL:
return HAVE_64BIT_ADDRESSES;
@@ -7272,7 +7309,8 @@ find_altered_opcode (struct mips_cl_insn *ip, const struct mips_opcode *end)
for (mo = ip->insn_mo; mo < end; mo++)
if (mo->pinfo != INSN_MACRO
- && (ip->insn_opcode & mo->mask) == mo->match)
+ && (ip->insn_opcode & mo->mask) == mo->match
+ && is_opcode_valid (mo))
{
ip->insn_mo = mo;
return;
@@ -7376,7 +7414,13 @@ micromips_map_reloc (bfd_reloc_code_real_type reloc)
{ BFD_RELOC_HI16, BFD_RELOC_MICROMIPS_HI16 },
{ BFD_RELOC_HI16_S, BFD_RELOC_MICROMIPS_HI16_S },
{ BFD_RELOC_LO16, BFD_RELOC_MICROMIPS_LO16 },
+ { BFD_RELOC_HI16_S_PCREL, BFD_RELOC_MICROMIPS_HI16_S_PCREL },
+ { BFD_RELOC_LO16_PCREL, BFD_RELOC_MICROMIPS_LO16_PCREL },
{ BFD_RELOC_MIPS_LITERAL, BFD_RELOC_MICROMIPS_LITERAL },
+ { BFD_RELOC_MIPS_21_PCREL_S2, BFD_RELOC_MICROMIPS_21_PCREL_S1 },
+ { BFD_RELOC_MIPS_26_PCREL_S2, BFD_RELOC_MICROMIPS_26_PCREL_S1 },
+ { BFD_RELOC_MIPS_18_PCREL_S3, BFD_RELOC_MICROMIPS_18_PCREL_S3 },
+ { BFD_RELOC_MIPS_19_PCREL_S2, BFD_RELOC_MICROMIPS_19_PCREL_S2 },
{ BFD_RELOC_MIPS_GOT16, BFD_RELOC_MICROMIPS_GOT16 },
{ BFD_RELOC_MIPS_CALL16, BFD_RELOC_MICROMIPS_CALL16 },
{ BFD_RELOC_MIPS_GOT_HI16, BFD_RELOC_MICROMIPS_GOT_HI16 },
@@ -7436,6 +7480,7 @@ calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
case BFD_RELOC_HI16_S:
case BFD_RELOC_HI16_S_PCREL:
case BFD_RELOC_MICROMIPS_HI16_S:
+ case BFD_RELOC_MICROMIPS_HI16_S_PCREL:
case BFD_RELOC_MIPS16_HI16_S:
*result = ((operand + 0x8000) >> 16) & 0xffff;
return true;
@@ -7449,6 +7494,7 @@ calculate_reloc (bfd_reloc_code_real_type reloc, offsetT operand,
case BFD_RELOC_LO16:
case BFD_RELOC_LO16_PCREL:
case BFD_RELOC_MICROMIPS_LO16:
+ case BFD_RELOC_MICROMIPS_LO16_PCREL:
case BFD_RELOC_MIPS16_LO16:
*result = operand & 0xffff;
return true;
@@ -7562,6 +7608,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
(unsigned long) address_expr->X_add_number);
ip->insn_opcode |= ((address_expr->X_add_number >> shift)
& 0xffff);
+ ip->complete_p = 1;
}
}
break;
@@ -7570,7 +7617,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
{
int shift;
- shift = 2;
+ shift = mips_opts.micromips ? 1 : 2;
if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
as_bad (_("branch to misaligned address (0x%lx)"),
(unsigned long) address_expr->X_add_number);
@@ -7580,6 +7627,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
(unsigned long) address_expr->X_add_number);
ip->insn_opcode |= ((address_expr->X_add_number >> shift)
& 0x1fffff);
+ ip->complete_p = 1;
}
break;
@@ -7587,7 +7635,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
{
int shift;
- shift = 2;
+ shift = mips_opts.micromips ? 1 : 2;
if ((address_expr->X_add_number & ((1 << shift) - 1)) != 0)
as_bad (_("branch to misaligned address (0x%lx)"),
(unsigned long) address_expr->X_add_number);
@@ -7597,6 +7645,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
(unsigned long) address_expr->X_add_number);
ip->insn_opcode |= ((address_expr->X_add_number >> shift)
& 0x3ffffff);
+ ip->complete_p = 1;
}
break;
@@ -7776,7 +7825,9 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
}
else if (mips_opts.micromips
&& address_expr
- && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2)
+ && ((relax32 && (*reloc_type == BFD_RELOC_16_PCREL_S2
+ || *reloc_type == BFD_RELOC_MIPS_21_PCREL_S2
+ || *reloc_type == BFD_RELOC_MIPS_26_PCREL_S2))
|| *reloc_type > BFD_RELOC_UNUSED)
&& (delayed_branch_p (ip) || compact_branch_p (ip))
/* Don't try branch relaxation when users specify
@@ -8989,6 +9040,7 @@ macro_end (void)
static const char * const brk_fmt[2][2] = { { "c", "c" }, { "mF", "c" } };
static const char * const cop12_fmt[2] = { "E,o(b)", "E,~(b)" };
+static const char * const cop12_r6fmt[2] = { "E,+:(d)", "E,+:(b)" };
static const char * const jalr_fmt[2] = { "d,s", "t,s" };
static const char * const lui_fmt[2] = { "t,u", "s,u" };
static const char * const mem12_fmt[2] = { "t,o(b)", "t,~(b)" };
@@ -8996,17 +9048,29 @@ static const char * const mfhl_fmt[2][2] = { { "d", "d" }, { "mj", "s" } };
static const char * const shft_fmt[2] = { "d,w,<", "t,r,<" };
static const char * const trap_fmt[2] = { "s,t,q", "s,t,|" };
+/* Instruction operand formats used in macros that vary between
+ microMIPSR3 and microMIPSR6 code. */
+static const char * const mm_jalr_fmt[2] = { "mj", "mp" };
+static const char * const mm_jal_fmt[2] = { "a", "+'" };
+
#define BRK_FMT (brk_fmt[mips_opts.micromips][mips_opts.insn32])
-#define COP12_FMT (ISA_IS_R6 (mips_opts.isa) ? "E,+:(d)" \
- : cop12_fmt[mips_opts.micromips])
+#define COP2_FMT (ISA_IS_R6 (mips_opts.isa) \
+ ? cop12_r6fmt[mips_opts.micromips] \
+ : cop12_fmt[mips_opts.micromips])
#define JALR_FMT (jalr_fmt[mips_opts.micromips])
-#define LUI_FMT (lui_fmt[mips_opts.micromips])
+#define LUI_FMT (lui_fmt[ISA_IS_R6 (mips_opts.isa) ? 0 : mips_opts.micromips])
#define MEM12_FMT (mem12_fmt[mips_opts.micromips])
-#define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) ? "t,+j(b)" \
- : mem12_fmt[mips_opts.micromips])
+#define LL_SC_FMT (ISA_IS_R6 (mips_opts.isa) \
+ ? "t,+j(b)" : mem12_fmt[mips_opts.micromips])
#define MFHL_FMT (mfhl_fmt[mips_opts.micromips][mips_opts.insn32])
#define SHFT_FMT (shft_fmt[mips_opts.micromips])
#define TRAP_FMT (trap_fmt[mips_opts.micromips])
+#define LL_SC_PAIRED_FMT (mips_opts.micromips ? "t,-p,s" : "t,d,s")
+
+#define MM_JALR_FMT (mm_jalr_fmt[ISA_IS_R6 (mips_opts.isa) \
+ && mips_opts.micromips])
+#define MM_JAL_FMT (mm_jal_fmt[ISA_IS_R6 (mips_opts.isa) \
+ && mips_opts.micromips])
/* Read a macro's relocation codes from *ARGS and store them in *R.
The first argument in *ARGS will be either the code for a single
@@ -9100,12 +9164,14 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
create_insn (&insn, mo);
for (; *fmt; ++fmt)
{
+ bfd_boolean normal_operand = TRUE;
switch (*fmt)
{
case ',':
case '(':
case ')':
case 'z':
+ normal_operand = FALSE;
break;
case 'i':
@@ -9135,10 +9201,12 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
|| *r == BFD_RELOC_MIPS_TLS_GOTTPREL
|| *r == BFD_RELOC_MIPS_TLS_TPREL_HI16
|| *r == BFD_RELOC_MIPS_TLS_TPREL_LO16)));
+ normal_operand = FALSE;
break;
case 'o':
macro_read_relocs (&args, r);
+ normal_operand = FALSE;
break;
case 'u':
@@ -9152,6 +9220,20 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
|| *r == BFD_RELOC_GPREL16
|| *r == BFD_RELOC_MIPS_GOT_HI16
|| *r == BFD_RELOC_MIPS_CALL_HI16))));
+ normal_operand = FALSE;
+ break;
+
+ case '+':
+ /* Only handle the +' and +" operands */
+ if (*(fmt + 1) != '\"' && *(fmt + 1) != '\'')
+ break;
+ gas_assert (ep != NULL);
+ ++fmt;
+ if (*(fmt) == '\'')
+ *r = BFD_RELOC_MIPS_26_PCREL_S2;
+ else if (*(fmt) == '\"')
+ *r = BFD_RELOC_MIPS_21_PCREL_S2;
+ normal_operand = FALSE;
break;
case 'p':
@@ -9181,14 +9263,18 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
}
else
*r = BFD_RELOC_16_PCREL_S2;
+ normal_operand = FALSE;
break;
case 'a':
gas_assert (ep != NULL);
*r = BFD_RELOC_MIPS_JMP;
+ normal_operand = FALSE;
break;
- default:
+ }
+ if (normal_operand)
+ {
operand = (mips_opts.micromips
? decode_micromips_operand (fmt)
: decode_mips_operand (fmt));
@@ -9196,13 +9282,12 @@ macro_build (expressionS *ep, const char *name, const char *fmt, ...)
abort ();
uval = va_arg (args, int);
- if (operand->type == OP_CLO_CLZ_DEST)
+ if (operand->type == OP_CLO_CLZ_DEST || operand->type == OP_SAME_RS_RT)
uval |= (uval << 5);
insn_insert_operand (&insn, operand, uval);
if (*fmt == '+' || *fmt == 'm' || *fmt == '-')
++fmt;
- break;
}
}
va_end (args);
@@ -9317,14 +9402,17 @@ macro_build_jalr (expressionS *ep, int cprestore)
}
if (mips_opts.micromips)
{
- jalr = ((mips_opts.noreorder && !cprestore) || mips_opts.insn32
+ jalr = (ISA_IS_R6 (mips_opts.isa)
+ || (mips_opts.noreorder && !cprestore)
+ || mips_opts.insn32
? "jalr" : "jalrs");
+
if (MIPS_JALR_HINT_P (ep)
|| mips_opts.insn32
|| (history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
macro_build (NULL, jalr, "t,s", RA, PIC_CALL_REG);
else
- macro_build (NULL, jalr, "mj", PIC_CALL_REG);
+ macro_build (NULL, jalr, MM_JALR_FMT, PIC_CALL_REG);
}
else
macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
@@ -10219,7 +10307,17 @@ macro_build_branch_rs (int type, expressionS *ep, unsigned int sreg)
if (mips_opts.micromips && brneg)
macro_build_branch_likely (br, brneg, call, ep, "s,p", sreg, ZERO);
else
- macro_build (ep, br, "s,p", sreg);
+ if (ISA_IS_R6 (mips_opts.isa) && mips_opts.micromips)
+ {
+ if (sreg == 0)
+ as_bad (_("the source register must not be $0"));
+ if (type == M_BGTZ || type == M_BLEZ)
+ macro_build (ep, br, "-t,p", sreg);
+ else
+ macro_build (ep, br, "+;,p", sreg);
+ }
+ else
+ macro_build (ep, br, "s,p", sreg);
}
/* Emit a three-argument branch macro specified by TYPE, using SREG and
@@ -10259,7 +10357,22 @@ macro_build_branch_rsrt (int type, expressionS *ep,
if (mips_opts.micromips && brneg)
macro_build_branch_likely (br, brneg, call, ep, "s,t,p", sreg, treg);
else
- macro_build (ep, br, "s,t,p", sreg, treg);
+ if (ISA_IS_R6 (mips_opts.isa) && mips_opts.micromips)
+ {
+ /* rs must not be equal to 0 for microMIPS R6 as it would generate
+ different instruction for beqc/beqzc/bnec/bnezc: beqzalc, jic,
+ bnezalc, and jialc respectively. */
+ if (sreg == 0)
+ as_bad (_("the source register must not be $0"));
+ if (treg == 0)
+ macro_build (ep, br, "-t,z,+\"", sreg, treg);
+ else if (treg > sreg)
+ macro_build (ep, br, "-s,-u,p", sreg, treg);
+ else
+ macro_build (ep, br, "t,-y,p", sreg, treg);
+ }
+ else
+ macro_build (ep, br, "s,t,p", sreg, treg);
}
/* Return the high part that should be loaded in order to make the low
@@ -10402,11 +10515,20 @@ macro (struct mips_cl_insn *ip, char *str)
micromips_label_expr (&label_expr);
else
label_expr.X_add_number = 8;
- macro_build (&label_expr, "bgez", "s,p", op[1]);
- if (op[0] == op[1])
- macro_build (NULL, "nop", "");
+ if (ISA_IS_R6 (mips_opts.isa) && mips_opts.micromips)
+ {
+ if (op[0] != op[1])
+ move_register (op[0], op[1]);
+ macro_build (&label_expr, "bgezc", "+;,p", op[1]);
+ }
else
- move_register (op[0], op[1]);
+ {
+ macro_build (&label_expr, "bgez", "s,p", op[1]);
+ if (op[0] == op[1])
+ macro_build (NULL, "nop", "");
+ else
+ move_register (op[0], op[1]);
+ }
macro_build (NULL, dbl ? "dsub" : "sub", "d,v,t", op[0], 0, op[1]);
if (mips_opts.micromips)
micromips_add_label ();
@@ -11682,7 +11804,7 @@ macro (struct mips_cl_insn *ip, char *str)
&& !mips_opts.insn32
&& op[0] == RA
&& !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
- macro_build (NULL, s, "mj", op[1]);
+ macro_build (NULL, s, MM_JALR_FMT, op[1]);
else
macro_build (NULL, s, JALR_FMT, op[0], op[1]);
}
@@ -11695,6 +11817,7 @@ macro (struct mips_cl_insn *ip, char *str)
as_warn (_("MIPS PIC call to register other than $25"));
s = ((mips_opts.micromips
+ && !ISA_IS_R6 (mips_opts.isa)
&& !mips_opts.insn32
&& (!mips_opts.noreorder || cprestore))
? "jalrs" : "jalr");
@@ -11702,11 +11825,14 @@ macro (struct mips_cl_insn *ip, char *str)
&& !mips_opts.insn32
&& op[0] == RA
&& !(history[0].insn_mo->pinfo2 & INSN2_BRANCH_DELAY_32BIT))
- macro_build (NULL, s, "mj", op[1]);
+ macro_build (NULL, s, MM_JALR_FMT, op[1]);
else
macro_build (NULL, s, JALR_FMT, op[0], op[1]);
if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
{
+ /* TODO: There is a bug here in .set noreorder code where
+ an explicitly filled delay slot of a JAL macro
+ is moved out of the delay slot by the NOP below */
if (mips_cprestore_offset < 0)
as_warn (_("no .cprestore pseudo-op used in PIC code"));
else
@@ -11747,7 +11873,7 @@ macro (struct mips_cl_insn *ip, char *str)
/* Fall through. */
case M_JAL_A:
if (mips_pic == NO_PIC)
- macro_build (&offset_expr, jals ? "jals" : "jal", "a");
+ macro_build (&offset_expr, jals ? "jals" : "jal", MM_JAL_FMT);
else if (mips_pic == SVR4_PIC)
{
/* If this is a reference to an external symbol, and we are
@@ -11999,9 +12125,9 @@ macro (struct mips_cl_insn *ip, char *str)
goto ld_st;
case M_LWC2_AB:
s = "lwc2";
- fmt = COP12_FMT;
- offbits = (mips_opts.micromips ? 12
- : ISA_IS_R6 (mips_opts.isa) ? 11
+ fmt = COP2_FMT;
+ offbits = (ISA_IS_R6 (mips_opts.isa) ? 11
+ : mips_opts.micromips ? 12
: 16);
/* Itbl support may require additional care here. */
coproc = 1;
@@ -12031,9 +12157,9 @@ macro (struct mips_cl_insn *ip, char *str)
goto ld_st;
case M_LDC2_AB:
s = "ldc2";
- fmt = COP12_FMT;
- offbits = (mips_opts.micromips ? 12
- : ISA_IS_R6 (mips_opts.isa) ? 11
+ fmt = COP2_FMT;
+ offbits = (ISA_IS_R6 (mips_opts.isa) ? 11
+ : mips_opts.micromips ? 12
: 16);
/* Itbl support may require additional care here. */
coproc = 1;
@@ -12063,15 +12189,33 @@ macro (struct mips_cl_insn *ip, char *str)
case M_LL_AB:
s = "ll";
fmt = LL_SC_FMT;
- offbits = (mips_opts.micromips ? 12
- : ISA_IS_R6 (mips_opts.isa) ? 9
+ offbits = (ISA_IS_R6 (mips_opts.isa) ? 9
+ : mips_opts.micromips ? 12
: 16);
goto ld;
+ case M_LLWPE_AB:
+ s = "llwpe";
+ fmt = LL_SC_PAIRED_FMT;
+ ll_sc_paired = 1;
+ offbits = 0;
+ goto ld;
+ case M_LLWP_AB:
+ s = "llwp";
+ fmt = LL_SC_PAIRED_FMT;
+ ll_sc_paired = 1;
+ offbits = 0;
+ goto ld;
+ case M_LLDP_AB:
+ s = "lldp";
+ fmt = LL_SC_PAIRED_FMT;
+ ll_sc_paired = 1;
+ offbits = 0;
+ goto ld;
case M_LLD_AB:
s = "lld";
fmt = LL_SC_FMT;
- offbits = (mips_opts.micromips ? 12
- : ISA_IS_R6 (mips_opts.isa) ? 9
+ offbits = (ISA_IS_R6 (mips_opts.isa) ? 9
+ : mips_opts.micromips ? 12
: 16);
goto ld;
case M_LWU_AB:
@@ -12093,14 +12237,6 @@ macro (struct mips_cl_insn *ip, char *str)
offbits = 12;
lp = 1;
goto ld;
- case M_LLDP_AB:
- case M_LLWP_AB:
- case M_LLWPE_AB:
- s = ip->insn_mo->name;
- fmt = "t,d,s";
- ll_sc_paired = 1;
- offbits = 0;
- goto ld;
case M_LWM_AB:
gas_assert (mips_opts.micromips);
s = "lwm";
@@ -12164,9 +12300,9 @@ macro (struct mips_cl_insn *ip, char *str)
goto ld_st;
case M_SWC2_AB:
s = "swc2";
- fmt = COP12_FMT;
- offbits = (mips_opts.micromips ? 12
- : ISA_IS_R6 (mips_opts.isa) ? 11
+ fmt = COP2_FMT;
+ offbits = (ISA_IS_R6 (mips_opts.isa) ? 11
+ : mips_opts.micromips ? 12
: 16);
/* Itbl support may require additional care here. */
coproc = 1;
@@ -12191,32 +12327,42 @@ macro (struct mips_cl_insn *ip, char *str)
case M_SC_AB:
s = "sc";
fmt = LL_SC_FMT;
- offbits = (mips_opts.micromips ? 12
- : ISA_IS_R6 (mips_opts.isa) ? 9
+ offbits = (ISA_IS_R6 (mips_opts.isa) ? 9
+ : mips_opts.micromips ? 12
: 16);
goto ld_st;
case M_SCD_AB:
s = "scd";
fmt = LL_SC_FMT;
- offbits = (mips_opts.micromips ? 12
- : ISA_IS_R6 (mips_opts.isa) ? 9
+ offbits = (ISA_IS_R6 (mips_opts.isa) ? 9
+ : mips_opts.micromips ? 12
: 16);
goto ld_st;
- case M_SCDP_AB:
- case M_SCWP_AB:
case M_SCWPE_AB:
- s = ip->insn_mo->name;
- fmt = "t,d,s";
+ s = "scwpe";
+ fmt = LL_SC_PAIRED_FMT;
+ ll_sc_paired = 1;
+ offbits = 0;
+ goto ld_st;
+ case M_SCWP_AB:
+ s = "scwp";
+ fmt = LL_SC_PAIRED_FMT;
+ ll_sc_paired = 1;
+ offbits = 0;
+ goto ld_st;
+ case M_SCDP_AB:
+ s = "scdp";
+ fmt = LL_SC_PAIRED_FMT;
ll_sc_paired = 1;
offbits = 0;
goto ld_st;
case M_CACHE_AB:
s = "cache";
- fmt = (mips_opts.micromips ? "k,~(b)"
- : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
+ fmt = (ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
+ : mips_opts.micromips ? "k,~(b)"
: "k,o(b)");
- offbits = (mips_opts.micromips ? 12
- : ISA_IS_R6 (mips_opts.isa) ? 9
+ offbits = (ISA_IS_R6 (mips_opts.isa) ? 9
+ : mips_opts.micromips ? 12
: 16);
goto ld_st;
case M_CACHEE_AB:
@@ -12226,11 +12372,11 @@ macro (struct mips_cl_insn *ip, char *str)
goto ld_st;
case M_PREF_AB:
s = "pref";
- fmt = (mips_opts.micromips ? "k,~(b)"
- : ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
+ fmt = (ISA_IS_R6 (mips_opts.isa) ? "k,+j(b)"
+ : mips_opts.micromips ? "k,~(b)"
: "k,o(b)");
- offbits = (mips_opts.micromips ? 12
- : ISA_IS_R6 (mips_opts.isa) ? 9
+ offbits = (ISA_IS_R6 (mips_opts.isa) ? 9
+ : mips_opts.micromips ? 12
: 16);
goto ld_st;
case M_PREFE_AB:
@@ -12246,9 +12392,9 @@ macro (struct mips_cl_insn *ip, char *str)
goto ld_st;
case M_SDC2_AB:
s = "sdc2";
- fmt = COP12_FMT;
- offbits = (mips_opts.micromips ? 12
- : ISA_IS_R6 (mips_opts.isa) ? 11
+ fmt = COP2_FMT;
+ offbits = (ISA_IS_R6 (mips_opts.isa) ? 11
+ : mips_opts.micromips ? 12
: 16);
/* Itbl support may require additional care here. */
coproc = 1;
@@ -12712,11 +12858,19 @@ macro (struct mips_cl_insn *ip, char *str)
case M_JRADDIUSP:
gas_assert (mips_opts.micromips);
gas_assert (mips_opts.insn32);
- start_noreorder ();
- macro_build (NULL, "jr", "s", RA);
expr1.X_add_number = op[0] << 2;
- macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
- end_noreorder ();
+ if (ISA_IS_R6 (mips_opts.isa))
+ {
+ macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
+ macro_build (NULL, "jrc", "s", RA);
+ }
+ else
+ {
+ start_noreorder ();
+ macro_build (NULL, "jr", "s", RA);
+ macro_build (&expr1, "addiu", "t,r,j", SP, SP, BFD_RELOC_LO16);
+ end_noreorder ();
+ }
break;
case M_JRC:
@@ -15385,7 +15539,6 @@ long
md_pcrel_from (fixS *fixP)
{
valueT addr = fixP->fx_where + fixP->fx_frag->fr_address;
-
switch (fixP->fx_r_type)
{
case BFD_RELOC_MICROMIPS_7_PCREL_S1:
@@ -15394,6 +15547,8 @@ md_pcrel_from (fixS *fixP)
return addr + 2;
case BFD_RELOC_MICROMIPS_16_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_21_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_26_PCREL_S1:
case BFD_RELOC_MICROMIPS_JMP:
case BFD_RELOC_MIPS16_16_PCREL_S1:
case BFD_RELOC_16_PCREL_S2:
@@ -15582,6 +15737,12 @@ mips_force_relocation (fixS *fixp)
/* We want all PC-relative relocations to be kept for R6 relaxation. */
if (ISA_IS_R6 (file_mips_opts.isa)
&& (fixp->fx_r_type == BFD_RELOC_16_PCREL_S2
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_21_PCREL_S1
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_26_PCREL_S1
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_18_PCREL_S3
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_19_PCREL_S2
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_HI16_S_PCREL
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_LO16_PCREL
|| fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
|| fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
|| fixp->fx_r_type == BFD_RELOC_MIPS_18_PCREL_S3
@@ -15755,6 +15916,9 @@ fix_bad_cross_mode_branch_p (fixS *fixP)
case BFD_RELOC_MICROMIPS_16_PCREL_S1:
return ((absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other))
&& opcode != 0x4060);
+ case BFD_RELOC_MICROMIPS_21_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_26_PCREL_S1:
+ return absolute_p ? !(val & 1) : !ELF_ST_IS_MICROMIPS (other);
case BFD_RELOC_MIPS_21_PCREL_S2:
case BFD_RELOC_MIPS_26_PCREL_S2:
return absolute_p ? val & 1 : ELF_ST_IS_COMPRESSED (other);
@@ -15860,6 +16024,12 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_MICROMIPS_7_PCREL_S1:
case BFD_RELOC_MICROMIPS_10_PCREL_S1:
case BFD_RELOC_MICROMIPS_16_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_21_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_26_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_18_PCREL_S3:
+ case BFD_RELOC_MICROMIPS_19_PCREL_S2:
+ case BFD_RELOC_MICROMIPS_HI16_S_PCREL:
+ case BFD_RELOC_MICROMIPS_LO16_PCREL:
case BFD_RELOC_32_PCREL:
case BFD_RELOC_MIPS_21_PCREL_S2:
case BFD_RELOC_MIPS_26_PCREL_S2:
@@ -16028,6 +16198,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_MICROMIPS_JALR:
case BFD_RELOC_MICROMIPS_HI16:
case BFD_RELOC_MICROMIPS_HI16_S:
+ case BFD_RELOC_MICROMIPS_HI16_S_PCREL:
+ case BFD_RELOC_MICROMIPS_LO16_PCREL:
case BFD_RELOC_MICROMIPS_LO16:
case BFD_RELOC_MICROMIPS_GPREL16:
case BFD_RELOC_MICROMIPS_LITERAL:
@@ -16123,11 +16295,20 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
_("branch out of range"));
break;
+ case BFD_RELOC_MICROMIPS_18_PCREL_S3:
case BFD_RELOC_MIPS_18_PCREL_S3:
- if (fixP->fx_addsy && (S_GET_VALUE (fixP->fx_addsy) & 0x7) != 0)
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("PC-relative access using misaligned symbol (%lx)"),
- (long) S_GET_VALUE (fixP->fx_addsy));
+ if (fixP->fx_addsy)
+ {
+ bfd_vma sym_val = S_GET_VALUE (fixP->fx_addsy);
+
+ if (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixP->fx_addsy)))
+ sym_val = (sym_val | 1) ^ 1;
+
+ if ((sym_val & 0x7) != 0)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC-relative access using misaligned symbol (%lx)"),
+ (long) sym_val);
+ }
if ((fixP->fx_offset & 0x7) != 0)
as_bad_where (fixP->fx_file, fixP->fx_line,
_("PC-relative access using misaligned offset (%lx)"),
@@ -16146,11 +16327,25 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
_("PC-relative access out of range"));
break;
+ case BFD_RELOC_MICROMIPS_19_PCREL_S2:
case BFD_RELOC_MIPS_19_PCREL_S2:
- if ((*valP & 0x3) != 0)
+ if (fixP->fx_addsy)
+ {
+ bfd_vma sym_val = S_GET_VALUE (fixP->fx_addsy);
+
+ if (ELF_ST_IS_MICROMIPS (S_GET_OTHER (fixP->fx_addsy)))
+ sym_val = (sym_val | 1) ^ 1;
+
+ if ((sym_val & 0x3) != 0)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("PC-relative access to misaligned symbol (%lx)"),
+ (long) sym_val);
+ }
+ if ((fixP->fx_offset & 0x3) != 0)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("PC-relative access to misaligned address (%lx)"),
- (long) *valP);
+ _("PC-relative access to misaligned offset (%lx)"),
+ (long) fixP->fx_offset);
+
if (!fixP->fx_done)
break;
@@ -16218,6 +16413,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
case BFD_RELOC_MICROMIPS_7_PCREL_S1:
case BFD_RELOC_MICROMIPS_10_PCREL_S1:
case BFD_RELOC_MICROMIPS_16_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_21_PCREL_S1:
+ case BFD_RELOC_MICROMIPS_26_PCREL_S1:
gas_assert (!fixP->fx_done);
if (fix_bad_cross_mode_branch_p (fixP))
as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -18002,6 +18199,7 @@ relaxed_branch_length (fragS *fragp, asection *sec, int update)
val -= addr;
+ /* TODO: MIPSR6 branches are wider for beqzc,bnezc,bc */
toofar = val < - (0x8000 << 2) || val >= (0x8000 << 2);
}
else
@@ -18083,6 +18281,7 @@ relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
short_insn_size = insn32 ? 4 : 2;
if (fragp
+ && fragp->fr_symbol
&& S_IS_DEFINED (fragp->fr_symbol)
&& !S_IS_WEAK (fragp->fr_symbol)
&& sec == S_GET_SEGMENT (fragp->fr_symbol))
@@ -18100,6 +18299,7 @@ relaxed_micromips_32bit_branch_length (fragS *fragp, asection *sec, int update)
val -= addr;
+ /* TODO: MIPSR6 branches are wider for beqzc,bnezc,bc */
toofar = val < - (0x8000 << 1) || val >= (0x8000 << 1);
}
else
@@ -18190,6 +18390,7 @@ relaxed_micromips_16bit_branch_length (fragS *fragp, asection *sec, int update)
bool toofar;
if (fragp
+ && fragp->fr_symbol
&& S_IS_DEFINED (fragp->fr_symbol)
&& !S_IS_WEAK (fragp->fr_symbol)
&& sec == S_GET_SEGMENT (fragp->fr_symbol))
@@ -18431,6 +18632,12 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
|| fixp->fx_r_type == BFD_RELOC_MICROMIPS_7_PCREL_S1
|| fixp->fx_r_type == BFD_RELOC_MICROMIPS_10_PCREL_S1
|| fixp->fx_r_type == BFD_RELOC_MICROMIPS_16_PCREL_S1
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_21_PCREL_S1
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_26_PCREL_S1
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_18_PCREL_S3
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_19_PCREL_S2
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_HI16_S_PCREL
+ || fixp->fx_r_type == BFD_RELOC_MICROMIPS_LO16_PCREL
|| fixp->fx_r_type == BFD_RELOC_32_PCREL
|| fixp->fx_r_type == BFD_RELOC_MIPS_21_PCREL_S2
|| fixp->fx_r_type == BFD_RELOC_MIPS_26_PCREL_S2
@@ -18818,9 +19025,31 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
/* We generate a fixup instead of applying it right now,
because if there is linker relaxation, we're going to
need the relocations. */
+ int r_type = -1;
+
+ if (ISA_IS_R6 (mips_opts.isa))
+ {
+ insn = read_compressed_insn (buf, 2);
+
+ /* TODO: For microMIPSR6 relax32 is not currently supported
+ therefore no 32-bit branches will be annotated
+ with the relax macros. This code also deals with
+ 16-bit branches that are out of range and
+ determines the relocs needed for the corresponding
+ 32-bit branches. */
+ gas_assert (type != 0);
+
+ if ((insn & 0xdc00) == 0x8c00) /* beqzc16/bnezc16 */
+ r_type = BFD_RELOC_MICROMIPS_21_PCREL_S1;
+ else /* bc16 */
+ r_type = BFD_RELOC_MICROMIPS_26_PCREL_S1;
+ }
+ else
+ r_type = BFD_RELOC_MICROMIPS_16_PCREL_S1;
+
fixp = fix_new (fragp, buf - fragp->fr_literal, 4,
fragp->fr_symbol, fragp->fr_offset,
- true, BFD_RELOC_MICROMIPS_16_PCREL_S1);
+ TRUE, r_type);
fixp->fx_file = fragp->fr_file;
fixp->fx_line = fragp->fr_line;
@@ -18848,16 +19077,26 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
{
insn = read_compressed_insn (buf, 2);
- if ((insn & 0xfc00) == 0xcc00) /* b16 */
- insn = 0x94000000; /* beq */
- else if ((insn & 0xdc00) == 0x8c00) /* beqz16/bnez16 */
+ if ((insn & 0xfc00) == 0xcc00) /* b[c]16 */
+ insn = 0x94000000; /* beq/bc32 */
+ else if ((insn & 0xdc00) == 0x8c00) /* beqz[c]16/bnez[c]16 */
{
unsigned long regno;
regno = (insn >> MICROMIPSOP_SH_MD) & MICROMIPSOP_MASK_MD;
regno = micromips_to_32_reg_d_map [regno];
- insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
- insn |= regno << MICROMIPSOP_SH_RS;
+
+ if (ISA_IS_R6 (mips_opts.isa))
+ {
+ /* beqzc/bnezc */
+ insn = ((insn & 0x2000) << 16) | 0x80000000;
+ insn |= regno << MICROMIPSOP_SH_RT;
+ }
+ else
+ {
+ insn = ((insn & 0x2000) << 16) | 0x94000000; /* beq/bne */
+ insn |= regno << MICROMIPSOP_SH_RS;
+ }
}
else
abort ();
@@ -18876,6 +19115,10 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
else
insn = read_compressed_insn (buf, 4);
+ if (ISA_IS_R6 (mips_opts.isa))
+ as_bad_where (fragp->fr_file, fragp->fr_line,
+ _("unable to relax out-of-range branch into a jump"));
+
/* Relax 32-bit branches to a sequence of instructions. */
as_warn_where (fragp->fr_file, fragp->fr_line,
_("relaxed out-of-range branch into a jump"));
diff --git a/gas/testsuite/gas/mips/abs.s b/gas/testsuite/gas/mips/abs.s
index 1f2172bcb02..6a8da8c7862 100644
--- a/gas/testsuite/gas/mips/abs.s
+++ b/gas/testsuite/gas/mips/abs.s
@@ -2,4 +2,5 @@
foo:
abs $4
abs $4,$5
+ .align 2
.space 8
diff --git a/gas/testsuite/gas/mips/bgeu.s b/gas/testsuite/gas/mips/bgeu.s
index dc0a93aea52..79707e38f73 100644
--- a/gas/testsuite/gas/mips/bgeu.s
+++ b/gas/testsuite/gas/mips/bgeu.s
@@ -2,7 +2,9 @@
text_label:
bgeu $4,$5,text_label
+ .ifndef compact_branches
bgeu $0,$5,text_label
+ .endif
# A second argument of 0 or $0 is always true
bgeu $4,1,text_label
bgeu $4,2,text_label
diff --git a/gas/testsuite/gas/mips/bltu.s b/gas/testsuite/gas/mips/bltu.s
index 8340e315d90..d1ac25ef5a5 100644
--- a/gas/testsuite/gas/mips/bltu.s
+++ b/gas/testsuite/gas/mips/bltu.s
@@ -2,7 +2,9 @@
text_label:
bltu $4,$5,text_label
+ .ifndef compact_branches
bltu $0,$5,text_label
+ .endif
# A second argument of 0 or $0 is always false
bltu $4,1,text_label
bltu $4,2,text_label
diff --git a/gas/testsuite/gas/mips/branch-local-ignore-3.d b/gas/testsuite/gas/mips/branch-local-ignore-3.d
index 918a2cedfda..add9276ecaa 100644
--- a/gas/testsuite/gas/mips/branch-local-ignore-3.d
+++ b/gas/testsuite/gas/mips/branch-local-ignore-3.d
@@ -8,7 +8,7 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 0000 02d0 not zero,zero
-[0-9a-f]+ <[^>]*> 001f 0f3c jr ra
+[0-9a-f]+ <[^>]*> 001f 0f3c jrc ra
[0-9a-f]+ <[^>]*> 0000 02d0 not zero,zero
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero
diff --git a/gas/testsuite/gas/mips/branch-local-ignore-n32-3.d b/gas/testsuite/gas/mips/branch-local-ignore-n32-3.d
index a4dbc7f5104..d167e528660 100644
--- a/gas/testsuite/gas/mips/branch-local-ignore-n32-3.d
+++ b/gas/testsuite/gas/mips/branch-local-ignore-n32-3.d
@@ -8,7 +8,7 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 0000 02d0 not zero,zero
-[0-9a-f]+ <[^>]*> 001f 0f3c jr ra
+[0-9a-f]+ <[^>]*> 001f 0f3c jrc ra
[0-9a-f]+ <[^>]*> 0000 02d0 not zero,zero
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero
diff --git a/gas/testsuite/gas/mips/branch-local-ignore-n64-3.d b/gas/testsuite/gas/mips/branch-local-ignore-n64-3.d
index 9d6dca90a0b..7b4f51edf05 100644
--- a/gas/testsuite/gas/mips/branch-local-ignore-n64-3.d
+++ b/gas/testsuite/gas/mips/branch-local-ignore-n64-3.d
@@ -8,7 +8,7 @@
Disassembly of section \.text:
\.\.\.
[0-9a-f]+ <[^>]*> 0000 02d0 not zero,zero
-[0-9a-f]+ <[^>]*> 001f 0f3c jr ra
+[0-9a-f]+ <[^>]*> 001f 0f3c jrc ra
[0-9a-f]+ <[^>]*> 0000 02d0 not zero,zero
[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero
diff --git a/gas/testsuite/gas/mips/llpscp-32-micromips.d b/gas/testsuite/gas/mips/llpscp-32-micromips.d
new file mode 100644
index 00000000000..36462f38599
--- /dev/null
+++ b/gas/testsuite/gas/mips/llpscp-32-micromips.d
@@ -0,0 +1,45 @@
+#objdump: -dr
+#as: -mips32r6 -mmicromips -meva
+#name: Paired LL/SC for micromipsr6
+#source: llpscp-32.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <test>:
+ 0: 6044 1030 llwp v0,v1,a0
+ 4: 6044 1030 llwp v0,v1,a0
+ 8: 3044 1234 addiu v0,a0,4660
+ c: 6042 1000 llwp v0,zero,v0
+ 10: 3062 0000 addiu v1,v0,0
+ 10: R_MICROMIPS_LO16 sync_mem
+ 14: 6043 1030 llwp v0,v1,v1
+ 18: 1040 0123 lui v0,0x123
+ 1c: 0062 1150 addu v0,v0,v1
+ 20: 3042 4567 addiu v0,v0,17767
+ 24: 6042 1030 llwp v0,v1,v0
+ 28: 1020 0000 lui at,0x0
+ 28: R_MICROMIPS_HI16 sync_mem
+ 2c: 3021 0000 addiu at,at,0
+ 2c: R_MICROMIPS_LO16 sync_mem
+ 30: 0081 0950 addu at,at,a0
+ 34: 6001 1000 llwp zero,zero,at
+ 38: 6044 9030 scwp v0,v1,a0
+ 3c: 6044 9030 scwp v0,v1,a0
+ 40: 3024 1234 addiu at,a0,4660
+ 44: 6041 9000 scwp v0,zero,at
+ 48: 3022 0000 addiu at,v0,0
+ 48: R_MICROMIPS_LO16 sync_mem
+ 4c: 6041 9030 scwp v0,v1,at
+ 50: 1020 0123 lui at,0x123
+ 54: 0061 0950 addu at,at,v1
+ 58: 3021 4567 addiu at,at,17767
+ 5c: 6041 9030 scwp v0,v1,at
+ 60: 1020 0000 lui at,0x0
+ 60: R_MICROMIPS_HI16 sync_mem
+ 64: 3021 0000 addiu at,at,0
+ 64: R_MICROMIPS_LO16 sync_mem
+ 68: 0081 0950 addu at,at,a0
+ 6c: 6001 9000 scwp zero,zero,at
+ ...
diff --git a/gas/testsuite/gas/mips/llpscp-64-micromips.d b/gas/testsuite/gas/mips/llpscp-64-micromips.d
new file mode 100644
index 00000000000..984197211c0
--- /dev/null
+++ b/gas/testsuite/gas/mips/llpscp-64-micromips.d
@@ -0,0 +1,45 @@
+#objdump: -dr
+#as: -mips64r6 -mmicromips
+#name: Paired LL/SC for micromips mips64r6
+#source: llpscp-64.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+00000000 <test>:
+ 0: 6044 5030 lldp v0,v1,a0
+ 4: 6044 5030 lldp v0,v1,a0
+ 8: 3044 1234 addiu v0,a0,4660
+ c: 6042 5000 lldp v0,zero,v0
+ 10: 3062 0000 addiu v1,v0,0
+ 10: R_MICROMIPS_LO16 sync_mem
+ 14: 6043 5030 lldp v0,v1,v1
+ 18: 1040 0123 lui v0,0x123
+ 1c: 0062 1150 addu v0,v0,v1
+ 20: 3042 4567 addiu v0,v0,17767
+ 24: 6042 5030 lldp v0,v1,v0
+ 28: 1020 0000 lui at,0x0
+ 28: R_MICROMIPS_HI16 sync_mem
+ 2c: 3021 0000 addiu at,at,0
+ 2c: R_MICROMIPS_LO16 sync_mem
+ 30: 0081 0950 addu at,at,a0
+ 34: 6001 5000 lldp zero,zero,at
+ 38: 6044 d030 scdp v0,v1,a0
+ 3c: 6044 d030 scdp v0,v1,a0
+ 40: 3024 1234 addiu at,a0,4660
+ 44: 6041 d000 scdp v0,zero,at
+ 48: 3022 0000 addiu at,v0,0
+ 48: R_MICROMIPS_LO16 sync_mem
+ 4c: 6041 d030 scdp v0,v1,at
+ 50: 1020 0123 lui at,0x123
+ 54: 0061 0950 addu at,at,v1
+ 58: 3021 4567 addiu at,at,17767
+ 5c: 6041 d030 scdp v0,v1,at
+ 60: 1020 0000 lui at,0x0
+ 60: R_MICROMIPS_HI16 sync_mem
+ 64: 3021 0000 addiu at,at,0
+ 64: R_MICROMIPS_LO16 sync_mem
+ 68: 0081 0950 addu at,at,a0
+ 6c: 6001 d000 scdp zero,zero,at
+ ...
diff --git a/gas/testsuite/gas/mips/micromips-compact.d b/gas/testsuite/gas/mips/micromips-compact.d
index ca3451b40aa..8e11a27a8bd 100644
--- a/gas/testsuite/gas/mips/micromips-compact.d
+++ b/gas/testsuite/gas/mips/micromips-compact.d
@@ -1,6 +1,6 @@
#objdump: -dr --show-raw-insn
#name: microMIPS for MIPS32r2 (with branch compaction)
-#as: -mips32r2 -32 -mfp64 -EB --defsym compact=1
+#as: -mips64r2 -32 -mfp64 -EB --defsym compact=1
#warning_output: micromips-warn.l
#source: micromips.s
@@ -5390,11 +5390,11 @@ Disassembly of section \.text:
[ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1
[ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31
[ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2
-[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
@@ -5415,18 +5415,18 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
@@ -5447,13 +5447,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
[ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0
[ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1
[ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2
@@ -5486,11 +5486,11 @@ Disassembly of section \.text:
[ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29
[ 0-9a-f]+: 00be cd3c cfc2 a1,\$30
[ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31
-[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
@@ -5511,18 +5511,18 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
@@ -5543,13 +5543,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
[ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0
[ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1
[ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2
diff --git a/gas/testsuite/gas/mips/micromips-insn32.d b/gas/testsuite/gas/mips/micromips-insn32.d
index e7851345080..1bb57c8d198 100644
--- a/gas/testsuite/gas/mips/micromips-insn32.d
+++ b/gas/testsuite/gas/mips/micromips-insn32.d
@@ -1,6 +1,6 @@
#objdump: -drz --show-raw-insn
#name: microMIPS for MIPS32r2 (insn32 mode)
-#as: -mips32r2 -32 -mfp64 -minsn32 -EB --defsym insn32=1
+#as: -32 -mfp64 -minsn32 -EB --defsym insn32=1
#warning_output: micromips-warn.l
#source: micromips.s
@@ -5414,11 +5414,11 @@ Disassembly of section \.text:
[ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1
[ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31
[ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2
-[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
@@ -5439,18 +5439,18 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
@@ -5471,13 +5471,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
[ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0
[ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1
[ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2
@@ -5510,11 +5510,11 @@ Disassembly of section \.text:
[ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29
[ 0-9a-f]+: 00be cd3c cfc2 a1,\$30
[ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31
-[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
@@ -5535,18 +5535,18 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
@@ -5567,13 +5567,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
[ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0
[ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1
[ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2
diff --git a/gas/testsuite/gas/mips/micromips-noinsn32.d b/gas/testsuite/gas/mips/micromips-noinsn32.d
index 3fa9a0613a1..2bb59d53239 100644
--- a/gas/testsuite/gas/mips/micromips-noinsn32.d
+++ b/gas/testsuite/gas/mips/micromips-noinsn32.d
@@ -1,6 +1,6 @@
#objdump: -dr --show-raw-insn
#name: microMIPS for MIPS32r2 (instructions valid in insn32 mode)
-#as: -mips32r2 -32 -mfp64 -EB --defsym insn32=1
+#as: -mips64r2 -32 -mfp64 -EB --defsym insn32=1
#warning_output: micromips-warn.l
#source: micromips.s
@@ -5391,11 +5391,11 @@ Disassembly of section \.text:
[ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1
[ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31
[ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2
-[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
@@ -5416,18 +5416,18 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
@@ -5448,13 +5448,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
[ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0
[ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1
[ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2
@@ -5487,11 +5487,11 @@ Disassembly of section \.text:
[ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29
[ 0-9a-f]+: 00be cd3c cfc2 a1,\$30
[ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31
-[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
@@ -5512,18 +5512,18 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
@@ -5544,13 +5544,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
[ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0
[ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1
[ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2
diff --git a/gas/testsuite/gas/mips/micromips-trap.d b/gas/testsuite/gas/mips/micromips-trap.d
index 0be6e289848..a6d6399024d 100644
--- a/gas/testsuite/gas/mips/micromips-trap.d
+++ b/gas/testsuite/gas/mips/micromips-trap.d
@@ -1,6 +1,6 @@
#objdump: -dr --show-raw-insn
#name: microMIPS for MIPS32r2 (w/traps)
-#as: -mips32r2 -32 -trap -mfp64 -EB
+#as: -mips64r2 -32 -trap -mfp64 -EB
#warning_output: micromips-warn.l
#source: micromips.s
@@ -5397,11 +5397,11 @@ Disassembly of section \.text:
[ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1
[ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31
[ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2
-[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
@@ -5422,18 +5422,18 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
@@ -5454,13 +5454,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
[ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0
[ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1
[ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2
@@ -5493,11 +5493,11 @@ Disassembly of section \.text:
[ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29
[ 0-9a-f]+: 00be cd3c cfc2 a1,\$30
[ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31
-[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
@@ -5518,18 +5518,18 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
@@ -5550,13 +5550,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
[ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0
[ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1
[ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2
diff --git a/gas/testsuite/gas/mips/micromips-warn.l b/gas/testsuite/gas/mips/micromips-warn.l
index cc5462f4f42..114ad8cdc83 100644
--- a/gas/testsuite/gas/mips/micromips-warn.l
+++ b/gas/testsuite/gas/mips/micromips-warn.l
@@ -1,27 +1,27 @@
.*: Assembler messages:
-.*:649: Warning: divide by zero
-.*:652: Warning: divide by zero
-.*:665: Warning: divide by zero
-.*:1649: Warning: divide by zero
-.*:1652: Warning: divide by zero
-.*:1665: Warning: divide by zero
-.*:2712: Warning: branch bge is always true
-.*:2715: Warning: branch bgeu is always true
-.*:2724: Warning: branch bgeu is always true
-.*:2799: Warning: branch ble is always true
-.*:2814: Warning: branch bleu is always true
-.*:2820: Warning: branch bleu is always true
-.*:2823: Warning: branch bleu is always true
-.*:2922: Warning: branch bgel is always true
-.*:2925: Warning: branch bgeul is always true
-.*:2934: Warning: branch bgeul is always true
-.*:3009: Warning: branch blel is always true
-.*:3024: Warning: branch bleul is always true
-.*:3030: Warning: branch bleul is always true
-.*:3033: Warning: branch bleul is always true
-.*:4849: Warning: divide by zero
-.*:4852: Warning: divide by zero
-.*:4865: Warning: divide by zero
-.*:5270: Warning: divide by zero
-.*:5280: Warning: divide by zero
-.*:5290: Warning: divide by zero
+.*:708: Warning: divide by zero
+.*:712: Warning: divide by zero
+.*:727: Warning: divide by zero
+.*:1725: Warning: divide by zero
+.*:1728: Warning: divide by zero
+.*:1741: Warning: divide by zero
+.*:2818: Warning: branch bge is always true
+.*:2821: Warning: branch bgeu is always true
+.*:2830: Warning: branch bgeu is always true
+.*:2905: Warning: branch ble is always true
+.*:2920: Warning: branch bleu is always true
+.*:2926: Warning: branch bleu is always true
+.*:2929: Warning: branch bleu is always true
+.*:3028: Warning: branch bgel is always true
+.*:3031: Warning: branch bgeul is always true
+.*:3040: Warning: branch bgeul is always true
+.*:3115: Warning: branch blel is always true
+.*:3130: Warning: branch bleul is always true
+.*:3136: Warning: branch bleul is always true
+.*:3139: Warning: branch bleul is always true
+.*:4995: Warning: divide by zero
+.*:4999: Warning: divide by zero
+.*:5016: Warning: divide by zero
+.*:5425: Warning: divide by zero
+.*:5435: Warning: divide by zero
+.*:5445: Warning: divide by zero
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromips.d b/gas/testsuite/gas/mips/micromips.d
index 4d965106321..cc471c016bd 100644
--- a/gas/testsuite/gas/mips/micromips.d
+++ b/gas/testsuite/gas/mips/micromips.d
@@ -1,6 +1,6 @@
#objdump: -dr --show-raw-insn
#name: microMIPS for MIPS32r2
-#as: -mips32r2 -32 -mfp64 -EB
+#as: -32 -mfp64 -EB
#warning_output: micromips-warn.l
#source: micromips.s
@@ -5469,11 +5469,11 @@ Disassembly of section \.text:
[ 0-9a-f]+: 5401 1b3b ceil\.w\.s \$f0,\$f1
[ 0-9a-f]+: 57df 1b3b ceil\.w\.s \$f30,\$f31
[ 0-9a-f]+: 5442 1b3b ceil\.w\.s \$f2,\$f2
-[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
@@ -5494,18 +5494,18 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 103b cfc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 103b cfc1 a1,c1_ufr
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ 0-9a-f]+: 54a4 103b cfc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
@@ -5526,13 +5526,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ 0-9a-f]+: 54b9 103b cfc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 103b cfc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ -9a-f]+: 54ba 103b cfc1 a1,\$26
[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ 0-9a-f]+: 54bc 103b cfc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ 0-9a-f]+: 54bf 103b cfc1 a1,c1_fcsr
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
[ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0
[ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1
[ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2
@@ -5565,11 +5565,11 @@ Disassembly of section \.text:
[ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29
[ 0-9a-f]+: 00be cd3c cfc2 a1,\$30
[ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31
-[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
@@ -5590,18 +5590,18 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr
-[ 0-9a-f]+: 54a0 183b ctc1 a1,c1_fir
-[ 0-9a-f]+: 54a1 183b ctc1 a1,c1_ufr
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ 0-9a-f]+: 54a4 183b ctc1 a1,c1_unfr
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
@@ -5622,13 +5622,13 @@ Disassembly of section \.text:
[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ 0-9a-f]+: 54b9 183b ctc1 a1,c1_fccr
-[ 0-9a-f]+: 54ba 183b ctc1 a1,c1_fexr
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ 0-9a-f]+: 54bc 183b ctc1 a1,c1_fenr
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ 0-9a-f]+: 54bf 183b ctc1 a1,c1_fcsr
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
[ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0
[ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1
[ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2
@@ -7784,4 +7784,4 @@ Disassembly of section \.text:
[ 0-9a-f]+: 4022 fffe bltzal v0,[0-9a-f]+ <.*\+0x[0-9a-f]+>
[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_spec107
[ 0-9a-f]+: 0000 0000 nop
-#pass
+#pass
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromips.l b/gas/testsuite/gas/mips/micromips.l
index 9236782b34f..cc3dcd27d0c 100644
--- a/gas/testsuite/gas/mips/micromips.l
+++ b/gas/testsuite/gas/mips/micromips.l
@@ -1,107 +1,107 @@
.*: Assembler messages:
-.*:49: Error: opcode not supported in the `insn32' mode `nop16'
-.*:108: Error: opcode not supported in the `insn32' mode `move16 \$2,\$22'
-.*:109: Error: opcode not supported in the `insn32' mode `move16 \$22,\$2'
-.*:116: Error: opcode not supported in the `insn32' mode `b16 test'
-.*:123: Error: opcode not supported in the `insn32' mode `b16 1f'
-.*:131: Error: opcode not supported in the `insn32' mode `b16 1b'
-.*:292: Error: opcode not supported in the `insn32' mode `and16 \$2,\$2,\$3'
-.*:330: Error: opcode not supported in the `insn32' mode `andi16 \$7,65535'
-.*:426: Error: opcode not supported in the `insn32' mode `beqz16 \$16,test2'
-.*:543: Error: opcode not supported in the `insn32' mode `bnez16 \$16,test3'
-.*:649: Warning: divide by zero
-.*:652: Warning: divide by zero
-.*:665: Warning: divide by zero
-.*:1649: Warning: divide by zero
-.*:1652: Warning: divide by zero
-.*:1665: Warning: divide by zero
-.*:2712: Warning: branch bge is always true
-.*:2715: Warning: branch bgeu is always true
-.*:2724: Warning: branch bgeu is always true
-.*:2799: Warning: branch ble is always true
-.*:2814: Warning: branch bleu is always true
-.*:2820: Warning: branch bleu is always true
-.*:2823: Warning: branch bleu is always true
-.*:2922: Warning: branch bgel is always true
-.*:2925: Warning: branch bgeul is always true
-.*:2934: Warning: branch bgeul is always true
-.*:3009: Warning: branch blel is always true
-.*:3024: Warning: branch bleul is always true
-.*:3030: Warning: branch bleul is always true
-.*:3033: Warning: branch bleul is always true
-.*:3100: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,0'
-.*:3101: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,1<<2'
-.*:3102: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,2<<2'
-.*:3103: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,3<<2'
-.*:3104: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,4<<2'
-.*:3105: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,63<<2'
-.*:3106: Error: opcode not supported in the `insn32' mode `addiur1sp \$3,63<<2'
-.*:3107: Error: opcode not supported in the `insn32' mode `addiur1sp \$4,63<<2'
-.*:3108: Error: opcode not supported in the `insn32' mode `addiur1sp \$5,63<<2'
-.*:3109: Error: opcode not supported in the `insn32' mode `addiur1sp \$6,63<<2'
-.*:3110: Error: opcode not supported in the `insn32' mode `addiur1sp \$7,63<<2'
-.*:3111: Error: opcode not supported in the `insn32' mode `addiur1sp \$16,63<<2'
-.*:3112: Error: opcode not supported in the `insn32' mode `addiur1sp \$17,63<<2'
-.*:3114: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$2,-1'
-.*:3115: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$3,-1'
-.*:3116: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$4,-1'
-.*:3117: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$5,-1'
-.*:3118: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$6,-1'
-.*:3119: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$7,-1'
-.*:3120: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$16,-1'
-.*:3121: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$17,-1'
-.*:3122: Error: opcode not supported in the `insn32' mode `addiur2 \$3,\$17,-1'
-.*:3123: Error: opcode not supported in the `insn32' mode `addiur2 \$4,\$17,-1'
-.*:3124: Error: opcode not supported in the `insn32' mode `addiur2 \$5,\$17,-1'
-.*:3125: Error: opcode not supported in the `insn32' mode `addiur2 \$6,\$17,-1'
-.*:3126: Error: opcode not supported in the `insn32' mode `addiur2 \$7,\$17,-1'
-.*:3127: Error: opcode not supported in the `insn32' mode `addiur2 \$16,\$17,-1'
-.*:3128: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,-1'
-.*:3129: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,1'
-.*:3130: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,4'
-.*:3131: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,8'
-.*:3132: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,12'
-.*:3133: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,16'
-.*:3134: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,20'
-.*:3135: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,24'
-.*:3137: Error: opcode not supported in the `insn32' mode `addiusp 2 ?<< ?2'
-.*:3138: Error: opcode not supported in the `insn32' mode `addiusp 3 ?<< ?2'
-.*:3139: Error: opcode not supported in the `insn32' mode `addiusp 254 ?<< ?2'
-.*:3140: Error: opcode not supported in the `insn32' mode `addiusp 255 ?<< ?2'
-.*:3141: Error: opcode not supported in the `insn32' mode `addiusp 256 ?<< ?2'
-.*:3142: Error: opcode not supported in the `insn32' mode `addiusp 257 ?<< ?2'
-.*:3143: Error: opcode not supported in the `insn32' mode `addiusp -3 ?<< ?2'
-.*:3144: Error: opcode not supported in the `insn32' mode `addiusp -4 ?<< ?2'
-.*:3145: Error: opcode not supported in the `insn32' mode `addiusp -255 ?<< ?2'
-.*:3146: Error: opcode not supported in the `insn32' mode `addiusp -256 ?<< ?2'
-.*:3147: Error: opcode not supported in the `insn32' mode `addiusp -257 ?<< ?2'
-.*:3148: Error: opcode not supported in the `insn32' mode `addiusp -258 ?<< ?2'
-.*:3150: Error: opcode not supported in the `insn32' mode `addius5 \$0,0'
-.*:3151: Error: opcode not supported in the `insn32' mode `addius5 \$2,0'
-.*:3152: Error: opcode not supported in the `insn32' mode `addius5 \$3,0'
-.*:3153: Error: opcode not supported in the `insn32' mode `addius5 \$30,0'
-.*:3154: Error: opcode not supported in the `insn32' mode `addius5 \$31,0'
-.*:3155: Error: opcode not supported in the `insn32' mode `addius5 \$31,1'
-.*:3156: Error: opcode not supported in the `insn32' mode `addius5 \$31,2'
-.*:3157: Error: opcode not supported in the `insn32' mode `addius5 \$31,3'
-.*:3158: Error: opcode not supported in the `insn32' mode `addius5 \$31,7'
-.*:3159: Error: opcode not supported in the `insn32' mode `addius5 \$31,-6'
-.*:3160: Error: opcode not supported in the `insn32' mode `addius5 \$31,-7'
-.*:3161: Error: opcode not supported in the `insn32' mode `addius5 \$31,-8'
-.*:4849: Warning: divide by zero
-.*:4852: Warning: divide by zero
-.*:4865: Warning: divide by zero
-.*:5270: Warning: divide by zero
-.*:5280: Warning: divide by zero
-.*:5290: Warning: divide by zero
-.*:5658: Error: opcode not supported in the `insn32' mode `jalr16 \$2'
-.*:5663: Error: opcode not supported in the `insn32' mode `jr16 \$2'
-.*:5670: Error: opcode not supported in the `insn32' mode `jals test_delay_slot'
-.*:5671: Error: opcode not supported in the `insn32' mode `jalrs16 \$2'
-.*:5672: Error: opcode not supported in the `insn32' mode `jalrs32 \$2'
-.*:5673: Error: opcode not supported in the `insn32' mode `jrs \$2'
-.*:5674: Error: opcode not supported in the `insn32' mode `jalrs\.hb \$2'
-.*:5675: Error: opcode not supported in the `insn32' mode `jrs\.hb \$2'
-.*:5756: Error: opcode not supported in the `insn32' mode `bals test_spec107'
-.*:5758: Error: opcode not supported in the `insn32' mode `bgezals \$2,test_spec107'
-.*:5760: Error: opcode not supported in the `insn32' mode `bltzals \$2,test_spec107'
+.*:72: Error: opcode not supported in the `insn32' mode `nop16'
+.*:131: Error: opcode not supported in the `insn32' mode `move16 \$2,\$22'
+.*:132: Error: opcode not supported in the `insn32' mode `move16 \$22,\$2'
+.*:139: Error: opcode not supported in the `insn32' mode `b16 test'
+.*:146: Error: opcode not supported in the `insn32' mode `b16 1f'
+.*:154: Error: opcode not supported in the `insn32' mode `b16 1b'
+.*:317: Error: opcode not supported in the `insn32' mode `and16 \$2,\$2,\$3'
+.*:355: Error: opcode not supported in the `insn32' mode `andi16 \$7,65535'
+.*:452: Error: opcode not supported in the `insn32' mode `beqz16 \$16,test2'
+.*:571: Error: opcode not supported in the `insn32' mode `bnez16 \$16,test3'
+.*:708: Warning: divide by zero
+.*:712: Warning: divide by zero
+.*:727: Warning: divide by zero
+.*:1725: Warning: divide by zero
+.*:1728: Warning: divide by zero
+.*:1741: Warning: divide by zero
+.*:2818: Warning: branch bge is always true
+.*:2821: Warning: branch bgeu is always true
+.*:2830: Warning: branch bgeu is always true
+.*:2905: Warning: branch ble is always true
+.*:2920: Warning: branch bleu is always true
+.*:2926: Warning: branch bleu is always true
+.*:2929: Warning: branch bleu is always true
+.*:3028: Warning: branch bgel is always true
+.*:3031: Warning: branch bgeul is always true
+.*:3040: Warning: branch bgeul is always true
+.*:3115: Warning: branch blel is always true
+.*:3130: Warning: branch bleul is always true
+.*:3136: Warning: branch bleul is always true
+.*:3139: Warning: branch bleul is always true
+.*:3207: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,0'
+.*:3208: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,1<<2'
+.*:3209: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,2<<2'
+.*:3210: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,3<<2'
+.*:3211: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,4<<2'
+.*:3212: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,63<<2'
+.*:3213: Error: opcode not supported in the `insn32' mode `addiur1sp \$3,63<<2'
+.*:3214: Error: opcode not supported in the `insn32' mode `addiur1sp \$4,63<<2'
+.*:3215: Error: opcode not supported in the `insn32' mode `addiur1sp \$5,63<<2'
+.*:3216: Error: opcode not supported in the `insn32' mode `addiur1sp \$6,63<<2'
+.*:3217: Error: opcode not supported in the `insn32' mode `addiur1sp \$7,63<<2'
+.*:3218: Error: opcode not supported in the `insn32' mode `addiur1sp \$16,63<<2'
+.*:3219: Error: opcode not supported in the `insn32' mode `addiur1sp \$17,63<<2'
+.*:3221: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$2,-1'
+.*:3222: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$3,-1'
+.*:3223: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$4,-1'
+.*:3224: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$5,-1'
+.*:3225: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$6,-1'
+.*:3226: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$7,-1'
+.*:3227: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$16,-1'
+.*:3228: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$17,-1'
+.*:3229: Error: opcode not supported in the `insn32' mode `addiur2 \$3,\$17,-1'
+.*:3230: Error: opcode not supported in the `insn32' mode `addiur2 \$4,\$17,-1'
+.*:3231: Error: opcode not supported in the `insn32' mode `addiur2 \$5,\$17,-1'
+.*:3232: Error: opcode not supported in the `insn32' mode `addiur2 \$6,\$17,-1'
+.*:3233: Error: opcode not supported in the `insn32' mode `addiur2 \$7,\$17,-1'
+.*:3234: Error: opcode not supported in the `insn32' mode `addiur2 \$16,\$17,-1'
+.*:3235: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,-1'
+.*:3236: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,1'
+.*:3237: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,4'
+.*:3238: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,8'
+.*:3239: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,12'
+.*:3240: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,16'
+.*:3241: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,20'
+.*:3242: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,24'
+.*:3244: Error: opcode not supported in the `insn32' mode `addiusp 2<<2'
+.*:3245: Error: opcode not supported in the `insn32' mode `addiusp 3<<2'
+.*:3246: Error: opcode not supported in the `insn32' mode `addiusp 254<<2'
+.*:3247: Error: opcode not supported in the `insn32' mode `addiusp 255<<2'
+.*:3248: Error: opcode not supported in the `insn32' mode `addiusp 256<<2'
+.*:3249: Error: opcode not supported in the `insn32' mode `addiusp 257<<2'
+.*:3250: Error: opcode not supported in the `insn32' mode `addiusp -3<<2'
+.*:3251: Error: opcode not supported in the `insn32' mode `addiusp -4<<2'
+.*:3252: Error: opcode not supported in the `insn32' mode `addiusp -255<<2'
+.*:3253: Error: opcode not supported in the `insn32' mode `addiusp -256<<2'
+.*:3254: Error: opcode not supported in the `insn32' mode `addiusp -257<<2'
+.*:3255: Error: opcode not supported in the `insn32' mode `addiusp -258<<2'
+.*:3257: Error: opcode not supported in the `insn32' mode `addius5 \$0,0'
+.*:3258: Error: opcode not supported in the `insn32' mode `addius5 \$2,0'
+.*:3259: Error: opcode not supported in the `insn32' mode `addius5 \$3,0'
+.*:3260: Error: opcode not supported in the `insn32' mode `addius5 \$30,0'
+.*:3261: Error: opcode not supported in the `insn32' mode `addius5 \$31,0'
+.*:3262: Error: opcode not supported in the `insn32' mode `addius5 \$31,1'
+.*:3263: Error: opcode not supported in the `insn32' mode `addius5 \$31,2'
+.*:3264: Error: opcode not supported in the `insn32' mode `addius5 \$31,3'
+.*:3265: Error: opcode not supported in the `insn32' mode `addius5 \$31,7'
+.*:3266: Error: opcode not supported in the `insn32' mode `addius5 \$31,-6'
+.*:3267: Error: opcode not supported in the `insn32' mode `addius5 \$31,-7'
+.*:3268: Error: opcode not supported in the `insn32' mode `addius5 \$31,-8'
+.*:4995: Warning: divide by zero
+.*:4999: Warning: divide by zero
+.*:5016: Warning: divide by zero
+.*:5425: Warning: divide by zero
+.*:5435: Warning: divide by zero
+.*:5445: Warning: divide by zero
+.*:5838: Error: opcode not supported in the `insn32' mode `jalr16 \$2'
+.*:5843: Error: opcode not supported in the `insn32' mode `jr16 \$2'
+.*:5850: Error: opcode not supported in the `insn32' mode `jals test_delay_slot'
+.*:5851: Error: opcode not supported in the `insn32' mode `jalrs16 \$2'
+.*:5852: Error: opcode not supported in the `insn32' mode `jalrs32 \$2'
+.*:5854: Error: opcode not supported in the `insn32' mode `jrs \$2'
+.*:5855: Error: opcode not supported in the `insn32' mode `jalrs.hb \$2'
+.*:5856: Error: opcode not supported in the `insn32' mode `jrs.hb \$2'
+.*:5949: Error: opcode not supported in the `insn32' mode `bals test_spec107'
+.*:5951: Error: opcode not supported in the `insn32' mode `bgezals \$2,test_spec107'
+.*:5953: Error: opcode not supported in the `insn32' mode `bltzals \$2,test_spec107'
diff --git a/gas/testsuite/gas/mips/micromips.s b/gas/testsuite/gas/mips/micromips.s
index 56ad82a4d60..6a0a4247446 100644
--- a/gas/testsuite/gas/mips/micromips.s
+++ b/gas/testsuite/gas/mips/micromips.s
@@ -15,10 +15,17 @@
.globl test
test:
pref 0, 0
+ .ifndef r6
pref 0, 2047
pref 0, -2048
pref 0, 2048
pref 0, -2049
+ .else
+ pref 0, 255
+ pref 0, -256
+ pref 0, 256
+ pref 0, -257
+ .endif
pref 0, ($0)
pref 0, 0($0)
pref 1, 0($0)
@@ -28,19 +35,35 @@ test:
pref 5, 0($0)
pref 6, 0($0)
pref 7, 0($0)
+ .ifndef r6
pref 7, 511($0)
pref 7, -512($0)
pref 31, 2047($0)
pref 31, -2048($0)
pref 31, 2048($0)
pref 31, -2049($0)
+ .else
+ pref 7, 127($0)
+ pref 7, -128($0)
+ pref 31, 255($0)
+ pref 31, -256($0)
+ pref 31, 256($0)
+ pref 31, -257($0)
+ .endif
pref 3, 32767($0)
pref 3, -32768($0)
+ .ifndef r6
pref 31, 2047($2)
pref 31, -2048($2)
pref 31, 2048($2)
pref 31, -2049($2)
+ .else
+ pref 31, 255($2)
+ pref 31, -256($2)
+ pref 31, 256($2)
+ pref 31, -257($2)
+ .endif
pref 3, 32767($2)
pref 3, -32768($2)
@@ -142,6 +165,7 @@ test:
add $29, $30, $31
add $2, $2, $4
add $2, $4
+ .ifndef r6
add $2, $2, 0
add $2, $2, 1
add $2, $2, 32767
@@ -154,6 +178,7 @@ test:
addi $3, $4, 65535
addi $3, $3, 65535
addi $3, 65535
+ .endif
addiu $0, -8
addiu $2, -8
@@ -339,6 +364,7 @@ test:
and $2, $3, 65536
and $2, $3, 0xffff0001
+ .ifndef r6
bc2f test
bc2f $cc0, test
bc2f $cc1, test
@@ -370,7 +396,7 @@ test:
addu $3, $4, $5
bc2tl $cc4, test
addu $6, $7, $8
-
+ .endif
test2:
DSNOP
@@ -440,6 +466,7 @@ test2:
beq $16, 32767, test2
beq $16, 65536, test2
+ .ifndef r6
.set noreorder
beql $16, $17, test2
addu $3, $4, $5
@@ -488,6 +515,7 @@ test2:
beql $16, $17, test2
beqzl $17, test2
+ .endif
DSNOP
DSNOP
@@ -584,15 +612,29 @@ test3:
break32 1023,1023
cache 0, 0
+ .ifndef r6
cache 0, -2048
cache 0, 2047
cache 0, -2049
cache 0, 2048
+ .else
+ cache 0, -256
+ cache 0, 255
+ cache 0, -257
+ cache 0, 256
+ .endif
cache 0, 0($2)
+ .ifndef r6
cache 0, -2048($2)
cache 0, 2047($2)
cache 0, -2049($2)
cache 0, 2048($2)
+ .else
+ cache 0, -256($2)
+ cache 0, 255($2)
+ cache 0, -257($2)
+ cache 0, 256($2)
+ .endif
cache 0, ($0)
cache 0, 0($0)
@@ -603,14 +645,26 @@ test3:
cache 5, 0($0)
cache 6, 0($0)
cache 31, 0($0)
+ .ifndef r6
cache 31, 2047($0)
cache 31, -2048($0)
cache 0, 2047($0)
cache 0, -2048($0)
+ .else
+ cache 31, 255($0)
+ cache 31, -256($0)
+ cache 0, 255($0)
+ cache 0, -256($0)
+ .endif
cache 31, 65536($3)
+ .ifndef r6
cache 31, 2048($3)
cache 31, -2049($3)
+ .else
+ cache 31, 256($3)
+ cache 31, -257($3)
+ .endif
cache 31, 65537($3)
cache 31, 0xffffffff($3)
cache 31, 0xffff0000($3)
@@ -618,8 +672,13 @@ test3:
cache 31, 0xffff($3)
cache 31, 65536($0)
+ .ifndef r6
cache 31, 2048($0)
cache 31, -2049($0)
+ .else
+ cache 31, 256($0)
+ cache 31, -257($0)
+ .endif
cache 31, 65537($0)
cache 31, 0xffffffff($0)
cache 31, 0xffff0000($0)
@@ -649,10 +708,12 @@ test3:
div $2, $3, $0
div $2, $3, $4
+ .ifndef r6
div $3, $4, 0
div $3, $4, 1
div $3, $4, -1
div $3, $4, 2
+ .endif
divu $0, $2, $3
divu $0, $30, $31
@@ -662,10 +723,12 @@ test3:
divu $2, $3, $0
divu $2, $3, $4
+ .ifndef r6
divu $3, $4, 0
divu $3, $4, 1
divu $3, $4, -1
divu $3, $4, 2
+ .endif
ei
ei $0
@@ -844,8 +907,10 @@ test3:
jal test
jal test2
+ .ifndef r6
jalx test
jalx test4
+ .endif
la $2, test
lca $2, test
@@ -1222,6 +1287,7 @@ test3:
lwp $2, 32767($0)
lwp $2, 65535($0)
+ .ifndef r6
lwl $3, 4
lwl $3, 4($0)
lwl $3, ($0)
@@ -1345,10 +1411,13 @@ test3:
flush $3, 0xf0000000($4)
flush $3, 0xffffffff($4)
flush $3, 0x12345678($4)
+ .endif
lwxs $3, $4($5)
+ .ifndef r6
madd $4,$5
maddu $4,$5
+ .endif
mfc0 $2, $0
mfc0 $2, $1
@@ -1408,6 +1477,7 @@ test3:
mfc0 $2, $2, 6
mfc0 $2, $2, 7
+ .ifndef r6
mfhi $0
mfhi $2
mfhi $3
@@ -1450,6 +1520,7 @@ test3:
msub $4,$5
msubu $4,$5
+ .endif
mtc0 $2, $0
mtc0 $2, $1
@@ -1509,6 +1580,7 @@ test3:
mtc0 $2, $2, 6
mtc0 $2, $2, 7
+ .ifndef r6
mthi $0
mthi $2
mthi $3
@@ -1524,11 +1596,13 @@ test3:
mtlo $29
mtlo $30
mtlo $31
+ .endif
mul $2, $3, $4
mul $29, $30, $31
mul $2, $2, $4
mul $2, $4
+ .ifndef r6
mul $2, $2, 0
mul $2, $2, 1
mul $2, $2, 32767
@@ -1542,6 +1616,7 @@ test3:
mult $2, $3
multu $2, $3
+ .endif
neg $2, $3
neg $2, $2
@@ -1641,6 +1716,7 @@ test3:
rdpgpr $2, $2
rdpgpr $2
+ .ifndef r6
rem $0, $2, $3
rem $0, $30, $31
rem $0, $3
@@ -1666,6 +1742,7 @@ test3:
remu $3, $4, 1
remu $3, $4, -1
remu $3, $4, 2
+ .endif
rol $2, $3, $4
rol $2, $2, $4
@@ -1755,8 +1832,13 @@ test3:
sc $3, 4
sc $3, 4($0)
+ .ifndef r6
sc $3, 2047($0)
sc $3, -2048($0)
+ .else
+ sc $3, 255($0)
+ sc $3, -256($0)
+ .endif
sc $3, 32767($0)
sc $3, -32768($0)
sc $3, 65535($0)
@@ -1769,8 +1851,13 @@ test3:
sc $3, 0x12345678($0)
sc $3, ($4)
sc $3, 0($4)
+ .ifndef r6
sc $3, 2047($4)
sc $3, -2048($4)
+ .else
+ sc $3, 255($4)
+ sc $3, -256($4)
+ .endif
sc $3, 32767($4)
sc $3, -32768($4)
sc $3, 65535($4)
@@ -2076,11 +2163,13 @@ test3:
sub $29, $30, $31
sub $2, $2, $4
sub $2, $4
+ .ifndef r6
sub $2, $2, 0
sub $2, $2, 1
sub $2, $2, 32767
sub $2, $2, -32768
sub $2, $2, 65535
+ .endif
subu $2, $3, $2
subu $2, $3, $3
@@ -2193,6 +2282,7 @@ test3:
sw $3, 0xffffffff($4)
sw $3, 0x12345678($4)
+ .ifndef r6
swl $3, 4
swl $3, 4($0)
swl $3, 2047($0)
@@ -2308,6 +2398,7 @@ test3:
invalidate $3, 0xf0000000($4)
invalidate $3, 0xffffffff($4)
invalidate $3, 0x12345678($4)
+ .endif
swm $s0, $ra, 12<<2($29)
swm $s0, $s1, $ra, 12<<2($29)
@@ -2418,10 +2509,12 @@ test3:
syscall 2
syscall 255
+ .ifndef r6
teqi $2, 0
teqi $2, -32768
teqi $2, 32767
teqi $2, 65535
+ .endif
teq $2, $3
teq $3, $2
teq $2, $3, 0
@@ -2432,10 +2525,12 @@ test3:
teq $2, 32767
teq $2, 65535
+ .ifndef r6
tgei $2, 0
tgei $2, -32768
tgei $2, 32767
tgei $2, 65535
+ .endif
tge $2, $3
tge $3, $2
tge $2, $3, 0
@@ -2446,10 +2541,12 @@ test3:
tge $2, 32767
tge $2, 65535
+ .ifndef r6
tgeiu $2, 0
tgeiu $2, -32768
tgeiu $2, 32767
tgeiu $2, 65535
+ .endif
tgeu $2, $3
tgeu $3, $2
tgeu $2, $3, 0
@@ -2465,10 +2562,12 @@ test3:
tlbwi
tlbwr
+ .ifndef r6
tlti $2, 0
tlti $2, -32768
tlti $2, 32767
tlti $2, 65535
+ .endif
tlt $2, $3
tlt $3, $2
tlt $2, $3, 0
@@ -2479,10 +2578,12 @@ test3:
tlt $2, 32767
tlt $2, 65535
+ .ifndef r6
tltiu $2, 0
tltiu $2, -32768
tltiu $2, 32767
tltiu $2, 65535
+ .endif
tltu $2, $3
tltu $3, $2
tltu $2, $3, 0
@@ -2495,10 +2596,12 @@ test3:
tltu $2, 65536
tltu $2, 0xffffffff
+ .ifndef r6
tnei $2, 0
tnei $2, -32768
tnei $2, 32767
tnei $2, 65535
+ .endif
tne $2, $3
tne $3, $2
tne $2, $3, 0
@@ -2511,6 +2614,7 @@ test3:
tne $2, 65536
tne $2, 0xffffffff
+ .ifndef r6
ulh $3, 4
ulh $3, 4($0)
ulh $3, ($4)
@@ -2622,6 +2726,7 @@ test3:
usw $3, 0xf0000000($4)
usw $3, 0xffffffff($4)
usw $3, 0x12345678($4)
+ .endif
wait
wait 0
@@ -2676,6 +2781,7 @@ test3:
.set noreorder
+ .ifndef r6
beqz $9, test
addu $3, $4, $5
@@ -3095,6 +3201,7 @@ test3:
bnel $9, 1, test
addu $3, $4, $5
+ .endif
.ifndef insn32
addiur1sp $2, 0
@@ -3430,18 +3537,23 @@ test3:
swp $2, %lo(test)($3)
ll $2, %lo(test)($3)
sc $2, %lo(test)($3)
+
+ .ifndef r6
lwl $2, %lo(test)($3)
lwr $2, %lo(test)($3)
swl $2, %lo(test)($3)
swr $2, %lo(test)($3)
+ .endif
lwm $16, %lo(test)($3)
swm $16, %lo(test)($3)
lwc2 $16, %lo(test)($3)
swc2 $16, %lo(test)($3)
+ .ifndef r6
lcache $2, %lo(test)($3)
flush $2, %lo(test)($3)
scache $2, %lo(test)($3)
invalidate $2, %lo(test)($3)
+ .endif
sdbbp 1023
wait 1023
@@ -3456,6 +3568,7 @@ test3:
.ent fp_test
.globl fp_test
fp_test:
+ .ifndef r6
prefx 0, $0($0)
prefx 0, $0($2)
prefx 0, $0($31)
@@ -3464,6 +3577,7 @@ fp_test:
prefx 1, $31($31)
prefx 2, $31($31)
prefx 31, $31($31)
+ .endif
abs.s $f0, $f1
abs.s $f30, $f31
@@ -3473,10 +3587,12 @@ fp_test:
abs.d $f30, $f31
abs.d $f2, $f2
abs.d $f2
+ .ifndef r6
abs.ps $f0, $f1
abs.ps $f30, $f31
abs.ps $f2, $f2
abs.ps $f2
+ .endif
add.s $f0, $f1, $f2
add.s $f29, $f30, $f31
@@ -3486,6 +3602,7 @@ fp_test:
add.d $f29, $f30, $f31
add.d $f29, $f29, $f30
add.d $f29, $f30
+ .ifndef r6
add.ps $f0, $f1, $f2
add.ps $f29, $f30, $f31
add.ps $f29, $f29, $f30
@@ -3772,6 +3889,7 @@ fp_test:
c.ngt.ps $fcc0, $f30, $f31
c.ngt.ps $fcc2, $f30, $f31
c.ngt.ps $fcc6, $f30, $f31
+ .endif
ceil.l.d $f0, $f1
ceil.l.d $f30, $f31
@@ -4033,10 +4151,12 @@ fp_test:
cvt.w.d $f30, $f31
cvt.w.d $f2, $f2
+ .ifndef r6
cvt.ps.s $f0, $f1, $f2
cvt.ps.s $f29, $f30, $f31
cvt.ps.s $f29, $f29, $f31
cvt.ps.s $f29, $f31
+ .endif
div.d $f0, $f1, $f2
div.d $f29, $f30, $f31
@@ -4106,6 +4226,7 @@ fp_test:
l.d $f3, 32767($4)
l.d $f3, -32768($4)
+ .ifndef r6
ldxc1 $f0, $0($0)
ldxc1 $f0, $0($2)
ldxc1 $f0, $0($31)
@@ -4123,6 +4244,7 @@ fp_test:
luxc1 $f1, $31($31)
luxc1 $f2, $31($31)
luxc1 $f31, $31($31)
+ .endif
lwc1 $3, 0
lwc1 $3, ($0)
@@ -4174,6 +4296,7 @@ fp_test:
l.s $f3, 0xffffffff($4)
l.s $f3, 0x12345678($4)
+ .ifndef r6
lwxc1 $f0, $0($0)
lwxc1 $f0, $0($2)
lwxc1 $f0, $0($31)
@@ -4189,6 +4312,7 @@ fp_test:
madd.s $f28, $f29, $f30, $f31
madd.ps $f0, $f1, $f2, $f3
madd.ps $f28, $f29, $f30, $f31
+ .endif
mfc1 $5, $0
mfc1 $5, $1
@@ -4324,6 +4448,7 @@ fp_test:
mov.d $f30, $f31
mov.s $f0, $f1
mov.s $f30, $f31
+ .ifndef r6
mov.ps $f0, $f1
mov.ps $f30, $f31
@@ -4381,6 +4506,7 @@ fp_test:
msub.s $f28, $f29, $f30, $f31
msub.ps $f0, $f1, $f2, $f3
msub.ps $f28, $f29, $f30, $f31
+ .endif
mtc1 $5, $0
mtc1 $5, $1
@@ -4520,10 +4646,12 @@ fp_test:
mul.d $f29, $f30, $f31
mul.d $f29, $f29, $f30
mul.d $f29, $f30
+ .ifndef r6
mul.ps $f0, $f1, $f2
mul.ps $f29, $f30, $f31
mul.ps $f29, $f29, $f30
mul.ps $f29, $f30
+ .endif
neg.s $f0, $f1
neg.s $f30, $f31
@@ -4533,6 +4661,7 @@ fp_test:
neg.d $f30, $f31
neg.d $f2, $f2
neg.d $f2
+ .ifndef r6
neg.ps $f0, $f1
neg.ps $f30, $f31
neg.ps $f2, $f2
@@ -4568,6 +4697,7 @@ fp_test:
puu.ps $f29, $f30, $f31
puu.ps $f29, $f29, $f30
puu.ps $f29, $f30
+ .endif
recip.s $f0, $f1
recip.s $f30, $f31
@@ -4639,6 +4769,7 @@ fp_test:
s.d $f3, 32767($4)
s.d $f3, -32768($4)
+ .ifndef r6
sdxc1 $f0, $0($0)
sdxc1 $f0, $0($2)
sdxc1 $f0, $0($31)
@@ -4647,6 +4778,7 @@ fp_test:
sdxc1 $f1, $31($31)
sdxc1 $f2, $31($31)
sdxc1 $f31, $31($31)
+ .endif
sqrt.s $f0, $f1
sqrt.s $f30, $f31
@@ -4663,6 +4795,7 @@ fp_test:
sub.d $f29, $f30, $f31
sub.d $f29, $f29, $f30
sub.d $f29, $f30
+ .ifndef r6
sub.ps $f0, $f1, $f2
sub.ps $f29, $f30, $f31
sub.ps $f29, $f29, $f30
@@ -4676,6 +4809,7 @@ fp_test:
suxc1 $f1, $31($31)
suxc1 $f2, $31($31)
suxc1 $f31, $31($31)
+ .endif
swc1 $3, 0
swc1 $3, ($0)
@@ -4727,6 +4861,7 @@ fp_test:
s.s $f3, 0xffffffff($4)
s.s $f3, 0x12345678($4)
+ .ifndef r6
swxc1 $f0, $0($0)
swxc1 $f0, $0($2)
swxc1 $f0, $0($31)
@@ -4735,6 +4870,7 @@ fp_test:
swxc1 $f1, $31($31)
swxc1 $f2, $31($31)
swxc1 $f31, $31($31)
+ .endif
trunc.l.s $f0, $f1
trunc.l.s $f30, $f31
@@ -4750,6 +4886,7 @@ fp_test:
trunc.w.d $f30, $f31
trunc.w.d $f2, $f2
+ .ifndef r6
movf $2, $3, $fcc0
movf $30, $31, $fcc0
movf $30, $31, $fcc1
@@ -4781,10 +4918,15 @@ fp_test:
addu $3, $4, $5
bc1tl $fcc4, test
addu $6, $7, $8
+ .endif
.end fp_test
+ .ifndef r6
.set mips64r2
+ .else
+ .set mips64r6
+ .endif
.globl test_mips64
.ent test_mips64
@@ -4798,6 +4940,7 @@ test_mips64:
dadd $2, $2, $3
dadd $2, $3
+ .ifndef r6
dadd $2, $3, 0
dadd $2, $3, 1
dadd $2, $3, -512
@@ -4818,6 +4961,7 @@ test_mips64:
daddi $2, $3, -32768
daddi $2, $3, 65535
daddi $2, $3, 0x12345678
+ .endif
daddiu $2, $3, 0
daddiu $2, $3, -32768
@@ -4843,29 +4987,37 @@ test_mips64:
ddiv $0, $2, $3
ddiv $0, $30, $31
+ .ifndef r6
ddiv $0, $3
ddiv $0, $31
+ .endif
ddiv $2, $3, $0
ddiv $2, $3, $4
+ .ifndef r6
ddiv $3, $4, 0
ddiv $3, $4, 1
ddiv $3, $4, -1
ddiv $3, $4, 2
+ .endif
ddivu $0, $2, $3
ddivu $0, $30, $31
+ .ifndef r6
ddivu $0, $3
ddivu $0, $31
+ .endif
ddivu $2, $3, $0
ddivu $2, $3, $4
+ .ifndef r6
ddivu $3, $4, 0
ddivu $3, $4, 1
ddivu $3, $4, -1
ddivu $3, $4, 2
+ .endif
dext $2, $3, 31, 1
dext $2, $3, 0, 32
@@ -5255,10 +5407,13 @@ test_mips64:
dmtc2 $2, $2, 7
*/
+ .ifndef r6
dmult $2, $3
dmultu $2, $3
+ .endif
dmul $2, $3, $4
+ .ifndef r6
dmul $2, $3, 0x12345678
dmulo $2, $3, $4
@@ -5291,6 +5446,7 @@ test_mips64:
dremu $3, $4, 1
dremu $3, $4, -1
dremu $3, $4, 2
+ .endif
drol $2, $3, $4
drol $2, $2, $4
@@ -5353,6 +5509,7 @@ test_mips64:
dsubu $2, $3, 0x1234
dsubu $2, $3, 0x12345678
+ .ifndef r6
dsub $2, $3, 0
dsub $2, $3, 1
dsub $2, $3, 512
@@ -5362,6 +5519,7 @@ test_mips64:
dsub $2, $3, 65535
dsub $2, $3, 0x12345678
dsub $2, $3, 0x8888111112345678
+ .endif
.set push
.set noreorder
@@ -5376,6 +5534,7 @@ test_mips64:
ld $2, 32767($3)
.set pop
+ .ifndef r6
ldl $2, 0
ldl $2, 4
ldl $2, ($0)
@@ -5397,6 +5556,7 @@ test_mips64:
ldr $2, 511($3)
ldr $2, -32768($3)
ldr $2, 0x12345678($3)
+ .endif
lld $2, 0
lld $2, 4
@@ -5404,8 +5564,13 @@ test_mips64:
lld $2, 0($0)
lld $2, 4($0)
lld $2, 4($3)
+ .ifndef r6
lld $2, -512($3)
lld $2, 511($3)
+ .else
+ lld $2, -256($3)
+ lld $2, 255($3)
+ .endif
lld $2, -32768($3)
lld $2, 0x12345678($3)
@@ -5426,8 +5591,13 @@ test_mips64:
scd $2, 0($0)
scd $2, 4($0)
scd $2, 4($3)
+ .ifndef r6
scd $2, -512($3)
scd $2, 511($3)
+ .else
+ scd $2, -256($3)
+ scd $2, 255($3)
+ .endif
scd $2, -32768($3)
scd $2, 0x12345678($3)
@@ -5444,6 +5614,7 @@ test_mips64:
sd $2, 32767($3)
.set pop
+ .ifndef r6
sdl $2, 0
sdl $2, 4
sdl $2, ($0)
@@ -5463,6 +5634,7 @@ test_mips64:
sdr $2, -32768($3)
sdr $2, 32767($3)
sdr $2, 0x12345678($3)
+ .endif
ldm $s0, 0
ldm $s0, 4
@@ -5558,6 +5730,7 @@ test_mips64:
sdp $2, 65535($0)
sdp $2, 0x12345678($0)
+ .ifndef r6
uld $3, 0
uld $3, ($0)
uld $3, 4
@@ -5630,11 +5803,14 @@ test_mips64:
ldl $16, %lo(test)($3)
ldr $16, %lo(test)($3)
+ .endif
lld $16, %lo(test)($3)
lwu $16, %lo(test)($3)
scd $16, %lo(test)($3)
+ .ifndef r6
sdl $16, %lo(test)($3)
sdr $16, %lo(test)($3)
+ .endif
ldm $16, %lo(test)($3)
ldp $16, %lo(test)($3)
sdm $16, %lo(test)($3)
@@ -5650,10 +5826,14 @@ test_delay_slot:
bal test_delay_slot
bgezal $3, test_delay_slot
bltzal $3, test_delay_slot
+ .ifndef r6
bgezall $3, test_delay_slot
bltzall $3, test_delay_slot
+ .endif
jal test_delay_slot
+ .ifndef r6
jalx test_delay_slot_ext
+ .endif
.ifndef insn32
jalr16 $2
.endif
@@ -5670,10 +5850,12 @@ test_delay_slot:
jals test_delay_slot
jalrs16 $2
jalrs32 $2
+ .ifndef r6
jrs $2
jalrs.hb $2
jrs.hb $2
.endif
+ .endif
.end test_delay_slot
@@ -5712,8 +5894,13 @@ test_spec102:
addiu $7, $pc, 0
addiu $16, $pc, 0
addiu $17, $pc, 0
+ .ifndef r6
addiu $17, $pc, 4194303 << 2
addiu $17, $pc, -4194304 << 2
+ .else
+ addiu $17, $pc, 262143 << 2
+ addiu $17, $pc, -262144 << 2
+ .endif
addiupc $2, 0
addiupc $3, 0
addiupc $4, 0
@@ -5722,8 +5909,13 @@ test_spec102:
addiupc $7, 0
addiupc $16, 0
addiupc $17, 0
+ .ifndef r6
addiupc $17, 4194303 << 2
addiupc $17, -4194304 << 2
+ .else
+ addiupc $17, 262143 << 2
+ addiupc $17, -262144 << 2
+ .endif
.end test_spec102
@@ -5752,6 +5944,7 @@ test_spec107:
movep $4, $7, $20, $18
movep $4, $7, $20, $19
movep $4, $7, $20, $20
+ .ifndef r6
.ifndef insn32
bals test_spec107
nop
@@ -5766,5 +5959,6 @@ test_spec107:
nop
bltzal $2, test_spec107
nop
+ .endif
.end test_spec107
diff --git a/gas/testsuite/gas/mips/micromips@mips32-cp2.s b/gas/testsuite/gas/mips/micromips@mips32-cp2.s
index d52ce874a97..f4f716bb595 100644
--- a/gas/testsuite/gas/mips/micromips@mips32-cp2.s
+++ b/gas/testsuite/gas/mips/micromips@mips32-cp2.s
@@ -8,6 +8,7 @@ text_label:
# Unprivileged coprocessor instructions.
# These tests use cp2 to avoid other (cp0, fpu, prefetch) opcodes.
+ .ifndef r6
bc2f text_label
nop
bc2fl text_label
@@ -16,6 +17,7 @@ text_label:
nop
bc2tl text_label
nop
+ .endif
# XXX other BCzCond encodings not currently expressable.
cfc2 $1, $2
@@ -28,6 +30,7 @@ text_label:
mtc2 $6, $7
+ .ifndef r6
# Cop2 branches with cond code number, like bc1t/f.
bc2f $cc0,text_label
nop
@@ -37,6 +40,7 @@ text_label:
nop
bc2tl $cc7,text_label
nop
+ .endif
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
.align 2
diff --git a/gas/testsuite/gas/mips/micromips@mips32r2.d b/gas/testsuite/gas/mips/micromips@mips32r2.d
index 3e0bf9c9408..a7af4ebfb20 100644
--- a/gas/testsuite/gas/mips/micromips@mips32r2.d
+++ b/gas/testsuite/gas/mips/micromips@mips32r2.d
@@ -12,8 +12,11 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 0085 39ac ext \$4,\$5,0x6,0x8
[0-9a-f]+ <[^>]*> 0085 698c ins \$4,\$5,0x6,0x8
[0-9a-f]+ <[^>]*> 03e8 1f3c jalr\.hb \$8
+[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 0289 1f3c jalr\.hb \$20,\$9
+[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 0008 1f3c jr\.hb \$8
+[0-9a-f]+ <[^>]*> 0000 0000 nop
[0-9a-f]+ <[^>]*> 0140 6b3c rdhwr \$10,\$0
[0-9a-f]+ <[^>]*> 0161 6b3c rdhwr \$11,\$1
[0-9a-f]+ <[^>]*> 0182 6b3c rdhwr \$12,\$2
diff --git a/gas/testsuite/gas/mips/micromipsr6@24k-branch-delay-1.d b/gas/testsuite/gas/mips/micromipsr6@24k-branch-delay-1.d
new file mode 100644
index 00000000000..305d97c0042
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@24k-branch-delay-1.d
@@ -0,0 +1,22 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#name: 24K: Delay slot filling (microMIPS)
+#source: 24k-branch-delay-1.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 3043 0005 addiu v0,v1,5
+ *[0-9a-f]+: 6a20 lw a0,0\(v0\)
+ *[0-9a-f]+: e9a0 sw v1,0\(v0\)
+ *[0-9a-f]+: e9a2 sw v1,8\(v0\)
+ *[0-9a-f]+: e9a4 sw v1,16\(v0\)
+ *([0-9a-f]+): 805e 0000 beqzc v0,fffc0010 <\.L1\+0xfffbfffe>
+ [0-9a-f]+: R_MICROMIPS_PC21_S1 .*
+ *[0-9a-f]+: 69a2 lw v1,8\(v0\)
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 6aa4 lw a1,16\(v0\)
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-1.d b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-1.d
new file mode 100644
index 00000000000..e3fbcbaeef9
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-1.d
@@ -0,0 +1,52 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#name: 24K: Triple Store (Opcode Check)
+#source: 24k-triple-stores-1.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 185d 0000 sb v0,0\(sp\)
+ *[0-9a-f]+: 187d 0008 sb v1,8\(sp\)
+ *[0-9a-f]+: 189d 0010 sb a0,16\(sp\)
+ *[0-9a-f]+: 18bd 0018 sb a1,24\(sp\)
+ *[0-9a-f]+: 18dd 0020 sb a2,32\(sp\)
+ *[0-9a-f]+: 385d 0000 sh v0,0\(sp\)
+ *[0-9a-f]+: 387d 0008 sh v1,8\(sp\)
+ *[0-9a-f]+: 389d 0010 sh a0,16\(sp\)
+ *[0-9a-f]+: 38bd 0018 sh a1,24\(sp\)
+ *[0-9a-f]+: 38dd 0020 sh a2,32\(sp\)
+ *[0-9a-f]+: c840 sw v0,0\(sp\)
+ *[0-9a-f]+: c862 sw v1,8\(sp\)
+ *[0-9a-f]+: c884 sw a0,16\(sp\)
+ *[0-9a-f]+: c8a6 sw a1,24\(sp\)
+ *[0-9a-f]+: c8c8 sw a2,32\(sp\)
+ *[0-9a-f]+: 605d b000 sc v0,0\(sp\)
+ *[0-9a-f]+: 607d b008 sc v1,8\(sp\)
+ *[0-9a-f]+: 609d b010 sc a0,16\(sp\)
+ *[0-9a-f]+: 60bd b018 sc a1,24\(sp\)
+ *[0-9a-f]+: 60dd b020 sc a2,32\(sp\)
+ *[0-9a-f]+: 985d 0000 swc1 \$f2,0\(sp\)
+ *[0-9a-f]+: 987d 0008 swc1 \$f3,8\(sp\)
+ *[0-9a-f]+: 989d 0010 swc1 \$f4,16\(sp\)
+ *[0-9a-f]+: 98bd 0018 swc1 \$f5,24\(sp\)
+ *[0-9a-f]+: 98dd 0020 swc1 \$f6,32\(sp\)
+ *[0-9a-f]+: 205d 8000 swc2 \$2,0\(sp\)
+ *[0-9a-f]+: 207d 8008 swc2 \$3,8\(sp\)
+ *[0-9a-f]+: 209d 8010 swc2 \$4,16\(sp\)
+ *[0-9a-f]+: 20bd 8018 swc2 \$5,24\(sp\)
+ *[0-9a-f]+: 20dd 8020 swc2 \$6,32\(sp\)
+ *[0-9a-f]+: b85d 0000 sdc1 \$f2,0\(sp\)
+ *[0-9a-f]+: b87d 0008 sdc1 \$f3,8\(sp\)
+ *[0-9a-f]+: b89d 0010 sdc1 \$f4,16\(sp\)
+ *[0-9a-f]+: b8bd 0018 sdc1 \$f5,24\(sp\)
+ *[0-9a-f]+: b8dd 0020 sdc1 \$f6,32\(sp\)
+ *[0-9a-f]+: 205d a000 sdc2 \$2,0\(sp\)
+ *[0-9a-f]+: 207d a008 sdc2 \$3,8\(sp\)
+ *[0-9a-f]+: 209d a010 sdc2 \$4,16\(sp\)
+ *[0-9a-f]+: 20bd a018 sdc2 \$5,24\(sp\)
+ *[0-9a-f]+: 20dd a020 sdc2 \$6,32\(sp\)
+ *[0-9a-f]+: 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-2-llsc.d b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-2-llsc.d
new file mode 100644
index 00000000000..8f0e2ec3a9b
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-2-llsc.d
@@ -0,0 +1,16 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#name: 24K: Triple Store (Range Check, sc)
+#source: 24k-triple-stores-2-llsc.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 605d b020 sc v0,32\(sp\)
+ *[0-9a-f]+: 607d b008 sc v1,8\(sp\)
+ *[0-9a-f]+: 609d b1f8 sc a0,-8\(sp\)
+ *[0-9a-f]+: 60bd b000 sc a1,0\(sp\)
+ *[0-9a-f]+: 60dd b020 sc a2,32\(sp\)
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-2.d b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-2.d
new file mode 100644
index 00000000000..00fb4574668
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-2.d
@@ -0,0 +1,24 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#name: 24K: Triple Store (Range Check)
+#source: 24k-triple-stores-2.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 185d 0000 sb v0,0\(sp\)
+ *[0-9a-f]+: 187d 000a sb v1,10\(sp\)
+ *[0-9a-f]+: 189d 001f sb a0,31\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 385d 0000 sh v0,0\(sp\)
+ *[0-9a-f]+: 387d fff0 sh v1,-16\(sp\)
+ *[0-9a-f]+: 389d ffe0 sh a0,-32\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: c840 sw v0,0\(sp\)
+ *[0-9a-f]+: f87d fff8 sw v1,-8\(sp\)
+ *[0-9a-f]+: c882 sw a0,8\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-3.d b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-3.d
new file mode 100644
index 00000000000..1ebd342026d
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-3.d
@@ -0,0 +1,52 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#name: 24K: Triple Store (Double-word Check)
+#source: 24k-triple-stores-3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 185d 000b sb v0,11\(sp\)
+ *[0-9a-f]+: 187d 000b sb v1,11\(sp\)
+ *[0-9a-f]+: 189d 0004 sb a0,4\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 185d 0000 sb v0,0\(sp\)
+ *[0-9a-f]+: 187d 000b sb v1,11\(sp\)
+ *[0-9a-f]+: 189d 0005 sb a0,5\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 185d 0007 sb v0,7\(sp\)
+ *[0-9a-f]+: 187d 000b sb v1,11\(sp\)
+ *[0-9a-f]+: 189d 0010 sb a0,16\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1848 0000 sb v0,0\(t0\)
+ *[0-9a-f]+: 1868 0008 sb v1,8\(t0\)
+ *[0-9a-f]+: 1888 0009 sb a0,9\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 385d 0000 sh v0,0\(sp\)
+ *[0-9a-f]+: 387d ffe1 sh v1,-31\(sp\)
+ *[0-9a-f]+: 389d ffe2 sh a0,-30\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 385d 0006 sh v0,6\(sp\)
+ *[0-9a-f]+: 387d 0008 sh v1,8\(sp\)
+ *[0-9a-f]+: 389d 0010 sh a0,16\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 3848 0001 sh v0,1\(t0\)
+ *[0-9a-f]+: 3868 0003 sh v1,3\(t0\)
+ *[0-9a-f]+: 3888 000b sh a0,11\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: c842 sw v0,8\(sp\)
+ *[0-9a-f]+: f87d fff8 sw v1,-8\(sp\)
+ *[0-9a-f]+: c882 sw a0,8\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: c841 sw v0,4\(sp\)
+ *[0-9a-f]+: c862 sw v1,8\(sp\)
+ *[0-9a-f]+: c884 sw a0,16\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: f848 0003 sw v0,3\(t0\)
+ *[0-9a-f]+: f868 0007 sw v1,7\(t0\)
+ *[0-9a-f]+: f888 000f sw a0,15\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-4.d b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-4.d
new file mode 100644
index 00000000000..66bce58189b
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-4.d
@@ -0,0 +1,59 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#name: 24K: Triple Store (Range Check >= 32)
+#source: 24k-triple-stores-4.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 1a68 000a sb s3,10\(t0\)
+ *[0-9a-f]+: 3a68 0001 sh s3,1\(t0\)
+ *[0-9a-f]+: 1a68 0020 sb s3,32\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 000a sb s3,10\(t0\)
+ *[0-9a-f]+: 1a68 0001 sb s3,1\(t0\)
+ *[0-9a-f]+: 3a68 0020 sh s3,32\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0021 sb s3,33\(t0\)
+ *[0-9a-f]+: 3a68 0037 sh s3,55\(t0\)
+ *[0-9a-f]+: 1a68 0040 sb s3,64\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0021 sb s3,33\(t0\)
+ *[0-9a-f]+: 1a68 0037 sb s3,55\(t0\)
+ *[0-9a-f]+: 3a68 0040 sh s3,64\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 000c sb s3,12\(t0\)
+ *[0-9a-f]+: fa68 0001 sw s3,1\(t0\)
+ *[0-9a-f]+: 1a68 0020 sb s3,32\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 000c sb s3,12\(t0\)
+ *[0-9a-f]+: 1a68 0001 sb s3,1\(t0\)
+ *[0-9a-f]+: fa68 0020 sw s3,32\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0023 sb s3,35\(t0\)
+ *[0-9a-f]+: fa68 0037 sw s3,55\(t0\)
+ *[0-9a-f]+: 1a68 0040 sb s3,64\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0023 sb s3,35\(t0\)
+ *[0-9a-f]+: 1a68 0037 sb s3,55\(t0\)
+ *[0-9a-f]+: fa68 0040 sw s3,64\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0010 sb s3,16\(t0\)
+ *[0-9a-f]+: b808 0001 sdc1 \$f0,1\(t0\)
+ *[0-9a-f]+: 1a68 0020 sb s3,32\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0010 sb s3,16\(t0\)
+ *[0-9a-f]+: 1a68 0001 sb s3,1\(t0\)
+ *[0-9a-f]+: b808 0020 sdc1 \$f0,32\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0027 sb s3,39\(t0\)
+ *[0-9a-f]+: b808 0037 sdc1 \$f0,55\(t0\)
+ *[0-9a-f]+: 1a68 0040 sb s3,64\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0027 sb s3,39\(t0\)
+ *[0-9a-f]+: 1a68 0037 sb s3,55\(t0\)
+ *[0-9a-f]+: b808 0040 sdc1 \$f0,64\(t0\)
+ *[0-9a-f]+: 441b break
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-5.d b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-5.d
new file mode 100644
index 00000000000..2fa0d928c89
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-5.d
@@ -0,0 +1,35 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#name: 24K: Triple Store (Mix byte/half/word size check)
+#source: 24k-triple-stores-5.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 3848 0007 sh v0,7\(t0\)
+ *[0-9a-f]+: 1868 0000 sb v1,0\(t0\)
+ *[0-9a-f]+: f888 0001 sw a0,1\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 3848 0016 sh v0,22\(t0\)
+ *[0-9a-f]+: 1868 000f sb v1,15\(t0\)
+ *[0-9a-f]+: f888 0018 sw a0,24\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 3848 0000 sh v0,0\(t0\)
+ *[0-9a-f]+: 1868 0009 sb v1,9\(t0\)
+ *[0-9a-f]+: f888 0002 sw a0,2\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 3848 0006 sh v0,6\(t0\)
+ *[0-9a-f]+: 1868 0010 sb v1,16\(t0\)
+ *[0-9a-f]+: f888 000c sw a0,12\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 3848 000a sh v0,10\(t0\)
+ *[0-9a-f]+: 1868 000f sb v1,15\(t0\)
+ *[0-9a-f]+: f888 0004 sw a0,4\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 3848 000a sh v0,10\(t0\)
+ *[0-9a-f]+: 1868 0010 sb v1,16\(t0\)
+ *[0-9a-f]+: f888 0004 sw a0,4\(t0\)
+ *[0-9a-f]+: 441b break
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-6.d b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-6.d
new file mode 100644
index 00000000000..89950a3a43f
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-6.d
@@ -0,0 +1,19 @@
+#objdump: -dr
+#as: -mfix-24k -32 -EB
+#name: 24K: Triple Store (Store Macro Check)
+#source: 24k-triple-stores-6.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 981d 0050 swc1 \$f0,80\(sp\)
+ *[0-9a-f]+: 985d 0058 swc1 \$f2,88\(sp\)
+ *[0-9a-f]+: 989d 0060 swc1 \$f4,96\(sp\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: b81d 0050 sdc1 \$f0,80\(sp\)
+ *[0-9a-f]+: b85d 0058 sdc1 \$f2,88\(sp\)
+ *[0-9a-f]+: b89d 0060 sdc1 \$f4,96\(sp\)
+ *[0-9a-f]+: 441b break
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-7.d b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-7.d
new file mode 100644
index 00000000000..c1b8b59377c
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-7.d
@@ -0,0 +1,75 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#name: 24K: Triple Store (Extended Range Check)
+#source: 24k-triple-stores-7.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 1a68 0004 sb s3,4\(t0\)
+ *[0-9a-f]+: fa68 0008 sw s3,8\(t0\)
+ *[0-9a-f]+: 1a68 000f sb s3,15\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0003 sb s3,3\(t0\)
+ *[0-9a-f]+: fa68 0008 sw s3,8\(t0\)
+ *[0-9a-f]+: 1a68 000f sb s3,15\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: fa68 001c sw s3,28\(t0\)
+ *[0-9a-f]+: fa68 0008 sw s3,8\(t0\)
+ *[0-9a-f]+: 1a68 001f sb s3,31\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0005 sb s3,5\(t0\)
+ *[0-9a-f]+: fa68 0009 sw s3,9\(t0\)
+ *[0-9a-f]+: 1a68 0010 sb s3,16\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0004 sb s3,4\(t0\)
+ *[0-9a-f]+: fa68 0009 sw s3,9\(t0\)
+ *[0-9a-f]+: 1a68 0010 sb s3,16\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0006 sb s3,6\(t0\)
+ *[0-9a-f]+: 3a68 0008 sh s3,8\(t0\)
+ *[0-9a-f]+: 1a68 000f sb s3,15\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0005 sb s3,5\(t0\)
+ *[0-9a-f]+: 3a68 0008 sh s3,8\(t0\)
+ *[0-9a-f]+: 1a68 000f sb s3,15\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 3a68 001e sh s3,30\(t0\)
+ *[0-9a-f]+: 3a68 0008 sh s3,8\(t0\)
+ *[0-9a-f]+: 1a68 001f sb s3,31\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0007 sb s3,7\(t0\)
+ *[0-9a-f]+: 3a68 0009 sh s3,9\(t0\)
+ *[0-9a-f]+: 1a68 0010 sb s3,16\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0006 sb s3,6\(t0\)
+ *[0-9a-f]+: 3a68 0009 sh s3,9\(t0\)
+ *[0-9a-f]+: 1a68 0010 sb s3,16\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0007 sb s3,7\(t0\)
+ *[0-9a-f]+: b808 0008 sdc1 \$f0,8\(t0\)
+ *[0-9a-f]+: 1a68 000f sb s3,15\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0007 sb s3,7\(t0\)
+ *[0-9a-f]+: b808 0008 sdc1 \$f0,8\(t0\)
+ *[0-9a-f]+: 1a68 0010 sb s3,16\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0010 sb s3,16\(t0\)
+ *[0-9a-f]+: b808 0008 sdc1 \$f0,8\(t0\)
+ *[0-9a-f]+: 1a68 0017 sb s3,23\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0010 sb s3,16\(t0\)
+ *[0-9a-f]+: b808 0008 sdc1 \$f0,8\(t0\)
+ *[0-9a-f]+: 1a68 0018 sb s3,24\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0008 sb s3,8\(t0\)
+ *[0-9a-f]+: b808 0009 sdc1 \$f0,9\(t0\)
+ *[0-9a-f]+: 1a68 0010 sb s3,16\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 fffd sb s3,-3\(t0\)
+ *[0-9a-f]+: b808 fffe sdc1 \$f0,-2\(t0\)
+ *[0-9a-f]+: 1a68 0006 sb s3,6\(t0\)
+ *[0-9a-f]+: 441b break
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-8.d b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-8.d
new file mode 100644
index 00000000000..c4ffad59a69
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@24k-triple-stores-8.d
@@ -0,0 +1,59 @@
+#objdump: -dr
+#as: -mfix-24k -32
+#name: 24K: Triple Store (Range Check >= 24)
+#source: 24k-triple-stores-8.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <.*>:
+ *[0-9a-f]+: 1a68 0000 sb s3,0\(t0\)
+ *[0-9a-f]+: 1a68 0001 sb s3,1\(t0\)
+ *[0-9a-f]+: 1a68 0018 sb s3,24\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0000 sb s3,0\(t0\)
+ *[0-9a-f]+: 1a68 0001 sb s3,1\(t0\)
+ *[0-9a-f]+: 1a68 0019 sb s3,25\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0001 sb s3,1\(t0\)
+ *[0-9a-f]+: 1a68 0019 sb s3,25\(t0\)
+ *[0-9a-f]+: 1a68 001a sb s3,26\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0000 sb s3,0\(t0\)
+ *[0-9a-f]+: 3a68 0003 sh s3,3\(t0\)
+ *[0-9a-f]+: 1a68 001a sb s3,26\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 3a68 0000 sh s3,0\(t0\)
+ *[0-9a-f]+: 1a68 0003 sb s3,3\(t0\)
+ *[0-9a-f]+: 1a68 001a sb s3,26\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0023 sb s3,35\(t0\)
+ *[0-9a-f]+: 3a68 0020 sh s3,32\(t0\)
+ *[0-9a-f]+: 1a68 0009 sb s3,9\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0001 sb s3,1\(t0\)
+ *[0-9a-f]+: 3a68 0019 sh s3,25\(t0\)
+ *[0-9a-f]+: 1a68 001b sb s3,27\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0000 sb s3,0\(t0\)
+ *[0-9a-f]+: fa68 0007 sw s3,7\(t0\)
+ *[0-9a-f]+: 1a68 001c sb s3,28\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0000 sb s3,0\(t0\)
+ *[0-9a-f]+: 1a68 0007 sb s3,7\(t0\)
+ *[0-9a-f]+: fa68 001c sw s3,28\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0040 sb s3,64\(t0\)
+ *[0-9a-f]+: fa68 003b sw s3,59\(t0\)
+ *[0-9a-f]+: fa68 0025 sw s3,37\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: fa68 0040 sw s3,64\(t0\)
+ *[0-9a-f]+: 1a68 003d sb s3,61\(t0\)
+ *[0-9a-f]+: 1a68 0027 sb s3,39\(t0\)
+ *[0-9a-f]+: 441b break
+ *[0-9a-f]+: 1a68 0001 sb s3,1\(t0\)
+ *[0-9a-f]+: fa68 0019 sw s3,25\(t0\)
+ *[0-9a-f]+: 1a68 001d sb s3,29\(t0\)
+ *[0-9a-f]+: 441b break
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@abs.d b/gas/testsuite/gas/mips/micromipsr6@abs.d
new file mode 100644
index 00000000000..35b54b12b5f
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@abs.d
@@ -0,0 +1,19 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS abs
+#source: abs.s
+#as: -32
+
+# Test the abs macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> f484 fffe bgezc a0,[0-9a-f]+ <foo>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 0080 2190 neg a0,a0
+[0-9a-f]+ <[^>]*> 0c85 move a0,a1
+[0-9a-f]+ <[^>]*> f4a5 fffe bgezc a1,[0-9a-f]+ <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .*
+[0-9a-f]+ <[^>]*> 00a0 2190 neg a0,a1
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@add.d b/gas/testsuite/gas/mips/micromipsr6@add.d
new file mode 100644
index 00000000000..852024b4a4e
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@add.d
@@ -0,0 +1,25 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS add
+#source: add.s
+#as: -32
+
+# Test the add macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> li at,0
+0+0004 <[^>]*> add a0,a0,at
+0+0008 <[^>]*> li at,1
+0+000c <[^>]*> add a0,a0,at$
+0+0010 <[^>]*> li at,0x8000
+0+0014 <[^>]*> add a0,a0,at$
+0+0018 <[^>]*> li at,-32768
+0+001c <[^>]*> add a0,a0,at$
+0+0020 <[^>]*> lui at,0x1
+0+0024 <[^>]*> add a0,a0,at$
+0+0028 <[^>]*> lui at,0x1
+0+002c <[^>]*> ori at,at,0xa5a5$
+0+0030 <[^>]*> add a0,a0,at
+0+0034 <[^>]*> addiu a0,a0,1
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@and.d b/gas/testsuite/gas/mips/micromipsr6@and.d
new file mode 100644
index 00000000000..04ac221aede
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@and.d
@@ -0,0 +1,36 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS and
+#source: and.s
+#as: -32
+
+# Test the and macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> d084 0000 andi a0,a0,0x0
+[0-9a-f]+ <[^>]*> d084 0001 andi a0,a0,0x1
+[0-9a-f]+ <[^>]*> d084 8000 andi a0,a0,0x8000
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 0024 2250 and a0,a0,at
+[0-9a-f]+ <[^>]*> 1020 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 0024 2250 and a0,a0,at
+[0-9a-f]+ <[^>]*> 1020 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 0024 2250 and a0,a0,at
+[0-9a-f]+ <[^>]*> 5085 0000 ori a0,a1,0x0
+[0-9a-f]+ <[^>]*> 0004 22d0 not a0,a0
+[0-9a-f]+ <[^>]*> 5085 0001 ori a0,a1,0x1
+[0-9a-f]+ <[^>]*> 0004 22d0 not a0,a0
+[0-9a-f]+ <[^>]*> 5085 8000 ori a0,a1,0x8000
+[0-9a-f]+ <[^>]*> 0004 22d0 not a0,a0
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 0025 22d0 nor a0,a1,at
+[0-9a-f]+ <[^>]*> 1020 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 0025 22d0 nor a0,a1,at
+[0-9a-f]+ <[^>]*> 1020 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 0025 22d0 nor a0,a1,at
+[0-9a-f]+ <[^>]*> 5085 0000 ori a0,a1,0x0
+[0-9a-f]+ <[^>]*> 7085 0000 xori a0,a1,0x0
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msingle-float.l b/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msingle-float.l
new file mode 100644
index 00000000000..2f3b6f80efa
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msingle-float.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Warning: .gnu_attribute 4,1 is incompatible with `singlefloat'
+.*: Warning: .gnu_attribute 4,1 is incompatible with `gp=32 fp=64'
diff --git a/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msingle-float.s b/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msingle-float.s
new file mode 100644
index 00000000000..e985a56f6b1
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msingle-float.s
@@ -0,0 +1 @@
+.gnu_attribute 4,1
diff --git a/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msoft-float.l b/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msoft-float.l
new file mode 100644
index 00000000000..7e372d1a168
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msoft-float.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*: Warning: .gnu_attribute 4,1 is incompatible with `softfloat'
+.*: Warning: .gnu_attribute 4,1 is incompatible with `gp=32 fp=64'
diff --git a/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msoft-float.s b/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msoft-float.s
new file mode 100644
index 00000000000..e985a56f6b1
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@attr-gnu-4-1-msoft-float.s
@@ -0,0 +1 @@
+.gnu_attribute 4,1
diff --git a/gas/testsuite/gas/mips/micromipsr6@beq.d b/gas/testsuite/gas/mips/micromipsr6@beq.d
new file mode 100644
index 00000000000..de088f230fd
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@beq.d
@@ -0,0 +1,37 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS beq
+#source: beq.s
+#as: -32
+
+# Test the beq macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 74a4 fffe beqc a0,a1,0+0000 <text_label>
+ 0: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 807e 0000 beqzc v1,fffc0008 <text_label\+0xfffc0008>
+ 4: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> 3020 0001 li at,1
+[0-9a-f]+ <[^>]*> 7481 fffe beqc at,a0,0+00c <text_label\+0xc>
+ c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 5020 8000 li at,0x8000
+[0-9a-f]+ <[^>]*> 7481 fffe beqc at,a0,0+0014 <text_label\+0x14>
+ 14: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 3020 8000 li at,-32768
+[0-9a-f]+ <[^>]*> 7481 fffe beqc at,a0,0+001c <text_label\+0x1c>
+ 1c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 1020 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 7481 fffe beqc at,a0,0+0024 <text_label\+0x24>
+ 24: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> 1020 0001 lui at,0x1
+[0-9a-f]+ <[^>]*> 5021 a5a5 ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> 7481 fffe beqc at,a0,0+0030 <text_label\+0x30>
+ 30: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> a07e 0000 bnezc v1,fffc0038 <text_label\+0xfffc0038>
+ 34: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> 93fe 0000 slti ra,s8,0
+ 38: R_MICROMIPS_PC26_S1 external_label
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 3c: R_MICROMIPS_PC26_S1 external_label
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@bge.d b/gas/testsuite/gas/mips/micromipsr6@bge.d
new file mode 100644
index 00000000000..79553403688
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@bge.d
@@ -0,0 +1,56 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS bge (micromips-r6)
+#source: bge.s
+#as: -32
+
+# Test the bge macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> slt at,a0,a1
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*4: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> bgezc a0,00000008 <.*>
+[ ]*8: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> blezc a1,0000000c <.*>
+[ ]*c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> bgezc a0,00000010 <.*>
+[ ]*10: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> bgtzc a0,00000014 <.*>
+[ ]*14: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> slti at,a0,2
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*1c: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> li at,0x8000
+[0-9a-f]+ <[^>]*> slt at,a0,at
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*28: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> slti at,a0,-32768
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*30: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> lui at,0x1
+[0-9a-f]+ <[^>]*> slt at,a0,at
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*3c: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> lui at,0x1
+[0-9a-f]+ <[^>]*> ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> slt at,a0,at
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*4c: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> slt at,a1,a0
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*54: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> bgtzc a0,00000058 <.*>
+[ ]*58: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> bltzc a1,0000005c <.*>
+[ ]*5c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> bgtzc a0,00000060 <.*>
+[ ]*60: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> slt at,a0,a1
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*68: R_MICROMIPS_PC21_S1 external_label
+[0-9a-f]+ <[^>]*> slt at,a1,a0
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*70: R_MICROMIPS_PC21_S1 external_label
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@bgeu.d b/gas/testsuite/gas/mips/micromipsr6@bgeu.d
new file mode 100644
index 00000000000..653ff569137
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@bgeu.d
@@ -0,0 +1,48 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS bge (micromips-r6)
+#source: bgeu.s
+#as: -32
+
+# Test the bge macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> sltu at,a0,a1
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*4: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> bnezc v1,fffc000c <.*>
+[ ]*8: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> sltiu at,a0,2
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*10: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> li at,0x8000
+[0-9a-f]+ <[^>]*> sltu at,a0,at
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*1c: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> sltiu at,a0,-32768
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*24: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> lui at,0x1
+[0-9a-f]+ <[^>]*> sltu at,a0,at
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*30: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> lui at,0x1
+[0-9a-f]+ <[^>]*> ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> sltu at,a0,at
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*40: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> sltu at,a1,a0
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*48: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> bnezc v1,fffc0050 <.*>
+[ ]*4c: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> bnezc v1,fffc0054 <.*>
+[ ]*50: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> sltu at,a0,a1
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*58: R_MICROMIPS_PC21_S1 external_label
+[0-9a-f]+ <[^>]*> sltu at,a1,a0
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*60: R_MICROMIPS_PC21_S1 external_label
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@blt.d b/gas/testsuite/gas/mips/micromipsr6@blt.d
new file mode 100644
index 00000000000..0a51d8fe211
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@blt.d
@@ -0,0 +1,56 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS blt (micromips-r6)
+#source: blt.s
+#as: -32
+
+# Test the blt macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> slt at,a0,a1
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*4: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> bltzc a0,00000008 <.*>
+[ ]*8: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> bgtzc a1,0000000c <.*>
+[ ]*c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> bltzc a0,00000010 <.*>
+[ ]*10: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> blezc a0,00000014 <.*>
+[ ]*14: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> slti at,a0,2
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*1c: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> li at,0x8000
+[0-9a-f]+ <[^>]*> slt at,a0,at
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*28: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> slti at,a0,-32768
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*30: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> lui at,0x1
+[0-9a-f]+ <[^>]*> slt at,a0,at
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*3c: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> lui at,0x1
+[0-9a-f]+ <[^>]*> ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> slt at,a0,at
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*4c: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> slt at,a1,a0
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*54: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> blezc a0,00000058 <.*>
+[ ]*58: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> bgezc a1,0000005c <.*>
+[ ]*5c: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> blezc a0,00000060 <.*>
+[ ]*60: R_MICROMIPS_PC16_S1 text_label
+[0-9a-f]+ <[^>]*> slt at,a0,a1
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*68: R_MICROMIPS_PC21_S1 external_label
+[0-9a-f]+ <[^>]*> slt at,a1,a0
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*70: R_MICROMIPS_PC21_S1 external_label
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@bltu.d b/gas/testsuite/gas/mips/micromipsr6@bltu.d
new file mode 100644
index 00000000000..c7c87a69659
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@bltu.d
@@ -0,0 +1,48 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS bltu (micromips-r6)
+#source: bltu.s
+#as: -32
+
+# Test the bltu macro.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> sltu at,a0,a1
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*4: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> beqzc v1,fffc000c <.*>
+[ ]*8: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> sltiu at,a0,2
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*10: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> li at,0x8000
+[0-9a-f]+ <[^>]*> sltu at,a0,at
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*1c: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> sltiu at,a0,-32768
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*24: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> lui at,0x1
+[0-9a-f]+ <[^>]*> sltu at,a0,at
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*30: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> lui at,0x1
+[0-9a-f]+ <[^>]*> ori at,at,0xa5a5
+[0-9a-f]+ <[^>]*> sltu at,a0,at
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*40: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> sltu at,a1,a0
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*48: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> beqzc v1,fffc0050 <.*>
+[ ]*4c: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> beqzc v1,fffc0054 <.*>
+[ ]*50: R_MICROMIPS_PC21_S1 text_label
+[0-9a-f]+ <[^>]*> sltu at,a0,a1
+[0-9a-f]+ <[^>]*> jialc s8,0
+[ ]*58: R_MICROMIPS_PC21_S1 external_label
+[0-9a-f]+ <[^>]*> sltu at,a1,a0
+[0-9a-f]+ <[^>]*> jrc s8
+[ ]*60: R_MICROMIPS_PC21_S1 external_label
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-1.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-1.d
new file mode 100644
index 00000000000..a6341dfb985
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-1.d
@@ -0,0 +1,29 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-1
+#source: branch-misc-1.s
+#as: -32
+
+# Test the branches to local symbols in current file (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 3c: R_MICROMIPS_PC26_S1 l1
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 40: R_MICROMIPS_PC26_S1 l2
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 44: R_MICROMIPS_PC26_S1 l3
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 48: R_MICROMIPS_PC26_S1 l4
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 4c: R_MICROMIPS_PC26_S1 l5
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 50: R_MICROMIPS_PC26_S1 l6
+ \.\.\.
+ \.\.\.
+ \.\.\.
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-2-64.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-2-64.d
new file mode 100644
index 00000000000..d0422420b8c
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-2-64.d
@@ -0,0 +1,41 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2-64
+#source: branch-misc-2.s
+#as: -64 -non_shared
+
+# Test the backward branches to global symbols in current file (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+0040 <x\+0x4>
+ 3c: R_MICROMIPS_PC26_S1 g1\-0x4
+ 3c: R_MIPS_NONE \*ABS\*\-0x4
+ 3c: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+0044 <x\+0x8>
+ 40: R_MICROMIPS_PC26_S1 g2\-0x4
+ 40: R_MIPS_NONE \*ABS\*\-0x4
+ 40: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+0048 <x\+0xc>
+ 44: R_MICROMIPS_PC26_S1 g3\-0x4
+ 44: R_MIPS_NONE \*ABS\*\-0x4
+ 44: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+004c <x\+0x10>
+ 48: R_MICROMIPS_PC26_S1 g4\-0x4
+ 48: R_MIPS_NONE \*ABS\*\-0x4
+ 48: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+0050 <x\+0x14>
+ 4c: R_MICROMIPS_PC26_S1 g5\-0x4
+ 4c: R_MIPS_NONE \*ABS\*\-0x4
+ 4c: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+0054 <x\+0x18>
+ 50: R_MICROMIPS_PC26_S1 g6\-0x4
+ 50: R_MIPS_NONE \*ABS\*\-0x4
+ 50: R_MIPS_NONE \*ABS\*\-0x4
+ \.\.\.
+ \.\.\.
+ \.\.\.
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-2.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-2.d
new file mode 100644
index 00000000000..3c7edd5ac9f
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-2.d
@@ -0,0 +1,29 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2
+#source: branch-misc-2.s
+#as: -32 -non_shared
+
+# Test the backward branches to global symbols in current file (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 3c: R_MICROMIPS_PC26_S1 g1
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 40: R_MICROMIPS_PC26_S1 g2
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 44: R_MICROMIPS_PC26_S1 g3
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 48: R_MICROMIPS_PC26_S1 g4
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 4c: R_MICROMIPS_PC26_S1 g5
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 50: R_MICROMIPS_PC26_S1 g6
+ \.\.\.
+ \.\.\.
+ \.\.\.
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-2pic-64.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-2pic-64.d
new file mode 100644
index 00000000000..a9636f5a465
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-2pic-64.d
@@ -0,0 +1,41 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2pic-64
+#source: branch-misc-2.s
+#as: -64 -call_shared
+
+# Test the backward branches to globalc symbols in current file (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+0040 <x\+0x4>
+ 3c: R_MICROMIPS_PC26_S1 g1\-0x4
+ 3c: R_MIPS_NONE \*ABS\*\-0x4
+ 3c: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+0044 <x\+0x8>
+ 40: R_MICROMIPS_PC26_S1 g2\-0x4
+ 40: R_MIPS_NONE \*ABS\*\-0x4
+ 40: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+0048 <x\+0xc>
+ 44: R_MICROMIPS_PC26_S1 g3\-0x4
+ 44: R_MIPS_NONE \*ABS\*\-0x4
+ 44: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+004c <x\+0x10>
+ 48: R_MICROMIPS_PC26_S1 g4\-0x4
+ 48: R_MIPS_NONE \*ABS\*\-0x4
+ 48: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+0050 <x\+0x14>
+ 4c: R_MICROMIPS_PC26_S1 g5\-0x4
+ 4c: R_MIPS_NONE \*ABS\*\-0x4
+ 4c: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> b400 0000 balc 0+0054 <x\+0x18>
+ 50: R_MICROMIPS_PC26_S1 g6\-0x4
+ 50: R_MIPS_NONE \*ABS\*\-0x4
+ 50: R_MIPS_NONE \*ABS\*\-0x4
+ \.\.\.
+ \.\.\.
+ \.\.\.
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-2pic.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-2pic.d
new file mode 100644
index 00000000000..92de5d67ba4
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-2pic.d
@@ -0,0 +1,29 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-2pic
+#source: branch-misc-2.s
+#as: -32 -call_shared
+
+# Test the backward branches to global symbols in current file (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+ \.\.\.
+ \.\.\.
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 3c: R_MICROMIPS_PC26_S1 g1
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 40: R_MICROMIPS_PC26_S1 g2
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 44: R_MICROMIPS_PC26_S1 g3
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 48: R_MICROMIPS_PC26_S1 g4
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 4c: R_MICROMIPS_PC26_S1 g5
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 50: R_MICROMIPS_PC26_S1 g6
+ \.\.\.
+ \.\.\.
+ \.\.\.
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-4-64.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-4-64.d
new file mode 100644
index 00000000000..92f4ac08c50
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-4-64.d
@@ -0,0 +1,31 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-4-64
+#as: -64
+#source: branch-misc-4.s
+
+# Verify PC-relative relocations do not overflow (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+[0-9a-f]+ <[^>]*> 9400 0000 bc [0-9a-f]+ <\.Lfoo>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 bar-0x4
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4
+[0-9a-f]+ <[^>]*> 9400 0000 bc [0-9a-f]+ <\.Lfoo\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 \.Lbar-0x4
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4
+ \.\.\.
+
+Disassembly of section \.init:
+[0-9a-f]+ <[^>]*> 9400 0000 bc [0-9a-f]+ <\.Lbar>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 foo\-0x4
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\-0x4
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> 9400 0000 bc [0-9a-f]+ <\.Lbar\+0x[0-9a-f]+>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 \.Lfoo-0x4
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-4.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-4.d
new file mode 100644
index 00000000000..2e5325ef78e
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-4.d
@@ -0,0 +1,23 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-4
+#as: -32
+#source: branch-misc-4.s
+
+# Verify PC-relative relocations do not overflow (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+ \.\.\.
+([0-9a-f]+) <[^>]*> 93fe 0000 slti ra,s8,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 bar
+([0-9a-f]+) <[^>]*> 93fe 0000 slti ra,s8,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 \.Lbar
+ \.\.\.
+
+Disassembly of section \.init:
+([0-9a-f]+) <[^>]*> 93fe 0000 slti ra,s8,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 foo
+([0-9a-f]+) <[^>]*> 93fe 0000 slti ra,s8,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 \.Lfoo
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-5-64.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-5-64.d
new file mode 100644
index 00000000000..fffdba1f9c8
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-5-64.d
@@ -0,0 +1,24 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-5-64
+#source: branch-misc-5.s
+#as: -64 -non_shared
+
+# Test branches to undefined symbols and a defined local symbol
+# in another section (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 9400 0000 bc 0+0004 <g6\+0x4>
+ 0: R_MICROMIPS_PC26_S1 x1\-0x4
+ 0: R_MIPS_NONE \*ABS\*\-0x4
+ 0: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> 9400 0000 bc 0+0008 <g6\+0x8>
+ 4: R_MICROMIPS_PC26_S1 x2\-0x4
+ 4: R_MIPS_NONE \*ABS\*\-0x4
+ 4: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> 9400 0000 bc 0+000c <g6\+0xc>
+ 8: R_MICROMIPS_PC26_S1 \.Ldata\-0x4
+ 8: R_MIPS_NONE \*ABS\*\-0x4
+ 8: R_MIPS_NONE \*ABS\*\-0x4
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-5.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-5.d
new file mode 100644
index 00000000000..5c84fc1db24
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-5.d
@@ -0,0 +1,18 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-5
+#source: branch-misc-5.s
+#as: -32 -non_shared
+
+# Test branches to undefined symbols and a defined local symbol
+# in another section (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 93fe 0000 slti ra,s8,0
+ 0: R_MICROMIPS_PC26_S1 x1
+[0-9a-f]+ <[^>]*> 93fe 0000 slti ra,s8,0
+ 4: R_MICROMIPS_PC26_S1 x2
+[0-9a-f]+ <[^>]*> 93fe 0000 slti ra,s8,0
+ 8: R_MICROMIPS_PC26_S1 \.Ldata
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-5pic-64.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-5pic-64.d
new file mode 100644
index 00000000000..8e1a449de5d
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-5pic-64.d
@@ -0,0 +1,24 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-5pic-64
+#source: branch-misc-5.s
+#as: -64 -call_shared
+
+# Test branches to undefined symbols and a defined local symbol
+# in another section (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 9400 0000 bc 0+0004 <g6\+0x4>
+ 0: R_MICROMIPS_PC26_S1 x1\-0x4
+ 0: R_MIPS_NONE \*ABS\*\-0x4
+ 0: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> 9400 0000 bc 0+0008 <g6\+0x8>
+ 4: R_MICROMIPS_PC26_S1 x2\-0x4
+ 4: R_MIPS_NONE \*ABS\*\-0x4
+ 4: R_MIPS_NONE \*ABS\*\-0x4
+[0-9a-f]+ <[^>]*> 9400 0000 bc 0+000c <g6\+0xc>
+ 8: R_MICROMIPS_PC26_S1 \.Ldata\-0x4
+ 8: R_MIPS_NONE \*ABS\*\-0x4
+ 8: R_MIPS_NONE \*ABS\*\-0x4
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-misc-5pic.d b/gas/testsuite/gas/mips/micromipsr6@branch-misc-5pic.d
new file mode 100644
index 00000000000..0b5005b27c6
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-misc-5pic.d
@@ -0,0 +1,18 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS branch-misc-5pic
+#source: branch-misc-5.s
+#as: -32 -call_shared
+
+# Test branches to undefined symbols and a defined local symbol
+# in another section (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 93fe 0000 slti ra,s8,0
+ 0: R_MICROMIPS_PC26_S1 x1
+[0-9a-f]+ <[^>]*> 93fe 0000 slti ra,s8,0
+ 4: R_MICROMIPS_PC26_S1 x2
+[0-9a-f]+ <[^>]*> 93fe 0000 slti ra,s8,0
+ 8: R_MICROMIPS_PC26_S1 \.Ldata
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-swap-3.d b/gas/testsuite/gas/mips/micromipsr6@branch-swap-3.d
new file mode 100644
index 00000000000..866ba9ddff6
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-swap-3.d
@@ -0,0 +1,38 @@
+#objdump: -dr -M reg-names=numeric
+#as: -32 -O2 -aln=branch-swap-lst.lst
+#name: MIPS branch swapping with assembler listing
+#source: branch-swap-3.s
+
+# Check delay slot filling with a listing file works (microMIPS)
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <test>:
+[ 0-9a-f]+: 0e02 move \$16,\$2
+[ 0-9a-f]+: b3fe 0000 sltiu \$31,\$30,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 func
+[ 0-9a-f]+: 6c10 addiu \$16,\$17,1
+[ 0-9a-f]+: b3fe 0000 sltiu \$31,\$30,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 func
+[ 0-9a-f]+: 3211 0001 addiu \$16,\$17,1
+[ 0-9a-f]+: b3fe 0000 sltiu \$31,\$30,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 func
+[ 0-9a-f]+: 3211 3fff addiu \$16,\$17,16383
+[ 0-9a-f]+: b3fe 0000 sltiu \$31,\$30,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 func
+[ 0-9a-f]+: 3211 3fff addiu \$16,\$17,16383
+[ 0-9a-f]+: b3fe 0000 sltiu \$31,\$30,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 func
+[ 0-9a-f]+: 0e02 move \$16,\$2
+[ 0-9a-f]+: 47e3 jrc \$31
+[ 0-9a-f]+: 6c10 addiu \$16,\$17,1
+[ 0-9a-f]+: 47e3 jrc \$31
+[ 0-9a-f]+: 3211 0001 addiu \$16,\$17,1
+[ 0-9a-f]+: 47e3 jrc \$31
+[ 0-9a-f]+: 3211 3fff addiu \$16,\$17,16383
+[ 0-9a-f]+: 47e3 jrc \$31
+[ 0-9a-f]+: 3211 3fff addiu \$16,\$17,16383
+[ 0-9a-f]+: 47e3 jrc \$31
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@branch-swap-4.d b/gas/testsuite/gas/mips/micromipsr6@branch-swap-4.d
new file mode 100644
index 00000000000..1ae04feab8a
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@branch-swap-4.d
@@ -0,0 +1,5 @@
+#objdump: -dr -M reg-names=numeric
+#as: -32 -O2
+#name: MIPS branch swapping without assembler listing
+#source: branch-swap-3.s
+#dump: micromipsr6@branch-swap-3.d
diff --git a/gas/testsuite/gas/mips/micromipsr6@c0.d b/gas/testsuite/gas/mips/micromipsr6@c0.d
new file mode 100644
index 00000000000..42b52089be4
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@c0.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS C0/COP0 instructions
+#as: -32
+#source: c0.s
+#error_output: micromipsr6@c0.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@c0.l b/gas/testsuite/gas/mips/micromipsr6@c0.l
new file mode 100644
index 00000000000..1e25e96832b
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@c0.l
@@ -0,0 +1,257 @@
+.*: Assembler messages:
+.*:3: Error: unrecognized opcode `c0 0x00'
+.*:4: Error: unrecognized opcode `c0 0x01'
+.*:5: Error: unrecognized opcode `c0 0x02'
+.*:6: Error: unrecognized opcode `c0 0x03'
+.*:7: Error: unrecognized opcode `c0 0x04'
+.*:8: Error: unrecognized opcode `c0 0x05'
+.*:9: Error: unrecognized opcode `c0 0x06'
+.*:10: Error: unrecognized opcode `c0 0x07'
+.*:11: Error: unrecognized opcode `c0 0x08'
+.*:12: Error: unrecognized opcode `c0 0x09'
+.*:13: Error: unrecognized opcode `c0 0x0a'
+.*:14: Error: unrecognized opcode `c0 0x0b'
+.*:15: Error: unrecognized opcode `c0 0x0c'
+.*:16: Error: unrecognized opcode `c0 0x0d'
+.*:17: Error: unrecognized opcode `c0 0x0e'
+.*:18: Error: unrecognized opcode `c0 0x0f'
+.*:19: Error: unrecognized opcode `c0 0x10'
+.*:20: Error: unrecognized opcode `c0 0x11'
+.*:21: Error: unrecognized opcode `c0 0x12'
+.*:22: Error: unrecognized opcode `c0 0x13'
+.*:23: Error: unrecognized opcode `c0 0x14'
+.*:24: Error: unrecognized opcode `c0 0x15'
+.*:25: Error: unrecognized opcode `c0 0x16'
+.*:26: Error: unrecognized opcode `c0 0x17'
+.*:27: Error: unrecognized opcode `c0 0x18'
+.*:28: Error: unrecognized opcode `c0 0x19'
+.*:29: Error: unrecognized opcode `c0 0x1a'
+.*:30: Error: unrecognized opcode `c0 0x1b'
+.*:31: Error: unrecognized opcode `c0 0x1c'
+.*:32: Error: unrecognized opcode `c0 0x1d'
+.*:33: Error: unrecognized opcode `c0 0x1e'
+.*:34: Error: unrecognized opcode `c0 0x1f'
+.*:35: Error: unrecognized opcode `c0 0x20'
+.*:36: Error: unrecognized opcode `c0 0x21'
+.*:37: Error: unrecognized opcode `c0 0x22'
+.*:38: Error: unrecognized opcode `c0 0x23'
+.*:39: Error: unrecognized opcode `c0 0x24'
+.*:40: Error: unrecognized opcode `c0 0x25'
+.*:41: Error: unrecognized opcode `c0 0x26'
+.*:42: Error: unrecognized opcode `c0 0x27'
+.*:43: Error: unrecognized opcode `c0 0x28'
+.*:44: Error: unrecognized opcode `c0 0x29'
+.*:45: Error: unrecognized opcode `c0 0x2a'
+.*:46: Error: unrecognized opcode `c0 0x2b'
+.*:47: Error: unrecognized opcode `c0 0x2c'
+.*:48: Error: unrecognized opcode `c0 0x2d'
+.*:49: Error: unrecognized opcode `c0 0x2e'
+.*:50: Error: unrecognized opcode `c0 0x2f'
+.*:51: Error: unrecognized opcode `c0 0x30'
+.*:52: Error: unrecognized opcode `c0 0x31'
+.*:53: Error: unrecognized opcode `c0 0x32'
+.*:54: Error: unrecognized opcode `c0 0x33'
+.*:55: Error: unrecognized opcode `c0 0x34'
+.*:56: Error: unrecognized opcode `c0 0x35'
+.*:57: Error: unrecognized opcode `c0 0x36'
+.*:58: Error: unrecognized opcode `c0 0x37'
+.*:59: Error: unrecognized opcode `c0 0x38'
+.*:60: Error: unrecognized opcode `c0 0x39'
+.*:61: Error: unrecognized opcode `c0 0x3a'
+.*:62: Error: unrecognized opcode `c0 0x3b'
+.*:63: Error: unrecognized opcode `c0 0x3c'
+.*:64: Error: unrecognized opcode `c0 0x3d'
+.*:65: Error: unrecognized opcode `c0 0x3e'
+.*:66: Error: unrecognized opcode `c0 0x3f'
+.*:68: Error: unrecognized opcode `c0 0x1000000'
+.*:69: Error: unrecognized opcode `c0 0x1000001'
+.*:70: Error: unrecognized opcode `c0 0x1000002'
+.*:71: Error: unrecognized opcode `c0 0x1000003'
+.*:72: Error: unrecognized opcode `c0 0x1000004'
+.*:73: Error: unrecognized opcode `c0 0x1000005'
+.*:74: Error: unrecognized opcode `c0 0x1000006'
+.*:75: Error: unrecognized opcode `c0 0x1000007'
+.*:76: Error: unrecognized opcode `c0 0x1000008'
+.*:77: Error: unrecognized opcode `c0 0x1000009'
+.*:78: Error: unrecognized opcode `c0 0x100000a'
+.*:79: Error: unrecognized opcode `c0 0x100000b'
+.*:80: Error: unrecognized opcode `c0 0x100000c'
+.*:81: Error: unrecognized opcode `c0 0x100000d'
+.*:82: Error: unrecognized opcode `c0 0x100000e'
+.*:83: Error: unrecognized opcode `c0 0x100000f'
+.*:84: Error: unrecognized opcode `c0 0x1000010'
+.*:85: Error: unrecognized opcode `c0 0x1000011'
+.*:86: Error: unrecognized opcode `c0 0x1000012'
+.*:87: Error: unrecognized opcode `c0 0x1000013'
+.*:88: Error: unrecognized opcode `c0 0x1000014'
+.*:89: Error: unrecognized opcode `c0 0x1000015'
+.*:90: Error: unrecognized opcode `c0 0x1000016'
+.*:91: Error: unrecognized opcode `c0 0x1000017'
+.*:92: Error: unrecognized opcode `c0 0x1000018'
+.*:93: Error: unrecognized opcode `c0 0x1000019'
+.*:94: Error: unrecognized opcode `c0 0x100001a'
+.*:95: Error: unrecognized opcode `c0 0x100001b'
+.*:96: Error: unrecognized opcode `c0 0x100001c'
+.*:97: Error: unrecognized opcode `c0 0x100001d'
+.*:98: Error: unrecognized opcode `c0 0x100001e'
+.*:99: Error: unrecognized opcode `c0 0x100001f'
+.*:100: Error: unrecognized opcode `c0 0x1000020'
+.*:101: Error: unrecognized opcode `c0 0x1000021'
+.*:102: Error: unrecognized opcode `c0 0x1000022'
+.*:103: Error: unrecognized opcode `c0 0x1000023'
+.*:104: Error: unrecognized opcode `c0 0x1000024'
+.*:105: Error: unrecognized opcode `c0 0x1000025'
+.*:106: Error: unrecognized opcode `c0 0x1000026'
+.*:107: Error: unrecognized opcode `c0 0x1000027'
+.*:108: Error: unrecognized opcode `c0 0x1000028'
+.*:109: Error: unrecognized opcode `c0 0x1000029'
+.*:110: Error: unrecognized opcode `c0 0x100002a'
+.*:111: Error: unrecognized opcode `c0 0x100002b'
+.*:112: Error: unrecognized opcode `c0 0x100002c'
+.*:113: Error: unrecognized opcode `c0 0x100002d'
+.*:114: Error: unrecognized opcode `c0 0x100002e'
+.*:115: Error: unrecognized opcode `c0 0x100002f'
+.*:116: Error: unrecognized opcode `c0 0x1000030'
+.*:117: Error: unrecognized opcode `c0 0x1000031'
+.*:118: Error: unrecognized opcode `c0 0x1000032'
+.*:119: Error: unrecognized opcode `c0 0x1000033'
+.*:120: Error: unrecognized opcode `c0 0x1000034'
+.*:121: Error: unrecognized opcode `c0 0x1000035'
+.*:122: Error: unrecognized opcode `c0 0x1000036'
+.*:123: Error: unrecognized opcode `c0 0x1000037'
+.*:124: Error: unrecognized opcode `c0 0x1000038'
+.*:125: Error: unrecognized opcode `c0 0x1000039'
+.*:126: Error: unrecognized opcode `c0 0x100003a'
+.*:127: Error: unrecognized opcode `c0 0x100003b'
+.*:128: Error: unrecognized opcode `c0 0x100003c'
+.*:129: Error: unrecognized opcode `c0 0x100003d'
+.*:130: Error: unrecognized opcode `c0 0x100003e'
+.*:131: Error: unrecognized opcode `c0 0x100003f'
+.*:133: Error: unrecognized opcode `cop0 0x00'
+.*:134: Error: unrecognized opcode `cop0 0x01'
+.*:135: Error: unrecognized opcode `cop0 0x02'
+.*:136: Error: unrecognized opcode `cop0 0x03'
+.*:137: Error: unrecognized opcode `cop0 0x04'
+.*:138: Error: unrecognized opcode `cop0 0x05'
+.*:139: Error: unrecognized opcode `cop0 0x06'
+.*:140: Error: unrecognized opcode `cop0 0x07'
+.*:141: Error: unrecognized opcode `cop0 0x08'
+.*:142: Error: unrecognized opcode `cop0 0x09'
+.*:143: Error: unrecognized opcode `cop0 0x0a'
+.*:144: Error: unrecognized opcode `cop0 0x0b'
+.*:145: Error: unrecognized opcode `cop0 0x0c'
+.*:146: Error: unrecognized opcode `cop0 0x0d'
+.*:147: Error: unrecognized opcode `cop0 0x0e'
+.*:148: Error: unrecognized opcode `cop0 0x0f'
+.*:149: Error: unrecognized opcode `cop0 0x10'
+.*:150: Error: unrecognized opcode `cop0 0x11'
+.*:151: Error: unrecognized opcode `cop0 0x12'
+.*:152: Error: unrecognized opcode `cop0 0x13'
+.*:153: Error: unrecognized opcode `cop0 0x14'
+.*:154: Error: unrecognized opcode `cop0 0x15'
+.*:155: Error: unrecognized opcode `cop0 0x16'
+.*:156: Error: unrecognized opcode `cop0 0x17'
+.*:157: Error: unrecognized opcode `cop0 0x18'
+.*:158: Error: unrecognized opcode `cop0 0x19'
+.*:159: Error: unrecognized opcode `cop0 0x1a'
+.*:160: Error: unrecognized opcode `cop0 0x1b'
+.*:161: Error: unrecognized opcode `cop0 0x1c'
+.*:162: Error: unrecognized opcode `cop0 0x1d'
+.*:163: Error: unrecognized opcode `cop0 0x1e'
+.*:164: Error: unrecognized opcode `cop0 0x1f'
+.*:165: Error: unrecognized opcode `cop0 0x20'
+.*:166: Error: unrecognized opcode `cop0 0x21'
+.*:167: Error: unrecognized opcode `cop0 0x22'
+.*:168: Error: unrecognized opcode `cop0 0x23'
+.*:169: Error: unrecognized opcode `cop0 0x24'
+.*:170: Error: unrecognized opcode `cop0 0x25'
+.*:171: Error: unrecognized opcode `cop0 0x26'
+.*:172: Error: unrecognized opcode `cop0 0x27'
+.*:173: Error: unrecognized opcode `cop0 0x28'
+.*:174: Error: unrecognized opcode `cop0 0x29'
+.*:175: Error: unrecognized opcode `cop0 0x2a'
+.*:176: Error: unrecognized opcode `cop0 0x2b'
+.*:177: Error: unrecognized opcode `cop0 0x2c'
+.*:178: Error: unrecognized opcode `cop0 0x2d'
+.*:179: Error: unrecognized opcode `cop0 0x2e'
+.*:180: Error: unrecognized opcode `cop0 0x2f'
+.*:181: Error: unrecognized opcode `cop0 0x30'
+.*:182: Error: unrecognized opcode `cop0 0x31'
+.*:183: Error: unrecognized opcode `cop0 0x32'
+.*:184: Error: unrecognized opcode `cop0 0x33'
+.*:185: Error: unrecognized opcode `cop0 0x34'
+.*:186: Error: unrecognized opcode `cop0 0x35'
+.*:187: Error: unrecognized opcode `cop0 0x36'
+.*:188: Error: unrecognized opcode `cop0 0x37'
+.*:189: Error: unrecognized opcode `cop0 0x38'
+.*:190: Error: unrecognized opcode `cop0 0x39'
+.*:191: Error: unrecognized opcode `cop0 0x3a'
+.*:192: Error: unrecognized opcode `cop0 0x3b'
+.*:193: Error: unrecognized opcode `cop0 0x3c'
+.*:194: Error: unrecognized opcode `cop0 0x3d'
+.*:195: Error: unrecognized opcode `cop0 0x3e'
+.*:196: Error: unrecognized opcode `cop0 0x3f'
+.*:198: Error: unrecognized opcode `cop0 0x1000000'
+.*:199: Error: unrecognized opcode `cop0 0x1000001'
+.*:200: Error: unrecognized opcode `cop0 0x1000002'
+.*:201: Error: unrecognized opcode `cop0 0x1000003'
+.*:202: Error: unrecognized opcode `cop0 0x1000004'
+.*:203: Error: unrecognized opcode `cop0 0x1000005'
+.*:204: Error: unrecognized opcode `cop0 0x1000006'
+.*:205: Error: unrecognized opcode `cop0 0x1000007'
+.*:206: Error: unrecognized opcode `cop0 0x1000008'
+.*:207: Error: unrecognized opcode `cop0 0x1000009'
+.*:208: Error: unrecognized opcode `cop0 0x100000a'
+.*:209: Error: unrecognized opcode `cop0 0x100000b'
+.*:210: Error: unrecognized opcode `cop0 0x100000c'
+.*:211: Error: unrecognized opcode `cop0 0x100000d'
+.*:212: Error: unrecognized opcode `cop0 0x100000e'
+.*:213: Error: unrecognized opcode `cop0 0x100000f'
+.*:214: Error: unrecognized opcode `cop0 0x1000010'
+.*:215: Error: unrecognized opcode `cop0 0x1000011'
+.*:216: Error: unrecognized opcode `cop0 0x1000012'
+.*:217: Error: unrecognized opcode `cop0 0x1000013'
+.*:218: Error: unrecognized opcode `cop0 0x1000014'
+.*:219: Error: unrecognized opcode `cop0 0x1000015'
+.*:220: Error: unrecognized opcode `cop0 0x1000016'
+.*:221: Error: unrecognized opcode `cop0 0x1000017'
+.*:222: Error: unrecognized opcode `cop0 0x1000018'
+.*:223: Error: unrecognized opcode `cop0 0x1000019'
+.*:224: Error: unrecognized opcode `cop0 0x100001a'
+.*:225: Error: unrecognized opcode `cop0 0x100001b'
+.*:226: Error: unrecognized opcode `cop0 0x100001c'
+.*:227: Error: unrecognized opcode `cop0 0x100001d'
+.*:228: Error: unrecognized opcode `cop0 0x100001e'
+.*:229: Error: unrecognized opcode `cop0 0x100001f'
+.*:230: Error: unrecognized opcode `cop0 0x1000020'
+.*:231: Error: unrecognized opcode `cop0 0x1000021'
+.*:232: Error: unrecognized opcode `cop0 0x1000022'
+.*:233: Error: unrecognized opcode `cop0 0x1000023'
+.*:234: Error: unrecognized opcode `cop0 0x1000024'
+.*:235: Error: unrecognized opcode `cop0 0x1000025'
+.*:236: Error: unrecognized opcode `cop0 0x1000026'
+.*:237: Error: unrecognized opcode `cop0 0x1000027'
+.*:238: Error: unrecognized opcode `cop0 0x1000028'
+.*:239: Error: unrecognized opcode `cop0 0x1000029'
+.*:240: Error: unrecognized opcode `cop0 0x100002a'
+.*:241: Error: unrecognized opcode `cop0 0x100002b'
+.*:242: Error: unrecognized opcode `cop0 0x100002c'
+.*:243: Error: unrecognized opcode `cop0 0x100002d'
+.*:244: Error: unrecognized opcode `cop0 0x100002e'
+.*:245: Error: unrecognized opcode `cop0 0x100002f'
+.*:246: Error: unrecognized opcode `cop0 0x1000030'
+.*:247: Error: unrecognized opcode `cop0 0x1000031'
+.*:248: Error: unrecognized opcode `cop0 0x1000032'
+.*:249: Error: unrecognized opcode `cop0 0x1000033'
+.*:250: Error: unrecognized opcode `cop0 0x1000034'
+.*:251: Error: unrecognized opcode `cop0 0x1000035'
+.*:252: Error: unrecognized opcode `cop0 0x1000036'
+.*:253: Error: unrecognized opcode `cop0 0x1000037'
+.*:254: Error: unrecognized opcode `cop0 0x1000038'
+.*:255: Error: unrecognized opcode `cop0 0x1000039'
+.*:256: Error: unrecognized opcode `cop0 0x100003a'
+.*:257: Error: unrecognized opcode `cop0 0x100003b'
+.*:258: Error: unrecognized opcode `cop0 0x100003c'
+.*:259: Error: unrecognized opcode `cop0 0x100003d'
+.*:260: Error: unrecognized opcode `cop0 0x100003e'
+.*:261: Error: unrecognized opcode `cop0 0x100003f'
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@c1.d b/gas/testsuite/gas/mips/micromipsr6@c1.d
new file mode 100644
index 00000000000..55ec0c96e60
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@c1.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS C1/COP1 instructions
+#as: -32
+#source: c1.s
+#error_output: micromipsr6@c1.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@c1.l b/gas/testsuite/gas/mips/micromipsr6@c1.l
new file mode 100644
index 00000000000..020f5b08309
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@c1.l
@@ -0,0 +1,257 @@
+.*: Assembler messages:
+.*:3: Error: unrecognized opcode `c1 0x00'
+.*:4: Error: unrecognized opcode `c1 0x01'
+.*:5: Error: unrecognized opcode `c1 0x02'
+.*:6: Error: unrecognized opcode `c1 0x03'
+.*:7: Error: unrecognized opcode `c1 0x04'
+.*:8: Error: unrecognized opcode `c1 0x05'
+.*:9: Error: unrecognized opcode `c1 0x06'
+.*:10: Error: unrecognized opcode `c1 0x07'
+.*:11: Error: unrecognized opcode `c1 0x08'
+.*:12: Error: unrecognized opcode `c1 0x09'
+.*:13: Error: unrecognized opcode `c1 0x0a'
+.*:14: Error: unrecognized opcode `c1 0x0b'
+.*:15: Error: unrecognized opcode `c1 0x0c'
+.*:16: Error: unrecognized opcode `c1 0x0d'
+.*:17: Error: unrecognized opcode `c1 0x0e'
+.*:18: Error: unrecognized opcode `c1 0x0f'
+.*:19: Error: unrecognized opcode `c1 0x10'
+.*:20: Error: unrecognized opcode `c1 0x11'
+.*:21: Error: unrecognized opcode `c1 0x12'
+.*:22: Error: unrecognized opcode `c1 0x13'
+.*:23: Error: unrecognized opcode `c1 0x14'
+.*:24: Error: unrecognized opcode `c1 0x15'
+.*:25: Error: unrecognized opcode `c1 0x16'
+.*:26: Error: unrecognized opcode `c1 0x17'
+.*:27: Error: unrecognized opcode `c1 0x18'
+.*:28: Error: unrecognized opcode `c1 0x19'
+.*:29: Error: unrecognized opcode `c1 0x1a'
+.*:30: Error: unrecognized opcode `c1 0x1b'
+.*:31: Error: unrecognized opcode `c1 0x1c'
+.*:32: Error: unrecognized opcode `c1 0x1d'
+.*:33: Error: unrecognized opcode `c1 0x1e'
+.*:34: Error: unrecognized opcode `c1 0x1f'
+.*:35: Error: unrecognized opcode `c1 0x20'
+.*:36: Error: unrecognized opcode `c1 0x21'
+.*:37: Error: unrecognized opcode `c1 0x22'
+.*:38: Error: unrecognized opcode `c1 0x23'
+.*:39: Error: unrecognized opcode `c1 0x24'
+.*:40: Error: unrecognized opcode `c1 0x25'
+.*:41: Error: unrecognized opcode `c1 0x26'
+.*:42: Error: unrecognized opcode `c1 0x27'
+.*:43: Error: unrecognized opcode `c1 0x28'
+.*:44: Error: unrecognized opcode `c1 0x29'
+.*:45: Error: unrecognized opcode `c1 0x2a'
+.*:46: Error: unrecognized opcode `c1 0x2b'
+.*:47: Error: unrecognized opcode `c1 0x2c'
+.*:48: Error: unrecognized opcode `c1 0x2d'
+.*:49: Error: unrecognized opcode `c1 0x2e'
+.*:50: Error: unrecognized opcode `c1 0x2f'
+.*:51: Error: unrecognized opcode `c1 0x30'
+.*:52: Error: unrecognized opcode `c1 0x31'
+.*:53: Error: unrecognized opcode `c1 0x32'
+.*:54: Error: unrecognized opcode `c1 0x33'
+.*:55: Error: unrecognized opcode `c1 0x34'
+.*:56: Error: unrecognized opcode `c1 0x35'
+.*:57: Error: unrecognized opcode `c1 0x36'
+.*:58: Error: unrecognized opcode `c1 0x37'
+.*:59: Error: unrecognized opcode `c1 0x38'
+.*:60: Error: unrecognized opcode `c1 0x39'
+.*:61: Error: unrecognized opcode `c1 0x3a'
+.*:62: Error: unrecognized opcode `c1 0x3b'
+.*:63: Error: unrecognized opcode `c1 0x3c'
+.*:64: Error: unrecognized opcode `c1 0x3d'
+.*:65: Error: unrecognized opcode `c1 0x3e'
+.*:66: Error: unrecognized opcode `c1 0x3f'
+.*:68: Error: unrecognized opcode `c1 0x1000000'
+.*:69: Error: unrecognized opcode `c1 0x1000001'
+.*:70: Error: unrecognized opcode `c1 0x1000002'
+.*:71: Error: unrecognized opcode `c1 0x1000003'
+.*:72: Error: unrecognized opcode `c1 0x1000004'
+.*:73: Error: unrecognized opcode `c1 0x1000005'
+.*:74: Error: unrecognized opcode `c1 0x1000006'
+.*:75: Error: unrecognized opcode `c1 0x1000007'
+.*:76: Error: unrecognized opcode `c1 0x1000008'
+.*:77: Error: unrecognized opcode `c1 0x1000009'
+.*:78: Error: unrecognized opcode `c1 0x100000a'
+.*:79: Error: unrecognized opcode `c1 0x100000b'
+.*:80: Error: unrecognized opcode `c1 0x100000c'
+.*:81: Error: unrecognized opcode `c1 0x100000d'
+.*:82: Error: unrecognized opcode `c1 0x100000e'
+.*:83: Error: unrecognized opcode `c1 0x100000f'
+.*:84: Error: unrecognized opcode `c1 0x1000010'
+.*:85: Error: unrecognized opcode `c1 0x1000011'
+.*:86: Error: unrecognized opcode `c1 0x1000012'
+.*:87: Error: unrecognized opcode `c1 0x1000013'
+.*:88: Error: unrecognized opcode `c1 0x1000014'
+.*:89: Error: unrecognized opcode `c1 0x1000015'
+.*:90: Error: unrecognized opcode `c1 0x1000016'
+.*:91: Error: unrecognized opcode `c1 0x1000017'
+.*:92: Error: unrecognized opcode `c1 0x1000018'
+.*:93: Error: unrecognized opcode `c1 0x1000019'
+.*:94: Error: unrecognized opcode `c1 0x100001a'
+.*:95: Error: unrecognized opcode `c1 0x100001b'
+.*:96: Error: unrecognized opcode `c1 0x100001c'
+.*:97: Error: unrecognized opcode `c1 0x100001d'
+.*:98: Error: unrecognized opcode `c1 0x100001e'
+.*:99: Error: unrecognized opcode `c1 0x100001f'
+.*:100: Error: unrecognized opcode `c1 0x1000020'
+.*:101: Error: unrecognized opcode `c1 0x1000021'
+.*:102: Error: unrecognized opcode `c1 0x1000022'
+.*:103: Error: unrecognized opcode `c1 0x1000023'
+.*:104: Error: unrecognized opcode `c1 0x1000024'
+.*:105: Error: unrecognized opcode `c1 0x1000025'
+.*:106: Error: unrecognized opcode `c1 0x1000026'
+.*:107: Error: unrecognized opcode `c1 0x1000027'
+.*:108: Error: unrecognized opcode `c1 0x1000028'
+.*:109: Error: unrecognized opcode `c1 0x1000029'
+.*:110: Error: unrecognized opcode `c1 0x100002a'
+.*:111: Error: unrecognized opcode `c1 0x100002b'
+.*:112: Error: unrecognized opcode `c1 0x100002c'
+.*:113: Error: unrecognized opcode `c1 0x100002d'
+.*:114: Error: unrecognized opcode `c1 0x100002e'
+.*:115: Error: unrecognized opcode `c1 0x100002f'
+.*:116: Error: unrecognized opcode `c1 0x1000030'
+.*:117: Error: unrecognized opcode `c1 0x1000031'
+.*:118: Error: unrecognized opcode `c1 0x1000032'
+.*:119: Error: unrecognized opcode `c1 0x1000033'
+.*:120: Error: unrecognized opcode `c1 0x1000034'
+.*:121: Error: unrecognized opcode `c1 0x1000035'
+.*:122: Error: unrecognized opcode `c1 0x1000036'
+.*:123: Error: unrecognized opcode `c1 0x1000037'
+.*:124: Error: unrecognized opcode `c1 0x1000038'
+.*:125: Error: unrecognized opcode `c1 0x1000039'
+.*:126: Error: unrecognized opcode `c1 0x100003a'
+.*:127: Error: unrecognized opcode `c1 0x100003b'
+.*:128: Error: unrecognized opcode `c1 0x100003c'
+.*:129: Error: unrecognized opcode `c1 0x100003d'
+.*:130: Error: unrecognized opcode `c1 0x100003e'
+.*:131: Error: unrecognized opcode `c1 0x100003f'
+.*:133: Error: unrecognized opcode `cop1 0x00'
+.*:134: Error: unrecognized opcode `cop1 0x01'
+.*:135: Error: unrecognized opcode `cop1 0x02'
+.*:136: Error: unrecognized opcode `cop1 0x03'
+.*:137: Error: unrecognized opcode `cop1 0x04'
+.*:138: Error: unrecognized opcode `cop1 0x05'
+.*:139: Error: unrecognized opcode `cop1 0x06'
+.*:140: Error: unrecognized opcode `cop1 0x07'
+.*:141: Error: unrecognized opcode `cop1 0x08'
+.*:142: Error: unrecognized opcode `cop1 0x09'
+.*:143: Error: unrecognized opcode `cop1 0x0a'
+.*:144: Error: unrecognized opcode `cop1 0x0b'
+.*:145: Error: unrecognized opcode `cop1 0x0c'
+.*:146: Error: unrecognized opcode `cop1 0x0d'
+.*:147: Error: unrecognized opcode `cop1 0x0e'
+.*:148: Error: unrecognized opcode `cop1 0x0f'
+.*:149: Error: unrecognized opcode `cop1 0x10'
+.*:150: Error: unrecognized opcode `cop1 0x11'
+.*:151: Error: unrecognized opcode `cop1 0x12'
+.*:152: Error: unrecognized opcode `cop1 0x13'
+.*:153: Error: unrecognized opcode `cop1 0x14'
+.*:154: Error: unrecognized opcode `cop1 0x15'
+.*:155: Error: unrecognized opcode `cop1 0x16'
+.*:156: Error: unrecognized opcode `cop1 0x17'
+.*:157: Error: unrecognized opcode `cop1 0x18'
+.*:158: Error: unrecognized opcode `cop1 0x19'
+.*:159: Error: unrecognized opcode `cop1 0x1a'
+.*:160: Error: unrecognized opcode `cop1 0x1b'
+.*:161: Error: unrecognized opcode `cop1 0x1c'
+.*:162: Error: unrecognized opcode `cop1 0x1d'
+.*:163: Error: unrecognized opcode `cop1 0x1e'
+.*:164: Error: unrecognized opcode `cop1 0x1f'
+.*:165: Error: unrecognized opcode `cop1 0x20'
+.*:166: Error: unrecognized opcode `cop1 0x21'
+.*:167: Error: unrecognized opcode `cop1 0x22'
+.*:168: Error: unrecognized opcode `cop1 0x23'
+.*:169: Error: unrecognized opcode `cop1 0x24'
+.*:170: Error: unrecognized opcode `cop1 0x25'
+.*:171: Error: unrecognized opcode `cop1 0x26'
+.*:172: Error: unrecognized opcode `cop1 0x27'
+.*:173: Error: unrecognized opcode `cop1 0x28'
+.*:174: Error: unrecognized opcode `cop1 0x29'
+.*:175: Error: unrecognized opcode `cop1 0x2a'
+.*:176: Error: unrecognized opcode `cop1 0x2b'
+.*:177: Error: unrecognized opcode `cop1 0x2c'
+.*:178: Error: unrecognized opcode `cop1 0x2d'
+.*:179: Error: unrecognized opcode `cop1 0x2e'
+.*:180: Error: unrecognized opcode `cop1 0x2f'
+.*:181: Error: unrecognized opcode `cop1 0x30'
+.*:182: Error: unrecognized opcode `cop1 0x31'
+.*:183: Error: unrecognized opcode `cop1 0x32'
+.*:184: Error: unrecognized opcode `cop1 0x33'
+.*:185: Error: unrecognized opcode `cop1 0x34'
+.*:186: Error: unrecognized opcode `cop1 0x35'
+.*:187: Error: unrecognized opcode `cop1 0x36'
+.*:188: Error: unrecognized opcode `cop1 0x37'
+.*:189: Error: unrecognized opcode `cop1 0x38'
+.*:190: Error: unrecognized opcode `cop1 0x39'
+.*:191: Error: unrecognized opcode `cop1 0x3a'
+.*:192: Error: unrecognized opcode `cop1 0x3b'
+.*:193: Error: unrecognized opcode `cop1 0x3c'
+.*:194: Error: unrecognized opcode `cop1 0x3d'
+.*:195: Error: unrecognized opcode `cop1 0x3e'
+.*:196: Error: unrecognized opcode `cop1 0x3f'
+.*:198: Error: unrecognized opcode `cop1 0x1000000'
+.*:199: Error: unrecognized opcode `cop1 0x1000001'
+.*:200: Error: unrecognized opcode `cop1 0x1000002'
+.*:201: Error: unrecognized opcode `cop1 0x1000003'
+.*:202: Error: unrecognized opcode `cop1 0x1000004'
+.*:203: Error: unrecognized opcode `cop1 0x1000005'
+.*:204: Error: unrecognized opcode `cop1 0x1000006'
+.*:205: Error: unrecognized opcode `cop1 0x1000007'
+.*:206: Error: unrecognized opcode `cop1 0x1000008'
+.*:207: Error: unrecognized opcode `cop1 0x1000009'
+.*:208: Error: unrecognized opcode `cop1 0x100000a'
+.*:209: Error: unrecognized opcode `cop1 0x100000b'
+.*:210: Error: unrecognized opcode `cop1 0x100000c'
+.*:211: Error: unrecognized opcode `cop1 0x100000d'
+.*:212: Error: unrecognized opcode `cop1 0x100000e'
+.*:213: Error: unrecognized opcode `cop1 0x100000f'
+.*:214: Error: unrecognized opcode `cop1 0x1000010'
+.*:215: Error: unrecognized opcode `cop1 0x1000011'
+.*:216: Error: unrecognized opcode `cop1 0x1000012'
+.*:217: Error: unrecognized opcode `cop1 0x1000013'
+.*:218: Error: unrecognized opcode `cop1 0x1000014'
+.*:219: Error: unrecognized opcode `cop1 0x1000015'
+.*:220: Error: unrecognized opcode `cop1 0x1000016'
+.*:221: Error: unrecognized opcode `cop1 0x1000017'
+.*:222: Error: unrecognized opcode `cop1 0x1000018'
+.*:223: Error: unrecognized opcode `cop1 0x1000019'
+.*:224: Error: unrecognized opcode `cop1 0x100001a'
+.*:225: Error: unrecognized opcode `cop1 0x100001b'
+.*:226: Error: unrecognized opcode `cop1 0x100001c'
+.*:227: Error: unrecognized opcode `cop1 0x100001d'
+.*:228: Error: unrecognized opcode `cop1 0x100001e'
+.*:229: Error: unrecognized opcode `cop1 0x100001f'
+.*:230: Error: unrecognized opcode `cop1 0x1000020'
+.*:231: Error: unrecognized opcode `cop1 0x1000021'
+.*:232: Error: unrecognized opcode `cop1 0x1000022'
+.*:233: Error: unrecognized opcode `cop1 0x1000023'
+.*:234: Error: unrecognized opcode `cop1 0x1000024'
+.*:235: Error: unrecognized opcode `cop1 0x1000025'
+.*:236: Error: unrecognized opcode `cop1 0x1000026'
+.*:237: Error: unrecognized opcode `cop1 0x1000027'
+.*:238: Error: unrecognized opcode `cop1 0x1000028'
+.*:239: Error: unrecognized opcode `cop1 0x1000029'
+.*:240: Error: unrecognized opcode `cop1 0x100002a'
+.*:241: Error: unrecognized opcode `cop1 0x100002b'
+.*:242: Error: unrecognized opcode `cop1 0x100002c'
+.*:243: Error: unrecognized opcode `cop1 0x100002d'
+.*:244: Error: unrecognized opcode `cop1 0x100002e'
+.*:245: Error: unrecognized opcode `cop1 0x100002f'
+.*:246: Error: unrecognized opcode `cop1 0x1000030'
+.*:247: Error: unrecognized opcode `cop1 0x1000031'
+.*:248: Error: unrecognized opcode `cop1 0x1000032'
+.*:249: Error: unrecognized opcode `cop1 0x1000033'
+.*:250: Error: unrecognized opcode `cop1 0x1000034'
+.*:251: Error: unrecognized opcode `cop1 0x1000035'
+.*:252: Error: unrecognized opcode `cop1 0x1000036'
+.*:253: Error: unrecognized opcode `cop1 0x1000037'
+.*:254: Error: unrecognized opcode `cop1 0x1000038'
+.*:255: Error: unrecognized opcode `cop1 0x1000039'
+.*:256: Error: unrecognized opcode `cop1 0x100003a'
+.*:257: Error: unrecognized opcode `cop1 0x100003b'
+.*:258: Error: unrecognized opcode `cop1 0x100003c'
+.*:259: Error: unrecognized opcode `cop1 0x100003d'
+.*:260: Error: unrecognized opcode `cop1 0x100003e'
+.*:261: Error: unrecognized opcode `cop1 0x100003f'
diff --git a/gas/testsuite/gas/mips/micromipsr6@c2.d b/gas/testsuite/gas/mips/micromipsr6@c2.d
new file mode 100644
index 00000000000..024a28df8e1
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@c2.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS C2/COP2 instructions
+#as: -32
+#source: c2.s
+#error_output: micromipsr6@c2.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@c2.l b/gas/testsuite/gas/mips/micromipsr6@c2.l
new file mode 100644
index 00000000000..3f9341b6ad2
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@c2.l
@@ -0,0 +1,193 @@
+.*: Assembler messages:
+.*:3: Error: unrecognized opcode `c2 0x00'
+.*:4: Error: unrecognized opcode `c2 0x01'
+.*:5: Error: unrecognized opcode `c2 0x02'
+.*:6: Error: unrecognized opcode `c2 0x03'
+.*:7: Error: unrecognized opcode `c2 0x04'
+.*:8: Error: unrecognized opcode `c2 0x05'
+.*:9: Error: unrecognized opcode `c2 0x06'
+.*:10: Error: unrecognized opcode `c2 0x07'
+.*:11: Error: unrecognized opcode `c2 0x08'
+.*:12: Error: unrecognized opcode `c2 0x09'
+.*:13: Error: unrecognized opcode `c2 0x0a'
+.*:14: Error: unrecognized opcode `c2 0x0b'
+.*:15: Error: unrecognized opcode `c2 0x0c'
+.*:16: Error: unrecognized opcode `c2 0x0d'
+.*:17: Error: unrecognized opcode `c2 0x0e'
+.*:18: Error: unrecognized opcode `c2 0x0f'
+.*:19: Error: unrecognized opcode `c2 0x10'
+.*:20: Error: unrecognized opcode `c2 0x11'
+.*:21: Error: unrecognized opcode `c2 0x12'
+.*:22: Error: unrecognized opcode `c2 0x13'
+.*:23: Error: unrecognized opcode `c2 0x14'
+.*:24: Error: unrecognized opcode `c2 0x15'
+.*:25: Error: unrecognized opcode `c2 0x16'
+.*:26: Error: unrecognized opcode `c2 0x17'
+.*:27: Error: unrecognized opcode `c2 0x18'
+.*:28: Error: unrecognized opcode `c2 0x19'
+.*:29: Error: unrecognized opcode `c2 0x1a'
+.*:30: Error: unrecognized opcode `c2 0x1b'
+.*:31: Error: unrecognized opcode `c2 0x1c'
+.*:32: Error: unrecognized opcode `c2 0x1d'
+.*:33: Error: unrecognized opcode `c2 0x1e'
+.*:34: Error: unrecognized opcode `c2 0x1f'
+.*:35: Error: unrecognized opcode `c2 0x20'
+.*:36: Error: unrecognized opcode `c2 0x21'
+.*:37: Error: unrecognized opcode `c2 0x22'
+.*:38: Error: unrecognized opcode `c2 0x23'
+.*:39: Error: unrecognized opcode `c2 0x24'
+.*:40: Error: unrecognized opcode `c2 0x25'
+.*:41: Error: unrecognized opcode `c2 0x26'
+.*:42: Error: unrecognized opcode `c2 0x27'
+.*:43: Error: unrecognized opcode `c2 0x28'
+.*:44: Error: unrecognized opcode `c2 0x29'
+.*:45: Error: unrecognized opcode `c2 0x2a'
+.*:46: Error: unrecognized opcode `c2 0x2b'
+.*:47: Error: unrecognized opcode `c2 0x2c'
+.*:48: Error: unrecognized opcode `c2 0x2d'
+.*:49: Error: unrecognized opcode `c2 0x2e'
+.*:50: Error: unrecognized opcode `c2 0x2f'
+.*:51: Error: unrecognized opcode `c2 0x30'
+.*:52: Error: unrecognized opcode `c2 0x31'
+.*:53: Error: unrecognized opcode `c2 0x32'
+.*:54: Error: unrecognized opcode `c2 0x33'
+.*:55: Error: unrecognized opcode `c2 0x34'
+.*:56: Error: unrecognized opcode `c2 0x35'
+.*:57: Error: unrecognized opcode `c2 0x36'
+.*:58: Error: unrecognized opcode `c2 0x37'
+.*:59: Error: unrecognized opcode `c2 0x38'
+.*:60: Error: unrecognized opcode `c2 0x39'
+.*:61: Error: unrecognized opcode `c2 0x3a'
+.*:62: Error: unrecognized opcode `c2 0x3b'
+.*:63: Error: unrecognized opcode `c2 0x3c'
+.*:64: Error: unrecognized opcode `c2 0x3d'
+.*:65: Error: unrecognized opcode `c2 0x3e'
+.*:66: Error: unrecognized opcode `c2 0x3f'
+.*:68: Error: unrecognized opcode `c2 0x1000000'
+.*:69: Error: unrecognized opcode `c2 0x1000001'
+.*:70: Error: unrecognized opcode `c2 0x1000002'
+.*:71: Error: unrecognized opcode `c2 0x1000003'
+.*:72: Error: unrecognized opcode `c2 0x1000004'
+.*:73: Error: unrecognized opcode `c2 0x1000005'
+.*:74: Error: unrecognized opcode `c2 0x1000006'
+.*:75: Error: unrecognized opcode `c2 0x1000007'
+.*:76: Error: unrecognized opcode `c2 0x1000008'
+.*:77: Error: unrecognized opcode `c2 0x1000009'
+.*:78: Error: unrecognized opcode `c2 0x100000a'
+.*:79: Error: unrecognized opcode `c2 0x100000b'
+.*:80: Error: unrecognized opcode `c2 0x100000c'
+.*:81: Error: unrecognized opcode `c2 0x100000d'
+.*:82: Error: unrecognized opcode `c2 0x100000e'
+.*:83: Error: unrecognized opcode `c2 0x100000f'
+.*:84: Error: unrecognized opcode `c2 0x1000010'
+.*:85: Error: unrecognized opcode `c2 0x1000011'
+.*:86: Error: unrecognized opcode `c2 0x1000012'
+.*:87: Error: unrecognized opcode `c2 0x1000013'
+.*:88: Error: unrecognized opcode `c2 0x1000014'
+.*:89: Error: unrecognized opcode `c2 0x1000015'
+.*:90: Error: unrecognized opcode `c2 0x1000016'
+.*:91: Error: unrecognized opcode `c2 0x1000017'
+.*:92: Error: unrecognized opcode `c2 0x1000018'
+.*:93: Error: unrecognized opcode `c2 0x1000019'
+.*:94: Error: unrecognized opcode `c2 0x100001a'
+.*:95: Error: unrecognized opcode `c2 0x100001b'
+.*:96: Error: unrecognized opcode `c2 0x100001c'
+.*:97: Error: unrecognized opcode `c2 0x100001d'
+.*:98: Error: unrecognized opcode `c2 0x100001e'
+.*:99: Error: unrecognized opcode `c2 0x100001f'
+.*:100: Error: unrecognized opcode `c2 0x1000020'
+.*:101: Error: unrecognized opcode `c2 0x1000021'
+.*:102: Error: unrecognized opcode `c2 0x1000022'
+.*:103: Error: unrecognized opcode `c2 0x1000023'
+.*:104: Error: unrecognized opcode `c2 0x1000024'
+.*:105: Error: unrecognized opcode `c2 0x1000025'
+.*:106: Error: unrecognized opcode `c2 0x1000026'
+.*:107: Error: unrecognized opcode `c2 0x1000027'
+.*:108: Error: unrecognized opcode `c2 0x1000028'
+.*:109: Error: unrecognized opcode `c2 0x1000029'
+.*:110: Error: unrecognized opcode `c2 0x100002a'
+.*:111: Error: unrecognized opcode `c2 0x100002b'
+.*:112: Error: unrecognized opcode `c2 0x100002c'
+.*:113: Error: unrecognized opcode `c2 0x100002d'
+.*:114: Error: unrecognized opcode `c2 0x100002e'
+.*:115: Error: unrecognized opcode `c2 0x100002f'
+.*:116: Error: unrecognized opcode `c2 0x1000030'
+.*:117: Error: unrecognized opcode `c2 0x1000031'
+.*:118: Error: unrecognized opcode `c2 0x1000032'
+.*:119: Error: unrecognized opcode `c2 0x1000033'
+.*:120: Error: unrecognized opcode `c2 0x1000034'
+.*:121: Error: unrecognized opcode `c2 0x1000035'
+.*:122: Error: unrecognized opcode `c2 0x1000036'
+.*:123: Error: unrecognized opcode `c2 0x1000037'
+.*:124: Error: unrecognized opcode `c2 0x1000038'
+.*:125: Error: unrecognized opcode `c2 0x1000039'
+.*:126: Error: unrecognized opcode `c2 0x100003a'
+.*:127: Error: unrecognized opcode `c2 0x100003b'
+.*:128: Error: unrecognized opcode `c2 0x100003c'
+.*:129: Error: unrecognized opcode `c2 0x100003d'
+.*:130: Error: unrecognized opcode `c2 0x100003e'
+.*:131: Error: unrecognized opcode `c2 0x100003f'
+.*:198: Error: operand 1 out of range `cop2 0x1000000'
+.*:199: Error: operand 1 out of range `cop2 0x1000001'
+.*:200: Error: operand 1 out of range `cop2 0x1000002'
+.*:201: Error: operand 1 out of range `cop2 0x1000003'
+.*:202: Error: operand 1 out of range `cop2 0x1000004'
+.*:203: Error: operand 1 out of range `cop2 0x1000005'
+.*:204: Error: operand 1 out of range `cop2 0x1000006'
+.*:205: Error: operand 1 out of range `cop2 0x1000007'
+.*:206: Error: operand 1 out of range `cop2 0x1000008'
+.*:207: Error: operand 1 out of range `cop2 0x1000009'
+.*:208: Error: operand 1 out of range `cop2 0x100000a'
+.*:209: Error: operand 1 out of range `cop2 0x100000b'
+.*:210: Error: operand 1 out of range `cop2 0x100000c'
+.*:211: Error: operand 1 out of range `cop2 0x100000d'
+.*:212: Error: operand 1 out of range `cop2 0x100000e'
+.*:213: Error: operand 1 out of range `cop2 0x100000f'
+.*:214: Error: operand 1 out of range `cop2 0x1000010'
+.*:215: Error: operand 1 out of range `cop2 0x1000011'
+.*:216: Error: operand 1 out of range `cop2 0x1000012'
+.*:217: Error: operand 1 out of range `cop2 0x1000013'
+.*:218: Error: operand 1 out of range `cop2 0x1000014'
+.*:219: Error: operand 1 out of range `cop2 0x1000015'
+.*:220: Error: operand 1 out of range `cop2 0x1000016'
+.*:221: Error: operand 1 out of range `cop2 0x1000017'
+.*:222: Error: operand 1 out of range `cop2 0x1000018'
+.*:223: Error: operand 1 out of range `cop2 0x1000019'
+.*:224: Error: operand 1 out of range `cop2 0x100001a'
+.*:225: Error: operand 1 out of range `cop2 0x100001b'
+.*:226: Error: operand 1 out of range `cop2 0x100001c'
+.*:227: Error: operand 1 out of range `cop2 0x100001d'
+.*:228: Error: operand 1 out of range `cop2 0x100001e'
+.*:229: Error: operand 1 out of range `cop2 0x100001f'
+.*:230: Error: operand 1 out of range `cop2 0x1000020'
+.*:231: Error: operand 1 out of range `cop2 0x1000021'
+.*:232: Error: operand 1 out of range `cop2 0x1000022'
+.*:233: Error: operand 1 out of range `cop2 0x1000023'
+.*:234: Error: operand 1 out of range `cop2 0x1000024'
+.*:235: Error: operand 1 out of range `cop2 0x1000025'
+.*:236: Error: operand 1 out of range `cop2 0x1000026'
+.*:237: Error: operand 1 out of range `cop2 0x1000027'
+.*:238: Error: operand 1 out of range `cop2 0x1000028'
+.*:239: Error: operand 1 out of range `cop2 0x1000029'
+.*:240: Error: operand 1 out of range `cop2 0x100002a'
+.*:241: Error: operand 1 out of range `cop2 0x100002b'
+.*:242: Error: operand 1 out of range `cop2 0x100002c'
+.*:243: Error: operand 1 out of range `cop2 0x100002d'
+.*:244: Error: operand 1 out of range `cop2 0x100002e'
+.*:245: Error: operand 1 out of range `cop2 0x100002f'
+.*:246: Error: operand 1 out of range `cop2 0x1000030'
+.*:247: Error: operand 1 out of range `cop2 0x1000031'
+.*:248: Error: operand 1 out of range `cop2 0x1000032'
+.*:249: Error: operand 1 out of range `cop2 0x1000033'
+.*:250: Error: operand 1 out of range `cop2 0x1000034'
+.*:251: Error: operand 1 out of range `cop2 0x1000035'
+.*:252: Error: operand 1 out of range `cop2 0x1000036'
+.*:253: Error: operand 1 out of range `cop2 0x1000037'
+.*:254: Error: operand 1 out of range `cop2 0x1000038'
+.*:255: Error: operand 1 out of range `cop2 0x1000039'
+.*:256: Error: operand 1 out of range `cop2 0x100003a'
+.*:257: Error: operand 1 out of range `cop2 0x100003b'
+.*:258: Error: operand 1 out of range `cop2 0x100003c'
+.*:259: Error: operand 1 out of range `cop2 0x100003d'
+.*:260: Error: operand 1 out of range `cop2 0x100003e'
+.*:261: Error: operand 1 out of range `cop2 0x100003f'
diff --git a/gas/testsuite/gas/mips/micromipsr6@c3.d b/gas/testsuite/gas/mips/micromipsr6@c3.d
new file mode 100644
index 00000000000..b0faa402f79
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@c3.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS C3/COP3 instructions
+#as: -32
+#source: c3.s
+#error_output: micromipsr6@c3.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@c3.l b/gas/testsuite/gas/mips/micromipsr6@c3.l
new file mode 100644
index 00000000000..67a8913f234
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@c3.l
@@ -0,0 +1,257 @@
+.*: Assembler messages:
+.*:3: Error: unrecognized opcode `c3 0x00'
+.*:4: Error: unrecognized opcode `c3 0x01'
+.*:5: Error: unrecognized opcode `c3 0x02'
+.*:6: Error: unrecognized opcode `c3 0x03'
+.*:7: Error: unrecognized opcode `c3 0x04'
+.*:8: Error: unrecognized opcode `c3 0x05'
+.*:9: Error: unrecognized opcode `c3 0x06'
+.*:10: Error: unrecognized opcode `c3 0x07'
+.*:11: Error: unrecognized opcode `c3 0x08'
+.*:12: Error: unrecognized opcode `c3 0x09'
+.*:13: Error: unrecognized opcode `c3 0x0a'
+.*:14: Error: unrecognized opcode `c3 0x0b'
+.*:15: Error: unrecognized opcode `c3 0x0c'
+.*:16: Error: unrecognized opcode `c3 0x0d'
+.*:17: Error: unrecognized opcode `c3 0x0e'
+.*:18: Error: unrecognized opcode `c3 0x0f'
+.*:19: Error: unrecognized opcode `c3 0x10'
+.*:20: Error: unrecognized opcode `c3 0x11'
+.*:21: Error: unrecognized opcode `c3 0x12'
+.*:22: Error: unrecognized opcode `c3 0x13'
+.*:23: Error: unrecognized opcode `c3 0x14'
+.*:24: Error: unrecognized opcode `c3 0x15'
+.*:25: Error: unrecognized opcode `c3 0x16'
+.*:26: Error: unrecognized opcode `c3 0x17'
+.*:27: Error: unrecognized opcode `c3 0x18'
+.*:28: Error: unrecognized opcode `c3 0x19'
+.*:29: Error: unrecognized opcode `c3 0x1a'
+.*:30: Error: unrecognized opcode `c3 0x1b'
+.*:31: Error: unrecognized opcode `c3 0x1c'
+.*:32: Error: unrecognized opcode `c3 0x1d'
+.*:33: Error: unrecognized opcode `c3 0x1e'
+.*:34: Error: unrecognized opcode `c3 0x1f'
+.*:35: Error: unrecognized opcode `c3 0x20'
+.*:36: Error: unrecognized opcode `c3 0x21'
+.*:37: Error: unrecognized opcode `c3 0x22'
+.*:38: Error: unrecognized opcode `c3 0x23'
+.*:39: Error: unrecognized opcode `c3 0x24'
+.*:40: Error: unrecognized opcode `c3 0x25'
+.*:41: Error: unrecognized opcode `c3 0x26'
+.*:42: Error: unrecognized opcode `c3 0x27'
+.*:43: Error: unrecognized opcode `c3 0x28'
+.*:44: Error: unrecognized opcode `c3 0x29'
+.*:45: Error: unrecognized opcode `c3 0x2a'
+.*:46: Error: unrecognized opcode `c3 0x2b'
+.*:47: Error: unrecognized opcode `c3 0x2c'
+.*:48: Error: unrecognized opcode `c3 0x2d'
+.*:49: Error: unrecognized opcode `c3 0x2e'
+.*:50: Error: unrecognized opcode `c3 0x2f'
+.*:51: Error: unrecognized opcode `c3 0x30'
+.*:52: Error: unrecognized opcode `c3 0x31'
+.*:53: Error: unrecognized opcode `c3 0x32'
+.*:54: Error: unrecognized opcode `c3 0x33'
+.*:55: Error: unrecognized opcode `c3 0x34'
+.*:56: Error: unrecognized opcode `c3 0x35'
+.*:57: Error: unrecognized opcode `c3 0x36'
+.*:58: Error: unrecognized opcode `c3 0x37'
+.*:59: Error: unrecognized opcode `c3 0x38'
+.*:60: Error: unrecognized opcode `c3 0x39'
+.*:61: Error: unrecognized opcode `c3 0x3a'
+.*:62: Error: unrecognized opcode `c3 0x3b'
+.*:63: Error: unrecognized opcode `c3 0x3c'
+.*:64: Error: unrecognized opcode `c3 0x3d'
+.*:65: Error: unrecognized opcode `c3 0x3e'
+.*:66: Error: unrecognized opcode `c3 0x3f'
+.*:68: Error: unrecognized opcode `c3 0x1000000'
+.*:69: Error: unrecognized opcode `c3 0x1000001'
+.*:70: Error: unrecognized opcode `c3 0x1000002'
+.*:71: Error: unrecognized opcode `c3 0x1000003'
+.*:72: Error: unrecognized opcode `c3 0x1000004'
+.*:73: Error: unrecognized opcode `c3 0x1000005'
+.*:74: Error: unrecognized opcode `c3 0x1000006'
+.*:75: Error: unrecognized opcode `c3 0x1000007'
+.*:76: Error: unrecognized opcode `c3 0x1000008'
+.*:77: Error: unrecognized opcode `c3 0x1000009'
+.*:78: Error: unrecognized opcode `c3 0x100000a'
+.*:79: Error: unrecognized opcode `c3 0x100000b'
+.*:80: Error: unrecognized opcode `c3 0x100000c'
+.*:81: Error: unrecognized opcode `c3 0x100000d'
+.*:82: Error: unrecognized opcode `c3 0x100000e'
+.*:83: Error: unrecognized opcode `c3 0x100000f'
+.*:84: Error: unrecognized opcode `c3 0x1000010'
+.*:85: Error: unrecognized opcode `c3 0x1000011'
+.*:86: Error: unrecognized opcode `c3 0x1000012'
+.*:87: Error: unrecognized opcode `c3 0x1000013'
+.*:88: Error: unrecognized opcode `c3 0x1000014'
+.*:89: Error: unrecognized opcode `c3 0x1000015'
+.*:90: Error: unrecognized opcode `c3 0x1000016'
+.*:91: Error: unrecognized opcode `c3 0x1000017'
+.*:92: Error: unrecognized opcode `c3 0x1000018'
+.*:93: Error: unrecognized opcode `c3 0x1000019'
+.*:94: Error: unrecognized opcode `c3 0x100001a'
+.*:95: Error: unrecognized opcode `c3 0x100001b'
+.*:96: Error: unrecognized opcode `c3 0x100001c'
+.*:97: Error: unrecognized opcode `c3 0x100001d'
+.*:98: Error: unrecognized opcode `c3 0x100001e'
+.*:99: Error: unrecognized opcode `c3 0x100001f'
+.*:100: Error: unrecognized opcode `c3 0x1000020'
+.*:101: Error: unrecognized opcode `c3 0x1000021'
+.*:102: Error: unrecognized opcode `c3 0x1000022'
+.*:103: Error: unrecognized opcode `c3 0x1000023'
+.*:104: Error: unrecognized opcode `c3 0x1000024'
+.*:105: Error: unrecognized opcode `c3 0x1000025'
+.*:106: Error: unrecognized opcode `c3 0x1000026'
+.*:107: Error: unrecognized opcode `c3 0x1000027'
+.*:108: Error: unrecognized opcode `c3 0x1000028'
+.*:109: Error: unrecognized opcode `c3 0x1000029'
+.*:110: Error: unrecognized opcode `c3 0x100002a'
+.*:111: Error: unrecognized opcode `c3 0x100002b'
+.*:112: Error: unrecognized opcode `c3 0x100002c'
+.*:113: Error: unrecognized opcode `c3 0x100002d'
+.*:114: Error: unrecognized opcode `c3 0x100002e'
+.*:115: Error: unrecognized opcode `c3 0x100002f'
+.*:116: Error: unrecognized opcode `c3 0x1000030'
+.*:117: Error: unrecognized opcode `c3 0x1000031'
+.*:118: Error: unrecognized opcode `c3 0x1000032'
+.*:119: Error: unrecognized opcode `c3 0x1000033'
+.*:120: Error: unrecognized opcode `c3 0x1000034'
+.*:121: Error: unrecognized opcode `c3 0x1000035'
+.*:122: Error: unrecognized opcode `c3 0x1000036'
+.*:123: Error: unrecognized opcode `c3 0x1000037'
+.*:124: Error: unrecognized opcode `c3 0x1000038'
+.*:125: Error: unrecognized opcode `c3 0x1000039'
+.*:126: Error: unrecognized opcode `c3 0x100003a'
+.*:127: Error: unrecognized opcode `c3 0x100003b'
+.*:128: Error: unrecognized opcode `c3 0x100003c'
+.*:129: Error: unrecognized opcode `c3 0x100003d'
+.*:130: Error: unrecognized opcode `c3 0x100003e'
+.*:131: Error: unrecognized opcode `c3 0x100003f'
+.*:133: Error: unrecognized opcode `cop3 0x00'
+.*:134: Error: unrecognized opcode `cop3 0x01'
+.*:135: Error: unrecognized opcode `cop3 0x02'
+.*:136: Error: unrecognized opcode `cop3 0x03'
+.*:137: Error: unrecognized opcode `cop3 0x04'
+.*:138: Error: unrecognized opcode `cop3 0x05'
+.*:139: Error: unrecognized opcode `cop3 0x06'
+.*:140: Error: unrecognized opcode `cop3 0x07'
+.*:141: Error: unrecognized opcode `cop3 0x08'
+.*:142: Error: unrecognized opcode `cop3 0x09'
+.*:143: Error: unrecognized opcode `cop3 0x0a'
+.*:144: Error: unrecognized opcode `cop3 0x0b'
+.*:145: Error: unrecognized opcode `cop3 0x0c'
+.*:146: Error: unrecognized opcode `cop3 0x0d'
+.*:147: Error: unrecognized opcode `cop3 0x0e'
+.*:148: Error: unrecognized opcode `cop3 0x0f'
+.*:149: Error: unrecognized opcode `cop3 0x10'
+.*:150: Error: unrecognized opcode `cop3 0x11'
+.*:151: Error: unrecognized opcode `cop3 0x12'
+.*:152: Error: unrecognized opcode `cop3 0x13'
+.*:153: Error: unrecognized opcode `cop3 0x14'
+.*:154: Error: unrecognized opcode `cop3 0x15'
+.*:155: Error: unrecognized opcode `cop3 0x16'
+.*:156: Error: unrecognized opcode `cop3 0x17'
+.*:157: Error: unrecognized opcode `cop3 0x18'
+.*:158: Error: unrecognized opcode `cop3 0x19'
+.*:159: Error: unrecognized opcode `cop3 0x1a'
+.*:160: Error: unrecognized opcode `cop3 0x1b'
+.*:161: Error: unrecognized opcode `cop3 0x1c'
+.*:162: Error: unrecognized opcode `cop3 0x1d'
+.*:163: Error: unrecognized opcode `cop3 0x1e'
+.*:164: Error: unrecognized opcode `cop3 0x1f'
+.*:165: Error: unrecognized opcode `cop3 0x20'
+.*:166: Error: unrecognized opcode `cop3 0x21'
+.*:167: Error: unrecognized opcode `cop3 0x22'
+.*:168: Error: unrecognized opcode `cop3 0x23'
+.*:169: Error: unrecognized opcode `cop3 0x24'
+.*:170: Error: unrecognized opcode `cop3 0x25'
+.*:171: Error: unrecognized opcode `cop3 0x26'
+.*:172: Error: unrecognized opcode `cop3 0x27'
+.*:173: Error: unrecognized opcode `cop3 0x28'
+.*:174: Error: unrecognized opcode `cop3 0x29'
+.*:175: Error: unrecognized opcode `cop3 0x2a'
+.*:176: Error: unrecognized opcode `cop3 0x2b'
+.*:177: Error: unrecognized opcode `cop3 0x2c'
+.*:178: Error: unrecognized opcode `cop3 0x2d'
+.*:179: Error: unrecognized opcode `cop3 0x2e'
+.*:180: Error: unrecognized opcode `cop3 0x2f'
+.*:181: Error: unrecognized opcode `cop3 0x30'
+.*:182: Error: unrecognized opcode `cop3 0x31'
+.*:183: Error: unrecognized opcode `cop3 0x32'
+.*:184: Error: unrecognized opcode `cop3 0x33'
+.*:185: Error: unrecognized opcode `cop3 0x34'
+.*:186: Error: unrecognized opcode `cop3 0x35'
+.*:187: Error: unrecognized opcode `cop3 0x36'
+.*:188: Error: unrecognized opcode `cop3 0x37'
+.*:189: Error: unrecognized opcode `cop3 0x38'
+.*:190: Error: unrecognized opcode `cop3 0x39'
+.*:191: Error: unrecognized opcode `cop3 0x3a'
+.*:192: Error: unrecognized opcode `cop3 0x3b'
+.*:193: Error: unrecognized opcode `cop3 0x3c'
+.*:194: Error: unrecognized opcode `cop3 0x3d'
+.*:195: Error: unrecognized opcode `cop3 0x3e'
+.*:196: Error: unrecognized opcode `cop3 0x3f'
+.*:198: Error: unrecognized opcode `cop3 0x1000000'
+.*:199: Error: unrecognized opcode `cop3 0x1000001'
+.*:200: Error: unrecognized opcode `cop3 0x1000002'
+.*:201: Error: unrecognized opcode `cop3 0x1000003'
+.*:202: Error: unrecognized opcode `cop3 0x1000004'
+.*:203: Error: unrecognized opcode `cop3 0x1000005'
+.*:204: Error: unrecognized opcode `cop3 0x1000006'
+.*:205: Error: unrecognized opcode `cop3 0x1000007'
+.*:206: Error: unrecognized opcode `cop3 0x1000008'
+.*:207: Error: unrecognized opcode `cop3 0x1000009'
+.*:208: Error: unrecognized opcode `cop3 0x100000a'
+.*:209: Error: unrecognized opcode `cop3 0x100000b'
+.*:210: Error: unrecognized opcode `cop3 0x100000c'
+.*:211: Error: unrecognized opcode `cop3 0x100000d'
+.*:212: Error: unrecognized opcode `cop3 0x100000e'
+.*:213: Error: unrecognized opcode `cop3 0x100000f'
+.*:214: Error: unrecognized opcode `cop3 0x1000010'
+.*:215: Error: unrecognized opcode `cop3 0x1000011'
+.*:216: Error: unrecognized opcode `cop3 0x1000012'
+.*:217: Error: unrecognized opcode `cop3 0x1000013'
+.*:218: Error: unrecognized opcode `cop3 0x1000014'
+.*:219: Error: unrecognized opcode `cop3 0x1000015'
+.*:220: Error: unrecognized opcode `cop3 0x1000016'
+.*:221: Error: unrecognized opcode `cop3 0x1000017'
+.*:222: Error: unrecognized opcode `cop3 0x1000018'
+.*:223: Error: unrecognized opcode `cop3 0x1000019'
+.*:224: Error: unrecognized opcode `cop3 0x100001a'
+.*:225: Error: unrecognized opcode `cop3 0x100001b'
+.*:226: Error: unrecognized opcode `cop3 0x100001c'
+.*:227: Error: unrecognized opcode `cop3 0x100001d'
+.*:228: Error: unrecognized opcode `cop3 0x100001e'
+.*:229: Error: unrecognized opcode `cop3 0x100001f'
+.*:230: Error: unrecognized opcode `cop3 0x1000020'
+.*:231: Error: unrecognized opcode `cop3 0x1000021'
+.*:232: Error: unrecognized opcode `cop3 0x1000022'
+.*:233: Error: unrecognized opcode `cop3 0x1000023'
+.*:234: Error: unrecognized opcode `cop3 0x1000024'
+.*:235: Error: unrecognized opcode `cop3 0x1000025'
+.*:236: Error: unrecognized opcode `cop3 0x1000026'
+.*:237: Error: unrecognized opcode `cop3 0x1000027'
+.*:238: Error: unrecognized opcode `cop3 0x1000028'
+.*:239: Error: unrecognized opcode `cop3 0x1000029'
+.*:240: Error: unrecognized opcode `cop3 0x100002a'
+.*:241: Error: unrecognized opcode `cop3 0x100002b'
+.*:242: Error: unrecognized opcode `cop3 0x100002c'
+.*:243: Error: unrecognized opcode `cop3 0x100002d'
+.*:244: Error: unrecognized opcode `cop3 0x100002e'
+.*:245: Error: unrecognized opcode `cop3 0x100002f'
+.*:246: Error: unrecognized opcode `cop3 0x1000030'
+.*:247: Error: unrecognized opcode `cop3 0x1000031'
+.*:248: Error: unrecognized opcode `cop3 0x1000032'
+.*:249: Error: unrecognized opcode `cop3 0x1000033'
+.*:250: Error: unrecognized opcode `cop3 0x1000034'
+.*:251: Error: unrecognized opcode `cop3 0x1000035'
+.*:252: Error: unrecognized opcode `cop3 0x1000036'
+.*:253: Error: unrecognized opcode `cop3 0x1000037'
+.*:254: Error: unrecognized opcode `cop3 0x1000038'
+.*:255: Error: unrecognized opcode `cop3 0x1000039'
+.*:256: Error: unrecognized opcode `cop3 0x100003a'
+.*:257: Error: unrecognized opcode `cop3 0x100003b'
+.*:258: Error: unrecognized opcode `cop3 0x100003c'
+.*:259: Error: unrecognized opcode `cop3 0x100003d'
+.*:260: Error: unrecognized opcode `cop3 0x100003e'
+.*:261: Error: unrecognized opcode `cop3 0x100003f'
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@cache.d b/gas/testsuite/gas/mips/micromipsr6@cache.d
new file mode 100644
index 00000000000..dd129a476e5
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cache.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS CACHE instruction
+#as: -32 --defsym micromips=1
+#source: cache.s
+
+# Check MIPS CACHE instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 20a2 60ff cache 0x5,255\(v0\)
+[0-9a-f]+ <[^>]*> 20a3 6100 cache 0x5,-256\(v1\)
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp0b.d b/gas/testsuite/gas/mips/micromipsr6@cp0b.d
new file mode 100644
index 00000000000..3916c240714
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp0b.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch instructions
+#as: -32
+#source: cp0b.s
+#error_output: micromipsr6@cp0b.l
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp0b.l b/gas/testsuite/gas/mips/micromipsr6@cp0b.l
new file mode 100644
index 00000000000..214c1ae94e1
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp0b.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:4: Error: unrecognized opcode `bc0f 0f'
+.*:7: Error: unrecognized opcode `bc0t 0f'
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp0bl.d b/gas/testsuite/gas/mips/micromipsr6@cp0bl.d
new file mode 100644
index 00000000000..fbc467e9b14
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp0bl.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch likely instructions
+#as: -32
+#source: cp0bl.s
+#error_output: micromipsr6@cp0bl.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp0bl.l b/gas/testsuite/gas/mips/micromipsr6@cp0bl.l
new file mode 100644
index 00000000000..b56af71070d
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp0bl.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:4: Error: unrecognized opcode `bc0fl 0f'
+.*:7: Error: unrecognized opcode `bc0tl 0f'
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp0c.d b/gas/testsuite/gas/mips/micromipsr6@cp0c.d
new file mode 100644
index 00000000000..8fa22cb7427
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp0c.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+#error_output: micromipsr6@cp0c.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp0c.l b/gas/testsuite/gas/mips/micromipsr6@cp0c.l
new file mode 100644
index 00000000000..1c7750a6fdf
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp0c.l
@@ -0,0 +1,65 @@
+.*: Assembler messages:
+.*:4: Error: unrecognized opcode `ctc0 \$0,\$0'
+.*:5: Error: unrecognized opcode `ctc0 \$0,\$1'
+.*:6: Error: unrecognized opcode `ctc0 \$0,\$2'
+.*:7: Error: unrecognized opcode `ctc0 \$0,\$3'
+.*:8: Error: unrecognized opcode `ctc0 \$0,\$4'
+.*:9: Error: unrecognized opcode `ctc0 \$0,\$5'
+.*:10: Error: unrecognized opcode `ctc0 \$0,\$6'
+.*:11: Error: unrecognized opcode `ctc0 \$0,\$7'
+.*:12: Error: unrecognized opcode `ctc0 \$0,\$8'
+.*:13: Error: unrecognized opcode `ctc0 \$0,\$9'
+.*:14: Error: unrecognized opcode `ctc0 \$0,\$10'
+.*:15: Error: unrecognized opcode `ctc0 \$0,\$11'
+.*:16: Error: unrecognized opcode `ctc0 \$0,\$12'
+.*:17: Error: unrecognized opcode `ctc0 \$0,\$13'
+.*:18: Error: unrecognized opcode `ctc0 \$0,\$14'
+.*:19: Error: unrecognized opcode `ctc0 \$0,\$15'
+.*:20: Error: unrecognized opcode `ctc0 \$0,\$16'
+.*:21: Error: unrecognized opcode `ctc0 \$0,\$17'
+.*:22: Error: unrecognized opcode `ctc0 \$0,\$18'
+.*:23: Error: unrecognized opcode `ctc0 \$0,\$19'
+.*:24: Error: unrecognized opcode `ctc0 \$0,\$20'
+.*:25: Error: unrecognized opcode `ctc0 \$0,\$21'
+.*:26: Error: unrecognized opcode `ctc0 \$0,\$22'
+.*:27: Error: unrecognized opcode `ctc0 \$0,\$23'
+.*:28: Error: unrecognized opcode `ctc0 \$0,\$24'
+.*:29: Error: unrecognized opcode `ctc0 \$0,\$25'
+.*:30: Error: unrecognized opcode `ctc0 \$0,\$26'
+.*:31: Error: unrecognized opcode `ctc0 \$0,\$27'
+.*:32: Error: unrecognized opcode `ctc0 \$0,\$28'
+.*:33: Error: unrecognized opcode `ctc0 \$0,\$29'
+.*:34: Error: unrecognized opcode `ctc0 \$0,\$30'
+.*:35: Error: unrecognized opcode `ctc0 \$0,\$31'
+.*:37: Error: unrecognized opcode `cfc0 \$0,\$0'
+.*:38: Error: unrecognized opcode `cfc0 \$0,\$1'
+.*:39: Error: unrecognized opcode `cfc0 \$0,\$2'
+.*:40: Error: unrecognized opcode `cfc0 \$0,\$3'
+.*:41: Error: unrecognized opcode `cfc0 \$0,\$4'
+.*:42: Error: unrecognized opcode `cfc0 \$0,\$5'
+.*:43: Error: unrecognized opcode `cfc0 \$0,\$6'
+.*:44: Error: unrecognized opcode `cfc0 \$0,\$7'
+.*:45: Error: unrecognized opcode `cfc0 \$0,\$8'
+.*:46: Error: unrecognized opcode `cfc0 \$0,\$9'
+.*:47: Error: unrecognized opcode `cfc0 \$0,\$10'
+.*:48: Error: unrecognized opcode `cfc0 \$0,\$11'
+.*:49: Error: unrecognized opcode `cfc0 \$0,\$12'
+.*:50: Error: unrecognized opcode `cfc0 \$0,\$13'
+.*:51: Error: unrecognized opcode `cfc0 \$0,\$14'
+.*:52: Error: unrecognized opcode `cfc0 \$0,\$15'
+.*:53: Error: unrecognized opcode `cfc0 \$0,\$16'
+.*:54: Error: unrecognized opcode `cfc0 \$0,\$17'
+.*:55: Error: unrecognized opcode `cfc0 \$0,\$18'
+.*:56: Error: unrecognized opcode `cfc0 \$0,\$19'
+.*:57: Error: unrecognized opcode `cfc0 \$0,\$20'
+.*:58: Error: unrecognized opcode `cfc0 \$0,\$21'
+.*:59: Error: unrecognized opcode `cfc0 \$0,\$22'
+.*:60: Error: unrecognized opcode `cfc0 \$0,\$23'
+.*:61: Error: unrecognized opcode `cfc0 \$0,\$24'
+.*:62: Error: unrecognized opcode `cfc0 \$0,\$25'
+.*:63: Error: unrecognized opcode `cfc0 \$0,\$26'
+.*:64: Error: unrecognized opcode `cfc0 \$0,\$27'
+.*:65: Error: unrecognized opcode `cfc0 \$0,\$28'
+.*:66: Error: unrecognized opcode `cfc0 \$0,\$29'
+.*:67: Error: unrecognized opcode `cfc0 \$0,\$30'
+.*:68: Error: unrecognized opcode `cfc0 \$0,\$31'
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp0m.d b/gas/testsuite/gas/mips/micromipsr6@cp0m.d
new file mode 100644
index 00000000000..08c7d732ac4
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp0m.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 memory access instructions
+#as: -32
+#source: cp0m.s
+#error_output: micromipsr6@cp0m.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp0m.l b/gas/testsuite/gas/mips/micromipsr6@cp0m.l
new file mode 100644
index 00000000000..3a39426ce18
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp0m.l
@@ -0,0 +1,65 @@
+.*: Assembler messages:
+.*:4: Error: unrecognized opcode `lwc0 \$0,0\(\$0\)'
+.*:5: Error: unrecognized opcode `lwc0 \$1,0\(\$0\)'
+.*:6: Error: unrecognized opcode `lwc0 \$2,0\(\$0\)'
+.*:7: Error: unrecognized opcode `lwc0 \$3,0\(\$0\)'
+.*:8: Error: unrecognized opcode `lwc0 \$4,0\(\$0\)'
+.*:9: Error: unrecognized opcode `lwc0 \$5,0\(\$0\)'
+.*:10: Error: unrecognized opcode `lwc0 \$6,0\(\$0\)'
+.*:11: Error: unrecognized opcode `lwc0 \$7,0\(\$0\)'
+.*:12: Error: unrecognized opcode `lwc0 \$8,0\(\$0\)'
+.*:13: Error: unrecognized opcode `lwc0 \$9,0\(\$0\)'
+.*:14: Error: unrecognized opcode `lwc0 \$10,0\(\$0\)'
+.*:15: Error: unrecognized opcode `lwc0 \$11,0\(\$0\)'
+.*:16: Error: unrecognized opcode `lwc0 \$12,0\(\$0\)'
+.*:17: Error: unrecognized opcode `lwc0 \$13,0\(\$0\)'
+.*:18: Error: unrecognized opcode `lwc0 \$14,0\(\$0\)'
+.*:19: Error: unrecognized opcode `lwc0 \$15,0\(\$0\)'
+.*:20: Error: unrecognized opcode `lwc0 \$16,0\(\$0\)'
+.*:21: Error: unrecognized opcode `lwc0 \$17,0\(\$0\)'
+.*:22: Error: unrecognized opcode `lwc0 \$18,0\(\$0\)'
+.*:23: Error: unrecognized opcode `lwc0 \$19,0\(\$0\)'
+.*:24: Error: unrecognized opcode `lwc0 \$20,0\(\$0\)'
+.*:25: Error: unrecognized opcode `lwc0 \$21,0\(\$0\)'
+.*:26: Error: unrecognized opcode `lwc0 \$22,0\(\$0\)'
+.*:27: Error: unrecognized opcode `lwc0 \$23,0\(\$0\)'
+.*:28: Error: unrecognized opcode `lwc0 \$24,0\(\$0\)'
+.*:29: Error: unrecognized opcode `lwc0 \$25,0\(\$0\)'
+.*:30: Error: unrecognized opcode `lwc0 \$26,0\(\$0\)'
+.*:31: Error: unrecognized opcode `lwc0 \$27,0\(\$0\)'
+.*:32: Error: unrecognized opcode `lwc0 \$28,0\(\$0\)'
+.*:33: Error: unrecognized opcode `lwc0 \$29,0\(\$0\)'
+.*:34: Error: unrecognized opcode `lwc0 \$30,0\(\$0\)'
+.*:35: Error: unrecognized opcode `lwc0 \$31,0\(\$0\)'
+.*:37: Error: unrecognized opcode `swc0 \$0,0\(\$0\)'
+.*:38: Error: unrecognized opcode `swc0 \$1,0\(\$0\)'
+.*:39: Error: unrecognized opcode `swc0 \$2,0\(\$0\)'
+.*:40: Error: unrecognized opcode `swc0 \$3,0\(\$0\)'
+.*:41: Error: unrecognized opcode `swc0 \$4,0\(\$0\)'
+.*:42: Error: unrecognized opcode `swc0 \$5,0\(\$0\)'
+.*:43: Error: unrecognized opcode `swc0 \$6,0\(\$0\)'
+.*:44: Error: unrecognized opcode `swc0 \$7,0\(\$0\)'
+.*:45: Error: unrecognized opcode `swc0 \$8,0\(\$0\)'
+.*:46: Error: unrecognized opcode `swc0 \$9,0\(\$0\)'
+.*:47: Error: unrecognized opcode `swc0 \$10,0\(\$0\)'
+.*:48: Error: unrecognized opcode `swc0 \$11,0\(\$0\)'
+.*:49: Error: unrecognized opcode `swc0 \$12,0\(\$0\)'
+.*:50: Error: unrecognized opcode `swc0 \$13,0\(\$0\)'
+.*:51: Error: unrecognized opcode `swc0 \$14,0\(\$0\)'
+.*:52: Error: unrecognized opcode `swc0 \$15,0\(\$0\)'
+.*:53: Error: unrecognized opcode `swc0 \$16,0\(\$0\)'
+.*:54: Error: unrecognized opcode `swc0 \$17,0\(\$0\)'
+.*:55: Error: unrecognized opcode `swc0 \$18,0\(\$0\)'
+.*:56: Error: unrecognized opcode `swc0 \$19,0\(\$0\)'
+.*:57: Error: unrecognized opcode `swc0 \$20,0\(\$0\)'
+.*:58: Error: unrecognized opcode `swc0 \$21,0\(\$0\)'
+.*:59: Error: unrecognized opcode `swc0 \$22,0\(\$0\)'
+.*:60: Error: unrecognized opcode `swc0 \$23,0\(\$0\)'
+.*:61: Error: unrecognized opcode `swc0 \$24,0\(\$0\)'
+.*:62: Error: unrecognized opcode `swc0 \$25,0\(\$0\)'
+.*:63: Error: unrecognized opcode `swc0 \$26,0\(\$0\)'
+.*:64: Error: unrecognized opcode `swc0 \$27,0\(\$0\)'
+.*:65: Error: unrecognized opcode `swc0 \$28,0\(\$0\)'
+.*:66: Error: unrecognized opcode `swc0 \$29,0\(\$0\)'
+.*:67: Error: unrecognized opcode `swc0 \$30,0\(\$0\)'
+.*:68: Error: unrecognized opcode `swc0 \$31,0\(\$0\)'
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp2b.d b/gas/testsuite/gas/mips/micromipsr6@cp2b.d
new file mode 100644
index 00000000000..7cfb3cdd155
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp2b.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch instructions
+#as: -32
+#source: cp2b.s
+#error_output: micromipsr6@cp2b.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp2b.l b/gas/testsuite/gas/mips/micromipsr6@cp2b.l
new file mode 100644
index 00000000000..c4b17ffca42
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp2b.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: mips64r6 \(mips64r6\) `bc2f 0f'
+.*:7: Error: opcode not supported on this processor: mips64r6 \(mips64r6\) `bc2t 0f'
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp2bl.d b/gas/testsuite/gas/mips/micromipsr6@cp2bl.d
new file mode 100644
index 00000000000..75a2a8b9b00
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp2bl.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch likely instructions
+#as: -32
+#source: cp2bl.s
+#error_output: micromipsr6@cp2bl.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp2bl.l b/gas/testsuite/gas/mips/micromipsr6@cp2bl.l
new file mode 100644
index 00000000000..1009a72d0e1
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp2bl.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: mips64r6 \(mips64r6\) `bc2fl 0f'
+.*:7: Error: opcode not supported on this processor: mips64r6 \(mips64r6\) `bc2tl 0f'
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp3.d b/gas/testsuite/gas/mips/micromipsr6@cp3.d
new file mode 100644
index 00000000000..9206badf337
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp3.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 register move instructions
+#as: -32
+#source: cp3.s
+#error_output: micromipsr6@cp3.l
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp3.l b/gas/testsuite/gas/mips/micromipsr6@cp3.l
new file mode 100644
index 00000000000..55e32392c82
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp3.l
@@ -0,0 +1,129 @@
+.*: Assembler messages:
+.*:4: Error: unrecognized opcode `mtc3 \$0,\$0'
+.*:5: Error: unrecognized opcode `mtc3 \$0,\$1'
+.*:6: Error: unrecognized opcode `mtc3 \$0,\$2'
+.*:7: Error: unrecognized opcode `mtc3 \$0,\$3'
+.*:8: Error: unrecognized opcode `mtc3 \$0,\$4'
+.*:9: Error: unrecognized opcode `mtc3 \$0,\$5'
+.*:10: Error: unrecognized opcode `mtc3 \$0,\$6'
+.*:11: Error: unrecognized opcode `mtc3 \$0,\$7'
+.*:12: Error: unrecognized opcode `mtc3 \$0,\$8'
+.*:13: Error: unrecognized opcode `mtc3 \$0,\$9'
+.*:14: Error: unrecognized opcode `mtc3 \$0,\$10'
+.*:15: Error: unrecognized opcode `mtc3 \$0,\$11'
+.*:16: Error: unrecognized opcode `mtc3 \$0,\$12'
+.*:17: Error: unrecognized opcode `mtc3 \$0,\$13'
+.*:18: Error: unrecognized opcode `mtc3 \$0,\$14'
+.*:19: Error: unrecognized opcode `mtc3 \$0,\$15'
+.*:20: Error: unrecognized opcode `mtc3 \$0,\$16'
+.*:21: Error: unrecognized opcode `mtc3 \$0,\$17'
+.*:22: Error: unrecognized opcode `mtc3 \$0,\$18'
+.*:23: Error: unrecognized opcode `mtc3 \$0,\$19'
+.*:24: Error: unrecognized opcode `mtc3 \$0,\$20'
+.*:25: Error: unrecognized opcode `mtc3 \$0,\$21'
+.*:26: Error: unrecognized opcode `mtc3 \$0,\$22'
+.*:27: Error: unrecognized opcode `mtc3 \$0,\$23'
+.*:28: Error: unrecognized opcode `mtc3 \$0,\$24'
+.*:29: Error: unrecognized opcode `mtc3 \$0,\$25'
+.*:30: Error: unrecognized opcode `mtc3 \$0,\$26'
+.*:31: Error: unrecognized opcode `mtc3 \$0,\$27'
+.*:32: Error: unrecognized opcode `mtc3 \$0,\$28'
+.*:33: Error: unrecognized opcode `mtc3 \$0,\$29'
+.*:34: Error: unrecognized opcode `mtc3 \$0,\$30'
+.*:35: Error: unrecognized opcode `mtc3 \$0,\$31'
+.*:37: Error: unrecognized opcode `mfc3 \$0,\$0'
+.*:38: Error: unrecognized opcode `mfc3 \$0,\$1'
+.*:39: Error: unrecognized opcode `mfc3 \$0,\$2'
+.*:40: Error: unrecognized opcode `mfc3 \$0,\$3'
+.*:41: Error: unrecognized opcode `mfc3 \$0,\$4'
+.*:42: Error: unrecognized opcode `mfc3 \$0,\$5'
+.*:43: Error: unrecognized opcode `mfc3 \$0,\$6'
+.*:44: Error: unrecognized opcode `mfc3 \$0,\$7'
+.*:45: Error: unrecognized opcode `mfc3 \$0,\$8'
+.*:46: Error: unrecognized opcode `mfc3 \$0,\$9'
+.*:47: Error: unrecognized opcode `mfc3 \$0,\$10'
+.*:48: Error: unrecognized opcode `mfc3 \$0,\$11'
+.*:49: Error: unrecognized opcode `mfc3 \$0,\$12'
+.*:50: Error: unrecognized opcode `mfc3 \$0,\$13'
+.*:51: Error: unrecognized opcode `mfc3 \$0,\$14'
+.*:52: Error: unrecognized opcode `mfc3 \$0,\$15'
+.*:53: Error: unrecognized opcode `mfc3 \$0,\$16'
+.*:54: Error: unrecognized opcode `mfc3 \$0,\$17'
+.*:55: Error: unrecognized opcode `mfc3 \$0,\$18'
+.*:56: Error: unrecognized opcode `mfc3 \$0,\$19'
+.*:57: Error: unrecognized opcode `mfc3 \$0,\$20'
+.*:58: Error: unrecognized opcode `mfc3 \$0,\$21'
+.*:59: Error: unrecognized opcode `mfc3 \$0,\$22'
+.*:60: Error: unrecognized opcode `mfc3 \$0,\$23'
+.*:61: Error: unrecognized opcode `mfc3 \$0,\$24'
+.*:62: Error: unrecognized opcode `mfc3 \$0,\$25'
+.*:63: Error: unrecognized opcode `mfc3 \$0,\$26'
+.*:64: Error: unrecognized opcode `mfc3 \$0,\$27'
+.*:65: Error: unrecognized opcode `mfc3 \$0,\$28'
+.*:66: Error: unrecognized opcode `mfc3 \$0,\$29'
+.*:67: Error: unrecognized opcode `mfc3 \$0,\$30'
+.*:68: Error: unrecognized opcode `mfc3 \$0,\$31'
+.*:70: Error: unrecognized opcode `ctc3 \$0,\$0'
+.*:71: Error: unrecognized opcode `ctc3 \$0,\$1'
+.*:72: Error: unrecognized opcode `ctc3 \$0,\$2'
+.*:73: Error: unrecognized opcode `ctc3 \$0,\$3'
+.*:74: Error: unrecognized opcode `ctc3 \$0,\$4'
+.*:75: Error: unrecognized opcode `ctc3 \$0,\$5'
+.*:76: Error: unrecognized opcode `ctc3 \$0,\$6'
+.*:77: Error: unrecognized opcode `ctc3 \$0,\$7'
+.*:78: Error: unrecognized opcode `ctc3 \$0,\$8'
+.*:79: Error: unrecognized opcode `ctc3 \$0,\$9'
+.*:80: Error: unrecognized opcode `ctc3 \$0,\$10'
+.*:81: Error: unrecognized opcode `ctc3 \$0,\$11'
+.*:82: Error: unrecognized opcode `ctc3 \$0,\$12'
+.*:83: Error: unrecognized opcode `ctc3 \$0,\$13'
+.*:84: Error: unrecognized opcode `ctc3 \$0,\$14'
+.*:85: Error: unrecognized opcode `ctc3 \$0,\$15'
+.*:86: Error: unrecognized opcode `ctc3 \$0,\$16'
+.*:87: Error: unrecognized opcode `ctc3 \$0,\$17'
+.*:88: Error: unrecognized opcode `ctc3 \$0,\$18'
+.*:89: Error: unrecognized opcode `ctc3 \$0,\$19'
+.*:90: Error: unrecognized opcode `ctc3 \$0,\$20'
+.*:91: Error: unrecognized opcode `ctc3 \$0,\$21'
+.*:92: Error: unrecognized opcode `ctc3 \$0,\$22'
+.*:93: Error: unrecognized opcode `ctc3 \$0,\$23'
+.*:94: Error: unrecognized opcode `ctc3 \$0,\$24'
+.*:95: Error: unrecognized opcode `ctc3 \$0,\$25'
+.*:96: Error: unrecognized opcode `ctc3 \$0,\$26'
+.*:97: Error: unrecognized opcode `ctc3 \$0,\$27'
+.*:98: Error: unrecognized opcode `ctc3 \$0,\$28'
+.*:99: Error: unrecognized opcode `ctc3 \$0,\$29'
+.*:100: Error: unrecognized opcode `ctc3 \$0,\$30'
+.*:101: Error: unrecognized opcode `ctc3 \$0,\$31'
+.*:103: Error: unrecognized opcode `cfc3 \$0,\$0'
+.*:104: Error: unrecognized opcode `cfc3 \$0,\$1'
+.*:105: Error: unrecognized opcode `cfc3 \$0,\$2'
+.*:106: Error: unrecognized opcode `cfc3 \$0,\$3'
+.*:107: Error: unrecognized opcode `cfc3 \$0,\$4'
+.*:108: Error: unrecognized opcode `cfc3 \$0,\$5'
+.*:109: Error: unrecognized opcode `cfc3 \$0,\$6'
+.*:110: Error: unrecognized opcode `cfc3 \$0,\$7'
+.*:111: Error: unrecognized opcode `cfc3 \$0,\$8'
+.*:112: Error: unrecognized opcode `cfc3 \$0,\$9'
+.*:113: Error: unrecognized opcode `cfc3 \$0,\$10'
+.*:114: Error: unrecognized opcode `cfc3 \$0,\$11'
+.*:115: Error: unrecognized opcode `cfc3 \$0,\$12'
+.*:116: Error: unrecognized opcode `cfc3 \$0,\$13'
+.*:117: Error: unrecognized opcode `cfc3 \$0,\$14'
+.*:118: Error: unrecognized opcode `cfc3 \$0,\$15'
+.*:119: Error: unrecognized opcode `cfc3 \$0,\$16'
+.*:120: Error: unrecognized opcode `cfc3 \$0,\$17'
+.*:121: Error: unrecognized opcode `cfc3 \$0,\$18'
+.*:122: Error: unrecognized opcode `cfc3 \$0,\$19'
+.*:123: Error: unrecognized opcode `cfc3 \$0,\$20'
+.*:124: Error: unrecognized opcode `cfc3 \$0,\$21'
+.*:125: Error: unrecognized opcode `cfc3 \$0,\$22'
+.*:126: Error: unrecognized opcode `cfc3 \$0,\$23'
+.*:127: Error: unrecognized opcode `cfc3 \$0,\$24'
+.*:128: Error: unrecognized opcode `cfc3 \$0,\$25'
+.*:129: Error: unrecognized opcode `cfc3 \$0,\$26'
+.*:130: Error: unrecognized opcode `cfc3 \$0,\$27'
+.*:131: Error: unrecognized opcode `cfc3 \$0,\$28'
+.*:132: Error: unrecognized opcode `cfc3 \$0,\$29'
+.*:133: Error: unrecognized opcode `cfc3 \$0,\$30'
+.*:134: Error: unrecognized opcode `cfc3 \$0,\$31'
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp3b.d b/gas/testsuite/gas/mips/micromipsr6@cp3b.d
new file mode 100644
index 00000000000..fc60994b0c1
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp3b.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch instructions
+#as: -32
+#source: cp3b.s
+#error_output: micromipsr6@cp3b.l
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp3b.l b/gas/testsuite/gas/mips/micromipsr6@cp3b.l
new file mode 100644
index 00000000000..9a3e923d74a
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp3b.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:4: Error: unrecognized opcode `bc3f 0f'
+.*:7: Error: unrecognized opcode `bc3t 0f'
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp3bl.d b/gas/testsuite/gas/mips/micromipsr6@cp3bl.d
new file mode 100644
index 00000000000..1709d8454be
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp3bl.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch likely instructions
+#as: -32
+#source: cp3bl.s
+#error_output: micromipsr6@cp3bl.l
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp3bl.l b/gas/testsuite/gas/mips/micromipsr6@cp3bl.l
new file mode 100644
index 00000000000..982b8e61d15
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp3bl.l
@@ -0,0 +1,3 @@
+.*: Assembler messages:
+.*:4: Error: unrecognized opcode `bc3fl 0f'
+.*:7: Error: unrecognized opcode `bc3tl 0f'
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp3d.d b/gas/testsuite/gas/mips/micromipsr6@cp3d.d
new file mode 100644
index 00000000000..982b550b153
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp3d.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 doubleword memory access instructions
+#as: -32
+#source: cp3d.s
+#error_output: micromipsr6@cp3d.l
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp3d.l b/gas/testsuite/gas/mips/micromipsr6@cp3d.l
new file mode 100644
index 00000000000..f8d277719b5
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp3d.l
@@ -0,0 +1,65 @@
+.*: Assembler messages:
+.*:4: Error: unrecognized opcode `ldc3 \$0,0\(\$0\)'
+.*:5: Error: unrecognized opcode `ldc3 \$1,0\(\$0\)'
+.*:6: Error: unrecognized opcode `ldc3 \$2,0\(\$0\)'
+.*:7: Error: unrecognized opcode `ldc3 \$3,0\(\$0\)'
+.*:8: Error: unrecognized opcode `ldc3 \$4,0\(\$0\)'
+.*:9: Error: unrecognized opcode `ldc3 \$5,0\(\$0\)'
+.*:10: Error: unrecognized opcode `ldc3 \$6,0\(\$0\)'
+.*:11: Error: unrecognized opcode `ldc3 \$7,0\(\$0\)'
+.*:12: Error: unrecognized opcode `ldc3 \$8,0\(\$0\)'
+.*:13: Error: unrecognized opcode `ldc3 \$9,0\(\$0\)'
+.*:14: Error: unrecognized opcode `ldc3 \$10,0\(\$0\)'
+.*:15: Error: unrecognized opcode `ldc3 \$11,0\(\$0\)'
+.*:16: Error: unrecognized opcode `ldc3 \$12,0\(\$0\)'
+.*:17: Error: unrecognized opcode `ldc3 \$13,0\(\$0\)'
+.*:18: Error: unrecognized opcode `ldc3 \$14,0\(\$0\)'
+.*:19: Error: unrecognized opcode `ldc3 \$15,0\(\$0\)'
+.*:20: Error: unrecognized opcode `ldc3 \$16,0\(\$0\)'
+.*:21: Error: unrecognized opcode `ldc3 \$17,0\(\$0\)'
+.*:22: Error: unrecognized opcode `ldc3 \$18,0\(\$0\)'
+.*:23: Error: unrecognized opcode `ldc3 \$19,0\(\$0\)'
+.*:24: Error: unrecognized opcode `ldc3 \$20,0\(\$0\)'
+.*:25: Error: unrecognized opcode `ldc3 \$21,0\(\$0\)'
+.*:26: Error: unrecognized opcode `ldc3 \$22,0\(\$0\)'
+.*:27: Error: unrecognized opcode `ldc3 \$23,0\(\$0\)'
+.*:28: Error: unrecognized opcode `ldc3 \$24,0\(\$0\)'
+.*:29: Error: unrecognized opcode `ldc3 \$25,0\(\$0\)'
+.*:30: Error: unrecognized opcode `ldc3 \$26,0\(\$0\)'
+.*:31: Error: unrecognized opcode `ldc3 \$27,0\(\$0\)'
+.*:32: Error: unrecognized opcode `ldc3 \$28,0\(\$0\)'
+.*:33: Error: unrecognized opcode `ldc3 \$29,0\(\$0\)'
+.*:34: Error: unrecognized opcode `ldc3 \$30,0\(\$0\)'
+.*:35: Error: unrecognized opcode `ldc3 \$31,0\(\$0\)'
+.*:37: Error: unrecognized opcode `sdc3 \$0,0\(\$0\)'
+.*:38: Error: unrecognized opcode `sdc3 \$1,0\(\$0\)'
+.*:39: Error: unrecognized opcode `sdc3 \$2,0\(\$0\)'
+.*:40: Error: unrecognized opcode `sdc3 \$3,0\(\$0\)'
+.*:41: Error: unrecognized opcode `sdc3 \$4,0\(\$0\)'
+.*:42: Error: unrecognized opcode `sdc3 \$5,0\(\$0\)'
+.*:43: Error: unrecognized opcode `sdc3 \$6,0\(\$0\)'
+.*:44: Error: unrecognized opcode `sdc3 \$7,0\(\$0\)'
+.*:45: Error: unrecognized opcode `sdc3 \$8,0\(\$0\)'
+.*:46: Error: unrecognized opcode `sdc3 \$9,0\(\$0\)'
+.*:47: Error: unrecognized opcode `sdc3 \$10,0\(\$0\)'
+.*:48: Error: unrecognized opcode `sdc3 \$11,0\(\$0\)'
+.*:49: Error: unrecognized opcode `sdc3 \$12,0\(\$0\)'
+.*:50: Error: unrecognized opcode `sdc3 \$13,0\(\$0\)'
+.*:51: Error: unrecognized opcode `sdc3 \$14,0\(\$0\)'
+.*:52: Error: unrecognized opcode `sdc3 \$15,0\(\$0\)'
+.*:53: Error: unrecognized opcode `sdc3 \$16,0\(\$0\)'
+.*:54: Error: unrecognized opcode `sdc3 \$17,0\(\$0\)'
+.*:55: Error: unrecognized opcode `sdc3 \$18,0\(\$0\)'
+.*:56: Error: unrecognized opcode `sdc3 \$19,0\(\$0\)'
+.*:57: Error: unrecognized opcode `sdc3 \$20,0\(\$0\)'
+.*:58: Error: unrecognized opcode `sdc3 \$21,0\(\$0\)'
+.*:59: Error: unrecognized opcode `sdc3 \$22,0\(\$0\)'
+.*:60: Error: unrecognized opcode `sdc3 \$23,0\(\$0\)'
+.*:61: Error: unrecognized opcode `sdc3 \$24,0\(\$0\)'
+.*:62: Error: unrecognized opcode `sdc3 \$25,0\(\$0\)'
+.*:63: Error: unrecognized opcode `sdc3 \$26,0\(\$0\)'
+.*:64: Error: unrecognized opcode `sdc3 \$27,0\(\$0\)'
+.*:65: Error: unrecognized opcode `sdc3 \$28,0\(\$0\)'
+.*:66: Error: unrecognized opcode `sdc3 \$29,0\(\$0\)'
+.*:67: Error: unrecognized opcode `sdc3 \$30,0\(\$0\)'
+.*:68: Error: unrecognized opcode `sdc3 \$31,0\(\$0\)'
\ No newline at end of file
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp3m.d b/gas/testsuite/gas/mips/micromipsr6@cp3m.d
new file mode 100644
index 00000000000..a73f3d9bc6c
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp3m.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 memory access instructions
+#as: -32
+#source: cp3m.s
+#error_output: micromipsr6@cp3m.l
diff --git a/gas/testsuite/gas/mips/micromipsr6@cp3m.l b/gas/testsuite/gas/mips/micromipsr6@cp3m.l
new file mode 100644
index 00000000000..4426f961fdf
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@cp3m.l
@@ -0,0 +1,65 @@
+.*: Assembler messages:
+.*:4: Error: unrecognized opcode `lwc3 \$0,0\(\$0\)'
+.*:5: Error: unrecognized opcode `lwc3 \$1,0\(\$0\)'
+.*:6: Error: unrecognized opcode `lwc3 \$2,0\(\$0\)'
+.*:7: Error: unrecognized opcode `lwc3 \$3,0\(\$0\)'
+.*:8: Error: unrecognized opcode `lwc3 \$4,0\(\$0\)'
+.*:9: Error: unrecognized opcode `lwc3 \$5,0\(\$0\)'
+.*:10: Error: unrecognized opcode `lwc3 \$6,0\(\$0\)'
+.*:11: Error: unrecognized opcode `lwc3 \$7,0\(\$0\)'
+.*:12: Error: unrecognized opcode `lwc3 \$8,0\(\$0\)'
+.*:13: Error: unrecognized opcode `lwc3 \$9,0\(\$0\)'
+.*:14: Error: unrecognized opcode `lwc3 \$10,0\(\$0\)'
+.*:15: Error: unrecognized opcode `lwc3 \$11,0\(\$0\)'
+.*:16: Error: unrecognized opcode `lwc3 \$12,0\(\$0\)'
+.*:17: Error: unrecognized opcode `lwc3 \$13,0\(\$0\)'
+.*:18: Error: unrecognized opcode `lwc3 \$14,0\(\$0\)'
+.*:19: Error: unrecognized opcode `lwc3 \$15,0\(\$0\)'
+.*:20: Error: unrecognized opcode `lwc3 \$16,0\(\$0\)'
+.*:21: Error: unrecognized opcode `lwc3 \$17,0\(\$0\)'
+.*:22: Error: unrecognized opcode `lwc3 \$18,0\(\$0\)'
+.*:23: Error: unrecognized opcode `lwc3 \$19,0\(\$0\)'
+.*:24: Error: unrecognized opcode `lwc3 \$20,0\(\$0\)'
+.*:25: Error: unrecognized opcode `lwc3 \$21,0\(\$0\)'
+.*:26: Error: unrecognized opcode `lwc3 \$22,0\(\$0\)'
+.*:27: Error: unrecognized opcode `lwc3 \$23,0\(\$0\)'
+.*:28: Error: unrecognized opcode `lwc3 \$24,0\(\$0\)'
+.*:29: Error: unrecognized opcode `lwc3 \$25,0\(\$0\)'
+.*:30: Error: unrecognized opcode `lwc3 \$26,0\(\$0\)'
+.*:31: Error: unrecognized opcode `lwc3 \$27,0\(\$0\)'
+.*:32: Error: unrecognized opcode `lwc3 \$28,0\(\$0\)'
+.*:33: Error: unrecognized opcode `lwc3 \$29,0\(\$0\)'
+.*:34: Error: unrecognized opcode `lwc3 \$30,0\(\$0\)'
+.*:35: Error: unrecognized opcode `lwc3 \$31,0\(\$0\)'
+.*:37: Error: unrecognized opcode `swc3 \$0,0\(\$0\)'
+.*:38: Error: unrecognized opcode `swc3 \$1,0\(\$0\)'
+.*:39: Error: unrecognized opcode `swc3 \$2,0\(\$0\)'
+.*:40: Error: unrecognized opcode `swc3 \$3,0\(\$0\)'
+.*:41: Error: unrecognized opcode `swc3 \$4,0\(\$0\)'
+.*:42: Error: unrecognized opcode `swc3 \$5,0\(\$0\)'
+.*:43: Error: unrecognized opcode `swc3 \$6,0\(\$0\)'
+.*:44: Error: unrecognized opcode `swc3 \$7,0\(\$0\)'
+.*:45: Error: unrecognized opcode `swc3 \$8,0\(\$0\)'
+.*:46: Error: unrecognized opcode `swc3 \$9,0\(\$0\)'
+.*:47: Error: unrecognized opcode `swc3 \$10,0\(\$0\)'
+.*:48: Error: unrecognized opcode `swc3 \$11,0\(\$0\)'
+.*:49: Error: unrecognized opcode `swc3 \$12,0\(\$0\)'
+.*:50: Error: unrecognized opcode `swc3 \$13,0\(\$0\)'
+.*:51: Error: unrecognized opcode `swc3 \$14,0\(\$0\)'
+.*:52: Error: unrecognized opcode `swc3 \$15,0\(\$0\)'
+.*:53: Error: unrecognized opcode `swc3 \$16,0\(\$0\)'
+.*:54: Error: unrecognized opcode `swc3 \$17,0\(\$0\)'
+.*:55: Error: unrecognized opcode `swc3 \$18,0\(\$0\)'
+.*:56: Error: unrecognized opcode `swc3 \$19,0\(\$0\)'
+.*:57: Error: unrecognized opcode `swc3 \$20,0\(\$0\)'
+.*:58: Error: unrecognized opcode `swc3 \$21,0\(\$0\)'
+.*:59: Error: unrecognized opcode `swc3 \$22,0\(\$0\)'
+.*:60: Error: unrecognized opcode `swc3 \$23,0\(\$0\)'
+.*:61: Error: unrecognized opcode `swc3 \$24,0\(\$0\)'
+.*:62: Error: unrecognized opcode `swc3 \$25,0\(\$0\)'
+.*:63: Error: unrecognized opcode `swc3 \$26,0\(\$0\)'
+.*:64: Error: unrecognized opcode `swc3 \$27,0\(\$0\)'
+.*:65: Error: unrecognized opcode `swc3 \$28,0\(\$0\)'
+.*:66: Error: unrecognized opcode `swc3 \$29,0\(\$0\)'
+.*:67: Error: unrecognized opcode `swc3 \$30,0\(\$0\)'
+.*:68: Error: unrecognized opcode `swc3 \$31,0\(\$0\)'
diff --git a/gas/testsuite/gas/mips/micromipsr6@dadd.d b/gas/testsuite/gas/mips/micromipsr6@dadd.d
new file mode 100644
index 00000000000..85a535b9d3c
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@dadd.d
@@ -0,0 +1,5 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DADD immediate expansion for R6
+#as: -32
+#source: daddi.s
+#error_output: micromipsr6@dadd.l
diff --git a/gas/testsuite/gas/mips/micromipsr6@dadd.l b/gas/testsuite/gas/mips/micromipsr6@dadd.l
new file mode 100644
index 00000000000..248410ab5fd
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@dadd.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*:26: Error: invalid operands `dadd \$15,\$14,32768'
+.*:27: Error: invalid operands `dadd \$17,\$16,-32769'
+.*:28: Error: invalid operands `dadd \$19,\$18,33280'
+.*:29: Error: invalid operands `dadd \$21,\$20,-33281'
diff --git a/gas/testsuite/gas/mips/micromipsr6@dli.d b/gas/testsuite/gas/mips/micromipsr6@dli.d
new file mode 100644
index 00000000000..a2a04a05220
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@dli.d
@@ -0,0 +1,116 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS dli
+#source: dli.s
+#as: -64
+
+# Test the dli macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 3080 0000 li a0,0
+[0-9a-f]+ <[^>]*> 3080 0001 li a0,1
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5080 8000 li a0,0x8000
+[0-9a-f]+ <[^>]*> 3080 8000 li a0,-32768
+[0-9a-f]+ <[^>]*> 1080 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 1080 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 5084 a5a5 ori a0,a0,0xa5a5
+[0-9a-f]+ <[^>]*> 5080 8000 li a0,0x8000
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 1234 ori a0,a0,0x1234
+[0-9a-f]+ <[^>]*> 1080 ffff lui a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 0048 dsrl32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 1080 ffff lui a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 0048 dsrl32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 6040 dsrl a0,a0,0xc
+[0-9a-f]+ <[^>]*> 1080 8000 lui a0,0x8000
+[0-9a-f]+ <[^>]*> 5084 1234 ori a0,a0,0x1234
+[0-9a-f]+ <[^>]*> 3080 8000 li a0,-32768
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 1234 ori a0,a0,0x1234
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 5678 ori a0,a0,0x5678
+[0-9a-f]+ <[^>]*> 1080 8000 lui a0,0x8000
+[0-9a-f]+ <[^>]*> 5084 1234 ori a0,a0,0x1234
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 5678 ori a0,a0,0x5678
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 3080 8765 li a0,-30875
+[0-9a-f]+ <[^>]*> 1080 ffff lui a0,0xffff
+[0-9a-f]+ <[^>]*> 5084 4321 ori a0,a0,0x4321
+[0-9a-f]+ <[^>]*> 3080 fff0 li a0,-16
+[0-9a-f]+ <[^>]*> 3080 ff00 li a0,-256
+[0-9a-f]+ <[^>]*> 3080 f000 li a0,-4096
+[0-9a-f]+ <[^>]*> 1080 ffff lui a0,0xffff
+[0-9a-f]+ <[^>]*> 1080 fff0 lui a0,0xfff0
+[0-9a-f]+ <[^>]*> 1080 ff00 lui a0,0xff00
+[0-9a-f]+ <[^>]*> 1080 f000 lui a0,0xf000
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 0008 dsll32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 3080 fff0 li a0,-16
+[0-9a-f]+ <[^>]*> 5884 0008 dsll32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 3080 ff00 li a0,-256
+[0-9a-f]+ <[^>]*> 5884 0008 dsll32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 3080 f000 li a0,-4096
+[0-9a-f]+ <[^>]*> 5884 0008 dsll32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 5080 ffff li a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 8008 dsll32 a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5080 fff0 li a0,0xfff0
+[0-9a-f]+ <[^>]*> 5884 8008 dsll32 a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5080 ff00 li a0,0xff00
+[0-9a-f]+ <[^>]*> 5884 8008 dsll32 a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5080 f000 li a0,0xf000
+[0-9a-f]+ <[^>]*> 5884 8008 dsll32 a0,a0,0x10
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 2040 dsrl a0,a0,0x4
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 4040 dsrl a0,a0,0x8
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 6040 dsrl a0,a0,0xc
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 8040 dsrl a0,a0,0x10
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 a040 dsrl a0,a0,0x14
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 c040 dsrl a0,a0,0x18
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 e040 dsrl a0,a0,0x1c
+[0-9a-f]+ <[^>]*> 1080 ffff lui a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 0048 dsrl32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 1080 0fff lui a0,0xfff
+[0-9a-f]+ <[^>]*> 5084 ffff ori a0,a0,0xffff
+[0-9a-f]+ <[^>]*> 1080 00ff lui a0,0xff
+[0-9a-f]+ <[^>]*> 5084 ffff ori a0,a0,0xffff
+[0-9a-f]+ <[^>]*> 1080 000f lui a0,0xf
+[0-9a-f]+ <[^>]*> 5084 ffff ori a0,a0,0xffff
+[0-9a-f]+ <[^>]*> 5080 ffff li a0,0xffff
+[0-9a-f]+ <[^>]*> 3080 0fff li a0,4095
+[0-9a-f]+ <[^>]*> 3080 00ff li a0,255
+[0-9a-f]+ <[^>]*> 3080 000f li a0,15
+[0-9a-f]+ <[^>]*> 1080 0003 lui a0,0x3
+[0-9a-f]+ <[^>]*> 5084 fffc ori a0,a0,0xfffc
+[0-9a-f]+ <[^>]*> 5080 ffff li a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 f000 dsll a0,a0,0x1e
+[0-9a-f]+ <[^>]*> 5080 ffff li a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 1008 dsll32 a0,a0,0x2
+[0-9a-f]+ <[^>]*> 5080 ffff li a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 3008 dsll32 a0,a0,0x6
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 0008 dsll32 a0,a0,0x0
+[0-9a-f]+ <[^>]*> 5884 5040 dsrl a0,a0,0xa
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 e000 dsll a0,a0,0x1c
+[0-9a-f]+ <[^>]*> 5884 5040 dsrl a0,a0,0xa
+[0-9a-f]+ <[^>]*> 3080 ffff li a0,-1
+[0-9a-f]+ <[^>]*> 5884 c000 dsll a0,a0,0x18
+[0-9a-f]+ <[^>]*> 5884 5040 dsrl a0,a0,0xa
+[0-9a-f]+ <[^>]*> 1080 003f lui a0,0x3f
+[0-9a-f]+ <[^>]*> 5084 fc03 ori a0,a0,0xfc03
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 ffff ori a0,a0,0xffff
+[0-9a-f]+ <[^>]*> 5884 8000 dsll a0,a0,0x10
+[0-9a-f]+ <[^>]*> 5084 c000 ori a0,a0,0xc000
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@elf-rel29.d b/gas/testsuite/gas/mips/micromipsr6@elf-rel29.d
new file mode 100644
index 00000000000..58b012db162
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@elf-rel29.d
@@ -0,0 +1,18 @@
+#objdump: -dr --show-raw-insn
+#as: -64
+#name: MIPS ELF reloc 29
+#source: elf-rel29.s
+
+.*file format.*
+
+Disassembly .*
+
+0+0 <foo>:
+.*: 1080 1234 lui a0,0x1234
+.*: 5884 8000 dsll a0,a0,0x10
+.*: 5c84 5679 daddiu a0,a0,22137
+.*: 5884 8000 dsll a0,a0,0x10
+.*: 5c84 9abd daddiu a0,a0,-25923
+.*: 5884 8000 dsll a0,a0,0x10
+.*: fc84 def0 lw a0,-8464\(a0\)
+#pass
diff --git a/gas/testsuite/gas/mips/micromipsr6@eva.d b/gas/testsuite/gas/mips/micromipsr6@eva.d
new file mode 100644
index 00000000000..4b67a0bed32
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@eva.d
@@ -0,0 +1,950 @@
+#objdump: -dr -Mgpr-names=numeric --show-raw-insn
+#name: microMIPS EVA
+#as: -meva -32
+#source: eva.s
+
+.*: +file format .*mips.*
+
+
+Disassembly of section \.text:
+
+[ 0-9a-f]+ <test_eva>:
+[ 0-9a-f]+: 6002 6100 lbue \$0,-256\(\$2\)
+[ 0-9a-f]+: 6060 6100 lbue \$3,-256\(\$0\)
+[ 0-9a-f]+: 6085 60ff lbue \$4,255\(\$5\)
+[ 0-9a-f]+: 60c0 60ff lbue \$6,255\(\$0\)
+[ 0-9a-f]+: 3028 feff addiu \$1,\$8,-257
+[ 0-9a-f]+: 60e1 6000 lbue \$7,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 6121 6000 lbue \$9,0\(\$1\)
+[ 0-9a-f]+: 302b 0100 addiu \$1,\$11,256
+[ 0-9a-f]+: 6141 6000 lbue \$10,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 6181 6000 lbue \$12,0\(\$1\)
+[ 0-9a-f]+: 302e fe00 addiu \$1,\$14,-512
+[ 0-9a-f]+: 61a1 6000 lbue \$13,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 61e1 6000 lbue \$15,0\(\$1\)
+[ 0-9a-f]+: 3031 01ff addiu \$1,\$17,511
+[ 0-9a-f]+: 6201 6000 lbue \$16,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 6241 6000 lbue \$18,0\(\$1\)
+[ 0-9a-f]+: 3034 fc00 addiu \$1,\$20,-1024
+[ 0-9a-f]+: 6261 6000 lbue \$19,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 62a1 6000 lbue \$21,0\(\$1\)
+[ 0-9a-f]+: 3037 03ff addiu \$1,\$23,1023
+[ 0-9a-f]+: 62c1 6000 lbue \$22,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 6301 6000 lbue \$24,0\(\$1\)
+[ 0-9a-f]+: 303a f800 addiu \$1,\$26,-2048
+[ 0-9a-f]+: 6321 6000 lbue \$25,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 6361 6000 lbue \$27,0\(\$1\)
+[ 0-9a-f]+: 303d 07ff addiu \$1,\$29,2047
+[ 0-9a-f]+: 6381 6000 lbue \$28,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 63c1 6000 lbue \$30,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 63e1 6000 lbue \$31,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 6041 6000 lbue \$2,0\(\$1\)
+[ 0-9a-f]+: 3024 0fff addiu \$1,\$4,4095
+[ 0-9a-f]+: 6061 6000 lbue \$3,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 60a1 6000 lbue \$5,0\(\$1\)
+[ 0-9a-f]+: 3027 8000 addiu \$1,\$7,-32768
+[ 0-9a-f]+: 60c1 6000 lbue \$6,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6101 6000 lbue \$8,0\(\$1\)
+[ 0-9a-f]+: 302a 7fff addiu \$1,\$10,32767
+[ 0-9a-f]+: 6121 6000 lbue \$9,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 6161 6000 lbue \$11,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 01a1 0950 addu \$1,\$1,\$13
+[ 0-9a-f]+: 6181 61ff lbue \$12,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 61c1 61ff lbue \$14,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 0201 0950 addu \$1,\$1,\$16
+[ 0-9a-f]+: 61e1 6000 lbue \$15,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 6221 6000 lbue \$17,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0261 0950 addu \$1,\$1,\$19
+[ 0-9a-f]+: 6241 6000 lbue \$18,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6281 6000 lbue \$20,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 02c1 0950 addu \$1,\$1,\$22
+[ 0-9a-f]+: 62a1 61ff lbue \$21,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 62e1 61ff lbue \$23,-1\(\$1\)
+[ 0-9a-f]+: 6319 6000 lbue \$24,0\(\$25\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 6341 6000 lbue \$26,0\(\$1\)
+[ 0-9a-f]+: 637c 6300 lhue \$27,-256\(\$28\)
+[ 0-9a-f]+: 63a0 6300 lhue \$29,-256\(\$0\)
+[ 0-9a-f]+: 63df 62ff lhue \$30,255\(\$31\)
+[ 0-9a-f]+: 6000 62ff lhue \$0,255\(\$0\)
+[ 0-9a-f]+: 3023 feff addiu \$1,\$3,-257
+[ 0-9a-f]+: 6041 6200 lhue \$2,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 6081 6200 lhue \$4,0\(\$1\)
+[ 0-9a-f]+: 3026 0100 addiu \$1,\$6,256
+[ 0-9a-f]+: 60a1 6200 lhue \$5,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 60e1 6200 lhue \$7,0\(\$1\)
+[ 0-9a-f]+: 3029 fe00 addiu \$1,\$9,-512
+[ 0-9a-f]+: 6101 6200 lhue \$8,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 6141 6200 lhue \$10,0\(\$1\)
+[ 0-9a-f]+: 302c 01ff addiu \$1,\$12,511
+[ 0-9a-f]+: 6161 6200 lhue \$11,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 61a1 6200 lhue \$13,0\(\$1\)
+[ 0-9a-f]+: 302f fc00 addiu \$1,\$15,-1024
+[ 0-9a-f]+: 61c1 6200 lhue \$14,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 6201 6200 lhue \$16,0\(\$1\)
+[ 0-9a-f]+: 3032 03ff addiu \$1,\$18,1023
+[ 0-9a-f]+: 6221 6200 lhue \$17,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 6261 6200 lhue \$19,0\(\$1\)
+[ 0-9a-f]+: 3035 f800 addiu \$1,\$21,-2048
+[ 0-9a-f]+: 6281 6200 lhue \$20,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 62c1 6200 lhue \$22,0\(\$1\)
+[ 0-9a-f]+: 3038 07ff addiu \$1,\$24,2047
+[ 0-9a-f]+: 62e1 6200 lhue \$23,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 6321 6200 lhue \$25,0\(\$1\)
+[ 0-9a-f]+: 303b f000 addiu \$1,\$27,-4096
+[ 0-9a-f]+: 6341 6200 lhue \$26,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 6381 6200 lhue \$28,0\(\$1\)
+[ 0-9a-f]+: 303e 0fff addiu \$1,\$30,4095
+[ 0-9a-f]+: 63a1 6200 lhue \$29,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 63e1 6200 lhue \$31,0\(\$1\)
+[ 0-9a-f]+: 3022 8000 addiu \$1,\$2,-32768
+[ 0-9a-f]+: 6001 6200 lhue \$0,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6061 6200 lhue \$3,0\(\$1\)
+[ 0-9a-f]+: 3025 7fff addiu \$1,\$5,32767
+[ 0-9a-f]+: 6081 6200 lhue \$4,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 60c1 6200 lhue \$6,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 0101 0950 addu \$1,\$1,\$8
+[ 0-9a-f]+: 60e1 63ff lhue \$7,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6121 63ff lhue \$9,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 0161 0950 addu \$1,\$1,\$11
+[ 0-9a-f]+: 6141 6200 lhue \$10,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 6181 6200 lhue \$12,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 01c1 0950 addu \$1,\$1,\$14
+[ 0-9a-f]+: 61a1 6200 lhue \$13,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 61e1 6200 lhue \$15,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0221 0950 addu \$1,\$1,\$17
+[ 0-9a-f]+: 6201 63ff lhue \$16,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6241 63ff lhue \$18,-1\(\$1\)
+[ 0-9a-f]+: 6274 6200 lhue \$19,0\(\$20\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 62a1 6200 lhue \$21,0\(\$1\)
+[ 0-9a-f]+: 62d7 6900 lbe \$22,-256\(\$23\)
+[ 0-9a-f]+: 6300 6900 lbe \$24,-256\(\$0\)
+[ 0-9a-f]+: 633a 68ff lbe \$25,255\(\$26\)
+[ 0-9a-f]+: 6360 68ff lbe \$27,255\(\$0\)
+[ 0-9a-f]+: 303d feff addiu \$1,\$29,-257
+[ 0-9a-f]+: 6381 6800 lbe \$28,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 63c1 6800 lbe \$30,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 63e1 6800 lbe \$31,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 6041 6800 lbe \$2,0\(\$1\)
+[ 0-9a-f]+: 3024 fe00 addiu \$1,\$4,-512
+[ 0-9a-f]+: 6061 6800 lbe \$3,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 60a1 6800 lbe \$5,0\(\$1\)
+[ 0-9a-f]+: 3027 01ff addiu \$1,\$7,511
+[ 0-9a-f]+: 60c1 6800 lbe \$6,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 6101 6800 lbe \$8,0\(\$1\)
+[ 0-9a-f]+: 302a fc00 addiu \$1,\$10,-1024
+[ 0-9a-f]+: 6121 6800 lbe \$9,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 6161 6800 lbe \$11,0\(\$1\)
+[ 0-9a-f]+: 302d 03ff addiu \$1,\$13,1023
+[ 0-9a-f]+: 6181 6800 lbe \$12,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 61c1 6800 lbe \$14,0\(\$1\)
+[ 0-9a-f]+: 3030 f800 addiu \$1,\$16,-2048
+[ 0-9a-f]+: 61e1 6800 lbe \$15,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 6221 6800 lbe \$17,0\(\$1\)
+[ 0-9a-f]+: 3033 07ff addiu \$1,\$19,2047
+[ 0-9a-f]+: 6241 6800 lbe \$18,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 6281 6800 lbe \$20,0\(\$1\)
+[ 0-9a-f]+: 3036 f000 addiu \$1,\$22,-4096
+[ 0-9a-f]+: 62a1 6800 lbe \$21,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 62e1 6800 lbe \$23,0\(\$1\)
+[ 0-9a-f]+: 3039 0fff addiu \$1,\$25,4095
+[ 0-9a-f]+: 6301 6800 lbe \$24,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 6341 6800 lbe \$26,0\(\$1\)
+[ 0-9a-f]+: 303c 8000 addiu \$1,\$28,-32768
+[ 0-9a-f]+: 6361 6800 lbe \$27,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 63a1 6800 lbe \$29,0\(\$1\)
+[ 0-9a-f]+: 303f 7fff addiu \$1,\$31,32767
+[ 0-9a-f]+: 63c1 6800 lbe \$30,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 6001 6800 lbe \$0,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 0061 0950 addu \$1,\$1,\$3
+[ 0-9a-f]+: 6041 69ff lbe \$2,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6081 69ff lbe \$4,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 00c1 0950 addu \$1,\$1,\$6
+[ 0-9a-f]+: 60a1 6800 lbe \$5,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 60e1 6800 lbe \$7,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0121 0950 addu \$1,\$1,\$9
+[ 0-9a-f]+: 6101 6800 lbe \$8,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6141 6800 lbe \$10,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0181 0950 addu \$1,\$1,\$12
+[ 0-9a-f]+: 6161 69ff lbe \$11,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 61a1 69ff lbe \$13,-1\(\$1\)
+[ 0-9a-f]+: 61cf 6800 lbe \$14,0\(\$15\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 6201 6800 lbe \$16,0\(\$1\)
+[ 0-9a-f]+: 6232 6b00 lhe \$17,-256\(\$18\)
+[ 0-9a-f]+: 6260 6b00 lhe \$19,-256\(\$0\)
+[ 0-9a-f]+: 6295 6aff lhe \$20,255\(\$21\)
+[ 0-9a-f]+: 62c0 6aff lhe \$22,255\(\$0\)
+[ 0-9a-f]+: 3038 feff addiu \$1,\$24,-257
+[ 0-9a-f]+: 62e1 6a00 lhe \$23,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 6321 6a00 lhe \$25,0\(\$1\)
+[ 0-9a-f]+: 303b 0100 addiu \$1,\$27,256
+[ 0-9a-f]+: 6341 6a00 lhe \$26,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 6381 6a00 lhe \$28,0\(\$1\)
+[ 0-9a-f]+: 303e fe00 addiu \$1,\$30,-512
+[ 0-9a-f]+: 63a1 6a00 lhe \$29,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 63e1 6a00 lhe \$31,0\(\$1\)
+[ 0-9a-f]+: 3022 01ff addiu \$1,\$2,511
+[ 0-9a-f]+: 6001 6a00 lhe \$0,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 6061 6a00 lhe \$3,0\(\$1\)
+[ 0-9a-f]+: 3025 fc00 addiu \$1,\$5,-1024
+[ 0-9a-f]+: 6081 6a00 lhe \$4,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 60c1 6a00 lhe \$6,0\(\$1\)
+[ 0-9a-f]+: 3028 03ff addiu \$1,\$8,1023
+[ 0-9a-f]+: 60e1 6a00 lhe \$7,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 6121 6a00 lhe \$9,0\(\$1\)
+[ 0-9a-f]+: 302b f800 addiu \$1,\$11,-2048
+[ 0-9a-f]+: 6141 6a00 lhe \$10,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 6181 6a00 lhe \$12,0\(\$1\)
+[ 0-9a-f]+: 302e 07ff addiu \$1,\$14,2047
+[ 0-9a-f]+: 61a1 6a00 lhe \$13,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 61e1 6a00 lhe \$15,0\(\$1\)
+[ 0-9a-f]+: 3031 f000 addiu \$1,\$17,-4096
+[ 0-9a-f]+: 6201 6a00 lhe \$16,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 6241 6a00 lhe \$18,0\(\$1\)
+[ 0-9a-f]+: 3034 0fff addiu \$1,\$20,4095
+[ 0-9a-f]+: 6261 6a00 lhe \$19,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 62a1 6a00 lhe \$21,0\(\$1\)
+[ 0-9a-f]+: 3037 8000 addiu \$1,\$23,-32768
+[ 0-9a-f]+: 62c1 6a00 lhe \$22,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6301 6a00 lhe \$24,0\(\$1\)
+[ 0-9a-f]+: 303a 7fff addiu \$1,\$26,32767
+[ 0-9a-f]+: 6321 6a00 lhe \$25,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 6361 6a00 lhe \$27,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 03a1 0950 addu \$1,\$1,\$29
+[ 0-9a-f]+: 6381 6bff lhe \$28,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 63c1 6bff lhe \$30,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 63e1 6a00 lhe \$31,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 6041 6a00 lhe \$2,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0081 0950 addu \$1,\$1,\$4
+[ 0-9a-f]+: 6061 6a00 lhe \$3,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 60a1 6a00 lhe \$5,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 00e1 0950 addu \$1,\$1,\$7
+[ 0-9a-f]+: 60c1 6bff lhe \$6,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6101 6bff lhe \$8,-1\(\$1\)
+[ 0-9a-f]+: 612a 6a00 lhe \$9,0\(\$10\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 6161 6a00 lhe \$11,0\(\$1\)
+[ 0-9a-f]+: 618d 6d00 lle \$12,-256\(\$13\)
+[ 0-9a-f]+: 61c0 6d00 lle \$14,-256\(\$0\)
+[ 0-9a-f]+: 61f0 6cff lle \$15,255\(\$16\)
+[ 0-9a-f]+: 6220 6cff lle \$17,255\(\$0\)
+[ 0-9a-f]+: 3033 feff addiu \$1,\$19,-257
+[ 0-9a-f]+: 6241 6c00 lle \$18,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 6281 6c00 lle \$20,0\(\$1\)
+[ 0-9a-f]+: 3036 0100 addiu \$1,\$22,256
+[ 0-9a-f]+: 62a1 6c00 lle \$21,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 62e1 6c00 lle \$23,0\(\$1\)
+[ 0-9a-f]+: 3039 fe00 addiu \$1,\$25,-512
+[ 0-9a-f]+: 6301 6c00 lle \$24,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 6341 6c00 lle \$26,0\(\$1\)
+[ 0-9a-f]+: 303c 01ff addiu \$1,\$28,511
+[ 0-9a-f]+: 6361 6c00 lle \$27,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 63a1 6c00 lle \$29,0\(\$1\)
+[ 0-9a-f]+: 303f fc00 addiu \$1,\$31,-1024
+[ 0-9a-f]+: 63c1 6c00 lle \$30,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 6001 6c00 lle \$0,0\(\$1\)
+[ 0-9a-f]+: 3023 03ff addiu \$1,\$3,1023
+[ 0-9a-f]+: 6041 6c00 lle \$2,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 6081 6c00 lle \$4,0\(\$1\)
+[ 0-9a-f]+: 3026 f800 addiu \$1,\$6,-2048
+[ 0-9a-f]+: 60a1 6c00 lle \$5,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 60e1 6c00 lle \$7,0\(\$1\)
+[ 0-9a-f]+: 3029 07ff addiu \$1,\$9,2047
+[ 0-9a-f]+: 6101 6c00 lle \$8,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 6141 6c00 lle \$10,0\(\$1\)
+[ 0-9a-f]+: 302c f000 addiu \$1,\$12,-4096
+[ 0-9a-f]+: 6161 6c00 lle \$11,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 61a1 6c00 lle \$13,0\(\$1\)
+[ 0-9a-f]+: 302f 0fff addiu \$1,\$15,4095
+[ 0-9a-f]+: 61c1 6c00 lle \$14,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 6201 6c00 lle \$16,0\(\$1\)
+[ 0-9a-f]+: 3032 8000 addiu \$1,\$18,-32768
+[ 0-9a-f]+: 6221 6c00 lle \$17,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6261 6c00 lle \$19,0\(\$1\)
+[ 0-9a-f]+: 3035 7fff addiu \$1,\$21,32767
+[ 0-9a-f]+: 6281 6c00 lle \$20,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 62c1 6c00 lle \$22,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 0301 0950 addu \$1,\$1,\$24
+[ 0-9a-f]+: 62e1 6dff lle \$23,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6321 6dff lle \$25,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 0361 0950 addu \$1,\$1,\$27
+[ 0-9a-f]+: 6341 6c00 lle \$26,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 6381 6c00 lle \$28,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 03c1 0950 addu \$1,\$1,\$30
+[ 0-9a-f]+: 63a1 6c00 lle \$29,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 63e1 6c00 lle \$31,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0041 0950 addu \$1,\$1,\$2
+[ 0-9a-f]+: 6001 6dff lle \$0,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6061 6dff lle \$3,-1\(\$1\)
+[ 0-9a-f]+: 6085 6c00 lle \$4,0\(\$5\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 60c1 6c00 lle \$6,0\(\$1\)
+[ 0-9a-f]+: 60e8 6f00 lwe \$7,-256\(\$8\)
+[ 0-9a-f]+: 6120 6f00 lwe \$9,-256\(\$0\)
+[ 0-9a-f]+: 614b 6eff lwe \$10,255\(\$11\)
+[ 0-9a-f]+: 6180 6eff lwe \$12,255\(\$0\)
+[ 0-9a-f]+: 302e feff addiu \$1,\$14,-257
+[ 0-9a-f]+: 61a1 6e00 lwe \$13,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 61e1 6e00 lwe \$15,0\(\$1\)
+[ 0-9a-f]+: 3031 0100 addiu \$1,\$17,256
+[ 0-9a-f]+: 6201 6e00 lwe \$16,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 6241 6e00 lwe \$18,0\(\$1\)
+[ 0-9a-f]+: 3034 fe00 addiu \$1,\$20,-512
+[ 0-9a-f]+: 6261 6e00 lwe \$19,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 62a1 6e00 lwe \$21,0\(\$1\)
+[ 0-9a-f]+: 3037 01ff addiu \$1,\$23,511
+[ 0-9a-f]+: 62c1 6e00 lwe \$22,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 6301 6e00 lwe \$24,0\(\$1\)
+[ 0-9a-f]+: 303a fc00 addiu \$1,\$26,-1024
+[ 0-9a-f]+: 6321 6e00 lwe \$25,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 6361 6e00 lwe \$27,0\(\$1\)
+[ 0-9a-f]+: 303d 03ff addiu \$1,\$29,1023
+[ 0-9a-f]+: 6381 6e00 lwe \$28,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 63c1 6e00 lwe \$30,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 63e1 6e00 lwe \$31,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 6041 6e00 lwe \$2,0\(\$1\)
+[ 0-9a-f]+: 3024 07ff addiu \$1,\$4,2047
+[ 0-9a-f]+: 6061 6e00 lwe \$3,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 60a1 6e00 lwe \$5,0\(\$1\)
+[ 0-9a-f]+: 3027 f000 addiu \$1,\$7,-4096
+[ 0-9a-f]+: 60c1 6e00 lwe \$6,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 6101 6e00 lwe \$8,0\(\$1\)
+[ 0-9a-f]+: 302a 0fff addiu \$1,\$10,4095
+[ 0-9a-f]+: 6121 6e00 lwe \$9,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 6161 6e00 lwe \$11,0\(\$1\)
+[ 0-9a-f]+: 302d 8000 addiu \$1,\$13,-32768
+[ 0-9a-f]+: 6181 6e00 lwe \$12,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 61c1 6e00 lwe \$14,0\(\$1\)
+[ 0-9a-f]+: 3030 7fff addiu \$1,\$16,32767
+[ 0-9a-f]+: 61e1 6e00 lwe \$15,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 6221 6e00 lwe \$17,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 0261 0950 addu \$1,\$1,\$19
+[ 0-9a-f]+: 6241 6fff lwe \$18,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6281 6fff lwe \$20,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 02c1 0950 addu \$1,\$1,\$22
+[ 0-9a-f]+: 62a1 6e00 lwe \$21,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 62e1 6e00 lwe \$23,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0321 0950 addu \$1,\$1,\$25
+[ 0-9a-f]+: 6301 6e00 lwe \$24,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6341 6e00 lwe \$26,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0381 0950 addu \$1,\$1,\$28
+[ 0-9a-f]+: 6361 6fff lwe \$27,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 63a1 6fff lwe \$29,-1\(\$1\)
+[ 0-9a-f]+: 63df 6e00 lwe \$30,0\(\$31\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 6001 6e00 lwe \$0,0\(\$1\)
+[ 0-9a-f]+: 62f8 a900 sbe \$23,-256\(\$24\)
+[ 0-9a-f]+: 6320 a900 sbe \$25,-256\(\$0\)
+[ 0-9a-f]+: 635b a8ff sbe \$26,255\(\$27\)
+[ 0-9a-f]+: 6380 a8ff sbe \$28,255\(\$0\)
+[ 0-9a-f]+: 303e feff addiu \$1,\$30,-257
+[ 0-9a-f]+: 63a1 a800 sbe \$29,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 63e1 a800 sbe \$31,0\(\$1\)
+[ 0-9a-f]+: 3022 0100 addiu \$1,\$2,256
+[ 0-9a-f]+: 6001 a800 sbe \$0,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 6061 a800 sbe \$3,0\(\$1\)
+[ 0-9a-f]+: 3025 fe00 addiu \$1,\$5,-512
+[ 0-9a-f]+: 6081 a800 sbe \$4,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 60c1 a800 sbe \$6,0\(\$1\)
+[ 0-9a-f]+: 3028 01ff addiu \$1,\$8,511
+[ 0-9a-f]+: 60e1 a800 sbe \$7,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 6121 a800 sbe \$9,0\(\$1\)
+[ 0-9a-f]+: 302b fc00 addiu \$1,\$11,-1024
+[ 0-9a-f]+: 6141 a800 sbe \$10,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 6181 a800 sbe \$12,0\(\$1\)
+[ 0-9a-f]+: 302e 03ff addiu \$1,\$14,1023
+[ 0-9a-f]+: 61a1 a800 sbe \$13,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 61e1 a800 sbe \$15,0\(\$1\)
+[ 0-9a-f]+: 3031 f800 addiu \$1,\$17,-2048
+[ 0-9a-f]+: 6201 a800 sbe \$16,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 6241 a800 sbe \$18,0\(\$1\)
+[ 0-9a-f]+: 3034 07ff addiu \$1,\$20,2047
+[ 0-9a-f]+: 6261 a800 sbe \$19,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 62a1 a800 sbe \$21,0\(\$1\)
+[ 0-9a-f]+: 3037 f000 addiu \$1,\$23,-4096
+[ 0-9a-f]+: 62c1 a800 sbe \$22,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 6301 a800 sbe \$24,0\(\$1\)
+[ 0-9a-f]+: 303a 0fff addiu \$1,\$26,4095
+[ 0-9a-f]+: 6321 a800 sbe \$25,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 6361 a800 sbe \$27,0\(\$1\)
+[ 0-9a-f]+: 303d 8000 addiu \$1,\$29,-32768
+[ 0-9a-f]+: 6381 a800 sbe \$28,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 63c1 a800 sbe \$30,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 63e1 a800 sbe \$31,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 6041 a800 sbe \$2,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 0081 0950 addu \$1,\$1,\$4
+[ 0-9a-f]+: 6061 a9ff sbe \$3,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 60a1 a9ff sbe \$5,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 00e1 0950 addu \$1,\$1,\$7
+[ 0-9a-f]+: 60c1 a800 sbe \$6,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 6101 a800 sbe \$8,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0141 0950 addu \$1,\$1,\$10
+[ 0-9a-f]+: 6121 a800 sbe \$9,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6161 a800 sbe \$11,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 01a1 0950 addu \$1,\$1,\$13
+[ 0-9a-f]+: 6181 a9ff sbe \$12,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 61c1 a9ff sbe \$14,-1\(\$1\)
+[ 0-9a-f]+: 61f0 a800 sbe \$15,0\(\$16\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 6221 a800 sbe \$17,0\(\$1\)
+[ 0-9a-f]+: 6253 ad00 sce \$18,-256\(\$19\)
+[ 0-9a-f]+: 6280 ad00 sce \$20,-256\(\$0\)
+[ 0-9a-f]+: 62b6 acff sce \$21,255\(\$22\)
+[ 0-9a-f]+: 62e0 acff sce \$23,255\(\$0\)
+[ 0-9a-f]+: 3039 feff addiu \$1,\$25,-257
+[ 0-9a-f]+: 6301 ac00 sce \$24,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 6341 ac00 sce \$26,0\(\$1\)
+[ 0-9a-f]+: 303c 0100 addiu \$1,\$28,256
+[ 0-9a-f]+: 6361 ac00 sce \$27,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 63a1 ac00 sce \$29,0\(\$1\)
+[ 0-9a-f]+: 303f fe00 addiu \$1,\$31,-512
+[ 0-9a-f]+: 63c1 ac00 sce \$30,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 6001 ac00 sce \$0,0\(\$1\)
+[ 0-9a-f]+: 3023 01ff addiu \$1,\$3,511
+[ 0-9a-f]+: 6041 ac00 sce \$2,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 6081 ac00 sce \$4,0\(\$1\)
+[ 0-9a-f]+: 3026 fc00 addiu \$1,\$6,-1024
+[ 0-9a-f]+: 60a1 ac00 sce \$5,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 60e1 ac00 sce \$7,0\(\$1\)
+[ 0-9a-f]+: 3029 03ff addiu \$1,\$9,1023
+[ 0-9a-f]+: 6101 ac00 sce \$8,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 6141 ac00 sce \$10,0\(\$1\)
+[ 0-9a-f]+: 302c f800 addiu \$1,\$12,-2048
+[ 0-9a-f]+: 6161 ac00 sce \$11,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 61a1 ac00 sce \$13,0\(\$1\)
+[ 0-9a-f]+: 302f 07ff addiu \$1,\$15,2047
+[ 0-9a-f]+: 61c1 ac00 sce \$14,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 6201 ac00 sce \$16,0\(\$1\)
+[ 0-9a-f]+: 3032 f000 addiu \$1,\$18,-4096
+[ 0-9a-f]+: 6221 ac00 sce \$17,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 6261 ac00 sce \$19,0\(\$1\)
+[ 0-9a-f]+: 3035 0fff addiu \$1,\$21,4095
+[ 0-9a-f]+: 6281 ac00 sce \$20,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 62c1 ac00 sce \$22,0\(\$1\)
+[ 0-9a-f]+: 3038 8000 addiu \$1,\$24,-32768
+[ 0-9a-f]+: 62e1 ac00 sce \$23,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6321 ac00 sce \$25,0\(\$1\)
+[ 0-9a-f]+: 303b 7fff addiu \$1,\$27,32767
+[ 0-9a-f]+: 6341 ac00 sce \$26,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 6381 ac00 sce \$28,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 03c1 0950 addu \$1,\$1,\$30
+[ 0-9a-f]+: 63a1 adff sce \$29,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 63e1 adff sce \$31,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 0041 0950 addu \$1,\$1,\$2
+[ 0-9a-f]+: 6001 ac00 sce \$0,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 6061 ac00 sce \$3,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 00a1 0950 addu \$1,\$1,\$5
+[ 0-9a-f]+: 6081 ac00 sce \$4,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 60c1 ac00 sce \$6,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0101 0950 addu \$1,\$1,\$8
+[ 0-9a-f]+: 60e1 adff sce \$7,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6121 adff sce \$9,-1\(\$1\)
+[ 0-9a-f]+: 614b ac00 sce \$10,0\(\$11\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 6181 ac00 sce \$12,0\(\$1\)
+[ 0-9a-f]+: 61ae ab00 she \$13,-256\(\$14\)
+[ 0-9a-f]+: 61e0 ab00 she \$15,-256\(\$0\)
+[ 0-9a-f]+: 6211 aaff she \$16,255\(\$17\)
+[ 0-9a-f]+: 6240 aaff she \$18,255\(\$0\)
+[ 0-9a-f]+: 3034 feff addiu \$1,\$20,-257
+[ 0-9a-f]+: 6261 aa00 she \$19,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 62a1 aa00 she \$21,0\(\$1\)
+[ 0-9a-f]+: 3037 0100 addiu \$1,\$23,256
+[ 0-9a-f]+: 62c1 aa00 she \$22,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 6301 aa00 she \$24,0\(\$1\)
+[ 0-9a-f]+: 303a fe00 addiu \$1,\$26,-512
+[ 0-9a-f]+: 6321 aa00 she \$25,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 6361 aa00 she \$27,0\(\$1\)
+[ 0-9a-f]+: 303d 01ff addiu \$1,\$29,511
+[ 0-9a-f]+: 6381 aa00 she \$28,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 63c1 aa00 she \$30,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 63e1 aa00 she \$31,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 6041 aa00 she \$2,0\(\$1\)
+[ 0-9a-f]+: 3024 03ff addiu \$1,\$4,1023
+[ 0-9a-f]+: 6061 aa00 she \$3,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 60a1 aa00 she \$5,0\(\$1\)
+[ 0-9a-f]+: 3027 f800 addiu \$1,\$7,-2048
+[ 0-9a-f]+: 60c1 aa00 she \$6,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 6101 aa00 she \$8,0\(\$1\)
+[ 0-9a-f]+: 302a 07ff addiu \$1,\$10,2047
+[ 0-9a-f]+: 6121 aa00 she \$9,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 6161 aa00 she \$11,0\(\$1\)
+[ 0-9a-f]+: 302d f000 addiu \$1,\$13,-4096
+[ 0-9a-f]+: 6181 aa00 she \$12,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 61c1 aa00 she \$14,0\(\$1\)
+[ 0-9a-f]+: 3030 0fff addiu \$1,\$16,4095
+[ 0-9a-f]+: 61e1 aa00 she \$15,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 6221 aa00 she \$17,0\(\$1\)
+[ 0-9a-f]+: 3033 8000 addiu \$1,\$19,-32768
+[ 0-9a-f]+: 6241 aa00 she \$18,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6281 aa00 she \$20,0\(\$1\)
+[ 0-9a-f]+: 3036 7fff addiu \$1,\$22,32767
+[ 0-9a-f]+: 62a1 aa00 she \$21,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 62e1 aa00 she \$23,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 0321 0950 addu \$1,\$1,\$25
+[ 0-9a-f]+: 6301 abff she \$24,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6341 abff she \$26,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 0381 0950 addu \$1,\$1,\$28
+[ 0-9a-f]+: 6361 aa00 she \$27,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 63a1 aa00 she \$29,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 03e1 0950 addu \$1,\$1,\$31
+[ 0-9a-f]+: 63c1 aa00 she \$30,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6001 aa00 she \$0,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0061 0950 addu \$1,\$1,\$3
+[ 0-9a-f]+: 6041 abff she \$2,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6081 abff she \$4,-1\(\$1\)
+[ 0-9a-f]+: 60a6 aa00 she \$5,0\(\$6\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 60e1 aa00 she \$7,0\(\$1\)
+[ 0-9a-f]+: 6109 af00 swe \$8,-256\(\$9\)
+[ 0-9a-f]+: 6140 af00 swe \$10,-256\(\$0\)
+[ 0-9a-f]+: 616c aeff swe \$11,255\(\$12\)
+[ 0-9a-f]+: 61a0 aeff swe \$13,255\(\$0\)
+[ 0-9a-f]+: 302f feff addiu \$1,\$15,-257
+[ 0-9a-f]+: 61c1 ae00 swe \$14,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 6201 ae00 swe \$16,0\(\$1\)
+[ 0-9a-f]+: 3032 0100 addiu \$1,\$18,256
+[ 0-9a-f]+: 6221 ae00 swe \$17,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 6261 ae00 swe \$19,0\(\$1\)
+[ 0-9a-f]+: 3035 fe00 addiu \$1,\$21,-512
+[ 0-9a-f]+: 6281 ae00 swe \$20,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 62c1 ae00 swe \$22,0\(\$1\)
+[ 0-9a-f]+: 3038 01ff addiu \$1,\$24,511
+[ 0-9a-f]+: 62e1 ae00 swe \$23,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 6321 ae00 swe \$25,0\(\$1\)
+[ 0-9a-f]+: 303b fc00 addiu \$1,\$27,-1024
+[ 0-9a-f]+: 6341 ae00 swe \$26,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 6381 ae00 swe \$28,0\(\$1\)
+[ 0-9a-f]+: 303e 03ff addiu \$1,\$30,1023
+[ 0-9a-f]+: 63a1 ae00 swe \$29,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 63e1 ae00 swe \$31,0\(\$1\)
+[ 0-9a-f]+: 3022 f800 addiu \$1,\$2,-2048
+[ 0-9a-f]+: 6001 ae00 swe \$0,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 6061 ae00 swe \$3,0\(\$1\)
+[ 0-9a-f]+: 3025 07ff addiu \$1,\$5,2047
+[ 0-9a-f]+: 6081 ae00 swe \$4,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 60c1 ae00 swe \$6,0\(\$1\)
+[ 0-9a-f]+: 3028 f000 addiu \$1,\$8,-4096
+[ 0-9a-f]+: 60e1 ae00 swe \$7,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 6121 ae00 swe \$9,0\(\$1\)
+[ 0-9a-f]+: 302b 0fff addiu \$1,\$11,4095
+[ 0-9a-f]+: 6141 ae00 swe \$10,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 6181 ae00 swe \$12,0\(\$1\)
+[ 0-9a-f]+: 302e 8000 addiu \$1,\$14,-32768
+[ 0-9a-f]+: 61a1 ae00 swe \$13,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 61e1 ae00 swe \$15,0\(\$1\)
+[ 0-9a-f]+: 3031 7fff addiu \$1,\$17,32767
+[ 0-9a-f]+: 6201 ae00 swe \$16,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 6241 ae00 swe \$18,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 0281 0950 addu \$1,\$1,\$20
+[ 0-9a-f]+: 6261 afff swe \$19,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 62a1 afff swe \$21,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 02e1 0950 addu \$1,\$1,\$23
+[ 0-9a-f]+: 62c1 ae00 swe \$22,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 6301 ae00 swe \$24,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0341 0950 addu \$1,\$1,\$26
+[ 0-9a-f]+: 6321 ae00 swe \$25,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6361 ae00 swe \$27,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 03a1 0950 addu \$1,\$1,\$29
+[ 0-9a-f]+: 6381 afff swe \$28,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 63c1 afff swe \$30,-1\(\$1\)
+[ 0-9a-f]+: 63e0 ae00 swe \$31,0\(\$0\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 6041 ae00 swe \$2,0\(\$1\)
+[ 0-9a-f]+: 6319 a700 cachee 0x18,-256\(\$25\)
+[ 0-9a-f]+: 6340 a700 cachee 0x1a,-256\(\$0\)
+[ 0-9a-f]+: 637c a6ff cachee 0x1b,255\(\$28\)
+[ 0-9a-f]+: 63a0 a6ff cachee 0x1d,255\(\$0\)
+[ 0-9a-f]+: 303f feff addiu \$1,\$31,-257
+[ 0-9a-f]+: 63c1 a600 cachee 0x1e,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 6001 a600 cachee 0x0,0\(\$1\)
+[ 0-9a-f]+: 3023 0100 addiu \$1,\$3,256
+[ 0-9a-f]+: 6041 a600 cachee 0x2,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 6081 a600 cachee 0x4,0\(\$1\)
+[ 0-9a-f]+: 3026 fe00 addiu \$1,\$6,-512
+[ 0-9a-f]+: 60a1 a600 cachee 0x5,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 60e1 a600 cachee 0x7,0\(\$1\)
+[ 0-9a-f]+: 3029 01ff addiu \$1,\$9,511
+[ 0-9a-f]+: 6101 a600 cachee 0x8,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 6141 a600 cachee 0xa,0\(\$1\)
+[ 0-9a-f]+: 302c fc00 addiu \$1,\$12,-1024
+[ 0-9a-f]+: 6161 a600 cachee 0xb,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 61a1 a600 cachee 0xd,0\(\$1\)
+[ 0-9a-f]+: 302f 03ff addiu \$1,\$15,1023
+[ 0-9a-f]+: 61c1 a600 cachee 0xe,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 6201 a600 cachee 0x10,0\(\$1\)
+[ 0-9a-f]+: 3032 f800 addiu \$1,\$18,-2048
+[ 0-9a-f]+: 6221 a600 cachee 0x11,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 6261 a600 cachee 0x13,0\(\$1\)
+[ 0-9a-f]+: 3035 07ff addiu \$1,\$21,2047
+[ 0-9a-f]+: 6281 a600 cachee 0x14,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 62c1 a600 cachee 0x16,0\(\$1\)
+[ 0-9a-f]+: 3038 f000 addiu \$1,\$24,-4096
+[ 0-9a-f]+: 62e1 a600 cachee 0x17,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 6321 a600 cachee 0x19,0\(\$1\)
+[ 0-9a-f]+: 303b 0fff addiu \$1,\$27,4095
+[ 0-9a-f]+: 6341 a600 cachee 0x1a,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 6381 a600 cachee 0x1c,0\(\$1\)
+[ 0-9a-f]+: 303e 8000 addiu \$1,\$30,-32768
+[ 0-9a-f]+: 63a1 a600 cachee 0x1d,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 63e1 a600 cachee 0x1f,0\(\$1\)
+[ 0-9a-f]+: 3022 7fff addiu \$1,\$2,32767
+[ 0-9a-f]+: 6001 a600 cachee 0x0,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 6061 a600 cachee 0x3,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 00a1 0950 addu \$1,\$1,\$5
+[ 0-9a-f]+: 6081 a7ff cachee 0x4,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 60c1 a7ff cachee 0x6,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 0101 0950 addu \$1,\$1,\$8
+[ 0-9a-f]+: 60e1 a600 cachee 0x7,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 6121 a600 cachee 0x9,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0161 0950 addu \$1,\$1,\$11
+[ 0-9a-f]+: 6141 a600 cachee 0xa,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6181 a600 cachee 0xc,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 01c1 0950 addu \$1,\$1,\$14
+[ 0-9a-f]+: 61a1 a7ff cachee 0xd,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 61e1 a7ff cachee 0xf,-1\(\$1\)
+[ 0-9a-f]+: 6211 a600 cachee 0x10,0\(\$17\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 6241 a600 cachee 0x12,0\(\$1\)
+[ 0-9a-f]+: 6274 a500 prefe 0x13,-256\(\$20\)
+[ 0-9a-f]+: 62a0 a500 prefe 0x15,-256\(\$0\)
+[ 0-9a-f]+: 62d7 a4ff prefe 0x16,255\(\$23\)
+[ 0-9a-f]+: 6300 a4ff prefe 0x18,255\(\$0\)
+[ 0-9a-f]+: 303a feff addiu \$1,\$26,-257
+[ 0-9a-f]+: 6321 a400 prefe 0x19,0\(\$1\)
+[ 0-9a-f]+: 3020 feff li \$1,-257
+[ 0-9a-f]+: 6361 a400 prefe 0x1b,0\(\$1\)
+[ 0-9a-f]+: 303d 0100 addiu \$1,\$29,256
+[ 0-9a-f]+: 6381 a400 prefe 0x1c,0\(\$1\)
+[ 0-9a-f]+: 3020 0100 li \$1,256
+[ 0-9a-f]+: 63c1 a400 prefe 0x1e,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 63e1 a400 prefe 0x1f,0\(\$1\)
+[ 0-9a-f]+: 3020 fe00 li \$1,-512
+[ 0-9a-f]+: 6041 a400 prefe 0x2,0\(\$1\)
+[ 0-9a-f]+: 3024 01ff addiu \$1,\$4,511
+[ 0-9a-f]+: 6061 a400 prefe 0x3,0\(\$1\)
+[ 0-9a-f]+: 3020 01ff li \$1,511
+[ 0-9a-f]+: 60a1 a400 prefe 0x5,0\(\$1\)
+[ 0-9a-f]+: 3027 fc00 addiu \$1,\$7,-1024
+[ 0-9a-f]+: 60c1 a400 prefe 0x6,0\(\$1\)
+[ 0-9a-f]+: 3020 fc00 li \$1,-1024
+[ 0-9a-f]+: 6101 a400 prefe 0x8,0\(\$1\)
+[ 0-9a-f]+: 302a 03ff addiu \$1,\$10,1023
+[ 0-9a-f]+: 6121 a400 prefe 0x9,0\(\$1\)
+[ 0-9a-f]+: 3020 03ff li \$1,1023
+[ 0-9a-f]+: 6161 a400 prefe 0xb,0\(\$1\)
+[ 0-9a-f]+: 302d f800 addiu \$1,\$13,-2048
+[ 0-9a-f]+: 6181 a400 prefe 0xc,0\(\$1\)
+[ 0-9a-f]+: 3020 f800 li \$1,-2048
+[ 0-9a-f]+: 61c1 a400 prefe 0xe,0\(\$1\)
+[ 0-9a-f]+: 3030 07ff addiu \$1,\$16,2047
+[ 0-9a-f]+: 61e1 a400 prefe 0xf,0\(\$1\)
+[ 0-9a-f]+: 3020 07ff li \$1,2047
+[ 0-9a-f]+: 6221 a400 prefe 0x11,0\(\$1\)
+[ 0-9a-f]+: 3033 f000 addiu \$1,\$19,-4096
+[ 0-9a-f]+: 6241 a400 prefe 0x12,0\(\$1\)
+[ 0-9a-f]+: 3020 f000 li \$1,-4096
+[ 0-9a-f]+: 6281 a400 prefe 0x14,0\(\$1\)
+[ 0-9a-f]+: 3036 0fff addiu \$1,\$22,4095
+[ 0-9a-f]+: 62a1 a400 prefe 0x15,0\(\$1\)
+[ 0-9a-f]+: 3020 0fff li \$1,4095
+[ 0-9a-f]+: 62e1 a400 prefe 0x17,0\(\$1\)
+[ 0-9a-f]+: 3039 8000 addiu \$1,\$25,-32768
+[ 0-9a-f]+: 6301 a400 prefe 0x18,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6341 a400 prefe 0x1a,0\(\$1\)
+[ 0-9a-f]+: 303c 7fff addiu \$1,\$28,32767
+[ 0-9a-f]+: 6361 a400 prefe 0x1b,0\(\$1\)
+[ 0-9a-f]+: 3020 7fff li \$1,32767
+[ 0-9a-f]+: 63a1 a400 prefe 0x1d,0\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 03e1 0950 addu \$1,\$1,\$31
+[ 0-9a-f]+: 63c1 a5ff prefe 0x1e,-1\(\$1\)
+[ 0-9a-f]+: 3020 8000 li \$1,-32768
+[ 0-9a-f]+: 6001 a5ff prefe 0x0,-1\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 0061 0950 addu \$1,\$1,\$3
+[ 0-9a-f]+: 6041 a400 prefe 0x2,0\(\$1\)
+[ 0-9a-f]+: 5020 8000 li \$1,0x8000
+[ 0-9a-f]+: 6081 a400 prefe 0x4,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 00c1 0950 addu \$1,\$1,\$6
+[ 0-9a-f]+: 60a1 a400 prefe 0x5,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 60e1 a400 prefe 0x7,0\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 0121 0950 addu \$1,\$1,\$9
+[ 0-9a-f]+: 6101 a5ff prefe 0x8,-1\(\$1\)
+[ 0-9a-f]+: 1020 8000 lui \$1,0x8000
+[ 0-9a-f]+: 6141 a5ff prefe 0xa,-1\(\$1\)
+[ 0-9a-f]+: 616c a400 prefe 0xb,0\(\$12\)
+[ 0-9a-f]+: 1020 0000 lui \$1,0x0
+ [ 0-9a-f]+: R_MICROMIPS_HI16 MYDATA
+[ 0-9a-f]+: 3021 0000 addiu \$1,\$1,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 MYDATA
+[ 0-9a-f]+: 61a1 a400 prefe 0xd,0\(\$1\)
+[ 0-9a-f]+: 3026 0000 addiu \$1,\$6,0
+ [ 0-9a-f]+: R_MICROMIPS_LO16 foo
+[ 0-9a-f]+: 60a1 a400 prefe 0x5,0\(\$1\)
+#pass
diff --git a/gas/testsuite/gas/mips/micromipsr6@jal-mask-11.d b/gas/testsuite/gas/mips/micromipsr6@jal-mask-11.d
new file mode 100644
index 00000000000..b8ebd8ca79f
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@jal-mask-11.d
@@ -0,0 +1,19 @@
+#objdump: -dr --prefix-addresses --show-raw-insn --adjust-vma=0x55555550
+#name: MIPS jal mask 1.1
+#as: -32
+#source: jal-mask-1.s
+
+# Check address masks for JAL/J instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+55555550 <[^>]*> 9400 0000 bc 55555554 <[^>]*>
+ 55555550: R_MICROMIPS_PC26_S1 \*ABS\*
+55555554 <[^>]*> 9555 5556 bc 58000004 <[^>]*>
+ 55555554: R_MICROMIPS_PC26_S1 \*ABS\*
+55555558 <[^>]*> b400 0000 balc 5555555c <[^>]*>
+ 55555558: R_MICROMIPS_PC26_S1 \*ABS\*
+5555555c <[^>]*> b555 5556 balc 5800000c <[^>]*>
+ 5555555c: R_MICROMIPS_PC26_S1 \*ABS\*
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@jal-mask-12.d b/gas/testsuite/gas/mips/micromipsr6@jal-mask-12.d
new file mode 100644
index 00000000000..3ed412fe0a3
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@jal-mask-12.d
@@ -0,0 +1,19 @@
+#objdump: -dr --prefix-addresses --show-raw-insn --adjust-vma=0xaaaaaaa0
+#name: MIPS jal mask 1.2
+#as: -32
+#source: jal-mask-1.s
+
+# Check address masks for JAL/J instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+aaaaaaa0 <[^>]*> 9400 0000 bc aaaaaaa4 <[^>]*>
+ aaaaaaa0: R_MICROMIPS_PC26_S1 \*ABS\*
+aaaaaaa4 <[^>]*> 9555 5556 bc ad555554 <[^>]*>
+ aaaaaaa4: R_MICROMIPS_PC26_S1 \*ABS\*
+aaaaaaa8 <[^>]*> b400 0000 balc aaaaaaac <[^>]*>
+ aaaaaaa8: R_MICROMIPS_PC26_S1 \*ABS\*
+aaaaaaac <[^>]*> b555 5556 balc ad55555c <[^>]*>
+ aaaaaaac: R_MICROMIPS_PC26_S1 \*ABS\*
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@jal-range.l b/gas/testsuite/gas/mips/micromipsr6@jal-range.l
new file mode 100644
index 00000000000..cde93c16c06
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@jal-range.l
@@ -0,0 +1,8 @@
+.*: Assembler messages:
+.*:4: Error: branch to misaligned address \(0x1\)
+.*:5: Error: branch address range overflow \(0xffffffc\)
+.*:6: Error: branch to misaligned address \(0xfffffff\)
+.*:6: Error: branch address range overflow \(0xfffffff\)
+.*:7: Error: branch address range overflow \(0x10000000\)
+.*:8: Error: branch to misaligned address \(0x10000003\)
+.*:8: Error: branch address range overflow \(0x10000003\)
diff --git a/gas/testsuite/gas/mips/micromipsr6@jal-range.s b/gas/testsuite/gas/mips/micromipsr6@jal-range.s
new file mode 100644
index 00000000000..cd6cde040f5
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@jal-range.s
@@ -0,0 +1,8 @@
+# Source file used to test misaligned targets of absolute jumps
+
+ jal 0x0
+ jal 0x1
+ jal 0xffffffc
+ jal 0xfffffff
+ jal 0x10000000
+ jal 0x10000003
diff --git a/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local-n32.d b/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local-n32.d
new file mode 100644
index 00000000000..da2266fde7b
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local-n32.d
@@ -0,0 +1,32 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS JALR relocation against local symbol (n32)
+#as: -n32
+#source: jal-svr4pic-local-newabi.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4ff9 addiu sp,sp,-16
+[0-9a-f]+ <[^>]*> db9d 0000 sd gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 1380 0000 lui gp,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 foo
+[ ]*[0-9a-f]+: R_MICROMIPS_SUB \*ABS\*
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 \*ABS\*
+[0-9a-f]+ <[^>]*> 339c 0000 addiu gp,gp,0
+[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 foo
+[ ]*[0-9a-f]+: R_MICROMIPS_SUB \*ABS\*
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \*ABS\*
+[0-9a-f]+ <[^>]*> 033c e150 addu gp,gp,t9
+[0-9a-f]+ <[^>]*> dbfd 0008 sd ra,8\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT_DISP \.text\+0x31
+[0-9a-f]+ <[^>]*> 03f9 0f3c jalrc t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR \.text\+0x31
+[0-9a-f]+ <[^>]*> dffd 0008 ld ra,8\(sp\)
+[0-9a-f]+ <[^>]*> df9d 0000 ld gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 4c09 addiu sp,sp,16
+[0-9a-f]+ <[^>]*> 47e3 jrc ra
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
+[0-9a-f]+ <[^>]*> 47e3 jrc ra
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local-n64.d b/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local-n64.d
new file mode 100644
index 00000000000..0a0d46279f1
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local-n64.d
@@ -0,0 +1,36 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS JALR relocation against local symbol (n64)
+#as: -64
+#source: jal-svr4pic-local-newabi.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4ff9 addiu sp,sp,-16
+[0-9a-f]+ <[^>]*> db9d 0000 sd gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 1380 0000 lui gp,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 foo
+[ ]*[0-9a-f]+: R_MICROMIPS_SUB \*ABS\*
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 \*ABS\*
+[0-9a-f]+ <[^>]*> 339c 0000 addiu gp,gp,0
+[ ]*[0-9a-f]+: R_MICROMIPS_GPREL16 foo
+[ ]*[0-9a-f]+: R_MICROMIPS_SUB \*ABS\*
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \*ABS\*
+[0-9a-f]+ <[^>]*> 5b3c e150 daddu gp,gp,t9
+[0-9a-f]+ <[^>]*> dbfd 0008 sd ra,8\(sp\)
+[0-9a-f]+ <[^>]*> df3c 0000 ld t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT_DISP \.text\+0x31
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x31
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x31
+[0-9a-f]+ <[^>]*> 03f9 0f3c jalrc t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR \.text\+0x31
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x31
+[ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*\+0x31
+[0-9a-f]+ <[^>]*> dffd 0008 ld ra,8\(sp\)
+[0-9a-f]+ <[^>]*> df9d 0000 ld gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 4c09 addiu sp,sp,16
+[0-9a-f]+ <[^>]*> 47e3 jrc ra
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
+[0-9a-f]+ <[^>]*> 47e3 jrc ra
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local.d b/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local.d
new file mode 100644
index 00000000000..9038aaab6c8
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-local.d
@@ -0,0 +1,31 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS JALR relocation against local symbol
+#as: -32
+#not-target: *-*-irix*
+#source: jal-svr4pic-local.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1380 0000 lui gp,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 _gp_disp
+[0-9a-f]+ <[^>]*> 339c 0000 addiu gp,gp,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 _gp_disp
+[0-9a-f]+ <[^>]*> 033c e150 addu gp,gp,t9
+[0-9a-f]+ <[^>]*> 4ff1 addiu sp,sp,-32
+[0-9a-f]+ <[^>]*> cbe7 sw ra,28\(sp\)
+[0-9a-f]+ <[^>]*> fb9d 0010 sw gp,16\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 bar
+[0-9a-f]+ <[^>]*> 3339 0000 addiu t9,t9,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 bar
+[0-9a-f]+ <[^>]*> 03f9 0f3c jalrc t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR bar
+[0-9a-f]+ <[^>]*> ff9d 0010 lw gp,16\(sp\)
+[0-9a-f]+ <[^>]*> 4be7 lw ra,28\(sp\)
+[0-9a-f]+ <[^>]*> 4c11 addiu sp,sp,32
+[0-9a-f]+ <[^>]*> 47e3 jrc ra
+[0-9a-f]+ <[^>]*> 0000 0000 nop
+ \.\.\.
+[0-9a-f]+ <[^>]*> 47e3 jrc ra
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-noreorder.d b/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-noreorder.d
new file mode 100644
index 00000000000..d9a75bee0a6
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic-noreorder.d
@@ -0,0 +1,41 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS jal-svr4pic noreorder
+#as: -32 -KPIC
+#source: jal-svr4pic-noreorder.s
+
+# Test the jal macro with -KPIC and `.set noreorder' (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1380 0000 lui gp,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 _gp_disp
+[0-9a-f]+ <[^>]*> 339c 0000 addiu gp,gp,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 _gp_disp
+[0-9a-f]+ <[^>]*> 033c e150 addu gp,gp,t9
+[0-9a-f]+ <[^>]*> fb9d 0000 sw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 472b jalrc t9
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 0099 0f3c jalrc a0,t9
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 text_label
+[0-9a-f]+ <[^>]*> 3339 0000 addiu t9,t9,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 text_label
+[0-9a-f]+ <[^>]*> 03f9 0f3c jalrc t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR text_label
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_CALL16 weak_text_label
+[0-9a-f]+ <[^>]*> 03f9 0f3c jalrc t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR weak_text_label
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_CALL16 external_text_label
+[0-9a-f]+ <[^>]*> 03f9 0f3c jalrc t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR external_text_label
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+([0-9a-f]+) <[^>]*> 97ff fffe bc \1 <.*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic.d b/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic.d
new file mode 100644
index 00000000000..8f90574ec70
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@jal-svr4pic.d
@@ -0,0 +1,41 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS jal-svr4pic
+#as: -32 -KPIC
+#source: jal-svr4pic.s
+
+# Test the jal macro with -KPIC (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1380 0000 lui gp,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 _gp_disp
+[0-9a-f]+ <[^>]*> 339c 0000 addiu gp,gp,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 _gp_disp
+[0-9a-f]+ <[^>]*> 033c e150 addu gp,gp,t9
+[0-9a-f]+ <[^>]*> fb9d 0000 sw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 472b jalrc t9
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> 0099 0f3c jalrc a0,t9
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 text_label
+[0-9a-f]+ <[^>]*> 3339 0000 addiu t9,t9,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 text_label
+[0-9a-f]+ <[^>]*> 03f9 0f3c jalrc t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR text_label
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_CALL16 weak_text_label
+[0-9a-f]+ <[^>]*> 03f9 0f3c jalrc t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR weak_text_label
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+[0-9a-f]+ <[^>]*> ff3c 0000 lw t9,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_CALL16 external_text_label
+[0-9a-f]+ <[^>]*> 03f9 0f3c jalrc t9
+[ ]*[0-9a-f]+: R_MICROMIPS_JALR external_text_label
+[0-9a-f]+ <[^>]*> ff9d 0000 lw gp,0\(sp\)
+([0-9a-f]+) <[^>]*> 93fe 0000 slti ra,s8,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@jal.d b/gas/testsuite/gas/mips/micromipsr6@jal.d
new file mode 100644
index 00000000000..ce1398dc3a8
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@jal.d
@@ -0,0 +1,22 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS ELF jal
+#source: jal.s
+#as: -32
+
+# Test the jal macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 472b jalrc t9
+[0-9a-f]+ <[^>]*> 0099 0f3c jalrc a0,t9
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ 6: R_MICROMIPS_PC26_S1 text_label
+[0-9a-f]+ <[^>]*> b3fe 0000 sltiu ra,s8,0
+ a: R_MICROMIPS_PC26_S1 external_text_label
+[0-9a-f]+ <[^>]*> 93fe 0000 slti ra,s8,0
+ e: R_MICROMIPS_PC26_S1 text_label
+[0-9a-f]+ <[^>]*> 93fe 0000 slti ra,s8,0
+ 12: R_MICROMIPS_PC26_S1 external_text_label
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@lb-svr4pic-ilocks.d b/gas/testsuite/gas/mips/micromipsr6@lb-svr4pic-ilocks.d
new file mode 100644
index 00000000000..5a24e0dcc43
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@lb-svr4pic-ilocks.d
@@ -0,0 +1,155 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS lb-svr4pic-ilocks
+#source: lb-pic.s
+#as: -32 -KPIC
+
+# Test the lb macro with -KPIC (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1c80 0000 lb a0,0\(zero\)
+[0-9a-f]+ <[^>]*> 1c80 0001 lb a0,1\(zero\)
+[0-9a-f]+ <[^>]*> 1080 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 1c84 8000 lb a0,-32768\(a0\)
+[0-9a-f]+ <[^>]*> 1c80 8000 lb a0,-32768\(zero\)
+[0-9a-f]+ <[^>]*> 1080 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> 1080 0002 lui a0,0x2
+[0-9a-f]+ <[^>]*> 1c84 a5a5 lb a0,-23131\(a0\)
+[0-9a-f]+ <[^>]*> 1c85 0000 lb a0,0\(a1\)
+[0-9a-f]+ <[^>]*> 1c85 0001 lb a0,1\(a1\)
+[0-9a-f]+ <[^>]*> 1080 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 8000 lb a0,-32768\(a0\)
+[0-9a-f]+ <[^>]*> 1c85 8000 lb a0,-32768\(a1\)
+[0-9a-f]+ <[^>]*> 1080 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> 1080 0002 lui a0,0x2
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 a5a5 lb a0,-23131\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 data_label
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 data_label
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_data_label
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_data_label
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_common
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_common
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_local_common
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 big_local_common
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_local_common
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 small_local_common
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 data_label
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 data_label
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_data_label
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_data_label
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_common
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_common
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_local_common
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 big_local_common
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_local_common
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 small_local_common
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 data_label
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 data_label
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_data_label
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_data_label
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_local_common
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 big_local_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_local_common
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 small_local_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0000 lb a0,0\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 data_label
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 data_label
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_data_label
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_data_label
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_external_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_external_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 big_local_common
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 big_local_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> fc9c 0000 lw a0,0\(gp\)
+[ ]*[0-9a-f]+: R_MICROMIPS_GOT16 small_local_common
+[0-9a-f]+ <[^>]*> 3084 0000 addiu a0,a0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 small_local_common
+[0-9a-f]+ <[^>]*> 00a4 2150 addu a0,a0,a1
+[0-9a-f]+ <[^>]*> 1c84 0001 lb a0,1\(a0\)
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
diff --git a/gas/testsuite/gas/mips/micromipsr6@ld-zero-2.d b/gas/testsuite/gas/mips/micromipsr6@ld-zero-2.d
new file mode 100644
index 00000000000..2b1344f8ba2
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@ld-zero-2.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses
+#as: -32
+#name: MIPS II load $zero
+#source: ld-zero-2.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> lui at,0x1234
+[0-9a-f]+ <[^>]*> ori at,at,0x5600
+[0-9a-f]+ <[^>]*> addu at,at,v0
+[0-9a-f]+ <[^>]*> ll zero,120\(at\)
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@ld-zero-3.d b/gas/testsuite/gas/mips/micromipsr6@ld-zero-3.d
new file mode 100644
index 00000000000..c5b880c6294
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@ld-zero-3.d
@@ -0,0 +1,21 @@
+#objdump: -dr --prefix-addresses
+#as: -32
+#name: MIPS III load $zero
+#source: ld-zero-3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> lui at,0x1234
+[0-9a-f]+ <[^>]*> ori at,at,0x5000
+[0-9a-f]+ <[^>]*> addu at,at,v0
+[0-9a-f]+ <[^>]*> lwu zero,1656\(at\)
+[0-9a-f]+ <[^>]*> lui at,0x1234
+[0-9a-f]+ <[^>]*> addu at,v0,at
+[0-9a-f]+ <[^>]*> lw zero,22136\(at\)
+[0-9a-f]+ <[^>]*> lw at,22140\(at\)
+[0-9a-f]+ <[^>]*> lui at,0x1234
+[0-9a-f]+ <[^>]*> ori at,at,0x5600
+[0-9a-f]+ <[^>]*> addu at,at,v0
+[0-9a-f]+ <[^>]*> lld zero,120\(at\)
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@ldpc-unalign.l b/gas/testsuite/gas/mips/micromipsr6@ldpc-unalign.l
new file mode 100644
index 00000000000..5c9a458960a
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@ldpc-unalign.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*:2: Error: PC-relative access using misaligned offset \(4\)
+.*:3: Error: PC-relative access using misaligned offset \(4\)
+.*:4: Error: PC-relative access using misaligned symbol \(1a\)
+.*:5: Error: PC-relative access using misaligned symbol \(1a\)
+.*:6: Error: PC-relative access using misaligned symbol \(1a\)
+.*:6: Error: PC-relative access using misaligned offset \(4\)
+.*:7: Error: PC-relative access using misaligned symbol \(1a\)
+.*:7: Error: PC-relative access using misaligned offset \(4\)
diff --git a/gas/testsuite/gas/mips/micromipsr6@ldpc-unalign.s b/gas/testsuite/gas/mips/micromipsr6@ldpc-unalign.s
new file mode 100644
index 00000000000..ce81c472bb9
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@ldpc-unalign.s
@@ -0,0 +1,18 @@
+ .text
+ ldpc $4, 1f+4
+ ldpc $4, 1f+4
+ ldpc $4, 2f
+ ldpc $4, 2f
+ ldpc $4, 2f+4
+ ldpc $4, 2f+4
+ .align 3
+1:
+ nop
+2:
+ nop
+ nop
+ nop
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
diff --git a/gas/testsuite/gas/mips/micromipsr6@li.d b/gas/testsuite/gas/mips/micromipsr6@li.d
new file mode 100644
index 00000000000..05b6dbfd113
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@li.d
@@ -0,0 +1,18 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS li
+#source: li.s
+#as: -32
+
+# Test the li macro (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> ee00 li a0,0
+[0-9a-f]+ <[^>]*> ee01 li a0,1
+[0-9a-f]+ <[^>]*> 5080 8000 li a0,0x8000
+[0-9a-f]+ <[^>]*> 3080 8000 li a0,-32768
+[0-9a-f]+ <[^>]*> 1080 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 1080 0001 lui a0,0x1
+[0-9a-f]+ <[^>]*> 5084 a5a5 ori a0,a0,0xa5a5
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@lui.d b/gas/testsuite/gas/mips/micromipsr6@lui.d
new file mode 100644
index 00000000000..62ebd2d87d9
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@lui.d
@@ -0,0 +1,25 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS lui
+#as: -32
+#source: lui.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1040 0000 lui v0,0x0
+[0-9a-f]+ <[^>]*> 1040 ffff lui v0,0xffff
+[0-9a-f]+ <[^>]*> 1040 0008 lui v0,0x8
+[0-9a-f]+ <[^>]*> 1040 0008 lui v0,0x8
+[0-9a-f]+ <[^>]*> 1040 000c lui v0,0xc
+[0-9a-f]+ <[^>]*> 1040 000c lui v0,0xc
+[0-9a-f]+ <[^>]*> 1040 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 bar
+[0-9a-f]+ <[^>]*> 1040 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 ext
+[0-9a-f]+ <[^>]*> 1040 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.L3\^B1
+[0-9a-f]+ <[^>]*> 1040 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 \.L4\^B1
+[0-9a-f]+ <[^>]*> 1040 0000 lui v0,0x0
+[0-9a-f]+ <[^>]*> 1040 ffff lui v0,0xffff
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mcu.d b/gas/testsuite/gas/mips/micromipsr6@mcu.d
new file mode 100644
index 00000000000..957d4477ac2
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mcu.d
@@ -0,0 +1,110 @@
+#objdump: -dr --show-raw-insn
+#name: MCU for MIPS32r2
+#as: -32
+#source: mcu.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+
+[0-9a-f]+ <foo>:
+[ 0-9a-f]+: 0000 d37c iret
+[ 0-9a-f]+: 2000 b000 aclr 0x0,0\(zero\)
+[ 0-9a-f]+: 2000 b000 aclr 0x0,0\(zero\)
+[ 0-9a-f]+: 2000 b000 aclr 0x0,0\(zero\)
+[ 0-9a-f]+: 2020 b000 aclr 0x1,0\(zero\)
+[ 0-9a-f]+: 2040 b000 aclr 0x2,0\(zero\)
+[ 0-9a-f]+: 2060 b000 aclr 0x3,0\(zero\)
+[ 0-9a-f]+: 2080 b000 aclr 0x4,0\(zero\)
+[ 0-9a-f]+: 20a0 b000 aclr 0x5,0\(zero\)
+[ 0-9a-f]+: 20c0 b000 aclr 0x6,0\(zero\)
+[ 0-9a-f]+: 20e0 b000 aclr 0x7,0\(zero\)
+[ 0-9a-f]+: 20e2 b000 aclr 0x7,0\(v0\)
+[ 0-9a-f]+: 20ff b000 aclr 0x7,0\(ra\)
+[ 0-9a-f]+: 20ff b7ff aclr 0x7,2047\(ra\)
+[ 0-9a-f]+: 20ff b800 aclr 0x7,-2048\(ra\)
+[ 0-9a-f]+: 303f 0800 addiu at,ra,2048
+[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
+[ 0-9a-f]+: 303f f7ff addiu at,ra,-2049
+[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
+[ 0-9a-f]+: 303f 7fff addiu at,ra,32767
+[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
+[ 0-9a-f]+: 303f 8000 addiu at,ra,-32768
+[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 bfff aclr 0x7,-1\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 b001 aclr 0x7,1\(at\)
+[ 0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 b000 aclr 0x7,0\(at\)
+[ 0-9a-f]+: 20e4 bfff aclr 0x7,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 b678 aclr 0x7,1656\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 foo
+[ 0-9a-f]+: 2021 b000 aclr 0x1,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 foo
+[ 0-9a-f]+: 2021 3000 aset 0x1,0\(at\)
+[ 0-9a-f]+: 2000 3000 aset 0x0,0\(zero\)
+[ 0-9a-f]+: 2000 3000 aset 0x0,0\(zero\)
+[ 0-9a-f]+: 2000 3000 aset 0x0,0\(zero\)
+[ 0-9a-f]+: 2020 3000 aset 0x1,0\(zero\)
+[ 0-9a-f]+: 2040 3000 aset 0x2,0\(zero\)
+[ 0-9a-f]+: 2060 3000 aset 0x3,0\(zero\)
+[ 0-9a-f]+: 2080 3000 aset 0x4,0\(zero\)
+[ 0-9a-f]+: 20a0 3000 aset 0x5,0\(zero\)
+[ 0-9a-f]+: 20c0 3000 aset 0x6,0\(zero\)
+[ 0-9a-f]+: 20e0 3000 aset 0x7,0\(zero\)
+[ 0-9a-f]+: 20e2 3000 aset 0x7,0\(v0\)
+[ 0-9a-f]+: 20ff 3000 aset 0x7,0\(ra\)
+[ 0-9a-f]+: 20ff 37ff aset 0x7,2047\(ra\)
+[ 0-9a-f]+: 20ff 3800 aset 0x7,-2048\(ra\)
+[ 0-9a-f]+: 303f 0800 addiu at,ra,2048
+[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
+[ 0-9a-f]+: 303f f7ff addiu at,ra,-2049
+[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
+[ 0-9a-f]+: 303f 7fff addiu at,ra,32767
+[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
+[ 0-9a-f]+: 303f 8000 addiu at,ra,-32768
+[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 3fff aset 0x7,-1\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 3001 aset 0x7,1\(at\)
+[ 0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 3000 aset 0x7,0\(at\)
+[ 0-9a-f]+: 20e4 3fff aset 0x7,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 20e1 3678 aset 0x7,1656\(at\)
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@micromips-insn32.d b/gas/testsuite/gas/mips/micromipsr6@micromips-insn32.d
new file mode 100644
index 00000000000..66147ebfd6e
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@micromips-insn32.d
@@ -0,0 +1,4448 @@
+#objdump: -drz --show-raw-insn
+#name: microMIPS for MIPS32r6 (insn32 mode)
+#as: -32 -mfp64 -minsn32 -EB --defsym insn32=1
+#source: micromips.s
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <test>:
+[ 0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+[ 0-9a-f]+: 6000 20ff pref 0x0,255\(zero\)
+[ 0-9a-f]+: 6000 2100 pref 0x0,-256\(zero\)
+[ 0-9a-f]+: 3020 0100 li at,256
+[ 0-9a-f]+: 6001 2000 pref 0x0,0\(at\)
+[ 0-9a-f]+: 3020 feff li at,-257
+[ 0-9a-f]+: 6001 2000 pref 0x0,0\(at\)
+[ 0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+[ 0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+[ 0-9a-f]+: 6020 2000 pref 0x1,0\(zero\)
+[ 0-9a-f]+: 6040 2000 pref 0x2,0\(zero\)
+[ 0-9a-f]+: 6060 2000 pref 0x3,0\(zero\)
+[ 0-9a-f]+: 6080 2000 pref 0x4,0\(zero\)
+[ 0-9a-f]+: 60a0 2000 pref 0x5,0\(zero\)
+[ 0-9a-f]+: 60c0 2000 pref 0x6,0\(zero\)
+[ 0-9a-f]+: 60e0 2000 pref 0x7,0\(zero\)
+[ 0-9a-f]+: 60e0 207f pref 0x7,127\(zero\)
+[ 0-9a-f]+: 60e0 2180 pref 0x7,-128\(zero\)
+[ 0-9a-f]+: 63e0 20ff pref 0x1f,255\(zero\)
+[ 0-9a-f]+: 63e0 2100 pref 0x1f,-256\(zero\)
+[ 0-9a-f]+: 3020 0100 li at,256
+[ 0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
+[ 0-9a-f]+: 3020 feff li at,-257
+[ 0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+[ 0-9a-f]+: 63e2 20ff pref 0x1f,255\(v0\)
+[ 0-9a-f]+: 63e2 2100 pref 0x1f,-256\(v0\)
+[ 0-9a-f]+: 3022 0100 addiu at,v0,256
+[ 0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
+[ 0-9a-f]+: 3022 feff addiu at,v0,-257
+[ 0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
+[ 0-9a-f]+: 3022 7fff addiu at,v0,32767
+[ 0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+[ 0-9a-f]+: 3022 8000 addiu at,v0,-32768
+[ 0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0000 0800 ssnop
+[ 0-9a-f]+: 0000 1800 ehb
+[ 0-9a-f]+: 0000 2800 pause
+[ 0-9a-f]+: 3040 ffff li v0,-1
+[ 0-9a-f]+: 3060 ffff li v1,-1
+[ 0-9a-f]+: 3080 ffff li a0,-1
+[ 0-9a-f]+: 30a0 ffff li a1,-1
+[ 0-9a-f]+: 30c0 ffff li a2,-1
+[ 0-9a-f]+: 30e0 ffff li a3,-1
+[ 0-9a-f]+: 3200 ffff li s0,-1
+[ 0-9a-f]+: 3220 ffff li s1,-1
+[ 0-9a-f]+: 3220 0000 li s1,0
+[ 0-9a-f]+: 3220 007d li s1,125
+[ 0-9a-f]+: 3220 007e li s1,126
+[ 0-9a-f]+: 3220 007f li s1,127
+[ 0-9a-f]+: 3040 0000 li v0,0
+[ 0-9a-f]+: 3040 0001 li v0,1
+[ 0-9a-f]+: 3040 7fff li v0,32767
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 5040 ffff li v0,0xffff
+[ 0-9a-f]+: 1040 0001 lui v0,0x1
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 3040 8001 li v0,-32767
+[ 0-9a-f]+: 3040 ffff li v0,-1
+[ 0-9a-f]+: 1040 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5678 ori v0,v0,0x5678
+[ 0-9a-f]+: 0016 0290 move zero,s6
+[ 0-9a-f]+: 0016 1290 move v0,s6
+[ 0-9a-f]+: 0016 1a90 move v1,s6
+[ 0-9a-f]+: 0016 2290 move a0,s6
+[ 0-9a-f]+: 0016 2a90 move a1,s6
+[ 0-9a-f]+: 0016 3290 move a2,s6
+[ 0-9a-f]+: 0016 3a90 move a3,s6
+[ 0-9a-f]+: 0016 4290 move t0,s6
+[ 0-9a-f]+: 0016 4a90 move t1,s6
+[ 0-9a-f]+: 0016 5290 move t2,s6
+[ 0-9a-f]+: 0016 f290 move s8,s6
+[ 0-9a-f]+: 0016 fa90 move ra,s6
+[ 0-9a-f]+: 0000 0290 move zero,zero
+[ 0-9a-f]+: 0002 0290 move zero,v0
+[ 0-9a-f]+: 0003 0290 move zero,v1
+[ 0-9a-f]+: 0004 0290 move zero,a0
+[ 0-9a-f]+: 0005 0290 move zero,a1
+[ 0-9a-f]+: 0006 0290 move zero,a2
+[ 0-9a-f]+: 0007 0290 move zero,a3
+[ 0-9a-f]+: 0008 0290 move zero,t0
+[ 0-9a-f]+: 0009 0290 move zero,t1
+[ 0-9a-f]+: 000a 0290 move zero,t2
+[ 0-9a-f]+: 001e 0290 move zero,s8
+[ 0-9a-f]+: 001f 0290 move zero,ra
+[ 0-9a-f]+: 0002 b290 move s6,v0
+[ 0-9a-f]+: 0016 1290 move v0,s6
+[ 0-9a-f]+: 0002 b290 move s6,v0
+[ 0-9a-f]+: 93fe 0000 slti ra,s8,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 test
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 93fe 0000 slti ra,s8,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 test
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 93fe 0000 slti ra,s8,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 \.L1\^B1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 93fe 0000 slti ra,s8,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 \.L1\^B1
+
+[0-9a-f]+ <\.L1\^B1>:
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 93fe 0000 slti ra,s8,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 \.L1\^B1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 93fe 0000 slti ra,s8,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 \.L1\^B1
+[ 0-9a-f]+: 0003 1290 move v0,v1
+[ 0-9a-f]+: f463 fffe bgezc v1,1a4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_0
+[ 0-9a-f]+: 0060 1190 neg v0,v1
+
+[0-9a-f]+ <\.L\^\_0>:
+[ 0-9a-f]+: 0004 1290 move v0,a0
+[ 0-9a-f]+: f484 fffe bgezc a0,1b0 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_1
+[ 0-9a-f]+: 0080 1190 neg v0,a0
+
+[0-9a-f]+ <\.L\^\_1>:
+[ 0-9a-f]+: f442 fffe bgezc v0,1b8 <\.L\^\_1>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_2
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+
+[0-9a-f]+ <\.L\^\_2>:
+[ 0-9a-f]+: f442 fffe bgezc v0,1c0 <\.L\^\_2>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_3
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+
+[0-9a-f]+ <\.L\^\_3>:
+[ 0-9a-f]+: 0083 1110 add v0,v1,a0
+[ 0-9a-f]+: 03fe e910 add sp,s8,ra
+[ 0-9a-f]+: 0082 1110 add v0,v0,a0
+[ 0-9a-f]+: 0082 1110 add v0,v0,a0
+[ 0-9a-f]+: 3000 fff8 li zero,-8
+[ 0-9a-f]+: 3042 fff8 addiu v0,v0,-8
+[ 0-9a-f]+: 3063 fff8 addiu v1,v1,-8
+[ 0-9a-f]+: 3084 fff8 addiu a0,a0,-8
+[ 0-9a-f]+: 30a5 fff8 addiu a1,a1,-8
+[ 0-9a-f]+: 30c6 fff8 addiu a2,a2,-8
+[ 0-9a-f]+: 30e7 fff8 addiu a3,a3,-8
+[ 0-9a-f]+: 3108 fff8 addiu t0,t0,-8
+[ 0-9a-f]+: 3129 fff8 addiu t1,t1,-8
+[ 0-9a-f]+: 314a fff8 addiu t2,t2,-8
+[ 0-9a-f]+: 33de fff8 addiu s8,s8,-8
+[ 0-9a-f]+: 33ff fff8 addiu ra,ra,-8
+[ 0-9a-f]+: 33ff fff9 addiu ra,ra,-7
+[ 0-9a-f]+: 33ff 0000 addiu ra,ra,0
+[ 0-9a-f]+: 33ff 0001 addiu ra,ra,1
+[ 0-9a-f]+: 33ff 0006 addiu ra,ra,6
+[ 0-9a-f]+: 33ff 0007 addiu ra,ra,7
+[ 0-9a-f]+: 33ff 0008 addiu ra,ra,8
+[ 0-9a-f]+: 33bd fbf8 addiu sp,sp,-1032
+[ 0-9a-f]+: 33bd fbfc addiu sp,sp,-1028
+[ 0-9a-f]+: 33bd fc00 addiu sp,sp,-1024
+[ 0-9a-f]+: 33bd 03fc addiu sp,sp,1020
+[ 0-9a-f]+: 33bd 0400 addiu sp,sp,1024
+[ 0-9a-f]+: 33bd 0404 addiu sp,sp,1028
+[ 0-9a-f]+: 33bd 0404 addiu sp,sp,1028
+[ 0-9a-f]+: 33bd 0408 addiu sp,sp,1032
+[ 0-9a-f]+: 3042 ffff addiu v0,v0,-1
+[ 0-9a-f]+: 3043 ffff addiu v0,v1,-1
+[ 0-9a-f]+: 3044 ffff addiu v0,a0,-1
+[ 0-9a-f]+: 3045 ffff addiu v0,a1,-1
+[ 0-9a-f]+: 3046 ffff addiu v0,a2,-1
+[ 0-9a-f]+: 3047 ffff addiu v0,a3,-1
+[ 0-9a-f]+: 3050 ffff addiu v0,s0,-1
+[ 0-9a-f]+: 3051 ffff addiu v0,s1,-1
+[ 0-9a-f]+: 3051 0001 addiu v0,s1,1
+[ 0-9a-f]+: 3051 0004 addiu v0,s1,4
+[ 0-9a-f]+: 3051 0008 addiu v0,s1,8
+[ 0-9a-f]+: 3051 000c addiu v0,s1,12
+[ 0-9a-f]+: 3051 0010 addiu v0,s1,16
+[ 0-9a-f]+: 3051 0014 addiu v0,s1,20
+[ 0-9a-f]+: 3051 0018 addiu v0,s1,24
+[ 0-9a-f]+: 3071 0018 addiu v1,s1,24
+[ 0-9a-f]+: 3091 0018 addiu a0,s1,24
+[ 0-9a-f]+: 30b1 0018 addiu a1,s1,24
+[ 0-9a-f]+: 30d1 0018 addiu a2,s1,24
+[ 0-9a-f]+: 30f1 0018 addiu a3,s1,24
+[ 0-9a-f]+: 3211 0018 addiu s0,s1,24
+[ 0-9a-f]+: 3231 0018 addiu s1,s1,24
+[ 0-9a-f]+: 305d 0000 addiu v0,sp,0
+[ 0-9a-f]+: 305d 0004 addiu v0,sp,4
+[ 0-9a-f]+: 305d 00f8 addiu v0,sp,248
+[ 0-9a-f]+: 305d 00fc addiu v0,sp,252
+[ 0-9a-f]+: 305d 0100 addiu v0,sp,256
+[ 0-9a-f]+: 305d 00fc addiu v0,sp,252
+[ 0-9a-f]+: 307d 00fc addiu v1,sp,252
+[ 0-9a-f]+: 309d 00fc addiu a0,sp,252
+[ 0-9a-f]+: 30bd 00fc addiu a1,sp,252
+[ 0-9a-f]+: 30dd 00fc addiu a2,sp,252
+[ 0-9a-f]+: 30fd 00fc addiu a3,sp,252
+[ 0-9a-f]+: 321d 00fc addiu s0,sp,252
+[ 0-9a-f]+: 323d 00fc addiu s1,sp,252
+[ 0-9a-f]+: 3064 8000 addiu v1,a0,-32768
+[ 0-9a-f]+: 3064 0000 addiu v1,a0,0
+[ 0-9a-f]+: 3064 7fff addiu v1,a0,32767
+[ 0-9a-f]+: 3064 ffff addiu v1,a0,-1
+[ 0-9a-f]+: 3063 ffff addiu v1,v1,-1
+[ 0-9a-f]+: 3063 ffff addiu v1,v1,-1
+[ 0-9a-f]+: 0016 1150 move v0,s6
+[ 0-9a-f]+: 0002 b150 move s6,v0
+[ 0-9a-f]+: 02c0 1150 addu v0,zero,s6
+[ 0-9a-f]+: 0040 b150 addu s6,zero,v0
+[ 0-9a-f]+: 0043 1150 addu v0,v1,v0
+[ 0-9a-f]+: 0063 1150 addu v0,v1,v1
+[ 0-9a-f]+: 0083 1150 addu v0,v1,a0
+[ 0-9a-f]+: 00a3 1150 addu v0,v1,a1
+[ 0-9a-f]+: 00c3 1150 addu v0,v1,a2
+[ 0-9a-f]+: 00e3 1150 addu v0,v1,a3
+[ 0-9a-f]+: 0203 1150 addu v0,v1,s0
+[ 0-9a-f]+: 0223 1150 addu v0,v1,s1
+[ 0-9a-f]+: 0222 1150 addu v0,v0,s1
+[ 0-9a-f]+: 0223 1150 addu v0,v1,s1
+[ 0-9a-f]+: 0224 1150 addu v0,a0,s1
+[ 0-9a-f]+: 0225 1150 addu v0,a1,s1
+[ 0-9a-f]+: 0226 1150 addu v0,a2,s1
+[ 0-9a-f]+: 0227 1150 addu v0,a3,s1
+[ 0-9a-f]+: 0230 1150 addu v0,s0,s1
+[ 0-9a-f]+: 0231 1150 addu v0,s1,s1
+[ 0-9a-f]+: 0222 1150 addu v0,v0,s1
+[ 0-9a-f]+: 0222 1950 addu v1,v0,s1
+[ 0-9a-f]+: 0222 2150 addu a0,v0,s1
+[ 0-9a-f]+: 0222 2950 addu a1,v0,s1
+[ 0-9a-f]+: 0222 3150 addu a2,v0,s1
+[ 0-9a-f]+: 0222 3950 addu a3,v0,s1
+[ 0-9a-f]+: 0222 8150 addu s0,v0,s1
+[ 0-9a-f]+: 0222 8950 addu s1,v0,s1
+[ 0-9a-f]+: 0047 3950 addu a3,a3,v0
+[ 0-9a-f]+: 0047 3950 addu a3,a3,v0
+[ 0-9a-f]+: 00e2 3950 addu a3,v0,a3
+[ 0-9a-f]+: 03fe e950 addu sp,s8,ra
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ 0-9a-f]+: 3042 0001 addiu v0,v0,1
+[ 0-9a-f]+: 3042 7fff addiu v0,v0,32767
+[ 0-9a-f]+: 3042 8000 addiu v0,v0,-32768
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 1150 addu v0,v0,at
+[ 0-9a-f]+: 0042 1250 and v0,v0,v0
+[ 0-9a-f]+: 0062 1250 and v0,v0,v1
+[ 0-9a-f]+: 0082 1250 and v0,v0,a0
+[ 0-9a-f]+: 00a2 1250 and v0,v0,a1
+[ 0-9a-f]+: 00c2 1250 and v0,v0,a2
+[ 0-9a-f]+: 00e2 1250 and v0,v0,a3
+[ 0-9a-f]+: 0202 1250 and v0,v0,s0
+[ 0-9a-f]+: 0222 1250 and v0,v0,s1
+[ 0-9a-f]+: 0043 1a50 and v1,v1,v0
+[ 0-9a-f]+: 0044 2250 and a0,a0,v0
+[ 0-9a-f]+: 0045 2a50 and a1,a1,v0
+[ 0-9a-f]+: 0046 3250 and a2,a2,v0
+[ 0-9a-f]+: 0047 3a50 and a3,a3,v0
+[ 0-9a-f]+: 0050 8250 and s0,s0,v0
+[ 0-9a-f]+: 0051 8a50 and s1,s1,v0
+[ 0-9a-f]+: 0062 1250 and v0,v0,v1
+[ 0-9a-f]+: 0062 1250 and v0,v0,v1
+[ 0-9a-f]+: 0043 1250 and v0,v1,v0
+[ 0-9a-f]+: 0062 1250 and v0,v0,v1
+[ 0-9a-f]+: d042 0001 andi v0,v0,0x1
+[ 0-9a-f]+: d042 0002 andi v0,v0,0x2
+[ 0-9a-f]+: d042 0003 andi v0,v0,0x3
+[ 0-9a-f]+: d042 0004 andi v0,v0,0x4
+[ 0-9a-f]+: d042 0007 andi v0,v0,0x7
+[ 0-9a-f]+: d042 0008 andi v0,v0,0x8
+[ 0-9a-f]+: d042 000f andi v0,v0,0xf
+[ 0-9a-f]+: d042 0010 andi v0,v0,0x10
+[ 0-9a-f]+: d042 001f andi v0,v0,0x1f
+[ 0-9a-f]+: d042 0020 andi v0,v0,0x20
+[ 0-9a-f]+: d042 003f andi v0,v0,0x3f
+[ 0-9a-f]+: d042 0040 andi v0,v0,0x40
+[ 0-9a-f]+: d042 0080 andi v0,v0,0x80
+[ 0-9a-f]+: d042 00ff andi v0,v0,0xff
+[ 0-9a-f]+: d042 8000 andi v0,v0,0x8000
+[ 0-9a-f]+: d042 ffff andi v0,v0,0xffff
+[ 0-9a-f]+: d043 ffff andi v0,v1,0xffff
+[ 0-9a-f]+: d044 ffff andi v0,a0,0xffff
+[ 0-9a-f]+: d045 ffff andi v0,a1,0xffff
+[ 0-9a-f]+: d046 ffff andi v0,a2,0xffff
+[ 0-9a-f]+: d047 ffff andi v0,a3,0xffff
+[ 0-9a-f]+: d050 ffff andi v0,s0,0xffff
+[ 0-9a-f]+: d051 ffff andi v0,s1,0xffff
+[ 0-9a-f]+: d071 ffff andi v1,s1,0xffff
+[ 0-9a-f]+: d091 ffff andi a0,s1,0xffff
+[ 0-9a-f]+: d0b1 ffff andi a1,s1,0xffff
+[ 0-9a-f]+: d0d1 ffff andi a2,s1,0xffff
+[ 0-9a-f]+: d0f1 ffff andi a3,s1,0xffff
+[ 0-9a-f]+: d211 ffff andi s0,s1,0xffff
+[ 0-9a-f]+: d231 ffff andi s1,s1,0xffff
+[ 0-9a-f]+: d0e7 ffff andi a3,a3,0xffff
+[ 0-9a-f]+: d0e7 ffff andi a3,a3,0xffff
+[ 0-9a-f]+: d0e7 ffff andi a3,a3,0xffff
+[ 0-9a-f]+: 0083 1250 and v0,v1,a0
+[ 0-9a-f]+: 0082 1250 and v0,v0,a0
+[ 0-9a-f]+: 0082 1250 and v0,v0,a0
+[ 0-9a-f]+: d043 0000 andi v0,v1,0x0
+[ 0-9a-f]+: d043 ffff andi v0,v1,0xffff
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1250 and v0,v1,at
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 0001 ori at,at,0x1
+[ 0-9a-f]+: 0023 1250 and v0,v1,at
+
+[0-9a-f]+ <test2>:
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 803e 0000 beqzc at,fffc047c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 805e 0000 beqzc v0,fffc0484 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 807e 0000 beqzc v1,fffc048c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 809e 0000 beqzc a0,fffc0494 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 80be 0000 beqzc a1,fffc049c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 80de 0000 beqzc a2,fffc04a4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 81fe 0000 beqzc t7,fffc04ac <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 821e 0000 beqzc s0,fffc04b4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 803e 0000 beqzc at,fffc04bc <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 805e 0000 beqzc v0,fffc04c4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 807e 0000 beqzc v1,fffc04cc <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 809e 0000 beqzc a0,fffc04d4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 80be 0000 beqzc a1,fffc04dc <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 80de 0000 beqzc a2,fffc04e4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 81fe 0000 beqzc t7,fffc04ec <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 821e 0000 beqzc s0,fffc04f4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 803e 0000 beqzc at,fffc04fc <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 805e 0000 beqzc v0,fffc0504 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 807e 0000 beqzc v1,fffc050c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 809e 0000 beqzc a0,fffc0514 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 80be 0000 beqzc a1,fffc051c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 80de 0000 beqzc a2,fffc0524 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 81fe 0000 beqzc t7,fffc052c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 821e 0000 beqzc s0,fffc0534 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 81fe 0000 beqzc t7,fffc053c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 821e 0000 beqzc s0,fffc0544 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 821e 0000 beqzc s0,fffc054c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 821e 0000 beqzc s0,fffc0550 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 81fe 0000 beqzc t7,fffc0558 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 3020 000a li at,10
+[ 0-9a-f]+: 7601 fffe beqc at,s0,55c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 7601 fffe beqc at,s0,564 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 7601 fffe beqc at,s0,56c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a03e 0000 bnezc at,fffc057c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a05e 0000 bnezc v0,fffc0584 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a07e 0000 bnezc v1,fffc058c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a09e 0000 bnezc a0,fffc0594 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a0be 0000 bnezc a1,fffc059c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a0de 0000 bnezc a2,fffc05a4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a1fe 0000 bnezc t7,fffc05ac <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a21e 0000 bnezc s0,fffc05b4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a03e 0000 bnezc at,fffc05bc <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a05e 0000 bnezc v0,fffc05c4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a07e 0000 bnezc v1,fffc05cc <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a09e 0000 bnezc a0,fffc05d4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a0be 0000 bnezc a1,fffc05dc <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a0de 0000 bnezc a2,fffc05e4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a1fe 0000 bnezc t7,fffc05ec <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a21e 0000 bnezc s0,fffc05f4 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a03e 0000 bnezc at,fffc05fc <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a05e 0000 bnezc v0,fffc0604 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a07e 0000 bnezc v1,fffc060c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a09e 0000 bnezc a0,fffc0614 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a0be 0000 bnezc a1,fffc061c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a0de 0000 bnezc a2,fffc0624 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a1fe 0000 bnezc t7,fffc062c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a21e 0000 bnezc s0,fffc0634 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a1fe 0000 bnezc t7,fffc063c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a21e 0000 bnezc s0,fffc0644 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: a21e 0000 bnezc s0,fffc064c <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+
+[0-9a-f]+ <test3>:
+[ 0-9a-f]+: a21e 0000 bnezc s0,fffc0650 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ 0-9a-f]+: 0000 0007 break
+[ 0-9a-f]+: 0000 0007 break
+[ 0-9a-f]+: 0001 0007 break 0x1
+[ 0-9a-f]+: 0002 0007 break 0x2
+[ 0-9a-f]+: 0003 0007 break 0x3
+[ 0-9a-f]+: 0004 0007 break 0x4
+[ 0-9a-f]+: 0005 0007 break 0x5
+[ 0-9a-f]+: 0006 0007 break 0x6
+[ 0-9a-f]+: 0007 0007 break 0x7
+[ 0-9a-f]+: 0008 0007 break 0x8
+[ 0-9a-f]+: 0009 0007 break 0x9
+[ 0-9a-f]+: 000a 0007 break 0xa
+[ 0-9a-f]+: 000b 0007 break 0xb
+[ 0-9a-f]+: 000c 0007 break 0xc
+[ 0-9a-f]+: 000d 0007 break 0xd
+[ 0-9a-f]+: 000e 0007 break 0xe
+[ 0-9a-f]+: 000f 0007 break 0xf
+[ 0-9a-f]+: 003f 0007 break 0x3f
+[ 0-9a-f]+: 0040 0007 break 0x40
+[ 0-9a-f]+: 03ff 0007 break 0x3ff
+[ 0-9a-f]+: 03ff ffc7 break 0x3ff,0x3ff
+[ 0-9a-f]+: 0000 0007 break
+[ 0-9a-f]+: 0000 0007 break
+[ 0-9a-f]+: 0001 0007 break 0x1
+[ 0-9a-f]+: 0002 0007 break 0x2
+[ 0-9a-f]+: 000f 0007 break 0xf
+[ 0-9a-f]+: 003f 0007 break 0x3f
+[ 0-9a-f]+: 0040 0007 break 0x40
+[ 0-9a-f]+: 03ff 0007 break 0x3ff
+[ 0-9a-f]+: 03ff ffc7 break 0x3ff,0x3ff
+[ 0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+[ 0-9a-f]+: 2000 6100 cache 0x0,-256\(zero\)
+[ 0-9a-f]+: 2000 60ff cache 0x0,255\(zero\)
+[ 0-9a-f]+: 3020 feff li at,-257
+[ 0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+[ 0-9a-f]+: 3020 0100 li at,256
+[ 0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+[ 0-9a-f]+: 2002 6000 cache 0x0,0\(v0\)
+[ 0-9a-f]+: 2002 6100 cache 0x0,-256\(v0\)
+[ 0-9a-f]+: 2002 60ff cache 0x0,255\(v0\)
+[ 0-9a-f]+: 3022 feff addiu at,v0,-257
+[ 0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+[ 0-9a-f]+: 3022 0100 addiu at,v0,256
+[ 0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+[ 0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+[ 0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+[ 0-9a-f]+: 2020 6000 cache 0x1,0\(zero\)
+[ 0-9a-f]+: 2040 6000 cache 0x2,0\(zero\)
+[ 0-9a-f]+: 2060 6000 cache 0x3,0\(zero\)
+[ 0-9a-f]+: 2080 6000 cache 0x4,0\(zero\)
+[ 0-9a-f]+: 20a0 6000 cache 0x5,0\(zero\)
+[ 0-9a-f]+: 20c0 6000 cache 0x6,0\(zero\)
+[ 0-9a-f]+: 23e0 6000 cache 0x1f,0\(zero\)
+[ 0-9a-f]+: 23e0 60ff cache 0x1f,255\(zero\)
+[ 0-9a-f]+: 23e0 6100 cache 0x1f,-256\(zero\)
+[ 0-9a-f]+: 2000 60ff cache 0x0,255\(zero\)
+[ 0-9a-f]+: 2000 6100 cache 0x0,-256\(zero\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 3023 0100 addiu at,v1,256
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 3023 feff addiu at,v1,-257
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 23e3 61ff cache 0x1f,-1\(v1\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 23e1 61ff cache 0x1f,-1\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 3020 0100 li at,256
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 3020 feff li at,-257
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 23e0 61ff cache 0x1f,-1\(zero\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 23e1 61ff cache 0x1f,-1\(at\)
+[ 0-9a-f]+: 0043 4b3c clo v0,v1
+[ 0-9a-f]+: 0062 4b3c clo v1,v0
+[ 0-9a-f]+: 0043 5b3c clz v0,v1
+[ 0-9a-f]+: 0062 5b3c clz v1,v0
+[ 0-9a-f]+: 0000 e37c deret
+[ 0-9a-f]+: 0000 477c di
+[ 0-9a-f]+: 0000 477c di
+[ 0-9a-f]+: 0002 477c di v0
+[ 0-9a-f]+: 0003 477c di v1
+[ 0-9a-f]+: 001e 477c di s8
+[ 0-9a-f]+: 001f 477c di ra
+[ 0-9a-f]+: 0062 0118 div zero,v0,v1
+[ 0-9a-f]+: 03fe 0118 div zero,s8,ra
+[ 0-9a-f]+: 0060 0118 div zero,zero,v1
+[ 0-9a-f]+: 03e0 0118 div zero,zero,ra
+[ 0-9a-f]+: 0003 1118 div v0,v1,zero
+[ 0-9a-f]+: 0083 1118 div v0,v1,a0
+[ 0-9a-f]+: 0062 0198 divu zero,v0,v1
+[ 0-9a-f]+: 03fe 0198 divu zero,s8,ra
+[ 0-9a-f]+: 0060 0198 divu zero,zero,v1
+[ 0-9a-f]+: 03e0 0198 divu zero,zero,ra
+[ 0-9a-f]+: 0003 1198 divu v0,v1,zero
+[ 0-9a-f]+: 0083 1198 divu v0,v1,a0
+[ 0-9a-f]+: 0000 577c ei
+[ 0-9a-f]+: 0000 577c ei
+[ 0-9a-f]+: 0002 577c ei v0
+[ 0-9a-f]+: 0003 577c ei v1
+[ 0-9a-f]+: 001e 577c ei s8
+[ 0-9a-f]+: 001f 577c ei ra
+[ 0-9a-f]+: 0000 f37c eret
+[ 0-9a-f]+: 0043 716c ext v0,v1,0x5,0xf
+[ 0-9a-f]+: 0043 f82c ext v0,v1,0x0,0x20
+[ 0-9a-f]+: 0043 07ec ext v0,v1,0x1f,0x1
+[ 0-9a-f]+: 03fe 07ec ext ra,s8,0x1f,0x1
+[ 0-9a-f]+: 0043 994c ins v0,v1,0x5,0xf
+[ 0-9a-f]+: 0043 f80c ins v0,v1,0x0,0x20
+[ 0-9a-f]+: 0043 ffcc ins v0,v1,0x1f,0x1
+[ 0-9a-f]+: 03fe ffcc ins ra,s8,0x1f,0x1
+[ 0-9a-f]+: 8000 0000 jrc zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8002 0000 jrc v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8003 0000 jrc v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8004 0000 jrc a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8005 0000 jrc a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8006 0000 jrc a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8007 0000 jrc a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8008 0000 jrc t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 801e 0000 jrc s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 8000 0000 jrc zero
+[ 0-9a-f]+: 8002 0000 jrc v0
+[ 0-9a-f]+: 8003 0000 jrc v1
+[ 0-9a-f]+: 8004 0000 jrc a0
+[ 0-9a-f]+: 8005 0000 jrc a1
+[ 0-9a-f]+: 8006 0000 jrc a2
+[ 0-9a-f]+: 8007 0000 jrc a3
+[ 0-9a-f]+: 8008 0000 jrc t0
+[ 0-9a-f]+: 801e 0000 jrc s8
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 8000 0000 jrc zero
+[ 0-9a-f]+: 8002 0000 jrc v0
+[ 0-9a-f]+: 8003 0000 jrc v1
+[ 0-9a-f]+: 8004 0000 jrc a0
+[ 0-9a-f]+: 8005 0000 jrc a1
+[ 0-9a-f]+: 8006 0000 jrc a2
+[ 0-9a-f]+: 8007 0000 jrc a3
+[ 0-9a-f]+: 8008 0000 jrc t0
+[ 0-9a-f]+: 801e 0000 jrc s8
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 0000 1f3c jrc.hb zero
+[ 0-9a-f]+: 0002 1f3c jrc.hb v0
+[ 0-9a-f]+: 0003 1f3c jrc.hb v1
+[ 0-9a-f]+: 0004 1f3c jrc.hb a0
+[ 0-9a-f]+: 0005 1f3c jrc.hb a1
+[ 0-9a-f]+: 0006 1f3c jrc.hb a2
+[ 0-9a-f]+: 0007 1f3c jrc.hb a3
+[ 0-9a-f]+: 0008 1f3c jrc.hb t0
+[ 0-9a-f]+: 001e 1f3c jrc.hb s8
+[ 0-9a-f]+: 001f 1f3c jrc.hb ra
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8000 0000 jrc zero
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8002 0000 jrc v0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8003 0000 jrc v1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8004 0000 jrc a0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8005 0000 jrc a1
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8006 0000 jrc a2
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8007 0000 jrc a3
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 8008 0000 jrc t0
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 801e 0000 jrc s8
+[ 0-9a-f]+: 0000 0000 nop
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 03e0 0f3c jalrc zero
+[ 0-9a-f]+: 03e2 0f3c jalrc v0
+[ 0-9a-f]+: 03e3 0f3c jalrc v1
+[ 0-9a-f]+: 03e4 0f3c jalrc a0
+[ 0-9a-f]+: 03e5 0f3c jalrc a1
+[ 0-9a-f]+: 03e6 0f3c jalrc a2
+[ 0-9a-f]+: 03e7 0f3c jalrc a3
+[ 0-9a-f]+: 03e8 0f3c jalrc t0
+[ 0-9a-f]+: 03fe 0f3c jalrc s8
+[ 0-9a-f]+: 03e0 0f3c jalrc zero
+[ 0-9a-f]+: 03e2 0f3c jalrc v0
+[ 0-9a-f]+: 03e3 0f3c jalrc v1
+[ 0-9a-f]+: 03e4 0f3c jalrc a0
+[ 0-9a-f]+: 03e5 0f3c jalrc a1
+[ 0-9a-f]+: 03e6 0f3c jalrc a2
+[ 0-9a-f]+: 03e7 0f3c jalrc a3
+[ 0-9a-f]+: 03e8 0f3c jalrc t0
+[ 0-9a-f]+: 03fe 0f3c jalrc s8
+[ 0-9a-f]+: 03e0 0f3c jalrc zero
+[ 0-9a-f]+: 03e2 0f3c jalrc v0
+[ 0-9a-f]+: 03e3 0f3c jalrc v1
+[ 0-9a-f]+: 03e4 0f3c jalrc a0
+[ 0-9a-f]+: 03e5 0f3c jalrc a1
+[ 0-9a-f]+: 03e6 0f3c jalrc a2
+[ 0-9a-f]+: 03e7 0f3c jalrc a3
+[ 0-9a-f]+: 03e8 0f3c jalrc t0
+[ 0-9a-f]+: 03fe 0f3c jalrc s8
+[ 0-9a-f]+: 03df 0f3c jalrc s8,ra
+[ 0-9a-f]+: 0040 0f3c jalrc v0,zero
+[ 0-9a-f]+: 0062 0f3c jalrc v1,v0
+[ 0-9a-f]+: 0043 0f3c jalrc v0,v1
+[ 0-9a-f]+: 0044 0f3c jalrc v0,a0
+[ 0-9a-f]+: 0045 0f3c jalrc v0,a1
+[ 0-9a-f]+: 0046 0f3c jalrc v0,a2
+[ 0-9a-f]+: 0047 0f3c jalrc v0,a3
+[ 0-9a-f]+: 0048 0f3c jalrc v0,t0
+[ 0-9a-f]+: 005e 0f3c jalrc v0,s8
+[ 0-9a-f]+: 005f 0f3c jalrc v0,ra
+[ 0-9a-f]+: 03e0 1f3c jalrc.hb zero
+[ 0-9a-f]+: 03e2 1f3c jalrc.hb v0
+[ 0-9a-f]+: 03e3 1f3c jalrc.hb v1
+[ 0-9a-f]+: 03e4 1f3c jalrc.hb a0
+[ 0-9a-f]+: 03e5 1f3c jalrc.hb a1
+[ 0-9a-f]+: 03e6 1f3c jalrc.hb a2
+[ 0-9a-f]+: 03e7 1f3c jalrc.hb a3
+[ 0-9a-f]+: 03e8 1f3c jalrc.hb t0
+[ 0-9a-f]+: 03fe 1f3c jalrc.hb s8
+[ 0-9a-f]+: 03e0 1f3c jalrc.hb zero
+[ 0-9a-f]+: 03e2 1f3c jalrc.hb v0
+[ 0-9a-f]+: 03e3 1f3c jalrc.hb v1
+[ 0-9a-f]+: 03e4 1f3c jalrc.hb a0
+[ 0-9a-f]+: 03e5 1f3c jalrc.hb a1
+[ 0-9a-f]+: 03e6 1f3c jalrc.hb a2
+[ 0-9a-f]+: 03e7 1f3c jalrc.hb a3
+[ 0-9a-f]+: 03e8 1f3c jalrc.hb t0
+[ 0-9a-f]+: 03fe 1f3c jalrc.hb s8
+[ 0-9a-f]+: 03df 1f3c jalrc.hb s8,ra
+[ 0-9a-f]+: 0040 1f3c jalrc.hb v0,zero
+[ 0-9a-f]+: 0062 1f3c jalrc.hb v1,v0
+[ 0-9a-f]+: 0043 1f3c jalrc.hb v0,v1
+[ 0-9a-f]+: 0044 1f3c jalrc.hb v0,a0
+[ 0-9a-f]+: 0045 1f3c jalrc.hb v0,a1
+[ 0-9a-f]+: 0046 1f3c jalrc.hb v0,a2
+[ 0-9a-f]+: 0047 1f3c jalrc.hb v0,a3
+[ 0-9a-f]+: 0048 1f3c jalrc.hb v0,t0
+[ 0-9a-f]+: 005e 1f3c jalrc.hb v0,s8
+[ 0-9a-f]+: 005f 1f3c jalrc.hb v0,ra
+[ 0-9a-f]+: 0043 0f3c jalrc v0,v1
+[ 0-9a-f]+: 03df 0f3c jalrc s8,ra
+[ 0-9a-f]+: 03e3 0f3c jalrc v1
+[ 0-9a-f]+: 03ff 0f3c jalrc ra
+[ 0-9a-f]+: b3fe 0000 sltiu ra,s8,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 test
+[ 0-9a-f]+: b3fe 0000 sltiu ra,s8,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 test2
+[ 0-9a-f]+: 1040 0000 lui v0,0x0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 1040 0000 lui v0,0x0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 1c60 0000 lb v1,0\(zero\)
+[ 0-9a-f]+: 1c60 0004 lb v1,4\(zero\)
+[ 0-9a-f]+: 1c60 0000 lb v1,0\(zero\)
+[ 0-9a-f]+: 1c60 0004 lb v1,4\(zero\)
+[ 0-9a-f]+: 1c60 7fff lb v1,32767\(zero\)
+[ 0-9a-f]+: 1c60 8000 lb v1,-32768\(zero\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 1c63 ffff lb v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c60 8000 lb v1,-32768\(zero\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 1c63 0001 lb v1,1\(v1\)
+[ 0-9a-f]+: 1c60 8001 lb v1,-32767\(zero\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c60 ffff lb v1,-1\(zero\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 1c63 5678 lb v1,22136\(v1\)
+[ 0-9a-f]+: 1c64 0000 lb v1,0\(a0\)
+[ 0-9a-f]+: 1c64 0000 lb v1,0\(a0\)
+[ 0-9a-f]+: 1c64 0004 lb v1,4\(a0\)
+[ 0-9a-f]+: 1c64 7fff lb v1,32767\(a0\)
+[ 0-9a-f]+: 1c64 8000 lb v1,-32768\(a0\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 ffff lb v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c64 8000 lb v1,-32768\(a0\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 0001 lb v1,1\(v1\)
+[ 0-9a-f]+: 1c64 8001 lb v1,-32767\(a0\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+[ 0-9a-f]+: 1c64 ffff lb v1,-1\(a0\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1c63 5678 lb v1,22136\(v1\)
+[ 0-9a-f]+: 1443 ffff lbu v0,-1\(v1\)
+[ 0-9a-f]+: 1443 0000 lbu v0,0\(v1\)
+[ 0-9a-f]+: 1443 0000 lbu v0,0\(v1\)
+[ 0-9a-f]+: 1443 0001 lbu v0,1\(v1\)
+[ 0-9a-f]+: 1443 0002 lbu v0,2\(v1\)
+[ 0-9a-f]+: 1443 0003 lbu v0,3\(v1\)
+[ 0-9a-f]+: 1443 0004 lbu v0,4\(v1\)
+[ 0-9a-f]+: 1443 0005 lbu v0,5\(v1\)
+[ 0-9a-f]+: 1443 0006 lbu v0,6\(v1\)
+[ 0-9a-f]+: 1443 0007 lbu v0,7\(v1\)
+[ 0-9a-f]+: 1443 0008 lbu v0,8\(v1\)
+[ 0-9a-f]+: 1443 0009 lbu v0,9\(v1\)
+[ 0-9a-f]+: 1443 000a lbu v0,10\(v1\)
+[ 0-9a-f]+: 1443 000b lbu v0,11\(v1\)
+[ 0-9a-f]+: 1443 000c lbu v0,12\(v1\)
+[ 0-9a-f]+: 1443 000d lbu v0,13\(v1\)
+[ 0-9a-f]+: 1443 000e lbu v0,14\(v1\)
+[ 0-9a-f]+: 1442 000e lbu v0,14\(v0\)
+[ 0-9a-f]+: 1444 000e lbu v0,14\(a0\)
+[ 0-9a-f]+: 1445 000e lbu v0,14\(a1\)
+[ 0-9a-f]+: 1446 000e lbu v0,14\(a2\)
+[ 0-9a-f]+: 1447 000e lbu v0,14\(a3\)
+[ 0-9a-f]+: 1450 000e lbu v0,14\(s0\)
+[ 0-9a-f]+: 1451 000e lbu v0,14\(s1\)
+[ 0-9a-f]+: 1471 000e lbu v1,14\(s1\)
+[ 0-9a-f]+: 1491 000e lbu a0,14\(s1\)
+[ 0-9a-f]+: 14b1 000e lbu a1,14\(s1\)
+[ 0-9a-f]+: 14d1 000e lbu a2,14\(s1\)
+[ 0-9a-f]+: 14f1 000e lbu a3,14\(s1\)
+[ 0-9a-f]+: 1611 000e lbu s0,14\(s1\)
+[ 0-9a-f]+: 1631 000e lbu s1,14\(s1\)
+[ 0-9a-f]+: 1460 0000 lbu v1,0\(zero\)
+[ 0-9a-f]+: 1460 0004 lbu v1,4\(zero\)
+[ 0-9a-f]+: 1460 0000 lbu v1,0\(zero\)
+[ 0-9a-f]+: 1460 0004 lbu v1,4\(zero\)
+[ 0-9a-f]+: 1460 7fff lbu v1,32767\(zero\)
+[ 0-9a-f]+: 1460 8000 lbu v1,-32768\(zero\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 1463 ffff lbu v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1460 8000 lbu v1,-32768\(zero\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 1463 0001 lbu v1,1\(v1\)
+[ 0-9a-f]+: 1460 8001 lbu v1,-32767\(zero\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1460 ffff lbu v1,-1\(zero\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 1463 5678 lbu v1,22136\(v1\)
+[ 0-9a-f]+: 1464 0000 lbu v1,0\(a0\)
+[ 0-9a-f]+: 1464 0000 lbu v1,0\(a0\)
+[ 0-9a-f]+: 1464 0004 lbu v1,4\(a0\)
+[ 0-9a-f]+: 1464 7fff lbu v1,32767\(a0\)
+[ 0-9a-f]+: 1464 8000 lbu v1,-32768\(a0\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 ffff lbu v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1464 8000 lbu v1,-32768\(a0\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 0001 lbu v1,1\(v1\)
+[ 0-9a-f]+: 1464 8001 lbu v1,-32767\(a0\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+[ 0-9a-f]+: 1464 ffff lbu v1,-1\(a0\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 1463 5678 lbu v1,22136\(v1\)
+[ 0-9a-f]+: 3c60 0000 lh v1,0\(zero\)
+[ 0-9a-f]+: 3c60 0004 lh v1,4\(zero\)
+[ 0-9a-f]+: 3c60 0000 lh v1,0\(zero\)
+[ 0-9a-f]+: 3c60 0004 lh v1,4\(zero\)
+[ 0-9a-f]+: 3c60 7fff lh v1,32767\(zero\)
+[ 0-9a-f]+: 3c60 8000 lh v1,-32768\(zero\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 3c63 ffff lh v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c60 8000 lh v1,-32768\(zero\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 3c63 0001 lh v1,1\(v1\)
+[ 0-9a-f]+: 3c60 8001 lh v1,-32767\(zero\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c60 ffff lh v1,-1\(zero\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 3c63 5678 lh v1,22136\(v1\)
+[ 0-9a-f]+: 3c64 0000 lh v1,0\(a0\)
+[ 0-9a-f]+: 3c64 0000 lh v1,0\(a0\)
+[ 0-9a-f]+: 3c64 0004 lh v1,4\(a0\)
+[ 0-9a-f]+: 3c64 7fff lh v1,32767\(a0\)
+[ 0-9a-f]+: 3c64 8000 lh v1,-32768\(a0\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 ffff lh v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c64 8000 lh v1,-32768\(a0\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 0001 lh v1,1\(v1\)
+[ 0-9a-f]+: 3c64 8001 lh v1,-32767\(a0\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+[ 0-9a-f]+: 3c64 ffff lh v1,-1\(a0\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3c63 5678 lh v1,22136\(v1\)
+[ 0-9a-f]+: 3443 0000 lhu v0,0\(v1\)
+[ 0-9a-f]+: 3443 0000 lhu v0,0\(v1\)
+[ 0-9a-f]+: 3443 0002 lhu v0,2\(v1\)
+[ 0-9a-f]+: 3443 0004 lhu v0,4\(v1\)
+[ 0-9a-f]+: 3443 0006 lhu v0,6\(v1\)
+[ 0-9a-f]+: 3443 0008 lhu v0,8\(v1\)
+[ 0-9a-f]+: 3443 000a lhu v0,10\(v1\)
+[ 0-9a-f]+: 3443 000c lhu v0,12\(v1\)
+[ 0-9a-f]+: 3443 000e lhu v0,14\(v1\)
+[ 0-9a-f]+: 3443 0010 lhu v0,16\(v1\)
+[ 0-9a-f]+: 3443 0012 lhu v0,18\(v1\)
+[ 0-9a-f]+: 3443 0014 lhu v0,20\(v1\)
+[ 0-9a-f]+: 3443 0016 lhu v0,22\(v1\)
+[ 0-9a-f]+: 3443 0018 lhu v0,24\(v1\)
+[ 0-9a-f]+: 3443 001a lhu v0,26\(v1\)
+[ 0-9a-f]+: 3443 001c lhu v0,28\(v1\)
+[ 0-9a-f]+: 3443 001e lhu v0,30\(v1\)
+[ 0-9a-f]+: 3444 001e lhu v0,30\(a0\)
+[ 0-9a-f]+: 3445 001e lhu v0,30\(a1\)
+[ 0-9a-f]+: 3446 001e lhu v0,30\(a2\)
+[ 0-9a-f]+: 3447 001e lhu v0,30\(a3\)
+[ 0-9a-f]+: 3442 001e lhu v0,30\(v0\)
+[ 0-9a-f]+: 3450 001e lhu v0,30\(s0\)
+[ 0-9a-f]+: 3451 001e lhu v0,30\(s1\)
+[ 0-9a-f]+: 3471 001e lhu v1,30\(s1\)
+[ 0-9a-f]+: 3491 001e lhu a0,30\(s1\)
+[ 0-9a-f]+: 34b1 001e lhu a1,30\(s1\)
+[ 0-9a-f]+: 34d1 001e lhu a2,30\(s1\)
+[ 0-9a-f]+: 34f1 001e lhu a3,30\(s1\)
+[ 0-9a-f]+: 3611 001e lhu s0,30\(s1\)
+[ 0-9a-f]+: 3631 001e lhu s1,30\(s1\)
+[ 0-9a-f]+: 3460 0000 lhu v1,0\(zero\)
+[ 0-9a-f]+: 3460 0004 lhu v1,4\(zero\)
+[ 0-9a-f]+: 3460 0000 lhu v1,0\(zero\)
+[ 0-9a-f]+: 3460 0004 lhu v1,4\(zero\)
+[ 0-9a-f]+: 3460 7fff lhu v1,32767\(zero\)
+[ 0-9a-f]+: 3460 8000 lhu v1,-32768\(zero\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 3463 ffff lhu v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3460 8000 lhu v1,-32768\(zero\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 3463 0001 lhu v1,1\(v1\)
+[ 0-9a-f]+: 3460 8001 lhu v1,-32767\(zero\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3460 ffff lhu v1,-1\(zero\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 3463 5678 lhu v1,22136\(v1\)
+[ 0-9a-f]+: 3464 0000 lhu v1,0\(a0\)
+[ 0-9a-f]+: 3464 0000 lhu v1,0\(a0\)
+[ 0-9a-f]+: 3464 0004 lhu v1,4\(a0\)
+[ 0-9a-f]+: 3464 7fff lhu v1,32767\(a0\)
+[ 0-9a-f]+: 3464 8000 lhu v1,-32768\(a0\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 ffff lhu v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3464 8000 lhu v1,-32768\(a0\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 0001 lhu v1,1\(v1\)
+[ 0-9a-f]+: 3464 8001 lhu v1,-32767\(a0\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+[ 0-9a-f]+: 3464 ffff lhu v1,-1\(a0\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 3463 5678 lhu v1,22136\(v1\)
+[ 0-9a-f]+: 6060 3000 ll v1,0\(zero\)
+[ 0-9a-f]+: 6060 3000 ll v1,0\(zero\)
+[ 0-9a-f]+: 6060 3004 ll v1,4\(zero\)
+[ 0-9a-f]+: 6060 3004 ll v1,4\(zero\)
+[ 0-9a-f]+: 3060 7fff li v1,32767
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 6063 31ff ll v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+[ 0-9a-f]+: 3060 8001 li v1,-32767
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 6060 31ff ll v1,-1\(zero\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 5063 5600 ori v1,v1,0x5600
+[ 0-9a-f]+: 6063 3078 ll v1,120\(v1\)
+[ 0-9a-f]+: 6064 3000 ll v1,0\(a0\)
+[ 0-9a-f]+: 6064 3000 ll v1,0\(a0\)
+[ 0-9a-f]+: 6064 3004 ll v1,4\(a0\)
+[ 0-9a-f]+: 3064 7fff addiu v1,a0,32767
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 3064 8000 addiu v1,a0,-32768
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 31ff ll v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 3064 8000 addiu v1,a0,-32768
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+[ 0-9a-f]+: 3064 8001 addiu v1,a0,-32767
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+[ 0-9a-f]+: 6064 31ff ll v1,-1\(a0\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 5063 5600 ori v1,v1,0x5600
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: 6063 3078 ll v1,120\(v1\)
+[ 0-9a-f]+: 1060 0000 lui v1,0x0
+[ 0-9a-f]+: 1060 7fff lui v1,0x7fff
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: fc44 0000 lw v0,0\(a0\)
+[ 0-9a-f]+: fc44 0000 lw v0,0\(a0\)
+[ 0-9a-f]+: fc44 0004 lw v0,4\(a0\)
+[ 0-9a-f]+: fc44 0008 lw v0,8\(a0\)
+[ 0-9a-f]+: fc44 000c lw v0,12\(a0\)
+[ 0-9a-f]+: fc44 0010 lw v0,16\(a0\)
+[ 0-9a-f]+: fc44 0014 lw v0,20\(a0\)
+[ 0-9a-f]+: fc44 0018 lw v0,24\(a0\)
+[ 0-9a-f]+: fc44 001c lw v0,28\(a0\)
+[ 0-9a-f]+: fc44 0020 lw v0,32\(a0\)
+[ 0-9a-f]+: fc44 0024 lw v0,36\(a0\)
+[ 0-9a-f]+: fc44 0028 lw v0,40\(a0\)
+[ 0-9a-f]+: fc44 002c lw v0,44\(a0\)
+[ 0-9a-f]+: fc44 0030 lw v0,48\(a0\)
+[ 0-9a-f]+: fc44 0034 lw v0,52\(a0\)
+[ 0-9a-f]+: fc44 0038 lw v0,56\(a0\)
+[ 0-9a-f]+: fc44 003c lw v0,60\(a0\)
+[ 0-9a-f]+: fc45 003c lw v0,60\(a1\)
+[ 0-9a-f]+: fc46 003c lw v0,60\(a2\)
+[ 0-9a-f]+: fc47 003c lw v0,60\(a3\)
+[ 0-9a-f]+: fc42 003c lw v0,60\(v0\)
+[ 0-9a-f]+: fc43 003c lw v0,60\(v1\)
+[ 0-9a-f]+: fc50 003c lw v0,60\(s0\)
+[ 0-9a-f]+: fc51 003c lw v0,60\(s1\)
+[ 0-9a-f]+: fc71 003c lw v1,60\(s1\)
+[ 0-9a-f]+: fc91 003c lw a0,60\(s1\)
+[ 0-9a-f]+: fcb1 003c lw a1,60\(s1\)
+[ 0-9a-f]+: fcd1 003c lw a2,60\(s1\)
+[ 0-9a-f]+: fcf1 003c lw a3,60\(s1\)
+[ 0-9a-f]+: fe11 003c lw s0,60\(s1\)
+[ 0-9a-f]+: fe31 003c lw s1,60\(s1\)
+[ 0-9a-f]+: fc9d 0000 lw a0,0\(sp\)
+[ 0-9a-f]+: fc9d 0000 lw a0,0\(sp\)
+[ 0-9a-f]+: fc9d 0004 lw a0,4\(sp\)
+[ 0-9a-f]+: fc9d 0008 lw a0,8\(sp\)
+[ 0-9a-f]+: fc9d 000c lw a0,12\(sp\)
+[ 0-9a-f]+: fc9d 0010 lw a0,16\(sp\)
+[ 0-9a-f]+: fc9d 0014 lw a0,20\(sp\)
+[ 0-9a-f]+: fc9d 007c lw a0,124\(sp\)
+[ 0-9a-f]+: fc5d 007c lw v0,124\(sp\)
+[ 0-9a-f]+: fc5d 007c lw v0,124\(sp\)
+[ 0-9a-f]+: fc7d 007c lw v1,124\(sp\)
+[ 0-9a-f]+: fc9d 007c lw a0,124\(sp\)
+[ 0-9a-f]+: fcbd 007c lw a1,124\(sp\)
+[ 0-9a-f]+: fcdd 007c lw a2,124\(sp\)
+[ 0-9a-f]+: fcfd 007c lw a3,124\(sp\)
+[ 0-9a-f]+: fd1d 007c lw t0,124\(sp\)
+[ 0-9a-f]+: fd3d 007c lw t1,124\(sp\)
+[ 0-9a-f]+: fd5d 007c lw t2,124\(sp\)
+[ 0-9a-f]+: ffdd 007c lw s8,124\(sp\)
+[ 0-9a-f]+: fffd 007c lw ra,124\(sp\)
+[ 0-9a-f]+: fc9d 01f8 lw a0,504\(sp\)
+[ 0-9a-f]+: fc9d 01fc lw a0,508\(sp\)
+[ 0-9a-f]+: fe1d 01fc lw s0,508\(sp\)
+[ 0-9a-f]+: fe3d 01fc lw s1,508\(sp\)
+[ 0-9a-f]+: fe5d 01fc lw s2,508\(sp\)
+[ 0-9a-f]+: fe7d 01fc lw s3,508\(sp\)
+[ 0-9a-f]+: fe9d 01fc lw s4,508\(sp\)
+[ 0-9a-f]+: febd 01fc lw s5,508\(sp\)
+[ 0-9a-f]+: fffd 01fc lw ra,508\(sp\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc60 7fff lw v1,32767\(zero\)
+[ 0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: fc63 ffff lw v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: fc63 0001 lw v1,1\(v1\)
+[ 0-9a-f]+: fc60 8001 lw v1,-32767\(zero\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc60 ffff lw v1,-1\(zero\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: fc63 5678 lw v1,22136\(v1\)
+[ 0-9a-f]+: fc64 0000 lw v1,0\(a0\)
+[ 0-9a-f]+: fc64 0000 lw v1,0\(a0\)
+[ 0-9a-f]+: fc64 0004 lw v1,4\(a0\)
+[ 0-9a-f]+: fc64 7fff lw v1,32767\(a0\)
+[ 0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 ffff lw v1,-1\(v1\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ 0-9a-f]+: 1060 ffff lui v1,0xffff
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 0001 lw v1,1\(v1\)
+[ 0-9a-f]+: fc64 8001 lw v1,-32767\(a0\)
+[ 0-9a-f]+: 1060 f000 lui v1,0xf000
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+[ 0-9a-f]+: fc64 ffff lw v1,-1\(a0\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 0083 1950 addu v1,v1,a0
+[ 0-9a-f]+: fc63 5678 lw v1,22136\(v1\)
+[ 0-9a-f]+: 223d 5030 lwm s0,ra,48\(sp\)
+[ 0-9a-f]+: 225d 5030 lwm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 225d 5030 lwm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 227d 5030 lwm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 227d 5030 lwm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 229d 5030 lwm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 229d 5030 lwm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 223d 5000 lwm s0,ra,0\(sp\)
+[ 0-9a-f]+: 223d 5000 lwm s0,ra,0\(sp\)
+[ 0-9a-f]+: 223d 5004 lwm s0,ra,4\(sp\)
+[ 0-9a-f]+: 223d 5008 lwm s0,ra,8\(sp\)
+[ 0-9a-f]+: 223d 500c lwm s0,ra,12\(sp\)
+[ 0-9a-f]+: 223d 5010 lwm s0,ra,16\(sp\)
+[ 0-9a-f]+: 223d 5014 lwm s0,ra,20\(sp\)
+[ 0-9a-f]+: 223d 5018 lwm s0,ra,24\(sp\)
+[ 0-9a-f]+: 223d 501c lwm s0,ra,28\(sp\)
+[ 0-9a-f]+: 223d 5020 lwm s0,ra,32\(sp\)
+[ 0-9a-f]+: 223d 5024 lwm s0,ra,36\(sp\)
+[ 0-9a-f]+: 223d 5028 lwm s0,ra,40\(sp\)
+[ 0-9a-f]+: 223d 502c lwm s0,ra,44\(sp\)
+[ 0-9a-f]+: 223d 5030 lwm s0,ra,48\(sp\)
+[ 0-9a-f]+: 223d 5034 lwm s0,ra,52\(sp\)
+[ 0-9a-f]+: 223d 5038 lwm s0,ra,56\(sp\)
+[ 0-9a-f]+: 223d 503c lwm s0,ra,60\(sp\)
+[ 0-9a-f]+: 2020 5000 lwm s0,0\(zero\)
+[ 0-9a-f]+: 2020 5004 lwm s0,4\(zero\)
+[ 0-9a-f]+: 2025 5000 lwm s0,0\(a1\)
+[ 0-9a-f]+: 2025 57ff lwm s0,2047\(a1\)
+[ 0-9a-f]+: 2045 57ff lwm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 57ff lwm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 57ff lwm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 57ff lwm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 57ff lwm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 57ff lwm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 57ff lwm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 57ff lwm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 57ff lwm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 5000 lwm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 5000 lwm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 5000 lwm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 5000 lwm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 5000 lwm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 5000 lwm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 5000 lwm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 5000 lwm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 5000 lwm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 2020 5000 lwm s0,0\(zero\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+[ 0-9a-f]+: 303d 8000 addiu at,sp,-32768
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 303d 7fff addiu at,sp,32767
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 203d 5000 lwm s0,0\(sp\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+[ 0-9a-f]+: 2040 1000 lwp v0,0\(zero\)
+[ 0-9a-f]+: 2040 1004 lwp v0,4\(zero\)
+[ 0-9a-f]+: 205d 1000 lwp v0,0\(sp\)
+[ 0-9a-f]+: 205d 1000 lwp v0,0\(sp\)
+[ 0-9a-f]+: 2043 1800 lwp v0,-2048\(v1\)
+[ 0-9a-f]+: 2043 17ff lwp v0,2047\(v1\)
+[ 0-9a-f]+: 3023 8000 addiu at,v1,-32768
+[ 0-9a-f]+: 2041 1000 lwp v0,0\(at\)
+[ 0-9a-f]+: 3023 7fff addiu at,v1,32767
+[ 0-9a-f]+: 2041 1000 lwp v0,0\(at\)
+[ 0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 1fff lwp v0,-1\(at\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
+[ 0-9a-f]+: 3060 7fff li v1,32767
+[ 0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 2043 1fff lwp v0,-1\(v1\)
+[ 0-9a-f]+: 0085 1900 lwxs v1,a0\(a1\)
+[ 0-9a-f]+: 0040 00fc mfc0 v0,c0_index
+[ 0-9a-f]+: 0041 00fc mfc0 v0,c0_random
+[ 0-9a-f]+: 0042 00fc mfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0043 00fc mfc0 v0,c0_entrylo1
+[ 0-9a-f]+: 0044 00fc mfc0 v0,c0_context
+[ 0-9a-f]+: 0045 00fc mfc0 v0,c0_pagemask
+[ 0-9a-f]+: 0046 00fc mfc0 v0,c0_wired
+[ 0-9a-f]+: 0047 00fc mfc0 v0,c0_hwrena
+[ 0-9a-f]+: 0048 00fc mfc0 v0,c0_badvaddr
+[ 0-9a-f]+: 0049 00fc mfc0 v0,c0_count
+[ 0-9a-f]+: 004a 00fc mfc0 v0,c0_entryhi
+[ 0-9a-f]+: 004b 00fc mfc0 v0,c0_compare
+[ 0-9a-f]+: 004c 00fc mfc0 v0,c0_status
+[ 0-9a-f]+: 004d 00fc mfc0 v0,c0_cause
+[ 0-9a-f]+: 004e 00fc mfc0 v0,c0_epc
+[ 0-9a-f]+: 004f 00fc mfc0 v0,c0_prid
+[ 0-9a-f]+: 0050 00fc mfc0 v0,c0_config
+[ 0-9a-f]+: 0051 00fc mfc0 v0,c0_lladdr
+[ 0-9a-f]+: 0052 00fc mfc0 v0,c0_watchlo
+[ 0-9a-f]+: 0053 00fc mfc0 v0,c0_watchhi
+[ 0-9a-f]+: 0054 00fc mfc0 v0,c0_xcontext
+[ 0-9a-f]+: 0055 00fc mfc0 v0,\$21
+[ 0-9a-f]+: 0056 00fc mfc0 v0,\$22
+[ 0-9a-f]+: 0057 00fc mfc0 v0,c0_debug
+[ 0-9a-f]+: 0058 00fc mfc0 v0,c0_depc
+[ 0-9a-f]+: 0059 00fc mfc0 v0,c0_perfcnt
+[ 0-9a-f]+: 005a 00fc mfc0 v0,c0_errctl
+[ 0-9a-f]+: 005b 00fc mfc0 v0,c0_cacheerr
+[ 0-9a-f]+: 005c 00fc mfc0 v0,c0_taglo
+[ 0-9a-f]+: 005d 00fc mfc0 v0,c0_taghi
+[ 0-9a-f]+: 005e 00fc mfc0 v0,c0_errorepc
+[ 0-9a-f]+: 005f 00fc mfc0 v0,c0_desave
+[ 0-9a-f]+: 0040 00fc mfc0 v0,c0_index
+[ 0-9a-f]+: 0040 08fc mfc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 0040 10fc mfc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 0040 18fc mfc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 0040 20fc mfc0 v0,\$0,4
+[ 0-9a-f]+: 0040 28fc mfc0 v0,\$0,5
+[ 0-9a-f]+: 0040 30fc mfc0 v0,\$0,6
+[ 0-9a-f]+: 0040 38fc mfc0 v0,\$0,7
+[ 0-9a-f]+: 0041 00fc mfc0 v0,c0_random
+[ 0-9a-f]+: 0041 08fc mfc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 0041 10fc mfc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 0041 18fc mfc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 0041 20fc mfc0 v0,c0_yqmask
+[ 0-9a-f]+: 0041 28fc mfc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 0041 30fc mfc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 0041 38fc mfc0 v0,\$1,7
+[ 0-9a-f]+: 0042 00fc mfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0042 08fc mfc0 v0,c0_tcstatus
+[ 0-9a-f]+: 0042 10fc mfc0 v0,c0_tcbind
+[ 0-9a-f]+: 0042 18fc mfc0 v0,c0_tcrestart
+[ 0-9a-f]+: 0042 20fc mfc0 v0,c0_tchalt
+[ 0-9a-f]+: 0042 28fc mfc0 v0,c0_tccontext
+[ 0-9a-f]+: 0042 30fc mfc0 v0,c0_tcschedule
+[ 0-9a-f]+: 0042 38fc mfc0 v0,c0_tcschefback
+[ 0-9a-f]+: 0040 02fc mtc0 v0,c0_index
+[ 0-9a-f]+: 0041 02fc mtc0 v0,c0_random
+[ 0-9a-f]+: 0042 02fc mtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0043 02fc mtc0 v0,c0_entrylo1
+[ 0-9a-f]+: 0044 02fc mtc0 v0,c0_context
+[ 0-9a-f]+: 0045 02fc mtc0 v0,c0_pagemask
+[ 0-9a-f]+: 0046 02fc mtc0 v0,c0_wired
+[ 0-9a-f]+: 0047 02fc mtc0 v0,c0_hwrena
+[ 0-9a-f]+: 0048 02fc mtc0 v0,c0_badvaddr
+[ 0-9a-f]+: 0049 02fc mtc0 v0,c0_count
+[ 0-9a-f]+: 004a 02fc mtc0 v0,c0_entryhi
+[ 0-9a-f]+: 004b 02fc mtc0 v0,c0_compare
+[ 0-9a-f]+: 004c 02fc mtc0 v0,c0_status
+[ 0-9a-f]+: 004d 02fc mtc0 v0,c0_cause
+[ 0-9a-f]+: 004e 02fc mtc0 v0,c0_epc
+[ 0-9a-f]+: 004f 02fc mtc0 v0,c0_prid
+[ 0-9a-f]+: 0050 02fc mtc0 v0,c0_config
+[ 0-9a-f]+: 0051 02fc mtc0 v0,c0_lladdr
+[ 0-9a-f]+: 0052 02fc mtc0 v0,c0_watchlo
+[ 0-9a-f]+: 0053 02fc mtc0 v0,c0_watchhi
+[ 0-9a-f]+: 0054 02fc mtc0 v0,c0_xcontext
+[ 0-9a-f]+: 0055 02fc mtc0 v0,\$21
+[ 0-9a-f]+: 0056 02fc mtc0 v0,\$22
+[ 0-9a-f]+: 0057 02fc mtc0 v0,c0_debug
+[ 0-9a-f]+: 0058 02fc mtc0 v0,c0_depc
+[ 0-9a-f]+: 0059 02fc mtc0 v0,c0_perfcnt
+[ 0-9a-f]+: 005a 02fc mtc0 v0,c0_errctl
+[ 0-9a-f]+: 005b 02fc mtc0 v0,c0_cacheerr
+[ 0-9a-f]+: 005c 02fc mtc0 v0,c0_taglo
+[ 0-9a-f]+: 005d 02fc mtc0 v0,c0_taghi
+[ 0-9a-f]+: 005e 02fc mtc0 v0,c0_errorepc
+[ 0-9a-f]+: 005f 02fc mtc0 v0,c0_desave
+[ 0-9a-f]+: 0040 02fc mtc0 v0,c0_index
+[ 0-9a-f]+: 0040 0afc mtc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 0040 12fc mtc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 0040 1afc mtc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 0040 22fc mtc0 v0,\$0,4
+[ 0-9a-f]+: 0040 2afc mtc0 v0,\$0,5
+[ 0-9a-f]+: 0040 32fc mtc0 v0,\$0,6
+[ 0-9a-f]+: 0040 3afc mtc0 v0,\$0,7
+[ 0-9a-f]+: 0041 02fc mtc0 v0,c0_random
+[ 0-9a-f]+: 0041 0afc mtc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 0041 12fc mtc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 0041 1afc mtc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 0041 22fc mtc0 v0,c0_yqmask
+[ 0-9a-f]+: 0041 2afc mtc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 0041 32fc mtc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 0041 3afc mtc0 v0,\$1,7
+[ 0-9a-f]+: 0042 02fc mtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 0042 0afc mtc0 v0,c0_tcstatus
+[ 0-9a-f]+: 0042 12fc mtc0 v0,c0_tcbind
+[ 0-9a-f]+: 0042 1afc mtc0 v0,c0_tcrestart
+[ 0-9a-f]+: 0042 22fc mtc0 v0,c0_tchalt
+[ 0-9a-f]+: 0042 2afc mtc0 v0,c0_tccontext
+[ 0-9a-f]+: 0042 32fc mtc0 v0,c0_tcschedule
+[ 0-9a-f]+: 0042 3afc mtc0 v0,c0_tcschefback
+[ 0-9a-f]+: 0083 1018 mul v0,v1,a0
+[ 0-9a-f]+: 03fe e818 mul sp,s8,ra
+[ 0-9a-f]+: 0082 1018 mul v0,v0,a0
+[ 0-9a-f]+: 0082 1018 mul v0,v0,a0
+[ 0-9a-f]+: 0060 1190 neg v0,v1
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+[ 0-9a-f]+: 0040 1190 neg v0,v0
+[ 0-9a-f]+: 0060 11d0 negu v0,v1
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0060 11d0 negu v0,v1
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0002 12d0 not v0,v0
+[ 0-9a-f]+: 0002 12d0 not v0,v0
+[ 0-9a-f]+: 0003 12d0 not v0,v1
+[ 0-9a-f]+: 0004 12d0 not v0,a0
+[ 0-9a-f]+: 0005 12d0 not v0,a1
+[ 0-9a-f]+: 0006 12d0 not v0,a2
+[ 0-9a-f]+: 0007 12d0 not v0,a3
+[ 0-9a-f]+: 0010 12d0 not v0,s0
+[ 0-9a-f]+: 0011 12d0 not v0,s1
+[ 0-9a-f]+: 0011 1ad0 not v1,s1
+[ 0-9a-f]+: 0011 22d0 not a0,s1
+[ 0-9a-f]+: 0011 2ad0 not a1,s1
+[ 0-9a-f]+: 0011 32d0 not a2,s1
+[ 0-9a-f]+: 0011 3ad0 not a3,s1
+[ 0-9a-f]+: 0011 82d0 not s0,s1
+[ 0-9a-f]+: 0011 8ad0 not s1,s1
+[ 0-9a-f]+: 0007 12d0 not v0,a3
+[ 0-9a-f]+: 00e0 12d0 nor v0,zero,a3
+[ 0-9a-f]+: 0083 12d0 nor v0,v1,a0
+[ 0-9a-f]+: 03fe ead0 nor sp,s8,ra
+[ 0-9a-f]+: 0082 12d0 nor v0,v0,a0
+[ 0-9a-f]+: 0082 12d0 nor v0,v0,a0
+[ 0-9a-f]+: 5043 8000 ori v0,v1,0x8000
+[ 0-9a-f]+: 0002 12d0 not v0,v0
+[ 0-9a-f]+: 5043 ffff ori v0,v1,0xffff
+[ 0-9a-f]+: 0002 12d0 not v0,v0
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ 0-9a-f]+: 0016 1290 move v0,s6
+[ 0-9a-f]+: 0002 b290 move s6,v0
+[ 0-9a-f]+: 02c0 1290 or v0,zero,s6
+[ 0-9a-f]+: 0040 b290 or s6,zero,v0
+[ 0-9a-f]+: 0042 1290 or v0,v0,v0
+[ 0-9a-f]+: 0062 1290 or v0,v0,v1
+[ 0-9a-f]+: 0082 1290 or v0,v0,a0
+[ 0-9a-f]+: 00a2 1290 or v0,v0,a1
+[ 0-9a-f]+: 00c2 1290 or v0,v0,a2
+[ 0-9a-f]+: 00e2 1290 or v0,v0,a3
+[ 0-9a-f]+: 0202 1290 or v0,v0,s0
+[ 0-9a-f]+: 0222 1290 or v0,v0,s1
+[ 0-9a-f]+: 0043 1a90 or v1,v1,v0
+[ 0-9a-f]+: 0044 2290 or a0,a0,v0
+[ 0-9a-f]+: 0045 2a90 or a1,a1,v0
+[ 0-9a-f]+: 0046 3290 or a2,a2,v0
+[ 0-9a-f]+: 0047 3a90 or a3,a3,v0
+[ 0-9a-f]+: 0050 8290 or s0,s0,v0
+[ 0-9a-f]+: 0051 8a90 or s1,s1,v0
+[ 0-9a-f]+: 0042 1290 or v0,v0,v0
+[ 0-9a-f]+: 0062 1290 or v0,v0,v1
+[ 0-9a-f]+: 0043 1290 or v0,v1,v0
+[ 0-9a-f]+: 0083 1290 or v0,v1,a0
+[ 0-9a-f]+: 03fe ea90 or sp,s8,ra
+[ 0-9a-f]+: 0082 1290 or v0,v0,a0
+[ 0-9a-f]+: 0082 1290 or v0,v0,a0
+[ 0-9a-f]+: 5043 8000 ori v0,v1,0x8000
+[ 0-9a-f]+: 5043 ffff ori v0,v1,0xffff
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1290 or v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0023 1290 or v0,v1,at
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1290 or v0,v1,at
+[ 0-9a-f]+: 5064 0000 ori v1,a0,0x0
+[ 0-9a-f]+: 5064 7fff ori v1,a0,0x7fff
+[ 0-9a-f]+: 5064 ffff ori v1,a0,0xffff
+[ 0-9a-f]+: 5063 ffff ori v1,v1,0xffff
+[ 0-9a-f]+: 5063 ffff ori v1,v1,0xffff
+[ 0-9a-f]+: 0040 01c0 rdhwr v0,hwr_cpunum
+[ 0-9a-f]+: 0041 01c0 rdhwr v0,hwr_synci_step
+[ 0-9a-f]+: 0042 01c0 rdhwr v0,hwr_cc
+[ 0-9a-f]+: 0043 01c0 rdhwr v0,hwr_ccres
+[ 0-9a-f]+: 0044 01c0 rdhwr v0,\$4
+[ 0-9a-f]+: 0045 01c0 rdhwr v0,\$5
+[ 0-9a-f]+: 0046 01c0 rdhwr v0,\$6
+[ 0-9a-f]+: 0047 01c0 rdhwr v0,\$7
+[ 0-9a-f]+: 0048 01c0 rdhwr v0,\$8
+[ 0-9a-f]+: 0049 01c0 rdhwr v0,\$9
+[ 0-9a-f]+: 004a 01c0 rdhwr v0,\$10
+[ 0-9a-f]+: 0043 e17c rdpgpr v0,v1
+[ 0-9a-f]+: 0042 e17c rdpgpr v0,v0
+[ 0-9a-f]+: 0042 e17c rdpgpr v0,v0
+[ 0-9a-f]+: 0080 11d0 negu v0,a0
+[ 0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ 0-9a-f]+: 0080 09d0 negu at,a0
+[ 0-9a-f]+: 0041 10d0 rorv v0,v0,at
+[ 0-9a-f]+: 0060 11d0 negu v0,v1
+[ 0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ 0-9a-f]+: 0040 11d0 negu v0,v0
+[ 0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ 0-9a-f]+: 0043 00c0 ror v0,v1,0x0
+[ 0-9a-f]+: 0043 f8c0 ror v0,v1,0x1f
+[ 0-9a-f]+: 0043 08c0 ror v0,v1,0x1
+[ 0-9a-f]+: 0042 08c0 ror v0,v0,0x1
+[ 0-9a-f]+: 0042 08c0 ror v0,v0,0x1
+[ 0-9a-f]+: 0043 00c0 ror v0,v1,0x0
+[ 0-9a-f]+: 0043 08c0 ror v0,v1,0x1
+[ 0-9a-f]+: 0043 f8c0 ror v0,v1,0x1f
+[ 0-9a-f]+: 0042 f8c0 ror v0,v0,0x1f
+[ 0-9a-f]+: 0042 f8c0 ror v0,v0,0x1f
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ 0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ 0-9a-f]+: 1803 0000 sb zero,0\(v1\)
+[ 0-9a-f]+: 1803 0000 sb zero,0\(v1\)
+[ 0-9a-f]+: 1803 0001 sb zero,1\(v1\)
+[ 0-9a-f]+: 1803 0002 sb zero,2\(v1\)
+[ 0-9a-f]+: 1803 0003 sb zero,3\(v1\)
+[ 0-9a-f]+: 1803 0004 sb zero,4\(v1\)
+[ 0-9a-f]+: 1803 0005 sb zero,5\(v1\)
+[ 0-9a-f]+: 1803 0006 sb zero,6\(v1\)
+[ 0-9a-f]+: 1803 0007 sb zero,7\(v1\)
+[ 0-9a-f]+: 1803 0008 sb zero,8\(v1\)
+[ 0-9a-f]+: 1803 0009 sb zero,9\(v1\)
+[ 0-9a-f]+: 1803 000a sb zero,10\(v1\)
+[ 0-9a-f]+: 1803 000b sb zero,11\(v1\)
+[ 0-9a-f]+: 1803 000c sb zero,12\(v1\)
+[ 0-9a-f]+: 1803 000d sb zero,13\(v1\)
+[ 0-9a-f]+: 1803 000e sb zero,14\(v1\)
+[ 0-9a-f]+: 1803 000f sb zero,15\(v1\)
+[ 0-9a-f]+: 1843 000f sb v0,15\(v1\)
+[ 0-9a-f]+: 1863 000f sb v1,15\(v1\)
+[ 0-9a-f]+: 1883 000f sb a0,15\(v1\)
+[ 0-9a-f]+: 18a3 000f sb a1,15\(v1\)
+[ 0-9a-f]+: 18c3 000f sb a2,15\(v1\)
+[ 0-9a-f]+: 18e3 000f sb a3,15\(v1\)
+[ 0-9a-f]+: 1a23 000f sb s1,15\(v1\)
+[ 0-9a-f]+: 1a24 000f sb s1,15\(a0\)
+[ 0-9a-f]+: 1a25 000f sb s1,15\(a1\)
+[ 0-9a-f]+: 1a26 000f sb s1,15\(a2\)
+[ 0-9a-f]+: 1a27 000f sb s1,15\(a3\)
+[ 0-9a-f]+: 1a22 000f sb s1,15\(v0\)
+[ 0-9a-f]+: 1a30 000f sb s1,15\(s0\)
+[ 0-9a-f]+: 1a31 000f sb s1,15\(s1\)
+[ 0-9a-f]+: 1860 0004 sb v1,4\(zero\)
+[ 0-9a-f]+: 1860 0004 sb v1,4\(zero\)
+[ 0-9a-f]+: 1860 7fff sb v1,32767\(zero\)
+[ 0-9a-f]+: 1860 8000 sb v1,-32768\(zero\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 1861 ffff sb v1,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1860 8000 sb v1,-32768\(zero\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 1860 8001 sb v1,-32767\(zero\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1860 ffff sb v1,-1\(zero\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 1861 5678 sb v1,22136\(at\)
+[ 0-9a-f]+: 1864 0000 sb v1,0\(a0\)
+[ 0-9a-f]+: 1864 0000 sb v1,0\(a0\)
+[ 0-9a-f]+: 1864 7fff sb v1,32767\(a0\)
+[ 0-9a-f]+: 1864 8000 sb v1,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 ffff sb v1,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1864 8000 sb v1,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ 0-9a-f]+: 1864 8001 sb v1,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ 0-9a-f]+: 1864 ffff sb v1,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 1861 5678 sb v1,22136\(at\)
+[ 0-9a-f]+: 6060 b004 sc v1,4\(zero\)
+[ 0-9a-f]+: 6060 b004 sc v1,4\(zero\)
+[ 0-9a-f]+: 6060 b0ff sc v1,255\(zero\)
+[ 0-9a-f]+: 6060 b100 sc v1,-256\(zero\)
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 6061 b1ff sc v1,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ 0-9a-f]+: 3020 8001 li at,-32767
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 6060 b1ff sc v1,-1\(zero\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5600 ori at,at,0x5600
+[ 0-9a-f]+: 6061 b078 sc v1,120\(at\)
+[ 0-9a-f]+: 6064 b000 sc v1,0\(a0\)
+[ 0-9a-f]+: 6064 b000 sc v1,0\(a0\)
+[ 0-9a-f]+: 6064 b0ff sc v1,255\(a0\)
+[ 0-9a-f]+: 6064 b100 sc v1,-256\(a0\)
+[ 0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b1ff sc v1,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ 0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ 0-9a-f]+: 6064 b1ff sc v1,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5600 ori at,at,0x5600
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 6061 b078 sc v1,120\(at\)
+[ 0-9a-f]+: 0000 db7c sdbbp
+[ 0-9a-f]+: 0000 db7c sdbbp
+[ 0-9a-f]+: 0001 db7c sdbbp 0x1
+[ 0-9a-f]+: 0002 db7c sdbbp 0x2
+[ 0-9a-f]+: 0003 db7c sdbbp 0x3
+[ 0-9a-f]+: 0004 db7c sdbbp 0x4
+[ 0-9a-f]+: 0005 db7c sdbbp 0x5
+[ 0-9a-f]+: 0006 db7c sdbbp 0x6
+[ 0-9a-f]+: 0007 db7c sdbbp 0x7
+[ 0-9a-f]+: 0008 db7c sdbbp 0x8
+[ 0-9a-f]+: 0009 db7c sdbbp 0x9
+[ 0-9a-f]+: 000a db7c sdbbp 0xa
+[ 0-9a-f]+: 000b db7c sdbbp 0xb
+[ 0-9a-f]+: 000c db7c sdbbp 0xc
+[ 0-9a-f]+: 000d db7c sdbbp 0xd
+[ 0-9a-f]+: 000e db7c sdbbp 0xe
+[ 0-9a-f]+: 000f db7c sdbbp 0xf
+[ 0-9a-f]+: 0000 db7c sdbbp
+[ 0-9a-f]+: 0000 db7c sdbbp
+[ 0-9a-f]+: 0001 db7c sdbbp 0x1
+[ 0-9a-f]+: 0002 db7c sdbbp 0x2
+[ 0-9a-f]+: 00ff db7c sdbbp 0xff
+[ 0-9a-f]+: 0043 2b3c seb v0,v1
+[ 0-9a-f]+: 0042 2b3c seb v0,v0
+[ 0-9a-f]+: 0042 2b3c seb v0,v0
+[ 0-9a-f]+: 0043 3b3c seh v0,v1
+[ 0-9a-f]+: 0042 3b3c seh v0,v0
+[ 0-9a-f]+: 0042 3b3c seh v0,v0
+[ 0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: b043 0001 sltiu v0,v1,1
+[ 0-9a-f]+: b044 0001 sltiu v0,a0,1
+[ 0-9a-f]+: b043 0001 sltiu v0,v1,1
+[ 0-9a-f]+: 7043 0001 xori v0,v1,0x1
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: 3043 0001 addiu v0,v1,1
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ 0-9a-f]+: 0083 1350 slt v0,v1,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 8000 slti v0,v1,-32768
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 9043 7fff slti v0,v1,32767
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0083 1390 sltu v0,v1,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 8000 sltiu v0,v1,-32768
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: b043 7fff sltiu v0,v1,32767
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0064 1350 slt v0,a0,v1
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 0064 1390 sltu v0,a0,v1
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 3843 0000 sh v0,0\(v1\)
+[ 0-9a-f]+: 3843 0000 sh v0,0\(v1\)
+[ 0-9a-f]+: 3843 0002 sh v0,2\(v1\)
+[ 0-9a-f]+: 3843 0004 sh v0,4\(v1\)
+[ 0-9a-f]+: 3843 0006 sh v0,6\(v1\)
+[ 0-9a-f]+: 3843 0008 sh v0,8\(v1\)
+[ 0-9a-f]+: 3843 000a sh v0,10\(v1\)
+[ 0-9a-f]+: 3843 000c sh v0,12\(v1\)
+[ 0-9a-f]+: 3843 000e sh v0,14\(v1\)
+[ 0-9a-f]+: 3843 0010 sh v0,16\(v1\)
+[ 0-9a-f]+: 3843 0012 sh v0,18\(v1\)
+[ 0-9a-f]+: 3843 0014 sh v0,20\(v1\)
+[ 0-9a-f]+: 3843 0016 sh v0,22\(v1\)
+[ 0-9a-f]+: 3843 0018 sh v0,24\(v1\)
+[ 0-9a-f]+: 3843 001a sh v0,26\(v1\)
+[ 0-9a-f]+: 3843 001c sh v0,28\(v1\)
+[ 0-9a-f]+: 3843 001e sh v0,30\(v1\)
+[ 0-9a-f]+: 3844 001e sh v0,30\(a0\)
+[ 0-9a-f]+: 3845 001e sh v0,30\(a1\)
+[ 0-9a-f]+: 3846 001e sh v0,30\(a2\)
+[ 0-9a-f]+: 3847 001e sh v0,30\(a3\)
+[ 0-9a-f]+: 3842 001e sh v0,30\(v0\)
+[ 0-9a-f]+: 3850 001e sh v0,30\(s0\)
+[ 0-9a-f]+: 3851 001e sh v0,30\(s1\)
+[ 0-9a-f]+: 3871 001e sh v1,30\(s1\)
+[ 0-9a-f]+: 3891 001e sh a0,30\(s1\)
+[ 0-9a-f]+: 38b1 001e sh a1,30\(s1\)
+[ 0-9a-f]+: 38d1 001e sh a2,30\(s1\)
+[ 0-9a-f]+: 38f1 001e sh a3,30\(s1\)
+[ 0-9a-f]+: 3a31 001e sh s1,30\(s1\)
+[ 0-9a-f]+: 3811 001e sh zero,30\(s1\)
+[ 0-9a-f]+: 3860 0004 sh v1,4\(zero\)
+[ 0-9a-f]+: 3860 0004 sh v1,4\(zero\)
+[ 0-9a-f]+: 3860 7fff sh v1,32767\(zero\)
+[ 0-9a-f]+: 3860 8000 sh v1,-32768\(zero\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 3861 ffff sh v1,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3860 8000 sh v1,-32768\(zero\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 3861 0001 sh v1,1\(at\)
+[ 0-9a-f]+: 3860 8001 sh v1,-32767\(zero\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3860 ffff sh v1,-1\(zero\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 3861 5678 sh v1,22136\(at\)
+[ 0-9a-f]+: 3864 0000 sh v1,0\(a0\)
+[ 0-9a-f]+: 3864 0000 sh v1,0\(a0\)
+[ 0-9a-f]+: 3864 7fff sh v1,32767\(a0\)
+[ 0-9a-f]+: 3864 8000 sh v1,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 ffff sh v1,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3864 8000 sh v1,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 0001 sh v1,1\(at\)
+[ 0-9a-f]+: 3864 8001 sh v1,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ 0-9a-f]+: 3864 ffff sh v1,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 3861 5678 sh v1,22136\(at\)
+[ 0-9a-f]+: 0064 1350 slt v0,a0,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1350 slt v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0064 1390 sltu v0,a0,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ 0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ 0-9a-f]+: 0042 0800 sll v0,v0,0x1
+[ 0-9a-f]+: 0042 1000 sll v0,v0,0x2
+[ 0-9a-f]+: 0042 1800 sll v0,v0,0x3
+[ 0-9a-f]+: 0042 2000 sll v0,v0,0x4
+[ 0-9a-f]+: 0042 2800 sll v0,v0,0x5
+[ 0-9a-f]+: 0042 3000 sll v0,v0,0x6
+[ 0-9a-f]+: 0042 3800 sll v0,v0,0x7
+[ 0-9a-f]+: 0042 4000 sll v0,v0,0x8
+[ 0-9a-f]+: 0043 4000 sll v0,v1,0x8
+[ 0-9a-f]+: 0044 4000 sll v0,a0,0x8
+[ 0-9a-f]+: 0045 4000 sll v0,a1,0x8
+[ 0-9a-f]+: 0046 4000 sll v0,a2,0x8
+[ 0-9a-f]+: 0047 4000 sll v0,a3,0x8
+[ 0-9a-f]+: 0050 4000 sll v0,s0,0x8
+[ 0-9a-f]+: 0051 4000 sll v0,s1,0x8
+[ 0-9a-f]+: 0062 4000 sll v1,v0,0x8
+[ 0-9a-f]+: 0082 4000 sll a0,v0,0x8
+[ 0-9a-f]+: 00a2 4000 sll a1,v0,0x8
+[ 0-9a-f]+: 00c2 4000 sll a2,v0,0x8
+[ 0-9a-f]+: 00e2 4000 sll a3,v0,0x8
+[ 0-9a-f]+: 0202 4000 sll s0,v0,0x8
+[ 0-9a-f]+: 0222 4000 sll s1,v0,0x8
+[ 0-9a-f]+: 0042 0800 sll v0,v0,0x1
+[ 0-9a-f]+: 0063 0800 sll v1,v1,0x1
+[ 0-9a-f]+: 0064 1010 sllv v0,v1,a0
+[ 0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ 0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ 0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ 0-9a-f]+: 0044 0000 sll v0,a0,0x0
+[ 0-9a-f]+: 0044 0800 sll v0,a0,0x1
+[ 0-9a-f]+: 0044 f800 sll v0,a0,0x1f
+[ 0-9a-f]+: 0042 f800 sll v0,v0,0x1f
+[ 0-9a-f]+: 0042 f800 sll v0,v0,0x1f
+[ 0-9a-f]+: 0083 1350 slt v0,v1,a0
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 9043 8000 slti v0,v1,-32768
+[ 0-9a-f]+: 9043 0000 slti v0,v1,0
+[ 0-9a-f]+: 9043 7fff slti v0,v1,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1350 slt v0,v1,at
+[ 0-9a-f]+: 9064 8000 slti v1,a0,-32768
+[ 0-9a-f]+: 9064 0000 slti v1,a0,0
+[ 0-9a-f]+: 9064 7fff slti v1,a0,32767
+[ 0-9a-f]+: 9064 ffff slti v1,a0,-1
+[ 0-9a-f]+: 9063 ffff slti v1,v1,-1
+[ 0-9a-f]+: 9063 ffff slti v1,v1,-1
+[ 0-9a-f]+: b064 8000 sltiu v1,a0,-32768
+[ 0-9a-f]+: b064 0000 sltiu v1,a0,0
+[ 0-9a-f]+: b064 7fff sltiu v1,a0,32767
+[ 0-9a-f]+: b064 ffff sltiu v1,a0,-1
+[ 0-9a-f]+: b063 ffff sltiu v1,v1,-1
+[ 0-9a-f]+: b063 ffff sltiu v1,v1,-1
+[ 0-9a-f]+: 0083 1390 sltu v0,v1,a0
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: b043 8000 sltiu v0,v1,-32768
+[ 0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ 0-9a-f]+: b043 7fff sltiu v0,v1,32767
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ 0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 0080 1390 sltu v0,zero,a0
+[ 0-9a-f]+: 0060 1390 sltu v0,zero,v1
+[ 0-9a-f]+: 0060 1390 sltu v0,zero,v1
+[ 0-9a-f]+: 7043 0001 xori v0,v1,0x1
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 3043 0001 addiu v0,v1,1
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ 0-9a-f]+: 0064 1090 srav v0,v1,a0
+[ 0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ 0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ 0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ 0-9a-f]+: 0044 0080 sra v0,a0,0x0
+[ 0-9a-f]+: 0044 0880 sra v0,a0,0x1
+[ 0-9a-f]+: 0044 f880 sra v0,a0,0x1f
+[ 0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ 0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ 0-9a-f]+: 0064 1050 srlv v0,v1,a0
+[ 0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ 0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ 0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ 0-9a-f]+: 0044 0040 srl v0,a0,0x0
+[ 0-9a-f]+: 0044 0840 srl v0,a0,0x1
+[ 0-9a-f]+: 0044 f840 srl v0,a0,0x1f
+[ 0-9a-f]+: 0042 f840 srl v0,v0,0x1f
+[ 0-9a-f]+: 0042 f840 srl v0,v0,0x1f
+[ 0-9a-f]+: 0042 0840 srl v0,v0,0x1
+[ 0-9a-f]+: 0042 1040 srl v0,v0,0x2
+[ 0-9a-f]+: 0042 1840 srl v0,v0,0x3
+[ 0-9a-f]+: 0042 2040 srl v0,v0,0x4
+[ 0-9a-f]+: 0042 2840 srl v0,v0,0x5
+[ 0-9a-f]+: 0042 3040 srl v0,v0,0x6
+[ 0-9a-f]+: 0042 3840 srl v0,v0,0x7
+[ 0-9a-f]+: 0042 4040 srl v0,v0,0x8
+[ 0-9a-f]+: 0043 4040 srl v0,v1,0x8
+[ 0-9a-f]+: 0044 4040 srl v0,a0,0x8
+[ 0-9a-f]+: 0045 4040 srl v0,a1,0x8
+[ 0-9a-f]+: 0046 4040 srl v0,a2,0x8
+[ 0-9a-f]+: 0047 4040 srl v0,a3,0x8
+[ 0-9a-f]+: 0050 4040 srl v0,s0,0x8
+[ 0-9a-f]+: 0051 4040 srl v0,s1,0x8
+[ 0-9a-f]+: 0042 4040 srl v0,v0,0x8
+[ 0-9a-f]+: 0062 4040 srl v1,v0,0x8
+[ 0-9a-f]+: 0082 4040 srl a0,v0,0x8
+[ 0-9a-f]+: 00a2 4040 srl a1,v0,0x8
+[ 0-9a-f]+: 00c2 4040 srl a2,v0,0x8
+[ 0-9a-f]+: 00e2 4040 srl a3,v0,0x8
+[ 0-9a-f]+: 0202 4040 srl s0,v0,0x8
+[ 0-9a-f]+: 0222 4040 srl s1,v0,0x8
+[ 0-9a-f]+: 0063 0840 srl v1,v1,0x1
+[ 0-9a-f]+: 0063 0840 srl v1,v1,0x1
+[ 0-9a-f]+: 0083 1190 sub v0,v1,a0
+[ 0-9a-f]+: 03fe e990 sub sp,s8,ra
+[ 0-9a-f]+: 0082 1190 sub v0,v0,a0
+[ 0-9a-f]+: 0082 1190 sub v0,v0,a0
+[ 0-9a-f]+: 0043 11d0 subu v0,v1,v0
+[ 0-9a-f]+: 0063 11d0 subu v0,v1,v1
+[ 0-9a-f]+: 0083 11d0 subu v0,v1,a0
+[ 0-9a-f]+: 00a3 11d0 subu v0,v1,a1
+[ 0-9a-f]+: 00c3 11d0 subu v0,v1,a2
+[ 0-9a-f]+: 00e3 11d0 subu v0,v1,a3
+[ 0-9a-f]+: 0203 11d0 subu v0,v1,s0
+[ 0-9a-f]+: 0223 11d0 subu v0,v1,s1
+[ 0-9a-f]+: 0222 11d0 subu v0,v0,s1
+[ 0-9a-f]+: 0224 11d0 subu v0,a0,s1
+[ 0-9a-f]+: 0225 11d0 subu v0,a1,s1
+[ 0-9a-f]+: 0226 11d0 subu v0,a2,s1
+[ 0-9a-f]+: 0227 11d0 subu v0,a3,s1
+[ 0-9a-f]+: 0230 11d0 subu v0,s0,s1
+[ 0-9a-f]+: 0231 11d0 subu v0,s1,s1
+[ 0-9a-f]+: 0222 11d0 subu v0,v0,s1
+[ 0-9a-f]+: 0222 19d0 subu v1,v0,s1
+[ 0-9a-f]+: 0222 21d0 subu a0,v0,s1
+[ 0-9a-f]+: 0222 29d0 subu a1,v0,s1
+[ 0-9a-f]+: 0222 31d0 subu a2,v0,s1
+[ 0-9a-f]+: 0222 39d0 subu a3,v0,s1
+[ 0-9a-f]+: 0222 81d0 subu s0,v0,s1
+[ 0-9a-f]+: 0222 89d0 subu s1,v0,s1
+[ 0-9a-f]+: 0047 39d0 subu a3,a3,v0
+[ 0-9a-f]+: 0047 39d0 subu a3,a3,v0
+[ 0-9a-f]+: 0083 11d0 subu v0,v1,a0
+[ 0-9a-f]+: 03fe e9d0 subu sp,s8,ra
+[ 0-9a-f]+: 0082 11d0 subu v0,v0,a0
+[ 0-9a-f]+: 0082 11d0 subu v0,v0,a0
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ 0-9a-f]+: 3042 ffff addiu v0,v0,-1
+[ 0-9a-f]+: 3042 8001 addiu v0,v0,-32767
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 11d0 subu v0,v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 11d0 subu v0,v0,at
+[ 0-9a-f]+: f844 0000 sw v0,0\(a0\)
+[ 0-9a-f]+: f844 0000 sw v0,0\(a0\)
+[ 0-9a-f]+: f844 0004 sw v0,4\(a0\)
+[ 0-9a-f]+: f844 0008 sw v0,8\(a0\)
+[ 0-9a-f]+: f844 000c sw v0,12\(a0\)
+[ 0-9a-f]+: f844 0010 sw v0,16\(a0\)
+[ 0-9a-f]+: f844 0014 sw v0,20\(a0\)
+[ 0-9a-f]+: f844 0018 sw v0,24\(a0\)
+[ 0-9a-f]+: f844 001c sw v0,28\(a0\)
+[ 0-9a-f]+: f844 0020 sw v0,32\(a0\)
+[ 0-9a-f]+: f844 0024 sw v0,36\(a0\)
+[ 0-9a-f]+: f844 0028 sw v0,40\(a0\)
+[ 0-9a-f]+: f844 002c sw v0,44\(a0\)
+[ 0-9a-f]+: f844 0030 sw v0,48\(a0\)
+[ 0-9a-f]+: f844 0034 sw v0,52\(a0\)
+[ 0-9a-f]+: f844 0038 sw v0,56\(a0\)
+[ 0-9a-f]+: f844 003c sw v0,60\(a0\)
+[ 0-9a-f]+: f845 003c sw v0,60\(a1\)
+[ 0-9a-f]+: f846 003c sw v0,60\(a2\)
+[ 0-9a-f]+: f847 003c sw v0,60\(a3\)
+[ 0-9a-f]+: f850 003c sw v0,60\(s0\)
+[ 0-9a-f]+: f851 003c sw v0,60\(s1\)
+[ 0-9a-f]+: f842 003c sw v0,60\(v0\)
+[ 0-9a-f]+: f843 003c sw v0,60\(v1\)
+[ 0-9a-f]+: f863 003c sw v1,60\(v1\)
+[ 0-9a-f]+: f883 003c sw a0,60\(v1\)
+[ 0-9a-f]+: f8a3 003c sw a1,60\(v1\)
+[ 0-9a-f]+: f8c3 003c sw a2,60\(v1\)
+[ 0-9a-f]+: f8e3 003c sw a3,60\(v1\)
+[ 0-9a-f]+: fa23 003c sw s1,60\(v1\)
+[ 0-9a-f]+: f803 003c sw zero,60\(v1\)
+[ 0-9a-f]+: f81d 0000 sw zero,0\(sp\)
+[ 0-9a-f]+: f81d 0000 sw zero,0\(sp\)
+[ 0-9a-f]+: f81d 0004 sw zero,4\(sp\)
+[ 0-9a-f]+: f81d 0008 sw zero,8\(sp\)
+[ 0-9a-f]+: f81d 000c sw zero,12\(sp\)
+[ 0-9a-f]+: f81d 0010 sw zero,16\(sp\)
+[ 0-9a-f]+: f81d 0014 sw zero,20\(sp\)
+[ 0-9a-f]+: f81d 0078 sw zero,120\(sp\)
+[ 0-9a-f]+: f81d 007c sw zero,124\(sp\)
+[ 0-9a-f]+: f85d 007c sw v0,124\(sp\)
+[ 0-9a-f]+: fa3d 007c sw s1,124\(sp\)
+[ 0-9a-f]+: f87d 007c sw v1,124\(sp\)
+[ 0-9a-f]+: f89d 007c sw a0,124\(sp\)
+[ 0-9a-f]+: f8bd 007c sw a1,124\(sp\)
+[ 0-9a-f]+: f8dd 007c sw a2,124\(sp\)
+[ 0-9a-f]+: f8fd 007c sw a3,124\(sp\)
+[ 0-9a-f]+: fbfd 007c sw ra,124\(sp\)
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f860 7fff sw v1,32767\(zero\)
+[ 0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f860 8001 sw v1,-32767\(zero\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f860 ffff sw v1,-1\(zero\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f864 7fff sw v1,32767\(a0\)
+[ 0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f864 8001 sw v1,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f864 ffff sw v1,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: 223d d030 swm s0,ra,48\(sp\)
+[ 0-9a-f]+: 225d d030 swm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 225d d030 swm s0-s1,ra,48\(sp\)
+[ 0-9a-f]+: 227d d030 swm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 227d d030 swm s0-s2,ra,48\(sp\)
+[ 0-9a-f]+: 229d d030 swm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 229d d030 swm s0-s3,ra,48\(sp\)
+[ 0-9a-f]+: 223d d000 swm s0,ra,0\(sp\)
+[ 0-9a-f]+: 223d d000 swm s0,ra,0\(sp\)
+[ 0-9a-f]+: 223d d004 swm s0,ra,4\(sp\)
+[ 0-9a-f]+: 223d d008 swm s0,ra,8\(sp\)
+[ 0-9a-f]+: 223d d00c swm s0,ra,12\(sp\)
+[ 0-9a-f]+: 223d d010 swm s0,ra,16\(sp\)
+[ 0-9a-f]+: 223d d014 swm s0,ra,20\(sp\)
+[ 0-9a-f]+: 223d d018 swm s0,ra,24\(sp\)
+[ 0-9a-f]+: 223d d01c swm s0,ra,28\(sp\)
+[ 0-9a-f]+: 223d d020 swm s0,ra,32\(sp\)
+[ 0-9a-f]+: 223d d024 swm s0,ra,36\(sp\)
+[ 0-9a-f]+: 223d d028 swm s0,ra,40\(sp\)
+[ 0-9a-f]+: 223d d02c swm s0,ra,44\(sp\)
+[ 0-9a-f]+: 223d d030 swm s0,ra,48\(sp\)
+[ 0-9a-f]+: 223d d034 swm s0,ra,52\(sp\)
+[ 0-9a-f]+: 223d d038 swm s0,ra,56\(sp\)
+[ 0-9a-f]+: 223d d03c swm s0,ra,60\(sp\)
+[ 0-9a-f]+: 2020 d000 swm s0,0\(zero\)
+[ 0-9a-f]+: 2020 d004 swm s0,4\(zero\)
+[ 0-9a-f]+: 2020 d7ff swm s0,2047\(zero\)
+[ 0-9a-f]+: 2020 d800 swm s0,-2048\(zero\)
+[ 0-9a-f]+: 3020 0800 li at,2048
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 3020 f7ff li at,-2049
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 2025 d000 swm s0,0\(a1\)
+[ 0-9a-f]+: 2025 d7ff swm s0,2047\(a1\)
+[ 0-9a-f]+: 2025 d800 swm s0,-2048\(a1\)
+[ 0-9a-f]+: 3025 0800 addiu at,a1,2048
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 3025 f7ff addiu at,a1,-2049
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 2045 d7ff swm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 d7ff swm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 d7ff swm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 d7ff swm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 d7ff swm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 d7ff swm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 d7ff swm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 d7ff swm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 d7ff swm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 d000 swm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 d000 swm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 d000 swm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 d000 swm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 d000 swm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 d000 swm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 d000 swm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 d000 swm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 d000 swm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 303d 8000 addiu at,sp,-32768
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 303d 7fff addiu at,sp,32767
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 203d d000 swm s0,0\(sp\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 dfff swm s0,-1\(at\)
+[ 0-9a-f]+: 2040 9000 swp v0,0\(zero\)
+[ 0-9a-f]+: 2040 9004 swp v0,4\(zero\)
+[ 0-9a-f]+: 2040 97ff swp v0,2047\(zero\)
+[ 0-9a-f]+: 2040 9800 swp v0,-2048\(zero\)
+[ 0-9a-f]+: 3020 0800 li at,2048
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 3020 f7ff li at,-2049
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 205d 9000 swp v0,0\(sp\)
+[ 0-9a-f]+: 205d 9000 swp v0,0\(sp\)
+[ 0-9a-f]+: 2043 97ff swp v0,2047\(v1\)
+[ 0-9a-f]+: 2043 9800 swp v0,-2048\(v1\)
+[ 0-9a-f]+: 3023 0800 addiu at,v1,2048
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 3023 f7ff addiu at,v1,-2049
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 3023 7fff addiu at,v1,32767
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 3023 8000 addiu at,v1,-32768
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 2043 9000 swp v0,0\(v1\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 9fff swp v0,-1\(at\)
+[ 0-9a-f]+: 0000 6b7c sync
+[ 0-9a-f]+: 0000 6b7c sync
+[ 0-9a-f]+: 0001 6b7c sync 0x1
+[ 0-9a-f]+: 0002 6b7c sync 0x2
+[ 0-9a-f]+: 0003 6b7c sync 0x3
+[ 0-9a-f]+: 0004 6b7c sync_wmb
+[ 0-9a-f]+: 001e 6b7c sync 0x1e
+[ 0-9a-f]+: 001f 6b7c sync 0x1f
+[ 0-9a-f]+: 4180 0000 synci 0\(zero\)
+[ 0-9a-f]+: 4180 0000 synci 0\(zero\)
+[ 0-9a-f]+: 4180 0000 synci 0\(zero\)
+[ 0-9a-f]+: 4180 07ff synci 2047\(zero\)
+[ 0-9a-f]+: 4180 f800 synci -2048\(zero\)
+[ 0-9a-f]+: 4180 0800 synci 2048\(zero\)
+[ 0-9a-f]+: 4180 f7ff synci -2049\(zero\)
+[ 0-9a-f]+: 4180 7fff synci 32767\(zero\)
+[ 0-9a-f]+: 4180 8000 synci -32768\(zero\)
+[ 0-9a-f]+: 4182 0000 synci 0\(v0\)
+[ 0-9a-f]+: 4183 0000 synci 0\(v1\)
+[ 0-9a-f]+: 4183 07ff synci 2047\(v1\)
+[ 0-9a-f]+: 4183 f800 synci -2048\(v1\)
+[ 0-9a-f]+: 4183 0800 synci 2048\(v1\)
+[ 0-9a-f]+: 4183 f7ff synci -2049\(v1\)
+[ 0-9a-f]+: 4183 7fff synci 32767\(v1\)
+[ 0-9a-f]+: 4183 8000 synci -32768\(v1\)
+[ 0-9a-f]+: 0000 8b7c syscall
+[ 0-9a-f]+: 0000 8b7c syscall
+[ 0-9a-f]+: 0001 8b7c syscall 0x1
+[ 0-9a-f]+: 0002 8b7c syscall 0x2
+[ 0-9a-f]+: 00ff 8b7c syscall 0xff
+[ 0-9a-f]+: 0062 003c teq v0,v1
+[ 0-9a-f]+: 0043 003c teq v1,v0
+[ 0-9a-f]+: 0062 003c teq v0,v1
+[ 0-9a-f]+: 0062 103c teq v0,v1,0x1
+[ 0-9a-f]+: 0062 f03c teq v0,v1,0xf
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0022 003c teq v0,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 003c teq v0,at
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0022 003c teq v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 003c teq v0,at
+[ 0-9a-f]+: 0062 023c tge v0,v1
+[ 0-9a-f]+: 0043 023c tge v1,v0
+[ 0-9a-f]+: 0062 023c tge v0,v1
+[ 0-9a-f]+: 0062 123c tge v0,v1,0x1
+[ 0-9a-f]+: 0062 f23c tge v0,v1,0xf
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0022 023c tge v0,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 023c tge v0,at
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0022 023c tge v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 023c tge v0,at
+[ 0-9a-f]+: 0062 043c tgeu v0,v1
+[ 0-9a-f]+: 0043 043c tgeu v1,v0
+[ 0-9a-f]+: 0062 043c tgeu v0,v1
+[ 0-9a-f]+: 0062 143c tgeu v0,v1,0x1
+[ 0-9a-f]+: 0062 f43c tgeu v0,v1,0xf
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0022 043c tgeu v0,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 043c tgeu v0,at
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0022 043c tgeu v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 043c tgeu v0,at
+[ 0-9a-f]+: 0000 037c tlbp
+[ 0-9a-f]+: 0000 137c tlbr
+[ 0-9a-f]+: 0000 237c tlbwi
+[ 0-9a-f]+: 0000 337c tlbwr
+[ 0-9a-f]+: 0062 083c tlt v0,v1
+[ 0-9a-f]+: 0043 083c tlt v1,v0
+[ 0-9a-f]+: 0062 083c tlt v0,v1
+[ 0-9a-f]+: 0062 183c tlt v0,v1,0x1
+[ 0-9a-f]+: 0062 f83c tlt v0,v1,0xf
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0022 083c tlt v0,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 083c tlt v0,at
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0022 083c tlt v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 083c tlt v0,at
+[ 0-9a-f]+: 0062 0a3c tltu v0,v1
+[ 0-9a-f]+: 0043 0a3c tltu v1,v0
+[ 0-9a-f]+: 0062 0a3c tltu v0,v1
+[ 0-9a-f]+: 0062 1a3c tltu v0,v1,0x1
+[ 0-9a-f]+: 0062 fa3c tltu v0,v1,0xf
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 0062 0c3c tne v0,v1
+[ 0-9a-f]+: 0043 0c3c tne v1,v0
+[ 0-9a-f]+: 0062 0c3c tne v0,v1
+[ 0-9a-f]+: 0062 1c3c tne v0,v1,0x1
+[ 0-9a-f]+: 0062 fc3c tne v0,v1,0xf
+[ 0-9a-f]+: 3020 0000 li at,0
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 3020 ffff li at,-1
+[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 0000 937c wait
+[ 0-9a-f]+: 0000 937c wait
+[ 0-9a-f]+: 0001 937c wait 0x1
+[ 0-9a-f]+: 00ff 937c wait 0xff
+[ 0-9a-f]+: 0043 f17c wrpgpr v0,v1
+[ 0-9a-f]+: 0044 f17c wrpgpr v0,a0
+[ 0-9a-f]+: 0042 f17c wrpgpr v0,v0
+[ 0-9a-f]+: 0042 f17c wrpgpr v0,v0
+[ 0-9a-f]+: 0043 7b3c wsbh v0,v1
+[ 0-9a-f]+: 0044 7b3c wsbh v0,a0
+[ 0-9a-f]+: 0042 7b3c wsbh v0,v0
+[ 0-9a-f]+: 0042 7b3c wsbh v0,v0
+[ 0-9a-f]+: 0042 1310 xor v0,v0,v0
+[ 0-9a-f]+: 0062 1310 xor v0,v0,v1
+[ 0-9a-f]+: 0082 1310 xor v0,v0,a0
+[ 0-9a-f]+: 00a2 1310 xor v0,v0,a1
+[ 0-9a-f]+: 00c2 1310 xor v0,v0,a2
+[ 0-9a-f]+: 00e2 1310 xor v0,v0,a3
+[ 0-9a-f]+: 0202 1310 xor v0,v0,s0
+[ 0-9a-f]+: 0222 1310 xor v0,v0,s1
+[ 0-9a-f]+: 0223 1b10 xor v1,v1,s1
+[ 0-9a-f]+: 0224 2310 xor a0,a0,s1
+[ 0-9a-f]+: 0225 2b10 xor a1,a1,s1
+[ 0-9a-f]+: 0226 3310 xor a2,a2,s1
+[ 0-9a-f]+: 0227 3b10 xor a3,a3,s1
+[ 0-9a-f]+: 0230 8310 xor s0,s0,s1
+[ 0-9a-f]+: 0231 8b10 xor s1,s1,s1
+[ 0-9a-f]+: 0062 1310 xor v0,v0,v1
+[ 0-9a-f]+: 0062 1310 xor v0,v0,v1
+[ 0-9a-f]+: 0043 1310 xor v0,v1,v0
+[ 0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ 0-9a-f]+: 03fe eb10 xor sp,s8,ra
+[ 0-9a-f]+: 0082 1310 xor v0,v0,a0
+[ 0-9a-f]+: 0082 1310 xor v0,v0,a0
+[ 0-9a-f]+: 7043 8000 xori v0,v1,0x8000
+[ 0-9a-f]+: 7043 ffff xori v0,v1,0xffff
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ 0-9a-f]+: 0023 1310 xor v0,v1,at
+[ 0-9a-f]+: 7064 0000 xori v1,a0,0x0
+[ 0-9a-f]+: 7064 7fff xori v1,a0,0x7fff
+[ 0-9a-f]+: 7064 ffff xori v1,a0,0xffff
+[ 0-9a-f]+: 7063 ffff xori v1,v1,0xffff
+[ 0-9a-f]+: 7063 ffff xori v1,v1,0xffff
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f880 0008 sw a0,8\(zero\)
+[ 0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ 0-9a-f]+: f880 0008 sw a0,8\(zero\)
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ 0-9a-f]+: f880 8004 sw a0,-32764\(zero\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ 0-9a-f]+: f880 8004 sw a0,-32764\(zero\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f881 0005 sw a0,5\(at\)
+[ 0-9a-f]+: f860 8001 sw v1,-32767\(zero\)
+[ 0-9a-f]+: f880 8005 sw a0,-32763\(zero\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: f860 ffff sw v1,-1\(zero\)
+[ 0-9a-f]+: f880 0003 sw a0,3\(zero\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: f881 567c sw a0,22140\(at\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f884 0004 sw a0,4\(a0\)
+[ 0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ 0-9a-f]+: f884 0004 sw a0,4\(a0\)
+[ 0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ 0-9a-f]+: f884 8004 sw a0,-32764\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ 0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ 0-9a-f]+: f884 8004 sw a0,-32764\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ 0-9a-f]+: f881 0005 sw a0,5\(at\)
+[ 0-9a-f]+: f864 8001 sw v1,-32767\(a0\)
+[ 0-9a-f]+: f884 8005 sw a0,-32763\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ 0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ 0-9a-f]+: f864 ffff sw v1,-1\(a0\)
+[ 0-9a-f]+: f884 0003 sw a0,3\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ 0-9a-f]+: f881 567c sw a0,22140\(at\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc80 0008 lw a0,8\(zero\)
+[ 0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ 0-9a-f]+: fc80 0008 lw a0,8\(zero\)
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ 0-9a-f]+: fc80 8004 lw a0,-32764\(zero\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ 0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ 0-9a-f]+: fc80 8004 lw a0,-32764\(zero\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: fc61 0001 lw v1,1\(at\)
+[ 0-9a-f]+: fc81 0005 lw a0,5\(at\)
+[ 0-9a-f]+: fc60 8001 lw v1,-32767\(zero\)
+[ 0-9a-f]+: fc80 8005 lw a0,-32763\(zero\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: fc60 ffff lw v1,-1\(zero\)
+[ 0-9a-f]+: fc80 0003 lw a0,3\(zero\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: fc61 5678 lw v1,22136\(at\)
+[ 0-9a-f]+: fc81 567c lw a0,22140\(at\)
+[ 0-9a-f]+: fc64 0000 lw v1,0\(a0\)
+[ 0-9a-f]+: fc84 0004 lw a0,4\(a0\)
+[ 0-9a-f]+: fc64 0000 lw v1,0\(a0\)
+[ 0-9a-f]+: fc84 0004 lw a0,4\(a0\)
+[ 0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ 0-9a-f]+: fc84 8004 lw a0,-32764\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ 0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ 0-9a-f]+: fc84 8004 lw a0,-32764\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 0001 lw v1,1\(at\)
+[ 0-9a-f]+: fc81 0005 lw a0,5\(at\)
+[ 0-9a-f]+: fc64 8001 lw v1,-32767\(a0\)
+[ 0-9a-f]+: fc84 8005 lw a0,-32763\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ 0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ 0-9a-f]+: fc64 ffff lw v1,-1\(a0\)
+[ 0-9a-f]+: fc84 0003 lw a0,3\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0024 0950 addu at,a0,at
+[ 0-9a-f]+: fc61 5678 lw v1,22136\(at\)
+[ 0-9a-f]+: fc81 567c lw a0,22140\(at\)
+[ 0-9a-f]+: 33bd 0000 addiu sp,sp,0
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 0004 addiu sp,sp,4
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 0008 addiu sp,sp,8
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 000c addiu sp,sp,12
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 0010 addiu sp,sp,16
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 0014 addiu sp,sp,20
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 0018 addiu sp,sp,24
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 001c addiu sp,sp,28
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 0020 addiu sp,sp,32
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 0024 addiu sp,sp,36
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 0028 addiu sp,sp,40
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 0078 addiu sp,sp,120
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 33bd 007c addiu sp,sp,124
+[ 0-9a-f]+: 801f 0000 jrc ra
+[ 0-9a-f]+: 2060 2000 ldc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 2000 ldc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 2004 ldc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 2004 ldc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 2000 ldc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 2000 ldc2 \$3,0\(a0\)
+[ 0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 27ff ldc2 \$3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2001 ldc2 \$3,1\(at\)
+[ 0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 27ff ldc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5800 ori at,at,0x5800
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 2678 ldc2 \$3,-392\(at\)
+[ 0-9a-f]+: 2060 0000 lwc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 0000 lwc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 0004 lwc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 0004 lwc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 0000 lwc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 0000 lwc2 \$3,0\(a0\)
+[ 0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 07ff lwc2 \$3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0001 lwc2 \$3,1\(at\)
+[ 0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 07ff lwc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5800 ori at,at,0x5800
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 0678 lwc2 \$3,-392\(at\)
+[ 0-9a-f]+: 00a0 4d3c mfc2 a1,\$0
+[ 0-9a-f]+: 00a1 4d3c mfc2 a1,\$1
+[ 0-9a-f]+: 00a2 4d3c mfc2 a1,\$2
+[ 0-9a-f]+: 00a3 4d3c mfc2 a1,\$3
+[ 0-9a-f]+: 00a4 4d3c mfc2 a1,\$4
+[ 0-9a-f]+: 00a5 4d3c mfc2 a1,\$5
+[ 0-9a-f]+: 00a6 4d3c mfc2 a1,\$6
+[ 0-9a-f]+: 00a7 4d3c mfc2 a1,\$7
+[ 0-9a-f]+: 00a8 4d3c mfc2 a1,\$8
+[ 0-9a-f]+: 00a9 4d3c mfc2 a1,\$9
+[ 0-9a-f]+: 00aa 4d3c mfc2 a1,\$10
+[ 0-9a-f]+: 00ab 4d3c mfc2 a1,\$11
+[ 0-9a-f]+: 00ac 4d3c mfc2 a1,\$12
+[ 0-9a-f]+: 00ad 4d3c mfc2 a1,\$13
+[ 0-9a-f]+: 00ae 4d3c mfc2 a1,\$14
+[ 0-9a-f]+: 00af 4d3c mfc2 a1,\$15
+[ 0-9a-f]+: 00b0 4d3c mfc2 a1,\$16
+[ 0-9a-f]+: 00b1 4d3c mfc2 a1,\$17
+[ 0-9a-f]+: 00b2 4d3c mfc2 a1,\$18
+[ 0-9a-f]+: 00b3 4d3c mfc2 a1,\$19
+[ 0-9a-f]+: 00b4 4d3c mfc2 a1,\$20
+[ 0-9a-f]+: 00b5 4d3c mfc2 a1,\$21
+[ 0-9a-f]+: 00b6 4d3c mfc2 a1,\$22
+[ 0-9a-f]+: 00b7 4d3c mfc2 a1,\$23
+[ 0-9a-f]+: 00b8 4d3c mfc2 a1,\$24
+[ 0-9a-f]+: 00b9 4d3c mfc2 a1,\$25
+[ 0-9a-f]+: 00ba 4d3c mfc2 a1,\$26
+[ 0-9a-f]+: 00bb 4d3c mfc2 a1,\$27
+[ 0-9a-f]+: 00bc 4d3c mfc2 a1,\$28
+[ 0-9a-f]+: 00bd 4d3c mfc2 a1,\$29
+[ 0-9a-f]+: 00be 4d3c mfc2 a1,\$30
+[ 0-9a-f]+: 00bf 4d3c mfc2 a1,\$31
+[ 0-9a-f]+: 00a0 8d3c mfhc2 a1,\$0
+[ 0-9a-f]+: 00a1 8d3c mfhc2 a1,\$1
+[ 0-9a-f]+: 00a2 8d3c mfhc2 a1,\$2
+[ 0-9a-f]+: 00a3 8d3c mfhc2 a1,\$3
+[ 0-9a-f]+: 00a4 8d3c mfhc2 a1,\$4
+[ 0-9a-f]+: 00a5 8d3c mfhc2 a1,\$5
+[ 0-9a-f]+: 00a6 8d3c mfhc2 a1,\$6
+[ 0-9a-f]+: 00a7 8d3c mfhc2 a1,\$7
+[ 0-9a-f]+: 00a8 8d3c mfhc2 a1,\$8
+[ 0-9a-f]+: 00a9 8d3c mfhc2 a1,\$9
+[ 0-9a-f]+: 00aa 8d3c mfhc2 a1,\$10
+[ 0-9a-f]+: 00ab 8d3c mfhc2 a1,\$11
+[ 0-9a-f]+: 00ac 8d3c mfhc2 a1,\$12
+[ 0-9a-f]+: 00ad 8d3c mfhc2 a1,\$13
+[ 0-9a-f]+: 00ae 8d3c mfhc2 a1,\$14
+[ 0-9a-f]+: 00af 8d3c mfhc2 a1,\$15
+[ 0-9a-f]+: 00b0 8d3c mfhc2 a1,\$16
+[ 0-9a-f]+: 00b1 8d3c mfhc2 a1,\$17
+[ 0-9a-f]+: 00b2 8d3c mfhc2 a1,\$18
+[ 0-9a-f]+: 00b3 8d3c mfhc2 a1,\$19
+[ 0-9a-f]+: 00b4 8d3c mfhc2 a1,\$20
+[ 0-9a-f]+: 00b5 8d3c mfhc2 a1,\$21
+[ 0-9a-f]+: 00b6 8d3c mfhc2 a1,\$22
+[ 0-9a-f]+: 00b7 8d3c mfhc2 a1,\$23
+[ 0-9a-f]+: 00b8 8d3c mfhc2 a1,\$24
+[ 0-9a-f]+: 00b9 8d3c mfhc2 a1,\$25
+[ 0-9a-f]+: 00ba 8d3c mfhc2 a1,\$26
+[ 0-9a-f]+: 00bb 8d3c mfhc2 a1,\$27
+[ 0-9a-f]+: 00bc 8d3c mfhc2 a1,\$28
+[ 0-9a-f]+: 00bd 8d3c mfhc2 a1,\$29
+[ 0-9a-f]+: 00be 8d3c mfhc2 a1,\$30
+[ 0-9a-f]+: 00bf 8d3c mfhc2 a1,\$31
+[ 0-9a-f]+: 00a0 5d3c mtc2 a1,\$0
+[ 0-9a-f]+: 00a1 5d3c mtc2 a1,\$1
+[ 0-9a-f]+: 00a2 5d3c mtc2 a1,\$2
+[ 0-9a-f]+: 00a3 5d3c mtc2 a1,\$3
+[ 0-9a-f]+: 00a4 5d3c mtc2 a1,\$4
+[ 0-9a-f]+: 00a5 5d3c mtc2 a1,\$5
+[ 0-9a-f]+: 00a6 5d3c mtc2 a1,\$6
+[ 0-9a-f]+: 00a7 5d3c mtc2 a1,\$7
+[ 0-9a-f]+: 00a8 5d3c mtc2 a1,\$8
+[ 0-9a-f]+: 00a9 5d3c mtc2 a1,\$9
+[ 0-9a-f]+: 00aa 5d3c mtc2 a1,\$10
+[ 0-9a-f]+: 00ab 5d3c mtc2 a1,\$11
+[ 0-9a-f]+: 00ac 5d3c mtc2 a1,\$12
+[ 0-9a-f]+: 00ad 5d3c mtc2 a1,\$13
+[ 0-9a-f]+: 00ae 5d3c mtc2 a1,\$14
+[ 0-9a-f]+: 00af 5d3c mtc2 a1,\$15
+[ 0-9a-f]+: 00b0 5d3c mtc2 a1,\$16
+[ 0-9a-f]+: 00b1 5d3c mtc2 a1,\$17
+[ 0-9a-f]+: 00b2 5d3c mtc2 a1,\$18
+[ 0-9a-f]+: 00b3 5d3c mtc2 a1,\$19
+[ 0-9a-f]+: 00b4 5d3c mtc2 a1,\$20
+[ 0-9a-f]+: 00b5 5d3c mtc2 a1,\$21
+[ 0-9a-f]+: 00b6 5d3c mtc2 a1,\$22
+[ 0-9a-f]+: 00b7 5d3c mtc2 a1,\$23
+[ 0-9a-f]+: 00b8 5d3c mtc2 a1,\$24
+[ 0-9a-f]+: 00b9 5d3c mtc2 a1,\$25
+[ 0-9a-f]+: 00ba 5d3c mtc2 a1,\$26
+[ 0-9a-f]+: 00bb 5d3c mtc2 a1,\$27
+[ 0-9a-f]+: 00bc 5d3c mtc2 a1,\$28
+[ 0-9a-f]+: 00bd 5d3c mtc2 a1,\$29
+[ 0-9a-f]+: 00be 5d3c mtc2 a1,\$30
+[ 0-9a-f]+: 00bf 5d3c mtc2 a1,\$31
+[ 0-9a-f]+: 00a0 9d3c mthc2 a1,\$0
+[ 0-9a-f]+: 00a1 9d3c mthc2 a1,\$1
+[ 0-9a-f]+: 00a2 9d3c mthc2 a1,\$2
+[ 0-9a-f]+: 00a3 9d3c mthc2 a1,\$3
+[ 0-9a-f]+: 00a4 9d3c mthc2 a1,\$4
+[ 0-9a-f]+: 00a5 9d3c mthc2 a1,\$5
+[ 0-9a-f]+: 00a6 9d3c mthc2 a1,\$6
+[ 0-9a-f]+: 00a7 9d3c mthc2 a1,\$7
+[ 0-9a-f]+: 00a8 9d3c mthc2 a1,\$8
+[ 0-9a-f]+: 00a9 9d3c mthc2 a1,\$9
+[ 0-9a-f]+: 00aa 9d3c mthc2 a1,\$10
+[ 0-9a-f]+: 00ab 9d3c mthc2 a1,\$11
+[ 0-9a-f]+: 00ac 9d3c mthc2 a1,\$12
+[ 0-9a-f]+: 00ad 9d3c mthc2 a1,\$13
+[ 0-9a-f]+: 00ae 9d3c mthc2 a1,\$14
+[ 0-9a-f]+: 00af 9d3c mthc2 a1,\$15
+[ 0-9a-f]+: 00b0 9d3c mthc2 a1,\$16
+[ 0-9a-f]+: 00b1 9d3c mthc2 a1,\$17
+[ 0-9a-f]+: 00b2 9d3c mthc2 a1,\$18
+[ 0-9a-f]+: 00b3 9d3c mthc2 a1,\$19
+[ 0-9a-f]+: 00b4 9d3c mthc2 a1,\$20
+[ 0-9a-f]+: 00b5 9d3c mthc2 a1,\$21
+[ 0-9a-f]+: 00b6 9d3c mthc2 a1,\$22
+[ 0-9a-f]+: 00b7 9d3c mthc2 a1,\$23
+[ 0-9a-f]+: 00b8 9d3c mthc2 a1,\$24
+[ 0-9a-f]+: 00b9 9d3c mthc2 a1,\$25
+[ 0-9a-f]+: 00ba 9d3c mthc2 a1,\$26
+[ 0-9a-f]+: 00bb 9d3c mthc2 a1,\$27
+[ 0-9a-f]+: 00bc 9d3c mthc2 a1,\$28
+[ 0-9a-f]+: 00bd 9d3c mthc2 a1,\$29
+[ 0-9a-f]+: 00be 9d3c mthc2 a1,\$30
+[ 0-9a-f]+: 00bf 9d3c mthc2 a1,\$31
+[ 0-9a-f]+: 2060 a000 sdc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 a000 sdc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 a004 sdc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 a004 sdc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 a000 sdc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 a000 sdc2 \$3,0\(a0\)
+[ 0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a7ff sdc2 \$3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a001 sdc2 \$3,1\(at\)
+[ 0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 a7ff sdc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5800 ori at,at,0x5800
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 a678 sdc2 \$3,-392\(at\)
+[ 0-9a-f]+: 2060 8000 swc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 8000 swc2 \$3,0\(zero\)
+[ 0-9a-f]+: 2060 8004 swc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2060 8004 swc2 \$3,4\(zero\)
+[ 0-9a-f]+: 2064 8000 swc2 \$3,0\(a0\)
+[ 0-9a-f]+: 2064 8000 swc2 \$3,0\(a0\)
+[ 0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 87ff swc2 \$3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8001 swc2 \$3,1\(at\)
+[ 0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ 0-9a-f]+: 2064 87ff swc2 \$3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5800 ori at,at,0x5800
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 2061 8678 swc2 \$3,-392\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2041 1000 lwp v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ 0-9a-f]+: 3043 0000 addiu v0,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6042 3000 ll v0,0\(v0\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6041 b000 sc v0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 0000 lwc2 \$16,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 8000 swc2 \$16,0\(at\)
+[ 0-9a-f]+: 03ff db7c sdbbp 0x3ff
+[ 0-9a-f]+: 03ff 937c wait 0x3ff
+[ 0-9a-f]+: 03ff 8b7c syscall 0x3ff
+[ 0-9a-f]+: 03ff fffa cop2 0x7fffff
+
+[0-9a-f]+ <fp_test>:
+[ 0-9a-f]+: 5401 037b abs.s \$f0,\$f1
+[ 0-9a-f]+: 57df 037b abs.s \$f30,\$f31
+[ 0-9a-f]+: 5442 037b abs.s \$f2,\$f2
+[ 0-9a-f]+: 5442 037b abs.s \$f2,\$f2
+[ 0-9a-f]+: 5401 237b abs.d \$f0,\$f1
+[ 0-9a-f]+: 57df 237b abs.d \$f30,\$f31
+[ 0-9a-f]+: 5442 237b abs.d \$f2,\$f2
+[ 0-9a-f]+: 5442 237b abs.d \$f2,\$f2
+[ 0-9a-f]+: 5441 0030 add.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e830 add.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e830 add.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e830 add.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0130 add.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e930 add.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e930 add.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e930 add.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5401 533b ceil.l.d \$f0,\$f1
+[ 0-9a-f]+: 57df 533b ceil.l.d \$f30,\$f31
+[ 0-9a-f]+: 5442 533b ceil.l.d \$f2,\$f2
+[ 0-9a-f]+: 5401 133b ceil.l.s \$f0,\$f1
+[ 0-9a-f]+: 57df 133b ceil.l.s \$f30,\$f31
+[ 0-9a-f]+: 5442 133b ceil.l.s \$f2,\$f2
+[ 0-9a-f]+: 5401 5b3b ceil.w.d \$f0,\$f1
+[ 0-9a-f]+: 57df 5b3b ceil.w.d \$f30,\$f31
+[ 0-9a-f]+: 5442 5b3b ceil.w.d \$f2,\$f2
+[ 0-9a-f]+: 5401 1b3b ceil.w.s \$f0,\$f1
+[ 0-9a-f]+: 57df 1b3b ceil.w.s \$f30,\$f31
+[ 0-9a-f]+: 5442 1b3b ceil.w.s \$f2,\$f2
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
+[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
+[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
+[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
+[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
+[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
+[ 0-9a-f]+: 54a8 103b cfc1 a1,\$8
+[ 0-9a-f]+: 54a9 103b cfc1 a1,\$9
+[ 0-9a-f]+: 54aa 103b cfc1 a1,\$10
+[ 0-9a-f]+: 54ab 103b cfc1 a1,\$11
+[ 0-9a-f]+: 54ac 103b cfc1 a1,\$12
+[ 0-9a-f]+: 54ad 103b cfc1 a1,\$13
+[ 0-9a-f]+: 54ae 103b cfc1 a1,\$14
+[ 0-9a-f]+: 54af 103b cfc1 a1,\$15
+[ 0-9a-f]+: 54b0 103b cfc1 a1,\$16
+[ 0-9a-f]+: 54b1 103b cfc1 a1,\$17
+[ 0-9a-f]+: 54b2 103b cfc1 a1,\$18
+[ 0-9a-f]+: 54b3 103b cfc1 a1,\$19
+[ 0-9a-f]+: 54b4 103b cfc1 a1,\$20
+[ 0-9a-f]+: 54b5 103b cfc1 a1,\$21
+[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
+[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
+[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
+[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
+[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
+[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ 0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ 0-9a-f]+: 54a1 103b cfc1 a1,\$1
+[ 0-9a-f]+: 54a2 103b cfc1 a1,\$2
+[ 0-9a-f]+: 54a3 103b cfc1 a1,\$3
+[ 0-9a-f]+: 54a4 103b cfc1 a1,\$4
+[ 0-9a-f]+: 54a5 103b cfc1 a1,\$5
+[ 0-9a-f]+: 54a6 103b cfc1 a1,\$6
+[ 0-9a-f]+: 54a7 103b cfc1 a1,\$7
+[ 0-9a-f]+: 54a8 103b cfc1 a1,\$8
+[ 0-9a-f]+: 54a9 103b cfc1 a1,\$9
+[ 0-9a-f]+: 54aa 103b cfc1 a1,\$10
+[ 0-9a-f]+: 54ab 103b cfc1 a1,\$11
+[ 0-9a-f]+: 54ac 103b cfc1 a1,\$12
+[ 0-9a-f]+: 54ad 103b cfc1 a1,\$13
+[ 0-9a-f]+: 54ae 103b cfc1 a1,\$14
+[ 0-9a-f]+: 54af 103b cfc1 a1,\$15
+[ 0-9a-f]+: 54b0 103b cfc1 a1,\$16
+[ 0-9a-f]+: 54b1 103b cfc1 a1,\$17
+[ 0-9a-f]+: 54b2 103b cfc1 a1,\$18
+[ 0-9a-f]+: 54b3 103b cfc1 a1,\$19
+[ 0-9a-f]+: 54b4 103b cfc1 a1,\$20
+[ 0-9a-f]+: 54b5 103b cfc1 a1,\$21
+[ 0-9a-f]+: 54b6 103b cfc1 a1,\$22
+[ 0-9a-f]+: 54b7 103b cfc1 a1,\$23
+[ 0-9a-f]+: 54b8 103b cfc1 a1,\$24
+[ 0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ 0-9a-f]+: 54ba 103b cfc1 a1,\$26
+[ 0-9a-f]+: 54bb 103b cfc1 a1,\$27
+[ 0-9a-f]+: 54bc 103b cfc1 a1,\$28
+[ 0-9a-f]+: 54bd 103b cfc1 a1,\$29
+[ 0-9a-f]+: 54be 103b cfc1 a1,\$30
+[ 0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ 0-9a-f]+: 00a0 cd3c cfc2 a1,\$0
+[ 0-9a-f]+: 00a1 cd3c cfc2 a1,\$1
+[ 0-9a-f]+: 00a2 cd3c cfc2 a1,\$2
+[ 0-9a-f]+: 00a3 cd3c cfc2 a1,\$3
+[ 0-9a-f]+: 00a4 cd3c cfc2 a1,\$4
+[ 0-9a-f]+: 00a5 cd3c cfc2 a1,\$5
+[ 0-9a-f]+: 00a6 cd3c cfc2 a1,\$6
+[ 0-9a-f]+: 00a7 cd3c cfc2 a1,\$7
+[ 0-9a-f]+: 00a8 cd3c cfc2 a1,\$8
+[ 0-9a-f]+: 00a9 cd3c cfc2 a1,\$9
+[ 0-9a-f]+: 00aa cd3c cfc2 a1,\$10
+[ 0-9a-f]+: 00ab cd3c cfc2 a1,\$11
+[ 0-9a-f]+: 00ac cd3c cfc2 a1,\$12
+[ 0-9a-f]+: 00ad cd3c cfc2 a1,\$13
+[ 0-9a-f]+: 00ae cd3c cfc2 a1,\$14
+[ 0-9a-f]+: 00af cd3c cfc2 a1,\$15
+[ 0-9a-f]+: 00b0 cd3c cfc2 a1,\$16
+[ 0-9a-f]+: 00b1 cd3c cfc2 a1,\$17
+[ 0-9a-f]+: 00b2 cd3c cfc2 a1,\$18
+[ 0-9a-f]+: 00b3 cd3c cfc2 a1,\$19
+[ 0-9a-f]+: 00b4 cd3c cfc2 a1,\$20
+[ 0-9a-f]+: 00b5 cd3c cfc2 a1,\$21
+[ 0-9a-f]+: 00b6 cd3c cfc2 a1,\$22
+[ 0-9a-f]+: 00b7 cd3c cfc2 a1,\$23
+[ 0-9a-f]+: 00b8 cd3c cfc2 a1,\$24
+[ 0-9a-f]+: 00b9 cd3c cfc2 a1,\$25
+[ 0-9a-f]+: 00ba cd3c cfc2 a1,\$26
+[ 0-9a-f]+: 00bb cd3c cfc2 a1,\$27
+[ 0-9a-f]+: 00bc cd3c cfc2 a1,\$28
+[ 0-9a-f]+: 00bd cd3c cfc2 a1,\$29
+[ 0-9a-f]+: 00be cd3c cfc2 a1,\$30
+[ 0-9a-f]+: 00bf cd3c cfc2 a1,\$31
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
+[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
+[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
+[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
+[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
+[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
+[ 0-9a-f]+: 54a8 183b ctc1 a1,\$8
+[ 0-9a-f]+: 54a9 183b ctc1 a1,\$9
+[ 0-9a-f]+: 54aa 183b ctc1 a1,\$10
+[ 0-9a-f]+: 54ab 183b ctc1 a1,\$11
+[ 0-9a-f]+: 54ac 183b ctc1 a1,\$12
+[ 0-9a-f]+: 54ad 183b ctc1 a1,\$13
+[ 0-9a-f]+: 54ae 183b ctc1 a1,\$14
+[ 0-9a-f]+: 54af 183b ctc1 a1,\$15
+[ 0-9a-f]+: 54b0 183b ctc1 a1,\$16
+[ 0-9a-f]+: 54b1 183b ctc1 a1,\$17
+[ 0-9a-f]+: 54b2 183b ctc1 a1,\$18
+[ 0-9a-f]+: 54b3 183b ctc1 a1,\$19
+[ 0-9a-f]+: 54b4 183b ctc1 a1,\$20
+[ 0-9a-f]+: 54b5 183b ctc1 a1,\$21
+[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
+[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
+[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
+[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
+[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
+[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ 0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ 0-9a-f]+: 54a1 183b ctc1 a1,\$1
+[ 0-9a-f]+: 54a2 183b ctc1 a1,\$2
+[ 0-9a-f]+: 54a3 183b ctc1 a1,\$3
+[ 0-9a-f]+: 54a4 183b ctc1 a1,\$4
+[ 0-9a-f]+: 54a5 183b ctc1 a1,\$5
+[ 0-9a-f]+: 54a6 183b ctc1 a1,\$6
+[ 0-9a-f]+: 54a7 183b ctc1 a1,\$7
+[ 0-9a-f]+: 54a8 183b ctc1 a1,\$8
+[ 0-9a-f]+: 54a9 183b ctc1 a1,\$9
+[ 0-9a-f]+: 54aa 183b ctc1 a1,\$10
+[ 0-9a-f]+: 54ab 183b ctc1 a1,\$11
+[ 0-9a-f]+: 54ac 183b ctc1 a1,\$12
+[ 0-9a-f]+: 54ad 183b ctc1 a1,\$13
+[ 0-9a-f]+: 54ae 183b ctc1 a1,\$14
+[ 0-9a-f]+: 54af 183b ctc1 a1,\$15
+[ 0-9a-f]+: 54b0 183b ctc1 a1,\$16
+[ 0-9a-f]+: 54b1 183b ctc1 a1,\$17
+[ 0-9a-f]+: 54b2 183b ctc1 a1,\$18
+[ 0-9a-f]+: 54b3 183b ctc1 a1,\$19
+[ 0-9a-f]+: 54b4 183b ctc1 a1,\$20
+[ 0-9a-f]+: 54b5 183b ctc1 a1,\$21
+[ 0-9a-f]+: 54b6 183b ctc1 a1,\$22
+[ 0-9a-f]+: 54b7 183b ctc1 a1,\$23
+[ 0-9a-f]+: 54b8 183b ctc1 a1,\$24
+[ 0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ 0-9a-f]+: 54ba 183b ctc1 a1,\$26
+[ 0-9a-f]+: 54bb 183b ctc1 a1,\$27
+[ 0-9a-f]+: 54bc 183b ctc1 a1,\$28
+[ 0-9a-f]+: 54bd 183b ctc1 a1,\$29
+[ 0-9a-f]+: 54be 183b ctc1 a1,\$30
+[ 0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ 0-9a-f]+: 00a0 dd3c ctc2 a1,\$0
+[ 0-9a-f]+: 00a1 dd3c ctc2 a1,\$1
+[ 0-9a-f]+: 00a2 dd3c ctc2 a1,\$2
+[ 0-9a-f]+: 00a3 dd3c ctc2 a1,\$3
+[ 0-9a-f]+: 00a4 dd3c ctc2 a1,\$4
+[ 0-9a-f]+: 00a5 dd3c ctc2 a1,\$5
+[ 0-9a-f]+: 00a6 dd3c ctc2 a1,\$6
+[ 0-9a-f]+: 00a7 dd3c ctc2 a1,\$7
+[ 0-9a-f]+: 00a8 dd3c ctc2 a1,\$8
+[ 0-9a-f]+: 00a9 dd3c ctc2 a1,\$9
+[ 0-9a-f]+: 00aa dd3c ctc2 a1,\$10
+[ 0-9a-f]+: 00ab dd3c ctc2 a1,\$11
+[ 0-9a-f]+: 00ac dd3c ctc2 a1,\$12
+[ 0-9a-f]+: 00ad dd3c ctc2 a1,\$13
+[ 0-9a-f]+: 00ae dd3c ctc2 a1,\$14
+[ 0-9a-f]+: 00af dd3c ctc2 a1,\$15
+[ 0-9a-f]+: 00b0 dd3c ctc2 a1,\$16
+[ 0-9a-f]+: 00b1 dd3c ctc2 a1,\$17
+[ 0-9a-f]+: 00b2 dd3c ctc2 a1,\$18
+[ 0-9a-f]+: 00b3 dd3c ctc2 a1,\$19
+[ 0-9a-f]+: 00b4 dd3c ctc2 a1,\$20
+[ 0-9a-f]+: 00b5 dd3c ctc2 a1,\$21
+[ 0-9a-f]+: 00b6 dd3c ctc2 a1,\$22
+[ 0-9a-f]+: 00b7 dd3c ctc2 a1,\$23
+[ 0-9a-f]+: 00b8 dd3c ctc2 a1,\$24
+[ 0-9a-f]+: 00b9 dd3c ctc2 a1,\$25
+[ 0-9a-f]+: 00ba dd3c ctc2 a1,\$26
+[ 0-9a-f]+: 00bb dd3c ctc2 a1,\$27
+[ 0-9a-f]+: 00bc dd3c ctc2 a1,\$28
+[ 0-9a-f]+: 00bd dd3c ctc2 a1,\$29
+[ 0-9a-f]+: 00be dd3c ctc2 a1,\$30
+[ 0-9a-f]+: 00bf dd3c ctc2 a1,\$31
+[ 0-9a-f]+: 5401 537b cvt.d.l \$f0,\$f1
+[ 0-9a-f]+: 57df 537b cvt.d.l \$f30,\$f31
+[ 0-9a-f]+: 5442 537b cvt.d.l \$f2,\$f2
+[ 0-9a-f]+: 5401 137b cvt.d.s \$f0,\$f1
+[ 0-9a-f]+: 57df 137b cvt.d.s \$f30,\$f31
+[ 0-9a-f]+: 5442 137b cvt.d.s \$f2,\$f2
+[ 0-9a-f]+: 5401 337b cvt.d.w \$f0,\$f1
+[ 0-9a-f]+: 57df 337b cvt.d.w \$f30,\$f31
+[ 0-9a-f]+: 5442 337b cvt.d.w \$f2,\$f2
+[ 0-9a-f]+: 5401 013b cvt.l.s \$f0,\$f1
+[ 0-9a-f]+: 57df 013b cvt.l.s \$f30,\$f31
+[ 0-9a-f]+: 5442 013b cvt.l.s \$f2,\$f2
+[ 0-9a-f]+: 5401 413b cvt.l.d \$f0,\$f1
+[ 0-9a-f]+: 57df 413b cvt.l.d \$f30,\$f31
+[ 0-9a-f]+: 5442 413b cvt.l.d \$f2,\$f2
+[ 0-9a-f]+: 5401 5b7b cvt.s.l \$f0,\$f1
+[ 0-9a-f]+: 57df 5b7b cvt.s.l \$f30,\$f31
+[ 0-9a-f]+: 5442 5b7b cvt.s.l \$f2,\$f2
+[ 0-9a-f]+: 5401 1b7b cvt.s.d \$f0,\$f1
+[ 0-9a-f]+: 57df 1b7b cvt.s.d \$f30,\$f31
+[ 0-9a-f]+: 5442 1b7b cvt.s.d \$f2,\$f2
+[ 0-9a-f]+: 5401 3b7b cvt.s.w \$f0,\$f1
+[ 0-9a-f]+: 57df 3b7b cvt.s.w \$f30,\$f31
+[ 0-9a-f]+: 5442 3b7b cvt.s.w \$f2,\$f2
+[ 0-9a-f]+: 5401 213b cvt.s.pl \$f0,\$f1
+[ 0-9a-f]+: 57df 213b cvt.s.pl \$f30,\$f31
+[ 0-9a-f]+: 5442 213b cvt.s.pl \$f2,\$f2
+[ 0-9a-f]+: 5401 293b cvt.s.pu \$f0,\$f1
+[ 0-9a-f]+: 57df 293b cvt.s.pu \$f30,\$f31
+[ 0-9a-f]+: 5442 293b cvt.s.pu \$f2,\$f2
+[ 0-9a-f]+: 5401 093b cvt.w.s \$f0,\$f1
+[ 0-9a-f]+: 57df 093b cvt.w.s \$f30,\$f31
+[ 0-9a-f]+: 5442 093b cvt.w.s \$f2,\$f2
+[ 0-9a-f]+: 5401 493b cvt.w.d \$f0,\$f1
+[ 0-9a-f]+: 57df 493b cvt.w.d \$f30,\$f31
+[ 0-9a-f]+: 5442 493b cvt.w.d \$f2,\$f2
+[ 0-9a-f]+: 5441 01f0 div.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e9f0 div.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e9f0 div.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e9f0 div.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 00f0 div.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e8f0 div.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e8f0 div.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e8f0 div.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5401 433b floor.l.d \$f0,\$f1
+[ 0-9a-f]+: 57df 433b floor.l.d \$f30,\$f31
+[ 0-9a-f]+: 5442 433b floor.l.d \$f2,\$f2
+[ 0-9a-f]+: 5401 033b floor.l.s \$f0,\$f1
+[ 0-9a-f]+: 57df 033b floor.l.s \$f30,\$f31
+[ 0-9a-f]+: 5442 033b floor.l.s \$f2,\$f2
+[ 0-9a-f]+: 5401 4b3b floor.w.d \$f0,\$f1
+[ 0-9a-f]+: 57df 4b3b floor.w.d \$f30,\$f31
+[ 0-9a-f]+: 5442 4b3b floor.w.d \$f2,\$f2
+[ 0-9a-f]+: 5401 0b3b floor.w.s \$f0,\$f1
+[ 0-9a-f]+: 57df 0b3b floor.w.s \$f30,\$f31
+[ 0-9a-f]+: 5442 0b3b floor.w.s \$f2,\$f2
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 ffff ldc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0001 ldc1 \$f3,1\(at\)
+[ 0-9a-f]+: bc64 8001 ldc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 ffff ldc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 5678 ldc1 \$f3,22136\(at\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 ffff ldc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0001 ldc1 \$f3,1\(at\)
+[ 0-9a-f]+: bc64 8001 ldc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ 0-9a-f]+: bc64 ffff ldc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: bc61 5678 ldc1 \$f3,22136\(at\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ 0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 54a0 203b mfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 203b mfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 203b mfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 203b mfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 203b mfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 203b mfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 203b mfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 203b mfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 203b mfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 203b mfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 203b mfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 203b mfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 203b mfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 203b mfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 203b mfc1 a1,\$f14
+[ 0-9a-f]+: 54af 203b mfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 203b mfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 203b mfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 203b mfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 203b mfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 203b mfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 203b mfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 203b mfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 203b mfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 203b mfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 203b mfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 203b mfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 203b mfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 203b mfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 203b mfc1 a1,\$f29
+[ 0-9a-f]+: 54be 203b mfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 203b mfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 203b mfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 203b mfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 203b mfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 203b mfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 203b mfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 203b mfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 203b mfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 203b mfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 203b mfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 203b mfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 203b mfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 203b mfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 203b mfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 203b mfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 203b mfc1 a1,\$f14
+[ 0-9a-f]+: 54af 203b mfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 203b mfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 203b mfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 203b mfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 203b mfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 203b mfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 203b mfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 203b mfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 203b mfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 203b mfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 203b mfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 203b mfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 203b mfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 203b mfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 203b mfc1 a1,\$f29
+[ 0-9a-f]+: 54be 203b mfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 203b mfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 303b mfhc1 a1,\$f0
+[ 0-9a-f]+: 54a1 303b mfhc1 a1,\$f1
+[ 0-9a-f]+: 54a2 303b mfhc1 a1,\$f2
+[ 0-9a-f]+: 54a3 303b mfhc1 a1,\$f3
+[ 0-9a-f]+: 54a4 303b mfhc1 a1,\$f4
+[ 0-9a-f]+: 54a5 303b mfhc1 a1,\$f5
+[ 0-9a-f]+: 54a6 303b mfhc1 a1,\$f6
+[ 0-9a-f]+: 54a7 303b mfhc1 a1,\$f7
+[ 0-9a-f]+: 54a8 303b mfhc1 a1,\$f8
+[ 0-9a-f]+: 54a9 303b mfhc1 a1,\$f9
+[ 0-9a-f]+: 54aa 303b mfhc1 a1,\$f10
+[ 0-9a-f]+: 54ab 303b mfhc1 a1,\$f11
+[ 0-9a-f]+: 54ac 303b mfhc1 a1,\$f12
+[ 0-9a-f]+: 54ad 303b mfhc1 a1,\$f13
+[ 0-9a-f]+: 54ae 303b mfhc1 a1,\$f14
+[ 0-9a-f]+: 54af 303b mfhc1 a1,\$f15
+[ 0-9a-f]+: 54b0 303b mfhc1 a1,\$f16
+[ 0-9a-f]+: 54b1 303b mfhc1 a1,\$f17
+[ 0-9a-f]+: 54b2 303b mfhc1 a1,\$f18
+[ 0-9a-f]+: 54b3 303b mfhc1 a1,\$f19
+[ 0-9a-f]+: 54b4 303b mfhc1 a1,\$f20
+[ 0-9a-f]+: 54b5 303b mfhc1 a1,\$f21
+[ 0-9a-f]+: 54b6 303b mfhc1 a1,\$f22
+[ 0-9a-f]+: 54b7 303b mfhc1 a1,\$f23
+[ 0-9a-f]+: 54b8 303b mfhc1 a1,\$f24
+[ 0-9a-f]+: 54b9 303b mfhc1 a1,\$f25
+[ 0-9a-f]+: 54ba 303b mfhc1 a1,\$f26
+[ 0-9a-f]+: 54bb 303b mfhc1 a1,\$f27
+[ 0-9a-f]+: 54bc 303b mfhc1 a1,\$f28
+[ 0-9a-f]+: 54bd 303b mfhc1 a1,\$f29
+[ 0-9a-f]+: 54be 303b mfhc1 a1,\$f30
+[ 0-9a-f]+: 54bf 303b mfhc1 a1,\$f31
+[ 0-9a-f]+: 54a0 303b mfhc1 a1,\$f0
+[ 0-9a-f]+: 54a1 303b mfhc1 a1,\$f1
+[ 0-9a-f]+: 54a2 303b mfhc1 a1,\$f2
+[ 0-9a-f]+: 54a3 303b mfhc1 a1,\$f3
+[ 0-9a-f]+: 54a4 303b mfhc1 a1,\$f4
+[ 0-9a-f]+: 54a5 303b mfhc1 a1,\$f5
+[ 0-9a-f]+: 54a6 303b mfhc1 a1,\$f6
+[ 0-9a-f]+: 54a7 303b mfhc1 a1,\$f7
+[ 0-9a-f]+: 54a8 303b mfhc1 a1,\$f8
+[ 0-9a-f]+: 54a9 303b mfhc1 a1,\$f9
+[ 0-9a-f]+: 54aa 303b mfhc1 a1,\$f10
+[ 0-9a-f]+: 54ab 303b mfhc1 a1,\$f11
+[ 0-9a-f]+: 54ac 303b mfhc1 a1,\$f12
+[ 0-9a-f]+: 54ad 303b mfhc1 a1,\$f13
+[ 0-9a-f]+: 54ae 303b mfhc1 a1,\$f14
+[ 0-9a-f]+: 54af 303b mfhc1 a1,\$f15
+[ 0-9a-f]+: 54b0 303b mfhc1 a1,\$f16
+[ 0-9a-f]+: 54b1 303b mfhc1 a1,\$f17
+[ 0-9a-f]+: 54b2 303b mfhc1 a1,\$f18
+[ 0-9a-f]+: 54b3 303b mfhc1 a1,\$f19
+[ 0-9a-f]+: 54b4 303b mfhc1 a1,\$f20
+[ 0-9a-f]+: 54b5 303b mfhc1 a1,\$f21
+[ 0-9a-f]+: 54b6 303b mfhc1 a1,\$f22
+[ 0-9a-f]+: 54b7 303b mfhc1 a1,\$f23
+[ 0-9a-f]+: 54b8 303b mfhc1 a1,\$f24
+[ 0-9a-f]+: 54b9 303b mfhc1 a1,\$f25
+[ 0-9a-f]+: 54ba 303b mfhc1 a1,\$f26
+[ 0-9a-f]+: 54bb 303b mfhc1 a1,\$f27
+[ 0-9a-f]+: 54bc 303b mfhc1 a1,\$f28
+[ 0-9a-f]+: 54bd 303b mfhc1 a1,\$f29
+[ 0-9a-f]+: 54be 303b mfhc1 a1,\$f30
+[ 0-9a-f]+: 54bf 303b mfhc1 a1,\$f31
+[ 0-9a-f]+: 5401 207b mov.d \$f0,\$f1
+[ 0-9a-f]+: 57df 207b mov.d \$f30,\$f31
+[ 0-9a-f]+: 5401 007b mov.s \$f0,\$f1
+[ 0-9a-f]+: 57df 007b mov.s \$f30,\$f31
+[ 0-9a-f]+: 54a0 283b mtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 283b mtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 283b mtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 283b mtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 283b mtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 283b mtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 283b mtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 283b mtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 283b mtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 283b mtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 283b mtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 283b mtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 283b mtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 283b mtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 283b mtc1 a1,\$f14
+[ 0-9a-f]+: 54af 283b mtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 283b mtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 283b mtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 283b mtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 283b mtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 283b mtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 283b mtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 283b mtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 283b mtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 283b mtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 283b mtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 283b mtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 283b mtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 283b mtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 283b mtc1 a1,\$f29
+[ 0-9a-f]+: 54be 283b mtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 283b mtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 283b mtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 283b mtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 283b mtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 283b mtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 283b mtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 283b mtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 283b mtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 283b mtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 283b mtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 283b mtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 283b mtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 283b mtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 283b mtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 283b mtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 283b mtc1 a1,\$f14
+[ 0-9a-f]+: 54af 283b mtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 283b mtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 283b mtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 283b mtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 283b mtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 283b mtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 283b mtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 283b mtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 283b mtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 283b mtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 283b mtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 283b mtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 283b mtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 283b mtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 283b mtc1 a1,\$f29
+[ 0-9a-f]+: 54be 283b mtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 283b mtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 383b mthc1 a1,\$f0
+[ 0-9a-f]+: 54a1 383b mthc1 a1,\$f1
+[ 0-9a-f]+: 54a2 383b mthc1 a1,\$f2
+[ 0-9a-f]+: 54a3 383b mthc1 a1,\$f3
+[ 0-9a-f]+: 54a4 383b mthc1 a1,\$f4
+[ 0-9a-f]+: 54a5 383b mthc1 a1,\$f5
+[ 0-9a-f]+: 54a6 383b mthc1 a1,\$f6
+[ 0-9a-f]+: 54a7 383b mthc1 a1,\$f7
+[ 0-9a-f]+: 54a8 383b mthc1 a1,\$f8
+[ 0-9a-f]+: 54a9 383b mthc1 a1,\$f9
+[ 0-9a-f]+: 54aa 383b mthc1 a1,\$f10
+[ 0-9a-f]+: 54ab 383b mthc1 a1,\$f11
+[ 0-9a-f]+: 54ac 383b mthc1 a1,\$f12
+[ 0-9a-f]+: 54ad 383b mthc1 a1,\$f13
+[ 0-9a-f]+: 54ae 383b mthc1 a1,\$f14
+[ 0-9a-f]+: 54af 383b mthc1 a1,\$f15
+[ 0-9a-f]+: 54b0 383b mthc1 a1,\$f16
+[ 0-9a-f]+: 54b1 383b mthc1 a1,\$f17
+[ 0-9a-f]+: 54b2 383b mthc1 a1,\$f18
+[ 0-9a-f]+: 54b3 383b mthc1 a1,\$f19
+[ 0-9a-f]+: 54b4 383b mthc1 a1,\$f20
+[ 0-9a-f]+: 54b5 383b mthc1 a1,\$f21
+[ 0-9a-f]+: 54b6 383b mthc1 a1,\$f22
+[ 0-9a-f]+: 54b7 383b mthc1 a1,\$f23
+[ 0-9a-f]+: 54b8 383b mthc1 a1,\$f24
+[ 0-9a-f]+: 54b9 383b mthc1 a1,\$f25
+[ 0-9a-f]+: 54ba 383b mthc1 a1,\$f26
+[ 0-9a-f]+: 54bb 383b mthc1 a1,\$f27
+[ 0-9a-f]+: 54bc 383b mthc1 a1,\$f28
+[ 0-9a-f]+: 54bd 383b mthc1 a1,\$f29
+[ 0-9a-f]+: 54be 383b mthc1 a1,\$f30
+[ 0-9a-f]+: 54bf 383b mthc1 a1,\$f31
+[ 0-9a-f]+: 54a0 383b mthc1 a1,\$f0
+[ 0-9a-f]+: 54a1 383b mthc1 a1,\$f1
+[ 0-9a-f]+: 54a2 383b mthc1 a1,\$f2
+[ 0-9a-f]+: 54a3 383b mthc1 a1,\$f3
+[ 0-9a-f]+: 54a4 383b mthc1 a1,\$f4
+[ 0-9a-f]+: 54a5 383b mthc1 a1,\$f5
+[ 0-9a-f]+: 54a6 383b mthc1 a1,\$f6
+[ 0-9a-f]+: 54a7 383b mthc1 a1,\$f7
+[ 0-9a-f]+: 54a8 383b mthc1 a1,\$f8
+[ 0-9a-f]+: 54a9 383b mthc1 a1,\$f9
+[ 0-9a-f]+: 54aa 383b mthc1 a1,\$f10
+[ 0-9a-f]+: 54ab 383b mthc1 a1,\$f11
+[ 0-9a-f]+: 54ac 383b mthc1 a1,\$f12
+[ 0-9a-f]+: 54ad 383b mthc1 a1,\$f13
+[ 0-9a-f]+: 54ae 383b mthc1 a1,\$f14
+[ 0-9a-f]+: 54af 383b mthc1 a1,\$f15
+[ 0-9a-f]+: 54b0 383b mthc1 a1,\$f16
+[ 0-9a-f]+: 54b1 383b mthc1 a1,\$f17
+[ 0-9a-f]+: 54b2 383b mthc1 a1,\$f18
+[ 0-9a-f]+: 54b3 383b mthc1 a1,\$f19
+[ 0-9a-f]+: 54b4 383b mthc1 a1,\$f20
+[ 0-9a-f]+: 54b5 383b mthc1 a1,\$f21
+[ 0-9a-f]+: 54b6 383b mthc1 a1,\$f22
+[ 0-9a-f]+: 54b7 383b mthc1 a1,\$f23
+[ 0-9a-f]+: 54b8 383b mthc1 a1,\$f24
+[ 0-9a-f]+: 54b9 383b mthc1 a1,\$f25
+[ 0-9a-f]+: 54ba 383b mthc1 a1,\$f26
+[ 0-9a-f]+: 54bb 383b mthc1 a1,\$f27
+[ 0-9a-f]+: 54bc 383b mthc1 a1,\$f28
+[ 0-9a-f]+: 54bd 383b mthc1 a1,\$f29
+[ 0-9a-f]+: 54be 383b mthc1 a1,\$f30
+[ 0-9a-f]+: 54bf 383b mthc1 a1,\$f31
+[ 0-9a-f]+: 5441 00b0 mul.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e8b0 mul.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e8b0 mul.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e8b0 mul.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 01b0 mul.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e9b0 mul.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e9b0 mul.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e9b0 mul.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5401 0b7b neg.s \$f0,\$f1
+[ 0-9a-f]+: 57df 0b7b neg.s \$f30,\$f31
+[ 0-9a-f]+: 5442 0b7b neg.s \$f2,\$f2
+[ 0-9a-f]+: 5442 0b7b neg.s \$f2,\$f2
+[ 0-9a-f]+: 5401 2b7b neg.d \$f0,\$f1
+[ 0-9a-f]+: 57df 2b7b neg.d \$f30,\$f31
+[ 0-9a-f]+: 5442 2b7b neg.d \$f2,\$f2
+[ 0-9a-f]+: 5442 2b7b neg.d \$f2,\$f2
+[ 0-9a-f]+: 5401 123b recip.s \$f0,\$f1
+[ 0-9a-f]+: 57df 123b recip.s \$f30,\$f31
+[ 0-9a-f]+: 5442 123b recip.s \$f2,\$f2
+[ 0-9a-f]+: 5401 523b recip.d \$f0,\$f1
+[ 0-9a-f]+: 57df 523b recip.d \$f30,\$f31
+[ 0-9a-f]+: 5442 523b recip.d \$f2,\$f2
+[ 0-9a-f]+: 5401 333b round.l.s \$f0,\$f1
+[ 0-9a-f]+: 57df 333b round.l.s \$f30,\$f31
+[ 0-9a-f]+: 5442 333b round.l.s \$f2,\$f2
+[ 0-9a-f]+: 5401 733b round.l.d \$f0,\$f1
+[ 0-9a-f]+: 57df 733b round.l.d \$f30,\$f31
+[ 0-9a-f]+: 5442 733b round.l.d \$f2,\$f2
+[ 0-9a-f]+: 5401 3b3b round.w.s \$f0,\$f1
+[ 0-9a-f]+: 57df 3b3b round.w.s \$f30,\$f31
+[ 0-9a-f]+: 5442 3b3b round.w.s \$f2,\$f2
+[ 0-9a-f]+: 5401 7b3b round.w.d \$f0,\$f1
+[ 0-9a-f]+: 57df 7b3b round.w.d \$f30,\$f31
+[ 0-9a-f]+: 5442 7b3b round.w.d \$f2,\$f2
+[ 0-9a-f]+: 5401 023b rsqrt.s \$f0,\$f1
+[ 0-9a-f]+: 57df 023b rsqrt.s \$f30,\$f31
+[ 0-9a-f]+: 5442 023b rsqrt.s \$f2,\$f2
+[ 0-9a-f]+: 5401 423b rsqrt.d \$f0,\$f1
+[ 0-9a-f]+: 57df 423b rsqrt.d \$f30,\$f31
+[ 0-9a-f]+: 5442 423b rsqrt.d \$f2,\$f2
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 ffff sdc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0001 sdc1 \$f3,1\(at\)
+[ 0-9a-f]+: b864 8001 sdc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 ffff sdc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 5678 sdc1 \$f3,22136\(at\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 ffff sdc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0001 sdc1 \$f3,1\(at\)
+[ 0-9a-f]+: b864 8001 sdc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ 0-9a-f]+: b864 ffff sdc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: b861 5678 sdc1 \$f3,22136\(at\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ 0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 5401 0a3b sqrt.s \$f0,\$f1
+[ 0-9a-f]+: 57df 0a3b sqrt.s \$f30,\$f31
+[ 0-9a-f]+: 5442 0a3b sqrt.s \$f2,\$f2
+[ 0-9a-f]+: 5401 4a3b sqrt.d \$f0,\$f1
+[ 0-9a-f]+: 57df 4a3b sqrt.d \$f30,\$f31
+[ 0-9a-f]+: 5442 4a3b sqrt.d \$f2,\$f2
+[ 0-9a-f]+: 5441 0070 sub.s \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e870 sub.s \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e870 sub.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e870 sub.s \$f29,\$f29,\$f30
+[ 0-9a-f]+: 5441 0170 sub.d \$f0,\$f1,\$f2
+[ 0-9a-f]+: 57fe e970 sub.d \$f29,\$f30,\$f31
+[ 0-9a-f]+: 57dd e970 sub.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 57dd e970 sub.d \$f29,\$f29,\$f30
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ 0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ 0-9a-f]+: 1020 ffff lui at,0xffff
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ 0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ 0-9a-f]+: 1020 f000 lui at,0xf000
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ 0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 0081 0950 addu at,at,a0
+[ 0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ 0-9a-f]+: 5401 233b trunc.l.s \$f0,\$f1
+[ 0-9a-f]+: 57df 233b trunc.l.s \$f30,\$f31
+[ 0-9a-f]+: 5442 233b trunc.l.s \$f2,\$f2
+[ 0-9a-f]+: 5401 633b trunc.l.d \$f0,\$f1
+[ 0-9a-f]+: 57df 633b trunc.l.d \$f30,\$f31
+[ 0-9a-f]+: 5442 633b trunc.l.d \$f2,\$f2
+[ 0-9a-f]+: 5401 2b3b trunc.w.s \$f0,\$f1
+[ 0-9a-f]+: 57df 2b3b trunc.w.s \$f30,\$f31
+[ 0-9a-f]+: 5442 2b3b trunc.w.s \$f2,\$f2
+[ 0-9a-f]+: 5401 6b3b trunc.w.d \$f0,\$f1
+[ 0-9a-f]+: 57df 6b3b trunc.w.d \$f30,\$f31
+[ 0-9a-f]+: 5442 6b3b trunc.w.d \$f2,\$f2
+
+[0-9a-f]+ <test_mips64>:
+[ 0-9a-f]+: 0003 1290 move v0,v1
+[ 0-9a-f]+: f463 fffe bgezc v1,3804 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_4
+[ 0-9a-f]+: 5860 1190 dneg v0,v1
+
+[0-9a-f]+ <\.L\^\_4>:
+[ 0-9a-f]+: f442 fffe bgezc v0,380c <\.L\^\_4>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_5
+[ 0-9a-f]+: 5840 1190 dneg v0,v0
+
+[0-9a-f]+ <\.L\^\_5>:
+[ 0-9a-f]+: f442 fffe bgezc v0,3814 <\.L\^\_5>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_6
+[ 0-9a-f]+: 5840 1190 dneg v0,v0
+
+[0-9a-f]+ <\.L\^\_6>:
+[ 0-9a-f]+: 5883 1110 dadd v0,v1,a0
+[ 0-9a-f]+: 5bfe e910 dadd sp,s8,ra
+[ 0-9a-f]+: 5862 1110 dadd v0,v0,v1
+[ 0-9a-f]+: 5862 1110 dadd v0,v0,v1
+[ 0-9a-f]+: 5c43 0000 daddiu v0,v1,0
+[ 0-9a-f]+: 5c43 8000 daddiu v0,v1,-32768
+[ 0-9a-f]+: 5c43 7fff daddiu v0,v1,32767
+[ 0-9a-f]+: 5c42 7fff daddiu v0,v0,32767
+[ 0-9a-f]+: 5c42 7fff daddiu v0,v0,32767
+[ 0-9a-f]+: 5883 1150 daddu v0,v1,a0
+[ 0-9a-f]+: 5bfe e950 daddu sp,s8,ra
+[ 0-9a-f]+: 5862 1150 daddu v0,v0,v1
+[ 0-9a-f]+: 5862 1150 daddu v0,v0,v1
+[ 0-9a-f]+: 5803 1150 move v0,v1
+[ 0-9a-f]+: 5c43 0000 daddiu v0,v1,0
+[ 0-9a-f]+: 5c43 0001 daddiu v0,v1,1
+[ 0-9a-f]+: 5c43 7fff daddiu v0,v1,32767
+[ 0-9a-f]+: 5c43 8000 daddiu v0,v1,-32768
+[ 0-9a-f]+: 5020 ffff li at,0xffff
+[ 0-9a-f]+: 5823 1150 daddu v0,v1,at
+[ 0-9a-f]+: 5843 4b3c dclo v0,v1
+[ 0-9a-f]+: 5862 4b3c dclo v1,v0
+[ 0-9a-f]+: 5843 5b3c dclz v0,v1
+[ 0-9a-f]+: 5862 5b3c dclz v1,v0
+[ 0-9a-f]+: 5862 0118 ddiv zero,v0,v1
+[ 0-9a-f]+: 5bfe 0118 ddiv zero,s8,ra
+[ 0-9a-f]+: 5803 1118 ddiv v0,v1,zero
+[ 0-9a-f]+: 5883 1118 ddiv v0,v1,a0
+[ 0-9a-f]+: 5862 0198 ddivu zero,v0,v1
+[ 0-9a-f]+: 5bfe 0198 ddivu zero,s8,ra
+[ 0-9a-f]+: 5803 1198 ddivu v0,v1,zero
+[ 0-9a-f]+: 5883 1198 ddivu v0,v1,a0
+[ 0-9a-f]+: 5843 07ec dext v0,v1,0x1f,0x1
+[ 0-9a-f]+: 5843 f82c dext v0,v1,0x0,0x20
+[ 0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa
+[ 0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa
+[ 0-9a-f]+: 5843 ffcc dins v0,v1,0x1f,0x1
+[ 0-9a-f]+: 5843 f80c dins v0,v1,0x0,0x20
+[ 0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21
+[ 0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa
+[ 0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa
+[ 0-9a-f]+: 1040 0000 lui v0,0x0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 1040 0000 lui v0,0x0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_HI16 test
+[ 0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 3040 8000 li v0,-32768
+[ 0-9a-f]+: 3040 7fff li v0,32767
+[ 0-9a-f]+: 5040 ffff li v0,0xffff
+[ 0-9a-f]+: 1040 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5678 ori v0,v0,0x5678
+[ 0-9a-f]+: 5840 00fc dmfc0 v0,c0_index
+[ 0-9a-f]+: 5841 00fc dmfc0 v0,c0_random
+[ 0-9a-f]+: 5842 00fc dmfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5843 00fc dmfc0 v0,c0_entrylo1
+[ 0-9a-f]+: 5844 00fc dmfc0 v0,c0_context
+[ 0-9a-f]+: 5845 00fc dmfc0 v0,c0_pagemask
+[ 0-9a-f]+: 5846 00fc dmfc0 v0,c0_wired
+[ 0-9a-f]+: 5847 00fc dmfc0 v0,c0_hwrena
+[ 0-9a-f]+: 5848 00fc dmfc0 v0,c0_badvaddr
+[ 0-9a-f]+: 5849 00fc dmfc0 v0,c0_count
+[ 0-9a-f]+: 584a 00fc dmfc0 v0,c0_entryhi
+[ 0-9a-f]+: 584b 00fc dmfc0 v0,c0_compare
+[ 0-9a-f]+: 584c 00fc dmfc0 v0,c0_status
+[ 0-9a-f]+: 584d 00fc dmfc0 v0,c0_cause
+[ 0-9a-f]+: 584e 00fc dmfc0 v0,c0_epc
+[ 0-9a-f]+: 584f 00fc dmfc0 v0,c0_prid
+[ 0-9a-f]+: 5850 00fc dmfc0 v0,c0_config
+[ 0-9a-f]+: 5851 00fc dmfc0 v0,c0_lladdr
+[ 0-9a-f]+: 5852 00fc dmfc0 v0,c0_watchlo
+[ 0-9a-f]+: 5853 00fc dmfc0 v0,c0_watchhi
+[ 0-9a-f]+: 5854 00fc dmfc0 v0,c0_xcontext
+[ 0-9a-f]+: 5855 00fc dmfc0 v0,\$21
+[ 0-9a-f]+: 5856 00fc dmfc0 v0,\$22
+[ 0-9a-f]+: 5857 00fc dmfc0 v0,c0_debug
+[ 0-9a-f]+: 5858 00fc dmfc0 v0,c0_depc
+[ 0-9a-f]+: 5859 00fc dmfc0 v0,c0_perfcnt
+[ 0-9a-f]+: 585a 00fc dmfc0 v0,c0_errctl
+[ 0-9a-f]+: 585b 00fc dmfc0 v0,c0_cacheerr
+[ 0-9a-f]+: 585c 00fc dmfc0 v0,c0_taglo
+[ 0-9a-f]+: 585d 00fc dmfc0 v0,c0_taghi
+[ 0-9a-f]+: 585e 00fc dmfc0 v0,c0_errorepc
+[ 0-9a-f]+: 585f 00fc dmfc0 v0,c0_desave
+[ 0-9a-f]+: 5840 00fc dmfc0 v0,c0_index
+[ 0-9a-f]+: 5840 08fc dmfc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 5840 10fc dmfc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 5840 18fc dmfc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 5840 20fc dmfc0 v0,\$0,4
+[ 0-9a-f]+: 5840 28fc dmfc0 v0,\$0,5
+[ 0-9a-f]+: 5840 30fc dmfc0 v0,\$0,6
+[ 0-9a-f]+: 5840 38fc dmfc0 v0,\$0,7
+[ 0-9a-f]+: 5841 00fc dmfc0 v0,c0_random
+[ 0-9a-f]+: 5841 08fc dmfc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 5841 10fc dmfc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 5841 18fc dmfc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 5841 20fc dmfc0 v0,c0_yqmask
+[ 0-9a-f]+: 5841 28fc dmfc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 5841 30fc dmfc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 5841 38fc dmfc0 v0,\$1,7
+[ 0-9a-f]+: 5842 00fc dmfc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5842 08fc dmfc0 v0,c0_tcstatus
+[ 0-9a-f]+: 5842 10fc dmfc0 v0,c0_tcbind
+[ 0-9a-f]+: 5842 18fc dmfc0 v0,c0_tcrestart
+[ 0-9a-f]+: 5842 20fc dmfc0 v0,c0_tchalt
+[ 0-9a-f]+: 5842 28fc dmfc0 v0,c0_tccontext
+[ 0-9a-f]+: 5842 30fc dmfc0 v0,c0_tcschedule
+[ 0-9a-f]+: 5842 38fc dmfc0 v0,c0_tcschefback
+[ 0-9a-f]+: 5840 02fc dmtc0 v0,c0_index
+[ 0-9a-f]+: 5841 02fc dmtc0 v0,c0_random
+[ 0-9a-f]+: 5842 02fc dmtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5843 02fc dmtc0 v0,c0_entrylo1
+[ 0-9a-f]+: 5844 02fc dmtc0 v0,c0_context
+[ 0-9a-f]+: 5845 02fc dmtc0 v0,c0_pagemask
+[ 0-9a-f]+: 5846 02fc dmtc0 v0,c0_wired
+[ 0-9a-f]+: 5847 02fc dmtc0 v0,c0_hwrena
+[ 0-9a-f]+: 5848 02fc dmtc0 v0,c0_badvaddr
+[ 0-9a-f]+: 5849 02fc dmtc0 v0,c0_count
+[ 0-9a-f]+: 584a 02fc dmtc0 v0,c0_entryhi
+[ 0-9a-f]+: 584b 02fc dmtc0 v0,c0_compare
+[ 0-9a-f]+: 584c 02fc dmtc0 v0,c0_status
+[ 0-9a-f]+: 584d 02fc dmtc0 v0,c0_cause
+[ 0-9a-f]+: 584e 02fc dmtc0 v0,c0_epc
+[ 0-9a-f]+: 584f 02fc dmtc0 v0,c0_prid
+[ 0-9a-f]+: 5850 02fc dmtc0 v0,c0_config
+[ 0-9a-f]+: 5851 02fc dmtc0 v0,c0_lladdr
+[ 0-9a-f]+: 5852 02fc dmtc0 v0,c0_watchlo
+[ 0-9a-f]+: 5853 02fc dmtc0 v0,c0_watchhi
+[ 0-9a-f]+: 5854 02fc dmtc0 v0,c0_xcontext
+[ 0-9a-f]+: 5855 02fc dmtc0 v0,\$21
+[ 0-9a-f]+: 5856 02fc dmtc0 v0,\$22
+[ 0-9a-f]+: 5857 02fc dmtc0 v0,c0_debug
+[ 0-9a-f]+: 5858 02fc dmtc0 v0,c0_depc
+[ 0-9a-f]+: 5859 02fc dmtc0 v0,c0_perfcnt
+[ 0-9a-f]+: 585a 02fc dmtc0 v0,c0_errctl
+[ 0-9a-f]+: 585b 02fc dmtc0 v0,c0_cacheerr
+[ 0-9a-f]+: 585c 02fc dmtc0 v0,c0_taglo
+[ 0-9a-f]+: 585d 02fc dmtc0 v0,c0_taghi
+[ 0-9a-f]+: 585e 02fc dmtc0 v0,c0_errorepc
+[ 0-9a-f]+: 585f 02fc dmtc0 v0,c0_desave
+[ 0-9a-f]+: 5840 02fc dmtc0 v0,c0_index
+[ 0-9a-f]+: 5840 0afc dmtc0 v0,c0_mvpcontrol
+[ 0-9a-f]+: 5840 12fc dmtc0 v0,c0_mvpconf0
+[ 0-9a-f]+: 5840 1afc dmtc0 v0,c0_mvpconf1
+[ 0-9a-f]+: 5840 22fc dmtc0 v0,\$0,4
+[ 0-9a-f]+: 5840 2afc dmtc0 v0,\$0,5
+[ 0-9a-f]+: 5840 32fc dmtc0 v0,\$0,6
+[ 0-9a-f]+: 5840 3afc dmtc0 v0,\$0,7
+[ 0-9a-f]+: 5841 02fc dmtc0 v0,c0_random
+[ 0-9a-f]+: 5841 0afc dmtc0 v0,c0_vpecontrol
+[ 0-9a-f]+: 5841 12fc dmtc0 v0,c0_vpeconf0
+[ 0-9a-f]+: 5841 1afc dmtc0 v0,c0_vpeconf1
+[ 0-9a-f]+: 5841 22fc dmtc0 v0,c0_yqmask
+[ 0-9a-f]+: 5841 2afc dmtc0 v0,c0_vpeschedule
+[ 0-9a-f]+: 5841 32fc dmtc0 v0,c0_vpeschefback
+[ 0-9a-f]+: 5841 3afc dmtc0 v0,\$1,7
+[ 0-9a-f]+: 5842 02fc dmtc0 v0,c0_entrylo0
+[ 0-9a-f]+: 5842 0afc dmtc0 v0,c0_tcstatus
+[ 0-9a-f]+: 5842 12fc dmtc0 v0,c0_tcbind
+[ 0-9a-f]+: 5842 1afc dmtc0 v0,c0_tcrestart
+[ 0-9a-f]+: 5842 22fc dmtc0 v0,c0_tchalt
+[ 0-9a-f]+: 5842 2afc dmtc0 v0,c0_tccontext
+[ 0-9a-f]+: 5842 32fc dmtc0 v0,c0_tcschedule
+[ 0-9a-f]+: 5842 3afc dmtc0 v0,c0_tcschefback
+[ 0-9a-f]+: 54a0 243b dmfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 243b dmfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 243b dmfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 243b dmfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 243b dmfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 243b dmfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 243b dmfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 243b dmfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 243b dmfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 243b dmfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 243b dmfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 243b dmfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 243b dmfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 243b dmfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 243b dmfc1 a1,\$f14
+[ 0-9a-f]+: 54af 243b dmfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 243b dmfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 243b dmfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 243b dmfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 243b dmfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 243b dmfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 243b dmfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 243b dmfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 243b dmfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 243b dmfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 243b dmfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 243b dmfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 243b dmfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 243b dmfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
+[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 243b dmfc1 a1,\$f0
+[ 0-9a-f]+: 54a1 243b dmfc1 a1,\$f1
+[ 0-9a-f]+: 54a2 243b dmfc1 a1,\$f2
+[ 0-9a-f]+: 54a3 243b dmfc1 a1,\$f3
+[ 0-9a-f]+: 54a4 243b dmfc1 a1,\$f4
+[ 0-9a-f]+: 54a5 243b dmfc1 a1,\$f5
+[ 0-9a-f]+: 54a6 243b dmfc1 a1,\$f6
+[ 0-9a-f]+: 54a7 243b dmfc1 a1,\$f7
+[ 0-9a-f]+: 54a8 243b dmfc1 a1,\$f8
+[ 0-9a-f]+: 54a9 243b dmfc1 a1,\$f9
+[ 0-9a-f]+: 54aa 243b dmfc1 a1,\$f10
+[ 0-9a-f]+: 54ab 243b dmfc1 a1,\$f11
+[ 0-9a-f]+: 54ac 243b dmfc1 a1,\$f12
+[ 0-9a-f]+: 54ad 243b dmfc1 a1,\$f13
+[ 0-9a-f]+: 54ae 243b dmfc1 a1,\$f14
+[ 0-9a-f]+: 54af 243b dmfc1 a1,\$f15
+[ 0-9a-f]+: 54b0 243b dmfc1 a1,\$f16
+[ 0-9a-f]+: 54b1 243b dmfc1 a1,\$f17
+[ 0-9a-f]+: 54b2 243b dmfc1 a1,\$f18
+[ 0-9a-f]+: 54b3 243b dmfc1 a1,\$f19
+[ 0-9a-f]+: 54b4 243b dmfc1 a1,\$f20
+[ 0-9a-f]+: 54b5 243b dmfc1 a1,\$f21
+[ 0-9a-f]+: 54b6 243b dmfc1 a1,\$f22
+[ 0-9a-f]+: 54b7 243b dmfc1 a1,\$f23
+[ 0-9a-f]+: 54b8 243b dmfc1 a1,\$f24
+[ 0-9a-f]+: 54b9 243b dmfc1 a1,\$f25
+[ 0-9a-f]+: 54ba 243b dmfc1 a1,\$f26
+[ 0-9a-f]+: 54bb 243b dmfc1 a1,\$f27
+[ 0-9a-f]+: 54bc 243b dmfc1 a1,\$f28
+[ 0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
+[ 0-9a-f]+: 54be 243b dmfc1 a1,\$f30
+[ 0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
+[ 0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ 0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ 0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ 0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ 0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ 0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ 0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ 0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ 0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ 0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ 0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ 0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ 0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ 0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ 0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ 0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ 0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ 0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ 0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ 0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ 0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ 0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ 0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ 0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ 0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ 0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ 0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ 0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ 0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ 0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ 0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ 0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
+[ 0-9a-f]+: 0040 6d3c dmfc2 v0,\$0
+[ 0-9a-f]+: 0041 6d3c dmfc2 v0,\$1
+[ 0-9a-f]+: 0042 6d3c dmfc2 v0,\$2
+[ 0-9a-f]+: 0043 6d3c dmfc2 v0,\$3
+[ 0-9a-f]+: 0044 6d3c dmfc2 v0,\$4
+[ 0-9a-f]+: 0045 6d3c dmfc2 v0,\$5
+[ 0-9a-f]+: 0046 6d3c dmfc2 v0,\$6
+[ 0-9a-f]+: 0047 6d3c dmfc2 v0,\$7
+[ 0-9a-f]+: 0048 6d3c dmfc2 v0,\$8
+[ 0-9a-f]+: 0049 6d3c dmfc2 v0,\$9
+[ 0-9a-f]+: 004a 6d3c dmfc2 v0,\$10
+[ 0-9a-f]+: 004b 6d3c dmfc2 v0,\$11
+[ 0-9a-f]+: 004c 6d3c dmfc2 v0,\$12
+[ 0-9a-f]+: 004d 6d3c dmfc2 v0,\$13
+[ 0-9a-f]+: 004e 6d3c dmfc2 v0,\$14
+[ 0-9a-f]+: 004f 6d3c dmfc2 v0,\$15
+[ 0-9a-f]+: 0050 6d3c dmfc2 v0,\$16
+[ 0-9a-f]+: 0051 6d3c dmfc2 v0,\$17
+[ 0-9a-f]+: 0052 6d3c dmfc2 v0,\$18
+[ 0-9a-f]+: 0053 6d3c dmfc2 v0,\$19
+[ 0-9a-f]+: 0054 6d3c dmfc2 v0,\$20
+[ 0-9a-f]+: 0055 6d3c dmfc2 v0,\$21
+[ 0-9a-f]+: 0056 6d3c dmfc2 v0,\$22
+[ 0-9a-f]+: 0057 6d3c dmfc2 v0,\$23
+[ 0-9a-f]+: 0058 6d3c dmfc2 v0,\$24
+[ 0-9a-f]+: 0059 6d3c dmfc2 v0,\$25
+[ 0-9a-f]+: 005a 6d3c dmfc2 v0,\$26
+[ 0-9a-f]+: 005b 6d3c dmfc2 v0,\$27
+[ 0-9a-f]+: 005c 6d3c dmfc2 v0,\$28
+[ 0-9a-f]+: 005d 6d3c dmfc2 v0,\$29
+[ 0-9a-f]+: 005e 6d3c dmfc2 v0,\$30
+[ 0-9a-f]+: 005f 6d3c dmfc2 v0,\$31
+[ 0-9a-f]+: 0040 7d3c dmtc2 v0,\$0
+[ 0-9a-f]+: 0041 7d3c dmtc2 v0,\$1
+[ 0-9a-f]+: 0042 7d3c dmtc2 v0,\$2
+[ 0-9a-f]+: 0043 7d3c dmtc2 v0,\$3
+[ 0-9a-f]+: 0044 7d3c dmtc2 v0,\$4
+[ 0-9a-f]+: 0045 7d3c dmtc2 v0,\$5
+[ 0-9a-f]+: 0046 7d3c dmtc2 v0,\$6
+[ 0-9a-f]+: 0047 7d3c dmtc2 v0,\$7
+[ 0-9a-f]+: 0048 7d3c dmtc2 v0,\$8
+[ 0-9a-f]+: 0049 7d3c dmtc2 v0,\$9
+[ 0-9a-f]+: 004a 7d3c dmtc2 v0,\$10
+[ 0-9a-f]+: 004b 7d3c dmtc2 v0,\$11
+[ 0-9a-f]+: 004c 7d3c dmtc2 v0,\$12
+[ 0-9a-f]+: 004d 7d3c dmtc2 v0,\$13
+[ 0-9a-f]+: 004e 7d3c dmtc2 v0,\$14
+[ 0-9a-f]+: 004f 7d3c dmtc2 v0,\$15
+[ 0-9a-f]+: 0050 7d3c dmtc2 v0,\$16
+[ 0-9a-f]+: 0051 7d3c dmtc2 v0,\$17
+[ 0-9a-f]+: 0052 7d3c dmtc2 v0,\$18
+[ 0-9a-f]+: 0053 7d3c dmtc2 v0,\$19
+[ 0-9a-f]+: 0054 7d3c dmtc2 v0,\$20
+[ 0-9a-f]+: 0055 7d3c dmtc2 v0,\$21
+[ 0-9a-f]+: 0056 7d3c dmtc2 v0,\$22
+[ 0-9a-f]+: 0057 7d3c dmtc2 v0,\$23
+[ 0-9a-f]+: 0058 7d3c dmtc2 v0,\$24
+[ 0-9a-f]+: 0059 7d3c dmtc2 v0,\$25
+[ 0-9a-f]+: 005a 7d3c dmtc2 v0,\$26
+[ 0-9a-f]+: 005b 7d3c dmtc2 v0,\$27
+[ 0-9a-f]+: 005c 7d3c dmtc2 v0,\$28
+[ 0-9a-f]+: 005d 7d3c dmtc2 v0,\$29
+[ 0-9a-f]+: 005e 7d3c dmtc2 v0,\$30
+[ 0-9a-f]+: 005f 7d3c dmtc2 v0,\$31
+[ 0-9a-f]+: 5883 1018 dmul v0,v1,a0
+[ 0-9a-f]+: 5880 11d0 dnegu v0,a0
+[ 0-9a-f]+: 5862 10d0 drorv v0,v1,v0
+[ 0-9a-f]+: 5880 09d0 dnegu at,a0
+[ 0-9a-f]+: 5841 10d0 drorv v0,v0,at
+[ 0-9a-f]+: 5843 e0c8 dror32 v0,v1,0x1c
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c0 dror v0,v1,0x4
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5880 11d0 dnegu v0,a0
+[ 0-9a-f]+: 5862 10d0 drorv v0,v1,v0
+[ 0-9a-f]+: 5880 09d0 dnegu at,a0
+[ 0-9a-f]+: 5841 10d0 drorv v0,v0,at
+[ 0-9a-f]+: 5843 e0c8 dror32 v0,v1,0x1c
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c0 dror v0,v1,0x4
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ 0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ 0-9a-f]+: 5843 7b3c dsbh v0,v1
+[ 0-9a-f]+: 5842 7b3c dsbh v0,v0
+[ 0-9a-f]+: 5842 7b3c dsbh v0,v0
+[ 0-9a-f]+: 5843 fb3c dshd v0,v1
+[ 0-9a-f]+: 5842 fb3c dshd v0,v0
+[ 0-9a-f]+: 5842 fb3c dshd v0,v0
+[ 0-9a-f]+: 5864 1010 dsllv v0,v1,a0
+[ 0-9a-f]+: 5843 f808 dsll32 v0,v1,0x1f
+[ 0-9a-f]+: 5864 1010 dsllv v0,v1,a0
+[ 0-9a-f]+: 5843 f808 dsll32 v0,v1,0x1f
+[ 0-9a-f]+: 5843 f800 dsll v0,v1,0x1f
+[ 0-9a-f]+: 5864 1090 dsrav v0,v1,a0
+[ 0-9a-f]+: 5843 2088 dsra32 v0,v1,0x4
+[ 0-9a-f]+: 5864 1090 dsrav v0,v1,a0
+[ 0-9a-f]+: 5843 2088 dsra32 v0,v1,0x4
+[ 0-9a-f]+: 5843 2080 dsra v0,v1,0x4
+[ 0-9a-f]+: 5864 1050 dsrlv v0,v1,a0
+[ 0-9a-f]+: 5843 f848 dsrl32 v0,v1,0x1f
+[ 0-9a-f]+: 5864 1050 dsrlv v0,v1,a0
+[ 0-9a-f]+: 5843 2048 dsrl32 v0,v1,0x4
+[ 0-9a-f]+: 5843 2040 dsrl v0,v1,0x4
+[ 0-9a-f]+: 5883 1190 dsub v0,v1,a0
+[ 0-9a-f]+: 5bfe e990 dsub sp,s8,ra
+[ 0-9a-f]+: 5862 1190 dsub v0,v0,v1
+[ 0-9a-f]+: 5862 1190 dsub v0,v0,v1
+[ 0-9a-f]+: 5883 11d0 dsubu v0,v1,a0
+[ 0-9a-f]+: 5bfe e9d0 dsubu sp,s8,ra
+[ 0-9a-f]+: 5862 11d0 dsubu v0,v0,v1
+[ 0-9a-f]+: 5862 11d0 dsubu v0,v0,v1
+[ 0-9a-f]+: 5c43 edcc daddiu v0,v1,-4660
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ 0-9a-f]+: 5823 11d0 dsubu v0,v1,at
+[ 0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ 0-9a-f]+: dc40 0004 ld v0,4\(zero\)
+[ 0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ 0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ 0-9a-f]+: dc40 0004 ld v0,4\(zero\)
+[ 0-9a-f]+: dc43 0004 ld v0,4\(v1\)
+[ 0-9a-f]+: dc43 8000 ld v0,-32768\(v1\)
+[ 0-9a-f]+: dc43 7fff ld v0,32767\(v1\)
+[ 0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ 0-9a-f]+: 6040 7004 lld v0,4\(zero\)
+[ 0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ 0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ 0-9a-f]+: 6040 7004 lld v0,4\(zero\)
+[ 0-9a-f]+: 6043 7004 lld v0,4\(v1\)
+[ 0-9a-f]+: 6043 7100 lld v0,-256\(v1\)
+[ 0-9a-f]+: 6043 70ff lld v0,255\(v1\)
+[ 0-9a-f]+: 3043 8000 addiu v0,v1,-32768
+[ 0-9a-f]+: 6042 7000 lld v0,0\(v0\)
+[ 0-9a-f]+: 1040 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5600 ori v0,v0,0x5600
+[ 0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ 0-9a-f]+: 6042 7078 lld v0,120\(v0\)
+[ 0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ 0-9a-f]+: 6040 e004 lwu v0,4\(zero\)
+[ 0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ 0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ 0-9a-f]+: 6040 e004 lwu v0,4\(zero\)
+[ 0-9a-f]+: 6043 e004 lwu v0,4\(v1\)
+[ 0-9a-f]+: 6043 ee00 lwu v0,-512\(v1\)
+[ 0-9a-f]+: 6043 e1ff lwu v0,511\(v1\)
+[ 0-9a-f]+: 3043 8000 addiu v0,v1,-32768
+[ 0-9a-f]+: 6042 e000 lwu v0,0\(v0\)
+[ 0-9a-f]+: 1040 1234 lui v0,0x1234
+[ 0-9a-f]+: 5042 5000 ori v0,v0,0x5000
+[ 0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ 0-9a-f]+: 6042 e678 lwu v0,1656\(v0\)
+[ 0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ 0-9a-f]+: 6040 f004 scd v0,4\(zero\)
+[ 0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ 0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ 0-9a-f]+: 6040 f004 scd v0,4\(zero\)
+[ 0-9a-f]+: 6043 f004 scd v0,4\(v1\)
+[ 0-9a-f]+: 6043 f100 scd v0,-256\(v1\)
+[ 0-9a-f]+: 6043 f0ff scd v0,255\(v1\)
+[ 0-9a-f]+: 3023 8000 addiu at,v1,-32768
+[ 0-9a-f]+: 6041 f000 scd v0,0\(at\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5600 ori at,at,0x5600
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 6041 f078 scd v0,120\(at\)
+[ 0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ 0-9a-f]+: d840 0004 sd v0,4\(zero\)
+[ 0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ 0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ 0-9a-f]+: d840 0004 sd v0,4\(zero\)
+[ 0-9a-f]+: d843 0004 sd v0,4\(v1\)
+[ 0-9a-f]+: d843 8000 sd v0,-32768\(v1\)
+[ 0-9a-f]+: d843 7fff sd v0,32767\(v1\)
+[ 0-9a-f]+: 2020 7000 ldm s0,0\(zero\)
+[ 0-9a-f]+: 2020 7004 ldm s0,4\(zero\)
+[ 0-9a-f]+: 2025 7000 ldm s0,0\(a1\)
+[ 0-9a-f]+: 2025 77ff ldm s0,2047\(a1\)
+[ 0-9a-f]+: 2045 77ff ldm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 77ff ldm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 77ff ldm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 77ff ldm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 77ff ldm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 77ff ldm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 77ff ldm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 77ff ldm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 77ff ldm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 7000 ldm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 7000 ldm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 7000 ldm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 7000 ldm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 7000 ldm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 7000 ldm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 7000 ldm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 7000 ldm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 7000 ldm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 2020 7000 ldm s0,0\(zero\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ 0-9a-f]+: 303d 8000 addiu at,sp,-32768
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 303d 7fff addiu at,sp,32767
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 203d 7000 ldm s0,0\(sp\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 7678 ldm s0,1656\(at\)
+[ 0-9a-f]+: 2040 4000 ldp v0,0\(zero\)
+[ 0-9a-f]+: 2040 4004 ldp v0,4\(zero\)
+[ 0-9a-f]+: 205d 4000 ldp v0,0\(sp\)
+[ 0-9a-f]+: 205d 4000 ldp v0,0\(sp\)
+[ 0-9a-f]+: 2043 4800 ldp v0,-2048\(v1\)
+[ 0-9a-f]+: 2043 47ff ldp v0,2047\(v1\)
+[ 0-9a-f]+: 3023 8000 addiu at,v1,-32768
+[ 0-9a-f]+: 2041 4000 ldp v0,0\(at\)
+[ 0-9a-f]+: 3023 7fff addiu at,v1,32767
+[ 0-9a-f]+: 2041 4000 ldp v0,0\(at\)
+[ 0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 4fff ldp v0,-1\(at\)
+[ 0-9a-f]+: 3060 8000 li v1,-32768
+[ 0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
+[ 0-9a-f]+: 3060 7fff li v1,32767
+[ 0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
+[ 0-9a-f]+: 1060 0001 lui v1,0x1
+[ 0-9a-f]+: 2043 4fff ldp v0,-1\(v1\)
+[ 0-9a-f]+: 1060 1234 lui v1,0x1234
+[ 0-9a-f]+: 5063 5000 ori v1,v1,0x5000
+[ 0-9a-f]+: 2043 4678 ldp v0,1656\(v1\)
+[ 0-9a-f]+: 2020 f000 sdm s0,0\(zero\)
+[ 0-9a-f]+: 2020 f004 sdm s0,4\(zero\)
+[ 0-9a-f]+: 2025 f000 sdm s0,0\(a1\)
+[ 0-9a-f]+: 2025 f7ff sdm s0,2047\(a1\)
+[ 0-9a-f]+: 2045 f7ff sdm s0-s1,2047\(a1\)
+[ 0-9a-f]+: 2065 f7ff sdm s0-s2,2047\(a1\)
+[ 0-9a-f]+: 2085 f7ff sdm s0-s3,2047\(a1\)
+[ 0-9a-f]+: 20a5 f7ff sdm s0-s4,2047\(a1\)
+[ 0-9a-f]+: 20c5 f7ff sdm s0-s5,2047\(a1\)
+[ 0-9a-f]+: 20e5 f7ff sdm s0-s6,2047\(a1\)
+[ 0-9a-f]+: 2105 f7ff sdm s0-s7,2047\(a1\)
+[ 0-9a-f]+: 2125 f7ff sdm s0-s7,s8,2047\(a1\)
+[ 0-9a-f]+: 2205 f7ff sdm ra,2047\(a1\)
+[ 0-9a-f]+: 2225 f000 sdm s0,ra,0\(a1\)
+[ 0-9a-f]+: 2245 f000 sdm s0-s1,ra,0\(a1\)
+[ 0-9a-f]+: 2265 f000 sdm s0-s2,ra,0\(a1\)
+[ 0-9a-f]+: 2285 f000 sdm s0-s3,ra,0\(a1\)
+[ 0-9a-f]+: 22a5 f000 sdm s0-s4,ra,0\(a1\)
+[ 0-9a-f]+: 22c5 f000 sdm s0-s5,ra,0\(a1\)
+[ 0-9a-f]+: 22e5 f000 sdm s0-s6,ra,0\(a1\)
+[ 0-9a-f]+: 2305 f000 sdm s0-s7,ra,0\(a1\)
+[ 0-9a-f]+: 2325 f000 sdm s0-s7,s8,ra,0\(a1\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 2020 f000 sdm s0,0\(zero\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ 0-9a-f]+: 303d 8000 addiu at,sp,-32768
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 303d 7fff addiu at,sp,32767
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 203d f000 sdm s0,0\(sp\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 03a1 0950 addu at,at,sp
+[ 0-9a-f]+: 2021 f678 sdm s0,1656\(at\)
+[ 0-9a-f]+: 2040 c000 sdp v0,0\(zero\)
+[ 0-9a-f]+: 2040 c004 sdp v0,4\(zero\)
+[ 0-9a-f]+: 205d c000 sdp v0,0\(sp\)
+[ 0-9a-f]+: 205d c000 sdp v0,0\(sp\)
+[ 0-9a-f]+: 2043 c800 sdp v0,-2048\(v1\)
+[ 0-9a-f]+: 2043 c7ff sdp v0,2047\(v1\)
+[ 0-9a-f]+: 3023 8000 addiu at,v1,-32768
+[ 0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ 0-9a-f]+: 3023 7fff addiu at,v1,32767
+[ 0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ 0-9a-f]+: 2043 c000 sdp v0,0\(v1\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 0061 0950 addu at,at,v1
+[ 0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ 0-9a-f]+: 3020 8000 li at,-32768
+[ 0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ 0-9a-f]+: 3020 7fff li at,32767
+[ 0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ 0-9a-f]+: 1020 0001 lui at,0x1
+[ 0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ 0-9a-f]+: 1020 1234 lui at,0x1234
+[ 0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ 0-9a-f]+: 2041 c678 sdp v0,1656\(at\)
+[ 0-9a-f]+: 3203 0000 addiu s0,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6210 7000 lld s0,0\(s0\)
+[ 0-9a-f]+: 3203 0000 addiu s0,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6210 e000 lwu s0,0\(s0\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 6201 f000 scd s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ 0-9a-f]+: 3223 0000 addiu s1,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2211 4000 ldp s0,0\(s1\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 c000 sdp s0,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 2000 ldc2 \$16,0\(at\)
+[ 0-9a-f]+: 3023 0000 addiu at,v1,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_LO16 test
+[ 0-9a-f]+: 2201 a000 sdc2 \$16,0\(at\)
+
+[0-9a-f]+ <test_delay_slot>:
+[ 0-9a-f]+: b3fe 0000 sltiu ra,s8,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
+[ 0-9a-f]+: c063 fffe bgezalc v1,41bc <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: e063 fffe bltzalc v1,41c0 <.*>
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ 0-9a-f]+: b3fe 0000 sltiu ra,s8,0
+[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
+[ 0-9a-f]+: 03e2 0f3c jalrc v0
+[ 0-9a-f]+: 8002 0000 jrc v0
+[ 0-9a-f]+: 03e2 1f3c jalrc.hb v0
+[ 0-9a-f]+: 0002 1f3c jrc.hb v0
+
+[0-9a-f]+ <test_spec102>:
+[ 0-9a-f]+: fc5c ff00 lw v0,-256\(gp\)
+[ 0-9a-f]+: fc7c ff00 lw v1,-256\(gp\)
+[ 0-9a-f]+: fc9c ff00 lw a0,-256\(gp\)
+[ 0-9a-f]+: fcbc ff00 lw a1,-256\(gp\)
+[ 0-9a-f]+: fcdc ff00 lw a2,-256\(gp\)
+[ 0-9a-f]+: fcfc ff00 lw a3,-256\(gp\)
+[ 0-9a-f]+: fe1c ff00 lw s0,-256\(gp\)
+[ 0-9a-f]+: fe3c ff00 lw s1,-256\(gp\)
+[ 0-9a-f]+: fe3c ff04 lw s1,-252\(gp\)
+[ 0-9a-f]+: fe3c fffc lw s1,-4\(gp\)
+[ 0-9a-f]+: fe3c 0000 lw s1,0\(gp\)
+[ 0-9a-f]+: fe3c 0004 lw s1,4\(gp\)
+[ 0-9a-f]+: fe3c 00f8 lw s1,248\(gp\)
+[ 0-9a-f]+: fe3c 00fc lw s1,252\(gp\)
+[ 0-9a-f]+: fe3c 0100 lw s1,256\(gp\)
+[ 0-9a-f]+: fe3c fefc lw s1,-260\(gp\)
+[ 0-9a-f]+: fe3c 0001 lw s1,1\(gp\)
+[ 0-9a-f]+: fe3c 0002 lw s1,2\(gp\)
+[ 0-9a-f]+: fe3c 0003 lw s1,3\(gp\)
+[ 0-9a-f]+: fe3c ffff lw s1,-1\(gp\)
+[ 0-9a-f]+: fe3c fffe lw s1,-2\(gp\)
+[ 0-9a-f]+: fe3c fffd lw s1,-3\(gp\)
+[ 0-9a-f]+: fe3b 0000 lw s1,0\(k1\)
+[ 0-9a-f]+: 7840 0000 lapc v0,4234 <.*>
+[ 0-9a-f]+: 7860 0000 lapc v1,4238 <.*>
+[ 0-9a-f]+: 7880 0000 lapc a0,423c <.*>
+[ 0-9a-f]+: 78a0 0000 lapc a1,4240 <.*>
+[ 0-9a-f]+: 78c0 0000 lapc a2,4244 <.*>
+[ 0-9a-f]+: 78e0 0000 lapc a3,4248 <.*>
+[ 0-9a-f]+: 7a00 0000 lapc s0,424c <.*>
+[ 0-9a-f]+: 7a20 0000 lapc s1,4250 <.*>
+[ 0-9a-f]+: 7a23 ffff lapc s1,104250 <.*>
+[ 0-9a-f]+: 7a24 0000 lapc s1,fff04258 <.*>
+[ 0-9a-f]+: 7840 0000 lapc v0,425c <.*>
+[ 0-9a-f]+: 7860 0000 lapc v1,4260 <.*>
+[ 0-9a-f]+: 7880 0000 lapc a0,4264 <.*>
+[ 0-9a-f]+: 78a0 0000 lapc a1,4268 <.*>
+[ 0-9a-f]+: 78c0 0000 lapc a2,426c <.*>
+[ 0-9a-f]+: 78e0 0000 lapc a3,4270 <.*>
+[ 0-9a-f]+: 7a00 0000 lapc s0,4274 <.*>
+[ 0-9a-f]+: 7a20 0000 lapc s1,4278 <.*>
+[ 0-9a-f]+: 7a23 ffff lapc s1,104278 <.*>
+[ 0-9a-f]+: 7a24 0000 lapc s1,fff04280 <.*>
+
+[0-9a-f]+ <test_spec107>:
+[ 0-9a-f]+: 0000 2a90 move a1,zero
+[ 0-9a-f]+: 0000 3290 move a2,zero
+[ 0-9a-f]+: 0000 2a90 move a1,zero
+[ 0-9a-f]+: 0000 3a90 move a3,zero
+[ 0-9a-f]+: 0000 3290 move a2,zero
+[ 0-9a-f]+: 0000 3a90 move a3,zero
+[ 0-9a-f]+: 0000 2290 move a0,zero
+[ 0-9a-f]+: 0000 aa90 move s5,zero
+[ 0-9a-f]+: 0000 2290 move a0,zero
+[ 0-9a-f]+: 0000 b290 move s6,zero
+[ 0-9a-f]+: 0000 2290 move a0,zero
+[ 0-9a-f]+: 0000 2a90 move a1,zero
+[ 0-9a-f]+: 0000 2290 move a0,zero
+[ 0-9a-f]+: 0000 3290 move a2,zero
+[ 0-9a-f]+: 0000 2290 move a0,zero
+[ 0-9a-f]+: 0000 3a90 move a3,zero
+[ 0-9a-f]+: 0011 2290 move a0,s1
+[ 0-9a-f]+: 0000 3a90 move a3,zero
+[ 0-9a-f]+: 0002 2290 move a0,v0
+[ 0-9a-f]+: 0000 3a90 move a3,zero
+[ 0-9a-f]+: 0003 2290 move a0,v1
+[ 0-9a-f]+: 0000 3a90 move a3,zero
+[ 0-9a-f]+: 0010 2290 move a0,s0
+[ 0-9a-f]+: 0000 3a90 move a3,zero
+[ 0-9a-f]+: 0012 2290 move a0,s2
+[ 0-9a-f]+: 0000 3a90 move a3,zero
+[ 0-9a-f]+: 0013 2290 move a0,s3
+[ 0-9a-f]+: 0000 3a90 move a3,zero
+[ 0-9a-f]+: 0014 2290 move a0,s4
+[ 0-9a-f]+: 0000 3a90 move a3,zero
+[ 0-9a-f]+: 0014 2290 move a0,s4
+[ 0-9a-f]+: 0011 3a90 move a3,s1
+[ 0-9a-f]+: 0014 2290 move a0,s4
+[ 0-9a-f]+: 0002 3a90 move a3,v0
+[ 0-9a-f]+: 0014 2290 move a0,s4
+[ 0-9a-f]+: 0003 3a90 move a3,v1
+[ 0-9a-f]+: 0014 2290 move a0,s4
+[ 0-9a-f]+: 0010 3a90 move a3,s0
+[ 0-9a-f]+: 0014 2290 move a0,s4
+[ 0-9a-f]+: 0012 3a90 move a3,s2
+[ 0-9a-f]+: 0014 2290 move a0,s4
+[ 0-9a-f]+: 0013 3a90 move a3,s3
+[ 0-9a-f]+: 0014 2290 move a0,s4
+[ 0-9a-f]+: 0014 3a90 move a3,s4
+[ 0-9a-f]+: 0000 0000 nop
+#pass
diff --git a/gas/testsuite/gas/mips/micromipsr6@micromips.d b/gas/testsuite/gas/mips/micromipsr6@micromips.d
new file mode 100644
index 00000000000..140d72af665
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@micromips.d
@@ -0,0 +1,4495 @@
+#objdump: -dr --show-raw-insn
+#name: microMIPS for MIPS32r6
+#as: -32 -mfp64 -EB
+#source: micromips.s
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+
+[ 0-9a-f]+ <test>:
+ [0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+ [0-9a-f]+: 6000 20ff pref 0x0,255\(zero\)
+ [0-9a-f]+: 6000 2100 pref 0x0,-256\(zero\)
+ [0-9a-f]+: 3020 0100 li at,256
+ [0-9a-f]+: 6001 2000 pref 0x0,0\(at\)
+ [0-9a-f]+: 3020 feff li at,-257
+ [0-9a-f]+: 6001 2000 pref 0x0,0\(at\)
+ [0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+ [0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
+ [0-9a-f]+: 6020 2000 pref 0x1,0\(zero\)
+ [0-9a-f]+: 6040 2000 pref 0x2,0\(zero\)
+ [0-9a-f]+: 6060 2000 pref 0x3,0\(zero\)
+ [0-9a-f]+: 6080 2000 pref 0x4,0\(zero\)
+ [0-9a-f]+: 60a0 2000 pref 0x5,0\(zero\)
+ [0-9a-f]+: 60c0 2000 pref 0x6,0\(zero\)
+ [0-9a-f]+: 60e0 2000 pref 0x7,0\(zero\)
+ [0-9a-f]+: 60e0 207f pref 0x7,127\(zero\)
+ [0-9a-f]+: 60e0 2180 pref 0x7,-128\(zero\)
+ [0-9a-f]+: 63e0 20ff pref 0x1f,255\(zero\)
+ [0-9a-f]+: 63e0 2100 pref 0x1f,-256\(zero\)
+ [0-9a-f]+: 3020 0100 li at,256
+ [0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
+ [0-9a-f]+: 3020 feff li at,-257
+ [0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
+ [0-9a-f]+: 3020 7fff li at,32767
+ [0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+ [0-9a-f]+: 3020 8000 li at,-32768
+ [0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+ [0-9a-f]+: 63e2 20ff pref 0x1f,255\(v0\)
+ [0-9a-f]+: 63e2 2100 pref 0x1f,-256\(v0\)
+ [0-9a-f]+: 3022 0100 addiu at,v0,256
+ [0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
+ [0-9a-f]+: 3022 feff addiu at,v0,-257
+ [0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
+ [0-9a-f]+: 3022 7fff addiu at,v0,32767
+ [0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+ [0-9a-f]+: 3022 8000 addiu at,v0,-32768
+ [0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 0000 0000 nop
+ [0-9a-f]+: 0000 0800 ssnop
+ [0-9a-f]+: 0000 1800 ehb
+ [0-9a-f]+: 0000 2800 pause
+ [0-9a-f]+: ed7f li v0,-1
+ [0-9a-f]+: edff li v1,-1
+ [0-9a-f]+: ee7f li a0,-1
+ [0-9a-f]+: eeff li a1,-1
+ [0-9a-f]+: ef7f li a2,-1
+ [0-9a-f]+: efff li a3,-1
+ [0-9a-f]+: ec7f li s0,-1
+ [0-9a-f]+: ecff li s1,-1
+ [0-9a-f]+: ec80 li s1,0
+ [0-9a-f]+: ecfd li s1,125
+ [0-9a-f]+: ecfe li s1,126
+ [0-9a-f]+: 3220 007f li s1,127
+ [0-9a-f]+: 3040 0000 li v0,0
+ [0-9a-f]+: 3040 0001 li v0,1
+ [0-9a-f]+: 3040 7fff li v0,32767
+ [0-9a-f]+: 3040 8000 li v0,-32768
+ [0-9a-f]+: 5040 ffff li v0,0xffff
+ [0-9a-f]+: 1040 0001 lui v0,0x1
+ [0-9a-f]+: 3040 8000 li v0,-32768
+ [0-9a-f]+: 3040 8001 li v0,-32767
+ [0-9a-f]+: 3040 ffff li v0,-1
+ [0-9a-f]+: 1040 1234 lui v0,0x1234
+ [0-9a-f]+: 5042 5678 ori v0,v0,0x5678
+ [0-9a-f]+: 0c16 move zero,s6
+ [0-9a-f]+: 0c56 move v0,s6
+ [0-9a-f]+: 0c76 move v1,s6
+ [0-9a-f]+: 0c96 move a0,s6
+ [0-9a-f]+: 0cb6 move a1,s6
+ [0-9a-f]+: 0cd6 move a2,s6
+ [0-9a-f]+: 0cf6 move a3,s6
+ [0-9a-f]+: 0d16 move t0,s6
+ [0-9a-f]+: 0d36 move t1,s6
+ [0-9a-f]+: 0d56 move t2,s6
+ [0-9a-f]+: 0fd6 move s8,s6
+ [0-9a-f]+: 0ff6 move ra,s6
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 0c02 move zero,v0
+ [0-9a-f]+: 0c03 move zero,v1
+ [0-9a-f]+: 0c04 move zero,a0
+ [0-9a-f]+: 0c05 move zero,a1
+ [0-9a-f]+: 0c06 move zero,a2
+ [0-9a-f]+: 0c07 move zero,a3
+ [0-9a-f]+: 0c08 move zero,t0
+ [0-9a-f]+: 0c09 move zero,t1
+ [0-9a-f]+: 0c0a move zero,t2
+ [0-9a-f]+: 0c1e move zero,s8
+ [0-9a-f]+: 0c1f move zero,ra
+ [0-9a-f]+: 0ec2 move s6,v0
+ [0-9a-f]+: 0c56 move v0,s6
+ [0-9a-f]+: 0ec2 move s6,v0
+ [0-9a-f]+: 0016 1290 move v0,s6
+ [0-9a-f]+: 0002 b290 move s6,v0
+ [0-9a-f]+: cfff bc 130 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC10_S1 test
+ [0-9a-f]+: cfff bc 132 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC10_S1 test
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 93fe 0000 slti ra,s8,0
+ [0-9a-f]+: R_MICROMIPS_PC26_S1 test
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: cfff bc 13c <.*>
+ [0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
+ [0-9a-f]+: cfff bc 13e <.*>
+ [0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 93fe 0000 slti ra,s8,0
+ [0-9a-f]+: R_MICROMIPS_PC26_S1 \.L1\^B1
+
+[ 0-9a-f]+ <\.L1\^B1>:
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: cfff bc 148 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
+ [0-9a-f]+: cfff bc 14a <.*>
+ [0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 93fe 0000 slti ra,s8,0
+ [0-9a-f]+: R_MICROMIPS_PC26_S1 \.L1\^B1
+ [0-9a-f]+: 0c43 move v0,v1
+ [0-9a-f]+: f463 fffe bgezc v1,154 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_0
+ [0-9a-f]+: 0060 1190 neg v0,v1
+
+[ 0-9a-f]+ <\.L\^\_0>:
+ [0-9a-f]+: 0c44 move v0,a0
+ [0-9a-f]+: f484 fffe bgezc a0,15e <.*>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_1
+ [0-9a-f]+: 0080 1190 neg v0,a0
+
+[ 0-9a-f]+ <\.L\^\_1>:
+ [0-9a-f]+: f442 fffe bgezc v0,166 <\.L\^\_1>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_2
+ [0-9a-f]+: 0040 1190 neg v0,v0
+
+[ 0-9a-f]+ <\.L\^\_2>:
+ [0-9a-f]+: f442 fffe bgezc v0,16e <\.L\^\_2>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_3
+ [0-9a-f]+: 0040 1190 neg v0,v0
+
+[ 0-9a-f]+ <\.L\^\_3>:
+ [0-9a-f]+: 0083 1110 add v0,v1,a0
+ [0-9a-f]+: 03fe e910 add sp,s8,ra
+ [0-9a-f]+: 0082 1110 add v0,v0,a0
+ [0-9a-f]+: 0082 1110 add v0,v0,a0
+ [0-9a-f]+: 4c10 addiu zero,zero,-8
+ [0-9a-f]+: 4c50 addiu v0,v0,-8
+ [0-9a-f]+: 4c70 addiu v1,v1,-8
+ [0-9a-f]+: 4c90 addiu a0,a0,-8
+ [0-9a-f]+: 4cb0 addiu a1,a1,-8
+ [0-9a-f]+: 4cd0 addiu a2,a2,-8
+ [0-9a-f]+: 4cf0 addiu a3,a3,-8
+ [0-9a-f]+: 4d10 addiu t0,t0,-8
+ [0-9a-f]+: 4d30 addiu t1,t1,-8
+ [0-9a-f]+: 4d50 addiu t2,t2,-8
+ [0-9a-f]+: 4fd0 addiu s8,s8,-8
+ [0-9a-f]+: 4ff0 addiu ra,ra,-8
+ [0-9a-f]+: 4ff2 addiu ra,ra,-7
+ [0-9a-f]+: 4fe0 addiu ra,ra,0
+ [0-9a-f]+: 4fe2 addiu ra,ra,1
+ [0-9a-f]+: 4fec addiu ra,ra,6
+ [0-9a-f]+: 4fee addiu ra,ra,7
+ [0-9a-f]+: 33ff 0008 addiu ra,ra,8
+ [0-9a-f]+: 4ffd addiu sp,sp,-1032
+ [0-9a-f]+: 4fff addiu sp,sp,-1028
+ [0-9a-f]+: 4e01 addiu sp,sp,-1024
+ [0-9a-f]+: 4dff addiu sp,sp,1020
+ [0-9a-f]+: 4c01 addiu sp,sp,1024
+ [0-9a-f]+: 4c03 addiu sp,sp,1028
+ [0-9a-f]+: 4c03 addiu sp,sp,1028
+ [0-9a-f]+: 33bd 0408 addiu sp,sp,1032
+ [0-9a-f]+: 6d2e addiu v0,v0,-1
+ [0-9a-f]+: 6d3e addiu v0,v1,-1
+ [0-9a-f]+: 6d4e addiu v0,a0,-1
+ [0-9a-f]+: 6d5e addiu v0,a1,-1
+ [0-9a-f]+: 6d6e addiu v0,a2,-1
+ [0-9a-f]+: 6d7e addiu v0,a3,-1
+ [0-9a-f]+: 6d0e addiu v0,s0,-1
+ [0-9a-f]+: 6d1e addiu v0,s1,-1
+ [0-9a-f]+: 6d10 addiu v0,s1,1
+ [0-9a-f]+: 6d12 addiu v0,s1,4
+ [0-9a-f]+: 6d14 addiu v0,s1,8
+ [0-9a-f]+: 6d16 addiu v0,s1,12
+ [0-9a-f]+: 6d18 addiu v0,s1,16
+ [0-9a-f]+: 6d1a addiu v0,s1,20
+ [0-9a-f]+: 6d1c addiu v0,s1,24
+ [0-9a-f]+: 6d9c addiu v1,s1,24
+ [0-9a-f]+: 6e1c addiu a0,s1,24
+ [0-9a-f]+: 6e9c addiu a1,s1,24
+ [0-9a-f]+: 6f1c addiu a2,s1,24
+ [0-9a-f]+: 6f9c addiu a3,s1,24
+ [0-9a-f]+: 6c1c addiu s0,s1,24
+ [0-9a-f]+: 6c9c addiu s1,s1,24
+ [0-9a-f]+: 0c5d move v0,sp
+ [0-9a-f]+: 6d03 addiu v0,sp,4
+ [0-9a-f]+: 6d7d addiu v0,sp,248
+ [0-9a-f]+: 6d7f addiu v0,sp,252
+ [0-9a-f]+: 305d 0100 addiu v0,sp,256
+ [0-9a-f]+: 6d7f addiu v0,sp,252
+ [0-9a-f]+: 6dff addiu v1,sp,252
+ [0-9a-f]+: 6e7f addiu a0,sp,252
+ [0-9a-f]+: 6eff addiu a1,sp,252
+ [0-9a-f]+: 6f7f addiu a2,sp,252
+ [0-9a-f]+: 6fff addiu a3,sp,252
+ [0-9a-f]+: 6c7f addiu s0,sp,252
+ [0-9a-f]+: 6cff addiu s1,sp,252
+ [0-9a-f]+: 3064 8000 addiu v1,a0,-32768
+ [0-9a-f]+: 0c64 move v1,a0
+ [0-9a-f]+: 3064 7fff addiu v1,a0,32767
+ [0-9a-f]+: 3064 ffff addiu v1,a0,-1
+ [0-9a-f]+: 3063 ffff addiu v1,v1,-1
+ [0-9a-f]+: 3063 ffff addiu v1,v1,-1
+ [0-9a-f]+: 0c56 move v0,s6
+ [0-9a-f]+: 0ec2 move s6,v0
+ [0-9a-f]+: 0c56 move v0,s6
+ [0-9a-f]+: 0ec2 move s6,v0
+ [0-9a-f]+: 05a4 addu v0,v1,v0
+ [0-9a-f]+: 05b4 addu v0,v1,v1
+ [0-9a-f]+: 05c4 addu v0,v1,a0
+ [0-9a-f]+: 05d4 addu v0,v1,a1
+ [0-9a-f]+: 05e4 addu v0,v1,a2
+ [0-9a-f]+: 05f4 addu v0,v1,a3
+ [0-9a-f]+: 0584 addu v0,v1,s0
+ [0-9a-f]+: 0594 addu v0,v1,s1
+ [0-9a-f]+: 0514 addu v0,v0,s1
+ [0-9a-f]+: 0594 addu v0,v1,s1
+ [0-9a-f]+: 0614 addu v0,a0,s1
+ [0-9a-f]+: 0694 addu v0,a1,s1
+ [0-9a-f]+: 0714 addu v0,a2,s1
+ [0-9a-f]+: 0794 addu v0,a3,s1
+ [0-9a-f]+: 0414 addu v0,s0,s1
+ [0-9a-f]+: 0494 addu v0,s1,s1
+ [0-9a-f]+: 0514 addu v0,v0,s1
+ [0-9a-f]+: 0516 addu v1,v0,s1
+ [0-9a-f]+: 0518 addu a0,v0,s1
+ [0-9a-f]+: 051a addu a1,v0,s1
+ [0-9a-f]+: 051c addu a2,v0,s1
+ [0-9a-f]+: 051e addu a3,v0,s1
+ [0-9a-f]+: 0510 addu s0,v0,s1
+ [0-9a-f]+: 0512 addu s1,v0,s1
+ [0-9a-f]+: 07ae addu a3,a3,v0
+ [0-9a-f]+: 07ae addu a3,a3,v0
+ [0-9a-f]+: 057e addu a3,v0,a3
+ [0-9a-f]+: 03fe e950 addu sp,s8,ra
+ [0-9a-f]+: 3042 0000 addiu v0,v0,0
+ [0-9a-f]+: 3042 0001 addiu v0,v0,1
+ [0-9a-f]+: 3042 7fff addiu v0,v0,32767
+ [0-9a-f]+: 3042 8000 addiu v0,v0,-32768
+ [0-9a-f]+: 5020 ffff li at,0xffff
+ [0-9a-f]+: 0022 1150 addu v0,v0,at
+ [0-9a-f]+: 4521 and v0,v0,v0
+ [0-9a-f]+: 4531 and v0,v0,v1
+ [0-9a-f]+: 4541 and v0,v0,a0
+ [0-9a-f]+: 4551 and v0,v0,a1
+ [0-9a-f]+: 4561 and v0,v0,a2
+ [0-9a-f]+: 4571 and v0,v0,a3
+ [0-9a-f]+: 4501 and v0,v0,s0
+ [0-9a-f]+: 4511 and v0,v0,s1
+ [0-9a-f]+: 45a1 and v1,v1,v0
+ [0-9a-f]+: 4621 and a0,a0,v0
+ [0-9a-f]+: 46a1 and a1,a1,v0
+ [0-9a-f]+: 4721 and a2,a2,v0
+ [0-9a-f]+: 47a1 and a3,a3,v0
+ [0-9a-f]+: 4421 and s0,s0,v0
+ [0-9a-f]+: 44a1 and s1,s1,v0
+ [0-9a-f]+: 4531 and v0,v0,v1
+ [0-9a-f]+: 4531 and v0,v0,v1
+ [0-9a-f]+: 4531 and v0,v0,v1
+ [0-9a-f]+: 4531 and v0,v0,v1
+ [0-9a-f]+: 0062 1250 and v0,v0,v1
+ [0-9a-f]+: 2d21 andi v0,v0,0x1
+ [0-9a-f]+: 2d22 andi v0,v0,0x2
+ [0-9a-f]+: 2d23 andi v0,v0,0x3
+ [0-9a-f]+: 2d24 andi v0,v0,0x4
+ [0-9a-f]+: 2d25 andi v0,v0,0x7
+ [0-9a-f]+: 2d26 andi v0,v0,0x8
+ [0-9a-f]+: 2d27 andi v0,v0,0xf
+ [0-9a-f]+: 2d28 andi v0,v0,0x10
+ [0-9a-f]+: 2d29 andi v0,v0,0x1f
+ [0-9a-f]+: 2d2a andi v0,v0,0x20
+ [0-9a-f]+: 2d2b andi v0,v0,0x3f
+ [0-9a-f]+: 2d2c andi v0,v0,0x40
+ [0-9a-f]+: 2d20 andi v0,v0,0x80
+ [0-9a-f]+: 2d2d andi v0,v0,0xff
+ [0-9a-f]+: 2d2e andi v0,v0,0x8000
+ [0-9a-f]+: 2d2f andi v0,v0,0xffff
+ [0-9a-f]+: 2d3f andi v0,v1,0xffff
+ [0-9a-f]+: 2d4f andi v0,a0,0xffff
+ [0-9a-f]+: 2d5f andi v0,a1,0xffff
+ [0-9a-f]+: 2d6f andi v0,a2,0xffff
+ [0-9a-f]+: 2d7f andi v0,a3,0xffff
+ [0-9a-f]+: 2d0f andi v0,s0,0xffff
+ [0-9a-f]+: 2d1f andi v0,s1,0xffff
+ [0-9a-f]+: 2d9f andi v1,s1,0xffff
+ [0-9a-f]+: 2e1f andi a0,s1,0xffff
+ [0-9a-f]+: 2e9f andi a1,s1,0xffff
+ [0-9a-f]+: 2f1f andi a2,s1,0xffff
+ [0-9a-f]+: 2f9f andi a3,s1,0xffff
+ [0-9a-f]+: 2c1f andi s0,s1,0xffff
+ [0-9a-f]+: 2c9f andi s1,s1,0xffff
+ [0-9a-f]+: 2fff andi a3,a3,0xffff
+ [0-9a-f]+: 2fff andi a3,a3,0xffff
+ [0-9a-f]+: 2fff andi a3,a3,0xffff
+ [0-9a-f]+: d0e7 ffff andi a3,a3,0xffff
+ [0-9a-f]+: 0083 1250 and v0,v1,a0
+ [0-9a-f]+: 0082 1250 and v0,v0,a0
+ [0-9a-f]+: 0082 1250 and v0,v0,a0
+ [0-9a-f]+: d043 0000 andi v0,v1,0x0
+ [0-9a-f]+: d043 ffff andi v0,v1,0xffff
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 0023 1250 and v0,v1,at
+ [0-9a-f]+: 1020 ffff lui at,0xffff
+ [0-9a-f]+: 5021 0001 ori at,at,0x1
+ [0-9a-f]+: 0023 1250 and v0,v1,at
+
+[ 0-9a-f]+ <test2>:
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8d7f beqzc v0,310 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8dff beqzc v1,314 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8e7f beqzc a0,318 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8eff beqzc a1,31c <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8f7f beqzc a2,320 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8fff beqzc a3,324 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8c7f beqzc s0,328 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8cff beqzc s1,32c <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8d7f beqzc v0,330 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8dff beqzc v1,334 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8e7f beqzc a0,338 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8eff beqzc a1,33c <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8f7f beqzc a2,340 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8fff beqzc a3,344 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8c7f beqzc s0,348 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8cff beqzc s1,34c <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8d7f beqzc v0,350 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8dff beqzc v1,354 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8e7f beqzc a0,358 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8eff beqzc a1,35c <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8f7f beqzc a2,360 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8fff beqzc a3,364 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8c7f beqzc s0,368 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8cff beqzc s1,36c <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 8c7f beqzc s0,36e <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 81fe 0000 beqzc t7,fffc0376 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 8cff beqzc s1,378 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 821e 0000 beqzc s0,fffc0380 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+ [0-9a-f]+: 8cff beqzc s1,380 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 81fe 0000 beqzc t7,fffc0388 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+ [0-9a-f]+: 3020 000a li at,10
+ [0-9a-f]+: 7601 fffe beqc at,s0,38c <.*>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+ [0-9a-f]+: 3020 7fff li at,32767
+ [0-9a-f]+: 7601 fffe beqc at,s0,394 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 7601 fffe beqc at,s0,39c <.*>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: ad7f bnezc v0,3a4 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: adff bnezc v1,3a8 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: ae7f bnezc a0,3ac <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: aeff bnezc a1,3b0 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: af7f bnezc a2,3b4 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: afff bnezc a3,3b8 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: ac7f bnezc s0,3bc <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: acff bnezc s1,3c0 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: ad7f bnezc v0,3c4 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: adff bnezc v1,3c8 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: ae7f bnezc a0,3cc <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: aeff bnezc a1,3d0 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: af7f bnezc a2,3d4 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: afff bnezc a3,3d8 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: ac7f bnezc s0,3dc <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: acff bnezc s1,3e0 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: ad7f bnezc v0,3e4 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: adff bnezc v1,3e8 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: ae7f bnezc a0,3ec <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: aeff bnezc a1,3f0 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: af7f bnezc a2,3f4 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: afff bnezc a3,3f8 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: ac7f bnezc s0,3fc <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: acff bnezc s1,400 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: ac7f bnezc s0,402 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: a1fe 0000 bnezc t7,fffc040a <.*>
+ [0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: a21e 0000 bnezc s0,fffc0410 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: a21e 0000 bnezc s0,fffc0416 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+
+[ 0-9a-f]+ <test3>:
+ [0-9a-f]+: a21e 0000 bnezc s0,fffc041a <.*>
+ [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+ [0-9a-f]+: 441b break
+ [0-9a-f]+: 441b break
+ [0-9a-f]+: 445b break 0x1
+ [0-9a-f]+: 449b break 0x2
+ [0-9a-f]+: 44db break 0x3
+ [0-9a-f]+: 451b break 0x4
+ [0-9a-f]+: 455b break 0x5
+ [0-9a-f]+: 459b break 0x6
+ [0-9a-f]+: 45db break 0x7
+ [0-9a-f]+: 461b break 0x8
+ [0-9a-f]+: 465b break 0x9
+ [0-9a-f]+: 469b break 0xa
+ [0-9a-f]+: 46db break 0xb
+ [0-9a-f]+: 471b break 0xc
+ [0-9a-f]+: 475b break 0xd
+ [0-9a-f]+: 479b break 0xe
+ [0-9a-f]+: 47db break 0xf
+ [0-9a-f]+: 003f 0007 break 0x3f
+ [0-9a-f]+: 0040 0007 break 0x40
+ [0-9a-f]+: 03ff 0007 break 0x3ff
+ [0-9a-f]+: 03ff ffc7 break 0x3ff,0x3ff
+ [0-9a-f]+: 0000 0007 break
+ [0-9a-f]+: 0000 0007 break
+ [0-9a-f]+: 0001 0007 break 0x1
+ [0-9a-f]+: 0002 0007 break 0x2
+ [0-9a-f]+: 000f 0007 break 0xf
+ [0-9a-f]+: 003f 0007 break 0x3f
+ [0-9a-f]+: 0040 0007 break 0x40
+ [0-9a-f]+: 03ff 0007 break 0x3ff
+ [0-9a-f]+: 03ff ffc7 break 0x3ff,0x3ff
+ [0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+ [0-9a-f]+: 2000 6100 cache 0x0,-256\(zero\)
+ [0-9a-f]+: 2000 60ff cache 0x0,255\(zero\)
+ [0-9a-f]+: 3020 feff li at,-257
+ [0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+ [0-9a-f]+: 3020 0100 li at,256
+ [0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+ [0-9a-f]+: 2002 6000 cache 0x0,0\(v0\)
+ [0-9a-f]+: 2002 6100 cache 0x0,-256\(v0\)
+ [0-9a-f]+: 2002 60ff cache 0x0,255\(v0\)
+ [0-9a-f]+: 3022 feff addiu at,v0,-257
+ [0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+ [0-9a-f]+: 3022 0100 addiu at,v0,256
+ [0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+ [0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+ [0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
+ [0-9a-f]+: 2020 6000 cache 0x1,0\(zero\)
+ [0-9a-f]+: 2040 6000 cache 0x2,0\(zero\)
+ [0-9a-f]+: 2060 6000 cache 0x3,0\(zero\)
+ [0-9a-f]+: 2080 6000 cache 0x4,0\(zero\)
+ [0-9a-f]+: 20a0 6000 cache 0x5,0\(zero\)
+ [0-9a-f]+: 20c0 6000 cache 0x6,0\(zero\)
+ [0-9a-f]+: 23e0 6000 cache 0x1f,0\(zero\)
+ [0-9a-f]+: 23e0 60ff cache 0x1f,255\(zero\)
+ [0-9a-f]+: 23e0 6100 cache 0x1f,-256\(zero\)
+ [0-9a-f]+: 2000 60ff cache 0x0,255\(zero\)
+ [0-9a-f]+: 2000 6100 cache 0x0,-256\(zero\)
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 0061 0950 addu at,at,v1
+ [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+ [0-9a-f]+: 3023 0100 addiu at,v1,256
+ [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+ [0-9a-f]+: 3023 feff addiu at,v1,-257
+ [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 0061 0950 addu at,at,v1
+ [0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+ [0-9a-f]+: 23e3 61ff cache 0x1f,-1\(v1\)
+ [0-9a-f]+: 1020 ffff lui at,0xffff
+ [0-9a-f]+: 0061 0950 addu at,at,v1
+ [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+ [0-9a-f]+: 1020 ffff lui at,0xffff
+ [0-9a-f]+: 0061 0950 addu at,at,v1
+ [0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 0061 0950 addu at,at,v1
+ [0-9a-f]+: 23e1 61ff cache 0x1f,-1\(at\)
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+ [0-9a-f]+: 3020 0100 li at,256
+ [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+ [0-9a-f]+: 3020 feff li at,-257
+ [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+ [0-9a-f]+: 23e0 61ff cache 0x1f,-1\(zero\)
+ [0-9a-f]+: 1020 ffff lui at,0xffff
+ [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
+ [0-9a-f]+: 1020 ffff lui at,0xffff
+ [0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 23e1 61ff cache 0x1f,-1\(at\)
+ [0-9a-f]+: 0043 4b3c clo v0,v1
+ [0-9a-f]+: 0062 4b3c clo v1,v0
+ [0-9a-f]+: 0043 5b3c clz v0,v1
+ [0-9a-f]+: 0062 5b3c clz v1,v0
+ [0-9a-f]+: 0000 e37c deret
+ [0-9a-f]+: 0000 477c di
+ [0-9a-f]+: 0000 477c di
+ [0-9a-f]+: 0002 477c di v0
+ [0-9a-f]+: 0003 477c di v1
+ [0-9a-f]+: 001e 477c di s8
+ [0-9a-f]+: 001f 477c di ra
+ [0-9a-f]+: 0062 0118 div zero,v0,v1
+ [0-9a-f]+: 03fe 0118 div zero,s8,ra
+ [0-9a-f]+: 0060 0118 div zero,zero,v1
+ [0-9a-f]+: 03e0 0118 div zero,zero,ra
+ [0-9a-f]+: 0003 1118 div v0,v1,zero
+ [0-9a-f]+: 0083 1118 div v0,v1,a0
+ [0-9a-f]+: 0062 0198 divu zero,v0,v1
+ [0-9a-f]+: 03fe 0198 divu zero,s8,ra
+ [0-9a-f]+: 0060 0198 divu zero,zero,v1
+ [0-9a-f]+: 03e0 0198 divu zero,zero,ra
+ [0-9a-f]+: 0003 1198 divu v0,v1,zero
+ [0-9a-f]+: 0083 1198 divu v0,v1,a0
+ [0-9a-f]+: 0000 577c ei
+ [0-9a-f]+: 0000 577c ei
+ [0-9a-f]+: 0002 577c ei v0
+ [0-9a-f]+: 0003 577c ei v1
+ [0-9a-f]+: 001e 577c ei s8
+ [0-9a-f]+: 001f 577c ei ra
+ [0-9a-f]+: 0000 f37c eret
+ [0-9a-f]+: 0043 716c ext v0,v1,0x5,0xf
+ [0-9a-f]+: 0043 f82c ext v0,v1,0x0,0x20
+ [0-9a-f]+: 0043 07ec ext v0,v1,0x1f,0x1
+ [0-9a-f]+: 03fe 07ec ext ra,s8,0x1f,0x1
+ [0-9a-f]+: 0043 994c ins v0,v1,0x5,0xf
+ [0-9a-f]+: 0043 f80c ins v0,v1,0x0,0x20
+ [0-9a-f]+: 0043 ffcc ins v0,v1,0x1f,0x1
+ [0-9a-f]+: 03fe ffcc ins ra,s8,0x1f,0x1
+ [0-9a-f]+: 4403 jrc zero
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 4443 jrc v0
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 4463 jrc v1
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 4483 jrc a0
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 44a3 jrc a1
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 44c3 jrc a2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 44e3 jrc a3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 4503 jrc t0
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 47c3 jrc s8
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 47e3 jrc ra
+ [0-9a-f]+: 8000 0000 jrc zero
+ [0-9a-f]+: 8002 0000 jrc v0
+ [0-9a-f]+: 8003 0000 jrc v1
+ [0-9a-f]+: 8004 0000 jrc a0
+ [0-9a-f]+: 8005 0000 jrc a1
+ [0-9a-f]+: 8006 0000 jrc a2
+ [0-9a-f]+: 8007 0000 jrc a3
+ [0-9a-f]+: 8008 0000 jrc t0
+ [0-9a-f]+: 801e 0000 jrc s8
+ [0-9a-f]+: 801f 0000 jrc ra
+ [0-9a-f]+: 4403 jrc zero
+ [0-9a-f]+: 4443 jrc v0
+ [0-9a-f]+: 4463 jrc v1
+ [0-9a-f]+: 4483 jrc a0
+ [0-9a-f]+: 44a3 jrc a1
+ [0-9a-f]+: 44c3 jrc a2
+ [0-9a-f]+: 44e3 jrc a3
+ [0-9a-f]+: 4503 jrc t0
+ [0-9a-f]+: 47c3 jrc s8
+ [0-9a-f]+: 47e3 jrc ra
+ [0-9a-f]+: 0000 1f3c jrc.hb zero
+ [0-9a-f]+: 0002 1f3c jrc.hb v0
+ [0-9a-f]+: 0003 1f3c jrc.hb v1
+ [0-9a-f]+: 0004 1f3c jrc.hb a0
+ [0-9a-f]+: 0005 1f3c jrc.hb a1
+ [0-9a-f]+: 0006 1f3c jrc.hb a2
+ [0-9a-f]+: 0007 1f3c jrc.hb a3
+ [0-9a-f]+: 0008 1f3c jrc.hb t0
+ [0-9a-f]+: 001e 1f3c jrc.hb s8
+ [0-9a-f]+: 001f 1f3c jrc.hb ra
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 4403 jrc zero
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 4443 jrc v0
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 4463 jrc v1
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 4483 jrc a0
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 44a3 jrc a1
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 44c3 jrc a2
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 44e3 jrc a3
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 4503 jrc t0
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 47c3 jrc s8
+ [0-9a-f]+: 0c00 nop
+ [0-9a-f]+: 47e3 jrc ra
+ [0-9a-f]+: 440b jalrc zero
+ [0-9a-f]+: 444b jalrc v0
+ [0-9a-f]+: 446b jalrc v1
+ [0-9a-f]+: 448b jalrc a0
+ [0-9a-f]+: 44ab jalrc a1
+ [0-9a-f]+: 44cb jalrc a2
+ [0-9a-f]+: 44eb jalrc a3
+ [0-9a-f]+: 450b jalrc t0
+ [0-9a-f]+: 47cb jalrc s8
+ [0-9a-f]+: 03e0 0f3c jalrc zero
+ [0-9a-f]+: 03e2 0f3c jalrc v0
+ [0-9a-f]+: 03e3 0f3c jalrc v1
+ [0-9a-f]+: 03e4 0f3c jalrc a0
+ [0-9a-f]+: 03e5 0f3c jalrc a1
+ [0-9a-f]+: 03e6 0f3c jalrc a2
+ [0-9a-f]+: 03e7 0f3c jalrc a3
+ [0-9a-f]+: 03e8 0f3c jalrc t0
+ [0-9a-f]+: 03fe 0f3c jalrc s8
+ [0-9a-f]+: 440b jalrc zero
+ [0-9a-f]+: 444b jalrc v0
+ [0-9a-f]+: 446b jalrc v1
+ [0-9a-f]+: 448b jalrc a0
+ [0-9a-f]+: 44ab jalrc a1
+ [0-9a-f]+: 44cb jalrc a2
+ [0-9a-f]+: 44eb jalrc a3
+ [0-9a-f]+: 450b jalrc t0
+ [0-9a-f]+: 47cb jalrc s8
+ [0-9a-f]+: 03df 0f3c jalrc s8,ra
+ [0-9a-f]+: 0040 0f3c jalrc v0,zero
+ [0-9a-f]+: 0062 0f3c jalrc v1,v0
+ [0-9a-f]+: 0043 0f3c jalrc v0,v1
+ [0-9a-f]+: 0044 0f3c jalrc v0,a0
+ [0-9a-f]+: 0045 0f3c jalrc v0,a1
+ [0-9a-f]+: 0046 0f3c jalrc v0,a2
+ [0-9a-f]+: 0047 0f3c jalrc v0,a3
+ [0-9a-f]+: 0048 0f3c jalrc v0,t0
+ [0-9a-f]+: 005e 0f3c jalrc v0,s8
+ [0-9a-f]+: 005f 0f3c jalrc v0,ra
+ [0-9a-f]+: 03e0 1f3c jalrc.hb zero
+ [0-9a-f]+: 03e2 1f3c jalrc.hb v0
+ [0-9a-f]+: 03e3 1f3c jalrc.hb v1
+ [0-9a-f]+: 03e4 1f3c jalrc.hb a0
+ [0-9a-f]+: 03e5 1f3c jalrc.hb a1
+ [0-9a-f]+: 03e6 1f3c jalrc.hb a2
+ [0-9a-f]+: 03e7 1f3c jalrc.hb a3
+ [0-9a-f]+: 03e8 1f3c jalrc.hb t0
+ [0-9a-f]+: 03fe 1f3c jalrc.hb s8
+ [0-9a-f]+: 03e0 1f3c jalrc.hb zero
+ [0-9a-f]+: 03e2 1f3c jalrc.hb v0
+ [0-9a-f]+: 03e3 1f3c jalrc.hb v1
+ [0-9a-f]+: 03e4 1f3c jalrc.hb a0
+ [0-9a-f]+: 03e5 1f3c jalrc.hb a1
+ [0-9a-f]+: 03e6 1f3c jalrc.hb a2
+ [0-9a-f]+: 03e7 1f3c jalrc.hb a3
+ [0-9a-f]+: 03e8 1f3c jalrc.hb t0
+ [0-9a-f]+: 03fe 1f3c jalrc.hb s8
+ [0-9a-f]+: 03df 1f3c jalrc.hb s8,ra
+ [0-9a-f]+: 0040 1f3c jalrc.hb v0,zero
+ [0-9a-f]+: 0062 1f3c jalrc.hb v1,v0
+ [0-9a-f]+: 0043 1f3c jalrc.hb v0,v1
+ [0-9a-f]+: 0044 1f3c jalrc.hb v0,a0
+ [0-9a-f]+: 0045 1f3c jalrc.hb v0,a1
+ [0-9a-f]+: 0046 1f3c jalrc.hb v0,a2
+ [0-9a-f]+: 0047 1f3c jalrc.hb v0,a3
+ [0-9a-f]+: 0048 1f3c jalrc.hb v0,t0
+ [0-9a-f]+: 005e 1f3c jalrc.hb v0,s8
+ [0-9a-f]+: 005f 1f3c jalrc.hb v0,ra
+ [0-9a-f]+: 0043 0f3c jalrc v0,v1
+ [0-9a-f]+: 03df 0f3c jalrc s8,ra
+ [0-9a-f]+: 446b jalrc v1
+ [0-9a-f]+: 47eb jalrc ra
+ [0-9a-f]+: b3fe 0000 sltiu ra,s8,0
+ [0-9a-f]+: R_MICROMIPS_PC26_S1 test
+ [0-9a-f]+: b3fe 0000 sltiu ra,s8,0
+ [0-9a-f]+: R_MICROMIPS_PC26_S1 test2
+ [0-9a-f]+: 1040 0000 lui v0,0x0
+ [0-9a-f]+: R_MICROMIPS_HI16 test
+ [0-9a-f]+: 3042 0000 addiu v0,v0,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+ [0-9a-f]+: 1040 0000 lui v0,0x0
+ [0-9a-f]+: R_MICROMIPS_HI16 test
+ [0-9a-f]+: 3042 0000 addiu v0,v0,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+ [0-9a-f]+: 1c60 0000 lb v1,0\(zero\)
+ [0-9a-f]+: 1c60 0004 lb v1,4\(zero\)
+ [0-9a-f]+: 1c60 0000 lb v1,0\(zero\)
+ [0-9a-f]+: 1c60 0004 lb v1,4\(zero\)
+ [0-9a-f]+: 1c60 7fff lb v1,32767\(zero\)
+ [0-9a-f]+: 1c60 8000 lb v1,-32768\(zero\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 1c63 ffff lb v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+ [0-9a-f]+: 1c60 8000 lb v1,-32768\(zero\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 1c63 0001 lb v1,1\(v1\)
+ [0-9a-f]+: 1c60 8001 lb v1,-32767\(zero\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+ [0-9a-f]+: 1c60 ffff lb v1,-1\(zero\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 1c63 5678 lb v1,22136\(v1\)
+ [0-9a-f]+: 1c64 0000 lb v1,0\(a0\)
+ [0-9a-f]+: 1c64 0000 lb v1,0\(a0\)
+ [0-9a-f]+: 1c64 0004 lb v1,4\(a0\)
+ [0-9a-f]+: 1c64 7fff lb v1,32767\(a0\)
+ [0-9a-f]+: 1c64 8000 lb v1,-32768\(a0\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 1c63 ffff lb v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+ [0-9a-f]+: 1c64 8000 lb v1,-32768\(a0\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 1c63 0001 lb v1,1\(v1\)
+ [0-9a-f]+: 1c64 8001 lb v1,-32767\(a0\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
+ [0-9a-f]+: 1c64 ffff lb v1,-1\(a0\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 1c63 5678 lb v1,22136\(v1\)
+ [0-9a-f]+: 093f lbu v0,-1\(v1\)
+ [0-9a-f]+: 0930 lbu v0,0\(v1\)
+ [0-9a-f]+: 0930 lbu v0,0\(v1\)
+ [0-9a-f]+: 0931 lbu v0,1\(v1\)
+ [0-9a-f]+: 0932 lbu v0,2\(v1\)
+ [0-9a-f]+: 0933 lbu v0,3\(v1\)
+ [0-9a-f]+: 0934 lbu v0,4\(v1\)
+ [0-9a-f]+: 0935 lbu v0,5\(v1\)
+ [0-9a-f]+: 0936 lbu v0,6\(v1\)
+ [0-9a-f]+: 0937 lbu v0,7\(v1\)
+ [0-9a-f]+: 0938 lbu v0,8\(v1\)
+ [0-9a-f]+: 0939 lbu v0,9\(v1\)
+ [0-9a-f]+: 093a lbu v0,10\(v1\)
+ [0-9a-f]+: 093b lbu v0,11\(v1\)
+ [0-9a-f]+: 093c lbu v0,12\(v1\)
+ [0-9a-f]+: 093d lbu v0,13\(v1\)
+ [0-9a-f]+: 093e lbu v0,14\(v1\)
+ [0-9a-f]+: 092e lbu v0,14\(v0\)
+ [0-9a-f]+: 094e lbu v0,14\(a0\)
+ [0-9a-f]+: 095e lbu v0,14\(a1\)
+ [0-9a-f]+: 096e lbu v0,14\(a2\)
+ [0-9a-f]+: 097e lbu v0,14\(a3\)
+ [0-9a-f]+: 090e lbu v0,14\(s0\)
+ [0-9a-f]+: 091e lbu v0,14\(s1\)
+ [0-9a-f]+: 099e lbu v1,14\(s1\)
+ [0-9a-f]+: 0a1e lbu a0,14\(s1\)
+ [0-9a-f]+: 0a9e lbu a1,14\(s1\)
+ [0-9a-f]+: 0b1e lbu a2,14\(s1\)
+ [0-9a-f]+: 0b9e lbu a3,14\(s1\)
+ [0-9a-f]+: 081e lbu s0,14\(s1\)
+ [0-9a-f]+: 089e lbu s1,14\(s1\)
+ [0-9a-f]+: 1460 0000 lbu v1,0\(zero\)
+ [0-9a-f]+: 1460 0004 lbu v1,4\(zero\)
+ [0-9a-f]+: 1460 0000 lbu v1,0\(zero\)
+ [0-9a-f]+: 1460 0004 lbu v1,4\(zero\)
+ [0-9a-f]+: 1460 7fff lbu v1,32767\(zero\)
+ [0-9a-f]+: 1460 8000 lbu v1,-32768\(zero\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 1463 ffff lbu v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+ [0-9a-f]+: 1460 8000 lbu v1,-32768\(zero\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 1463 0001 lbu v1,1\(v1\)
+ [0-9a-f]+: 1460 8001 lbu v1,-32767\(zero\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+ [0-9a-f]+: 1460 ffff lbu v1,-1\(zero\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 1463 5678 lbu v1,22136\(v1\)
+ [0-9a-f]+: 09c0 lbu v1,0\(a0\)
+ [0-9a-f]+: 09c0 lbu v1,0\(a0\)
+ [0-9a-f]+: 09c4 lbu v1,4\(a0\)
+ [0-9a-f]+: 1464 7fff lbu v1,32767\(a0\)
+ [0-9a-f]+: 1464 8000 lbu v1,-32768\(a0\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 1463 ffff lbu v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+ [0-9a-f]+: 1464 8000 lbu v1,-32768\(a0\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 1463 0001 lbu v1,1\(v1\)
+ [0-9a-f]+: 1464 8001 lbu v1,-32767\(a0\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
+ [0-9a-f]+: 1464 ffff lbu v1,-1\(a0\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 1463 5678 lbu v1,22136\(v1\)
+ [0-9a-f]+: 3c60 0000 lh v1,0\(zero\)
+ [0-9a-f]+: 3c60 0004 lh v1,4\(zero\)
+ [0-9a-f]+: 3c60 0000 lh v1,0\(zero\)
+ [0-9a-f]+: 3c60 0004 lh v1,4\(zero\)
+ [0-9a-f]+: 3c60 7fff lh v1,32767\(zero\)
+ [0-9a-f]+: 3c60 8000 lh v1,-32768\(zero\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 3c63 ffff lh v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+ [0-9a-f]+: 3c60 8000 lh v1,-32768\(zero\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 3c63 0001 lh v1,1\(v1\)
+ [0-9a-f]+: 3c60 8001 lh v1,-32767\(zero\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+ [0-9a-f]+: 3c60 ffff lh v1,-1\(zero\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 3c63 5678 lh v1,22136\(v1\)
+ [0-9a-f]+: 3c64 0000 lh v1,0\(a0\)
+ [0-9a-f]+: 3c64 0000 lh v1,0\(a0\)
+ [0-9a-f]+: 3c64 0004 lh v1,4\(a0\)
+ [0-9a-f]+: 3c64 7fff lh v1,32767\(a0\)
+ [0-9a-f]+: 3c64 8000 lh v1,-32768\(a0\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 3c63 ffff lh v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+ [0-9a-f]+: 3c64 8000 lh v1,-32768\(a0\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 3c63 0001 lh v1,1\(v1\)
+ [0-9a-f]+: 3c64 8001 lh v1,-32767\(a0\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
+ [0-9a-f]+: 3c64 ffff lh v1,-1\(a0\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 3c63 5678 lh v1,22136\(v1\)
+ [0-9a-f]+: 2930 lhu v0,0\(v1\)
+ [0-9a-f]+: 2930 lhu v0,0\(v1\)
+ [0-9a-f]+: 2931 lhu v0,2\(v1\)
+ [0-9a-f]+: 2932 lhu v0,4\(v1\)
+ [0-9a-f]+: 2933 lhu v0,6\(v1\)
+ [0-9a-f]+: 2934 lhu v0,8\(v1\)
+ [0-9a-f]+: 2935 lhu v0,10\(v1\)
+ [0-9a-f]+: 2936 lhu v0,12\(v1\)
+ [0-9a-f]+: 2937 lhu v0,14\(v1\)
+ [0-9a-f]+: 2938 lhu v0,16\(v1\)
+ [0-9a-f]+: 2939 lhu v0,18\(v1\)
+ [0-9a-f]+: 293a lhu v0,20\(v1\)
+ [0-9a-f]+: 293b lhu v0,22\(v1\)
+ [0-9a-f]+: 293c lhu v0,24\(v1\)
+ [0-9a-f]+: 293d lhu v0,26\(v1\)
+ [0-9a-f]+: 293e lhu v0,28\(v1\)
+ [0-9a-f]+: 293f lhu v0,30\(v1\)
+ [0-9a-f]+: 294f lhu v0,30\(a0\)
+ [0-9a-f]+: 295f lhu v0,30\(a1\)
+ [0-9a-f]+: 296f lhu v0,30\(a2\)
+ [0-9a-f]+: 297f lhu v0,30\(a3\)
+ [0-9a-f]+: 292f lhu v0,30\(v0\)
+ [0-9a-f]+: 290f lhu v0,30\(s0\)
+ [0-9a-f]+: 291f lhu v0,30\(s1\)
+ [0-9a-f]+: 299f lhu v1,30\(s1\)
+ [0-9a-f]+: 2a1f lhu a0,30\(s1\)
+ [0-9a-f]+: 2a9f lhu a1,30\(s1\)
+ [0-9a-f]+: 2b1f lhu a2,30\(s1\)
+ [0-9a-f]+: 2b9f lhu a3,30\(s1\)
+ [0-9a-f]+: 281f lhu s0,30\(s1\)
+ [0-9a-f]+: 289f lhu s1,30\(s1\)
+ [0-9a-f]+: 3460 0000 lhu v1,0\(zero\)
+ [0-9a-f]+: 3460 0004 lhu v1,4\(zero\)
+ [0-9a-f]+: 3460 0000 lhu v1,0\(zero\)
+ [0-9a-f]+: 3460 0004 lhu v1,4\(zero\)
+ [0-9a-f]+: 3460 7fff lhu v1,32767\(zero\)
+ [0-9a-f]+: 3460 8000 lhu v1,-32768\(zero\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 3463 ffff lhu v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+ [0-9a-f]+: 3460 8000 lhu v1,-32768\(zero\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 3463 0001 lhu v1,1\(v1\)
+ [0-9a-f]+: 3460 8001 lhu v1,-32767\(zero\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+ [0-9a-f]+: 3460 ffff lhu v1,-1\(zero\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 3463 5678 lhu v1,22136\(v1\)
+ [0-9a-f]+: 29c0 lhu v1,0\(a0\)
+ [0-9a-f]+: 29c0 lhu v1,0\(a0\)
+ [0-9a-f]+: 29c2 lhu v1,4\(a0\)
+ [0-9a-f]+: 3464 7fff lhu v1,32767\(a0\)
+ [0-9a-f]+: 3464 8000 lhu v1,-32768\(a0\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 3463 ffff lhu v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+ [0-9a-f]+: 3464 8000 lhu v1,-32768\(a0\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 3463 0001 lhu v1,1\(v1\)
+ [0-9a-f]+: 3464 8001 lhu v1,-32767\(a0\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
+ [0-9a-f]+: 3464 ffff lhu v1,-1\(a0\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 3463 5678 lhu v1,22136\(v1\)
+ [0-9a-f]+: 6060 3000 ll v1,0\(zero\)
+ [0-9a-f]+: 6060 3000 ll v1,0\(zero\)
+ [0-9a-f]+: 6060 3004 ll v1,4\(zero\)
+ [0-9a-f]+: 6060 3004 ll v1,4\(zero\)
+ [0-9a-f]+: 3060 7fff li v1,32767
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 3060 8000 li v1,-32768
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 6063 31ff ll v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 3060 8000 li v1,-32768
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+ [0-9a-f]+: 3060 8001 li v1,-32767
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 6060 31ff ll v1,-1\(zero\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 5063 5600 ori v1,v1,0x5600
+ [0-9a-f]+: 6063 3078 ll v1,120\(v1\)
+ [0-9a-f]+: 6064 3000 ll v1,0\(a0\)
+ [0-9a-f]+: 6064 3000 ll v1,0\(a0\)
+ [0-9a-f]+: 6064 3004 ll v1,4\(a0\)
+ [0-9a-f]+: 3064 7fff addiu v1,a0,32767
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 3064 8000 addiu v1,a0,-32768
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 6063 31ff ll v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 3064 8000 addiu v1,a0,-32768
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 6063 3001 ll v1,1\(v1\)
+ [0-9a-f]+: 3064 8001 addiu v1,a0,-32767
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
+ [0-9a-f]+: 6064 31ff ll v1,-1\(a0\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 5063 5600 ori v1,v1,0x5600
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: 6063 3078 ll v1,120\(v1\)
+ [0-9a-f]+: 1060 0000 lui v1,0x0
+ [0-9a-f]+: 1060 7fff lui v1,0x7fff
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 6940 lw v0,0\(a0\)
+ [0-9a-f]+: 6940 lw v0,0\(a0\)
+ [0-9a-f]+: 6941 lw v0,4\(a0\)
+ [0-9a-f]+: 6942 lw v0,8\(a0\)
+ [0-9a-f]+: 6943 lw v0,12\(a0\)
+ [0-9a-f]+: 6944 lw v0,16\(a0\)
+ [0-9a-f]+: 6945 lw v0,20\(a0\)
+ [0-9a-f]+: 6946 lw v0,24\(a0\)
+ [0-9a-f]+: 6947 lw v0,28\(a0\)
+ [0-9a-f]+: 6948 lw v0,32\(a0\)
+ [0-9a-f]+: 6949 lw v0,36\(a0\)
+ [0-9a-f]+: 694a lw v0,40\(a0\)
+ [0-9a-f]+: 694b lw v0,44\(a0\)
+ [0-9a-f]+: 694c lw v0,48\(a0\)
+ [0-9a-f]+: 694d lw v0,52\(a0\)
+ [0-9a-f]+: 694e lw v0,56\(a0\)
+ [0-9a-f]+: 694f lw v0,60\(a0\)
+ [0-9a-f]+: 695f lw v0,60\(a1\)
+ [0-9a-f]+: 696f lw v0,60\(a2\)
+ [0-9a-f]+: 697f lw v0,60\(a3\)
+ [0-9a-f]+: 692f lw v0,60\(v0\)
+ [0-9a-f]+: 693f lw v0,60\(v1\)
+ [0-9a-f]+: 690f lw v0,60\(s0\)
+ [0-9a-f]+: 691f lw v0,60\(s1\)
+ [0-9a-f]+: 699f lw v1,60\(s1\)
+ [0-9a-f]+: 6a1f lw a0,60\(s1\)
+ [0-9a-f]+: 6a9f lw a1,60\(s1\)
+ [0-9a-f]+: 6b1f lw a2,60\(s1\)
+ [0-9a-f]+: 6b9f lw a3,60\(s1\)
+ [0-9a-f]+: 681f lw s0,60\(s1\)
+ [0-9a-f]+: 689f lw s1,60\(s1\)
+ [0-9a-f]+: 4880 lw a0,0\(sp\)
+ [0-9a-f]+: 4880 lw a0,0\(sp\)
+ [0-9a-f]+: 4881 lw a0,4\(sp\)
+ [0-9a-f]+: 4882 lw a0,8\(sp\)
+ [0-9a-f]+: 4883 lw a0,12\(sp\)
+ [0-9a-f]+: 4884 lw a0,16\(sp\)
+ [0-9a-f]+: 4885 lw a0,20\(sp\)
+ [0-9a-f]+: 489f lw a0,124\(sp\)
+ [0-9a-f]+: 485f lw v0,124\(sp\)
+ [0-9a-f]+: 485f lw v0,124\(sp\)
+ [0-9a-f]+: 487f lw v1,124\(sp\)
+ [0-9a-f]+: 489f lw a0,124\(sp\)
+ [0-9a-f]+: 48bf lw a1,124\(sp\)
+ [0-9a-f]+: 48df lw a2,124\(sp\)
+ [0-9a-f]+: 48ff lw a3,124\(sp\)
+ [0-9a-f]+: 491f lw t0,124\(sp\)
+ [0-9a-f]+: 493f lw t1,124\(sp\)
+ [0-9a-f]+: 495f lw t2,124\(sp\)
+ [0-9a-f]+: 4bdf lw s8,124\(sp\)
+ [0-9a-f]+: 4bff lw ra,124\(sp\)
+ [0-9a-f]+: fc9d 01f8 lw a0,504\(sp\)
+ [0-9a-f]+: fc9d 01fc lw a0,508\(sp\)
+ [0-9a-f]+: fe1d 01fc lw s0,508\(sp\)
+ [0-9a-f]+: fe3d 01fc lw s1,508\(sp\)
+ [0-9a-f]+: fe5d 01fc lw s2,508\(sp\)
+ [0-9a-f]+: fe7d 01fc lw s3,508\(sp\)
+ [0-9a-f]+: fe9d 01fc lw s4,508\(sp\)
+ [0-9a-f]+: febd 01fc lw s5,508\(sp\)
+ [0-9a-f]+: fffd 01fc lw ra,508\(sp\)
+ [0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+ [0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+ [0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+ [0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+ [0-9a-f]+: fc60 0000 lw v1,0\(zero\)
+ [0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+ [0-9a-f]+: fc60 7fff lw v1,32767\(zero\)
+ [0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: fc63 ffff lw v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+ [0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: fc63 0001 lw v1,1\(v1\)
+ [0-9a-f]+: fc60 8001 lw v1,-32767\(zero\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+ [0-9a-f]+: fc60 ffff lw v1,-1\(zero\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: fc63 5678 lw v1,22136\(v1\)
+ [0-9a-f]+: 69c0 lw v1,0\(a0\)
+ [0-9a-f]+: 69c0 lw v1,0\(a0\)
+ [0-9a-f]+: 69c1 lw v1,4\(a0\)
+ [0-9a-f]+: fc64 7fff lw v1,32767\(a0\)
+ [0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: fc63 ffff lw v1,-1\(v1\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+ [0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+ [0-9a-f]+: 1060 ffff lui v1,0xffff
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: fc63 0001 lw v1,1\(v1\)
+ [0-9a-f]+: fc64 8001 lw v1,-32767\(a0\)
+ [0-9a-f]+: 1060 f000 lui v1,0xf000
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: fc63 0000 lw v1,0\(v1\)
+ [0-9a-f]+: fc64 ffff lw v1,-1\(a0\)
+ [0-9a-f]+: 1060 1234 lui v1,0x1234
+ [0-9a-f]+: 0083 1950 addu v1,v1,a0
+ [0-9a-f]+: fc63 5678 lw v1,22136\(v1\)
+ [0-9a-f]+: 44c2 lwm s0,ra,48\(sp\)
+ [0-9a-f]+: 45c2 lwm s0-s1,ra,48\(sp\)
+ [0-9a-f]+: 45c2 lwm s0-s1,ra,48\(sp\)
+ [0-9a-f]+: 46c2 lwm s0-s2,ra,48\(sp\)
+ [0-9a-f]+: 46c2 lwm s0-s2,ra,48\(sp\)
+ [0-9a-f]+: 47c2 lwm s0-s3,ra,48\(sp\)
+ [0-9a-f]+: 47c2 lwm s0-s3,ra,48\(sp\)
+ [0-9a-f]+: 4402 lwm s0,ra,0\(sp\)
+ [0-9a-f]+: 4402 lwm s0,ra,0\(sp\)
+ [0-9a-f]+: 4412 lwm s0,ra,4\(sp\)
+ [0-9a-f]+: 4422 lwm s0,ra,8\(sp\)
+ [0-9a-f]+: 4432 lwm s0,ra,12\(sp\)
+ [0-9a-f]+: 4442 lwm s0,ra,16\(sp\)
+ [0-9a-f]+: 4452 lwm s0,ra,20\(sp\)
+ [0-9a-f]+: 4462 lwm s0,ra,24\(sp\)
+ [0-9a-f]+: 4472 lwm s0,ra,28\(sp\)
+ [0-9a-f]+: 4482 lwm s0,ra,32\(sp\)
+ [0-9a-f]+: 4492 lwm s0,ra,36\(sp\)
+ [0-9a-f]+: 44a2 lwm s0,ra,40\(sp\)
+ [0-9a-f]+: 44b2 lwm s0,ra,44\(sp\)
+ [0-9a-f]+: 44c2 lwm s0,ra,48\(sp\)
+ [0-9a-f]+: 44d2 lwm s0,ra,52\(sp\)
+ [0-9a-f]+: 44e2 lwm s0,ra,56\(sp\)
+ [0-9a-f]+: 44f2 lwm s0,ra,60\(sp\)
+ [0-9a-f]+: 2020 5000 lwm s0,0\(zero\)
+ [0-9a-f]+: 2020 5004 lwm s0,4\(zero\)
+ [0-9a-f]+: 2025 5000 lwm s0,0\(a1\)
+ [0-9a-f]+: 2025 57ff lwm s0,2047\(a1\)
+ [0-9a-f]+: 2045 57ff lwm s0-s1,2047\(a1\)
+ [0-9a-f]+: 2065 57ff lwm s0-s2,2047\(a1\)
+ [0-9a-f]+: 2085 57ff lwm s0-s3,2047\(a1\)
+ [0-9a-f]+: 20a5 57ff lwm s0-s4,2047\(a1\)
+ [0-9a-f]+: 20c5 57ff lwm s0-s5,2047\(a1\)
+ [0-9a-f]+: 20e5 57ff lwm s0-s6,2047\(a1\)
+ [0-9a-f]+: 2105 57ff lwm s0-s7,2047\(a1\)
+ [0-9a-f]+: 2125 57ff lwm s0-s7,s8,2047\(a1\)
+ [0-9a-f]+: 2205 57ff lwm ra,2047\(a1\)
+ [0-9a-f]+: 2225 5000 lwm s0,ra,0\(a1\)
+ [0-9a-f]+: 2245 5000 lwm s0-s1,ra,0\(a1\)
+ [0-9a-f]+: 2265 5000 lwm s0-s2,ra,0\(a1\)
+ [0-9a-f]+: 2285 5000 lwm s0-s3,ra,0\(a1\)
+ [0-9a-f]+: 22a5 5000 lwm s0-s4,ra,0\(a1\)
+ [0-9a-f]+: 22c5 5000 lwm s0-s5,ra,0\(a1\)
+ [0-9a-f]+: 22e5 5000 lwm s0-s6,ra,0\(a1\)
+ [0-9a-f]+: 2305 5000 lwm s0-s7,ra,0\(a1\)
+ [0-9a-f]+: 2325 5000 lwm s0-s7,s8,ra,0\(a1\)
+ [0-9a-f]+: 3020 8000 li at,-32768
+ [0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+ [0-9a-f]+: 3020 7fff li at,32767
+ [0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+ [0-9a-f]+: 2020 5000 lwm s0,0\(zero\)
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+ [0-9a-f]+: 303d 8000 addiu at,sp,-32768
+ [0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+ [0-9a-f]+: 303d 7fff addiu at,sp,32767
+ [0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+ [0-9a-f]+: 203d 5000 lwm s0,0\(sp\)
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 03a1 0950 addu at,at,sp
+ [0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
+ [0-9a-f]+: 2040 1000 lwp v0,0\(zero\)
+ [0-9a-f]+: 2040 1004 lwp v0,4\(zero\)
+ [0-9a-f]+: 205d 1000 lwp v0,0\(sp\)
+ [0-9a-f]+: 205d 1000 lwp v0,0\(sp\)
+ [0-9a-f]+: 2043 1800 lwp v0,-2048\(v1\)
+ [0-9a-f]+: 2043 17ff lwp v0,2047\(v1\)
+ [0-9a-f]+: 3023 8000 addiu at,v1,-32768
+ [0-9a-f]+: 2041 1000 lwp v0,0\(at\)
+ [0-9a-f]+: 3023 7fff addiu at,v1,32767
+ [0-9a-f]+: 2041 1000 lwp v0,0\(at\)
+ [0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
+ [0-9a-f]+: 1020 0001 lui at,0x1
+ [0-9a-f]+: 0061 0950 addu at,at,v1
+ [0-9a-f]+: 2041 1fff lwp v0,-1\(at\)
+ [0-9a-f]+: 3060 8000 li v1,-32768
+ [0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
+ [0-9a-f]+: 3060 7fff li v1,32767
+ [0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
+ [0-9a-f]+: 1060 0001 lui v1,0x1
+ [0-9a-f]+: 2043 1fff lwp v0,-1\(v1\)
+ [0-9a-f]+: 0085 1900 lwxs v1,a0\(a1\)
+ [0-9a-f]+: 0040 00fc mfc0 v0,c0_index
+ [0-9a-f]+: 0041 00fc mfc0 v0,c0_random
+ [0-9a-f]+: 0042 00fc mfc0 v0,c0_entrylo0
+ [0-9a-f]+: 0043 00fc mfc0 v0,c0_entrylo1
+ [0-9a-f]+: 0044 00fc mfc0 v0,c0_context
+ [0-9a-f]+: 0045 00fc mfc0 v0,c0_pagemask
+ [0-9a-f]+: 0046 00fc mfc0 v0,c0_wired
+ [0-9a-f]+: 0047 00fc mfc0 v0,c0_hwrena
+ [0-9a-f]+: 0048 00fc mfc0 v0,c0_badvaddr
+ [0-9a-f]+: 0049 00fc mfc0 v0,c0_count
+ [0-9a-f]+: 004a 00fc mfc0 v0,c0_entryhi
+ [0-9a-f]+: 004b 00fc mfc0 v0,c0_compare
+ [0-9a-f]+: 004c 00fc mfc0 v0,c0_status
+ [0-9a-f]+: 004d 00fc mfc0 v0,c0_cause
+ [0-9a-f]+: 004e 00fc mfc0 v0,c0_epc
+ [0-9a-f]+: 004f 00fc mfc0 v0,c0_prid
+ [0-9a-f]+: 0050 00fc mfc0 v0,c0_config
+ [0-9a-f]+: 0051 00fc mfc0 v0,c0_lladdr
+ [0-9a-f]+: 0052 00fc mfc0 v0,c0_watchlo
+ [0-9a-f]+: 0053 00fc mfc0 v0,c0_watchhi
+ [0-9a-f]+: 0054 00fc mfc0 v0,c0_xcontext
+ [0-9a-f]+: 0055 00fc mfc0 v0,\$21
+ [0-9a-f]+: 0056 00fc mfc0 v0,\$22
+ [0-9a-f]+: 0057 00fc mfc0 v0,c0_debug
+ [0-9a-f]+: 0058 00fc mfc0 v0,c0_depc
+ [0-9a-f]+: 0059 00fc mfc0 v0,c0_perfcnt
+ [0-9a-f]+: 005a 00fc mfc0 v0,c0_errctl
+ [0-9a-f]+: 005b 00fc mfc0 v0,c0_cacheerr
+ [0-9a-f]+: 005c 00fc mfc0 v0,c0_taglo
+ [0-9a-f]+: 005d 00fc mfc0 v0,c0_taghi
+ [0-9a-f]+: 005e 00fc mfc0 v0,c0_errorepc
+ [0-9a-f]+: 005f 00fc mfc0 v0,c0_desave
+ [0-9a-f]+: 0040 00fc mfc0 v0,c0_index
+ [0-9a-f]+: 0040 08fc mfc0 v0,c0_mvpcontrol
+ [0-9a-f]+: 0040 10fc mfc0 v0,c0_mvpconf0
+ [0-9a-f]+: 0040 18fc mfc0 v0,c0_mvpconf1
+ [0-9a-f]+: 0040 20fc mfc0 v0,\$0,4
+ [0-9a-f]+: 0040 28fc mfc0 v0,\$0,5
+ [0-9a-f]+: 0040 30fc mfc0 v0,\$0,6
+ [0-9a-f]+: 0040 38fc mfc0 v0,\$0,7
+ [0-9a-f]+: 0041 00fc mfc0 v0,c0_random
+ [0-9a-f]+: 0041 08fc mfc0 v0,c0_vpecontrol
+ [0-9a-f]+: 0041 10fc mfc0 v0,c0_vpeconf0
+ [0-9a-f]+: 0041 18fc mfc0 v0,c0_vpeconf1
+ [0-9a-f]+: 0041 20fc mfc0 v0,c0_yqmask
+ [0-9a-f]+: 0041 28fc mfc0 v0,c0_vpeschedule
+ [0-9a-f]+: 0041 30fc mfc0 v0,c0_vpeschefback
+ [0-9a-f]+: 0041 38fc mfc0 v0,\$1,7
+ [0-9a-f]+: 0042 00fc mfc0 v0,c0_entrylo0
+ [0-9a-f]+: 0042 08fc mfc0 v0,c0_tcstatus
+ [0-9a-f]+: 0042 10fc mfc0 v0,c0_tcbind
+ [0-9a-f]+: 0042 18fc mfc0 v0,c0_tcrestart
+ [0-9a-f]+: 0042 20fc mfc0 v0,c0_tchalt
+ [0-9a-f]+: 0042 28fc mfc0 v0,c0_tccontext
+ [0-9a-f]+: 0042 30fc mfc0 v0,c0_tcschedule
+ [0-9a-f]+: 0042 38fc mfc0 v0,c0_tcschefback
+ [0-9a-f]+: 0040 02fc mtc0 v0,c0_index
+ [0-9a-f]+: 0041 02fc mtc0 v0,c0_random
+ [0-9a-f]+: 0042 02fc mtc0 v0,c0_entrylo0
+ [0-9a-f]+: 0043 02fc mtc0 v0,c0_entrylo1
+ [0-9a-f]+: 0044 02fc mtc0 v0,c0_context
+ [0-9a-f]+: 0045 02fc mtc0 v0,c0_pagemask
+ [0-9a-f]+: 0046 02fc mtc0 v0,c0_wired
+ [0-9a-f]+: 0047 02fc mtc0 v0,c0_hwrena
+ [0-9a-f]+: 0048 02fc mtc0 v0,c0_badvaddr
+ [0-9a-f]+: 0049 02fc mtc0 v0,c0_count
+ [0-9a-f]+: 004a 02fc mtc0 v0,c0_entryhi
+ [0-9a-f]+: 004b 02fc mtc0 v0,c0_compare
+ [0-9a-f]+: 004c 02fc mtc0 v0,c0_status
+ [0-9a-f]+: 004d 02fc mtc0 v0,c0_cause
+ [0-9a-f]+: 004e 02fc mtc0 v0,c0_epc
+ [0-9a-f]+: 004f 02fc mtc0 v0,c0_prid
+ [0-9a-f]+: 0050 02fc mtc0 v0,c0_config
+ [0-9a-f]+: 0051 02fc mtc0 v0,c0_lladdr
+ [0-9a-f]+: 0052 02fc mtc0 v0,c0_watchlo
+ [0-9a-f]+: 0053 02fc mtc0 v0,c0_watchhi
+ [0-9a-f]+: 0054 02fc mtc0 v0,c0_xcontext
+ [0-9a-f]+: 0055 02fc mtc0 v0,\$21
+ [0-9a-f]+: 0056 02fc mtc0 v0,\$22
+ [0-9a-f]+: 0057 02fc mtc0 v0,c0_debug
+ [0-9a-f]+: 0058 02fc mtc0 v0,c0_depc
+ [0-9a-f]+: 0059 02fc mtc0 v0,c0_perfcnt
+ [0-9a-f]+: 005a 02fc mtc0 v0,c0_errctl
+ [0-9a-f]+: 005b 02fc mtc0 v0,c0_cacheerr
+ [0-9a-f]+: 005c 02fc mtc0 v0,c0_taglo
+ [0-9a-f]+: 005d 02fc mtc0 v0,c0_taghi
+ [0-9a-f]+: 005e 02fc mtc0 v0,c0_errorepc
+ [0-9a-f]+: 005f 02fc mtc0 v0,c0_desave
+ [0-9a-f]+: 0040 02fc mtc0 v0,c0_index
+ [0-9a-f]+: 0040 0afc mtc0 v0,c0_mvpcontrol
+ [0-9a-f]+: 0040 12fc mtc0 v0,c0_mvpconf0
+ [0-9a-f]+: 0040 1afc mtc0 v0,c0_mvpconf1
+ [0-9a-f]+: 0040 22fc mtc0 v0,\$0,4
+ [0-9a-f]+: 0040 2afc mtc0 v0,\$0,5
+ [0-9a-f]+: 0040 32fc mtc0 v0,\$0,6
+ [0-9a-f]+: 0040 3afc mtc0 v0,\$0,7
+ [0-9a-f]+: 0041 02fc mtc0 v0,c0_random
+ [0-9a-f]+: 0041 0afc mtc0 v0,c0_vpecontrol
+ [0-9a-f]+: 0041 12fc mtc0 v0,c0_vpeconf0
+ [0-9a-f]+: 0041 1afc mtc0 v0,c0_vpeconf1
+ [0-9a-f]+: 0041 22fc mtc0 v0,c0_yqmask
+ [0-9a-f]+: 0041 2afc mtc0 v0,c0_vpeschedule
+ [0-9a-f]+: 0041 32fc mtc0 v0,c0_vpeschefback
+ [0-9a-f]+: 0041 3afc mtc0 v0,\$1,7
+ [0-9a-f]+: 0042 02fc mtc0 v0,c0_entrylo0
+ [0-9a-f]+: 0042 0afc mtc0 v0,c0_tcstatus
+ [0-9a-f]+: 0042 12fc mtc0 v0,c0_tcbind
+ [0-9a-f]+: 0042 1afc mtc0 v0,c0_tcrestart
+ [0-9a-f]+: 0042 22fc mtc0 v0,c0_tchalt
+ [0-9a-f]+: 0042 2afc mtc0 v0,c0_tccontext
+ [0-9a-f]+: 0042 32fc mtc0 v0,c0_tcschedule
+ [0-9a-f]+: 0042 3afc mtc0 v0,c0_tcschefback
+ [0-9a-f]+: 0083 1018 mul v0,v1,a0
+ [0-9a-f]+: 03fe e818 mul sp,s8,ra
+ [0-9a-f]+: 0082 1018 mul v0,v0,a0
+ [0-9a-f]+: 0082 1018 mul v0,v0,a0
+ [0-9a-f]+: 0060 1190 neg v0,v1
+ [0-9a-f]+: 0040 1190 neg v0,v0
+ [0-9a-f]+: 0040 1190 neg v0,v0
+ [0-9a-f]+: 0060 11d0 negu v0,v1
+ [0-9a-f]+: 0040 11d0 negu v0,v0
+ [0-9a-f]+: 0040 11d0 negu v0,v0
+ [0-9a-f]+: 0060 11d0 negu v0,v1
+ [0-9a-f]+: 0040 11d0 negu v0,v0
+ [0-9a-f]+: 0040 11d0 negu v0,v0
+ [0-9a-f]+: 4520 not v0,v0
+ [0-9a-f]+: 4520 not v0,v0
+ [0-9a-f]+: 4530 not v0,v1
+ [0-9a-f]+: 4540 not v0,a0
+ [0-9a-f]+: 4550 not v0,a1
+ [0-9a-f]+: 4560 not v0,a2
+ [0-9a-f]+: 4570 not v0,a3
+ [0-9a-f]+: 4500 not v0,s0
+ [0-9a-f]+: 4510 not v0,s1
+ [0-9a-f]+: 4590 not v1,s1
+ [0-9a-f]+: 4610 not a0,s1
+[ ]*[0-9a-f]+: 4690 not a1,s1
+[ ]*[0-9a-f]+: 4710 not a2,s1
+[ ]*[0-9a-f]+: 4790 not a3,s1
+[ ]*[0-9a-f]+: 4410 not s0,s1
+[ ]*[0-9a-f]+: 4490 not s1,s1
+[ ]*[0-9a-f]+: 4570 not v0,a3
+[ ]*[0-9a-f]+: 4570 not v0,a3
+[ ]*[0-9a-f]+: 0083 12d0 nor v0,v1,a0
+[ ]*[0-9a-f]+: 03fe ead0 nor sp,s8,ra
+[ ]*[0-9a-f]+: 0082 12d0 nor v0,v0,a0
+[ ]*[0-9a-f]+: 0082 12d0 nor v0,v0,a0
+[ ]*[0-9a-f]+: 5043 8000 ori v0,v1,0x8000
+[ ]*[0-9a-f]+: 0002 12d0 not v0,v0
+[ ]*[0-9a-f]+: 5043 ffff ori v0,v1,0xffff
+[ ]*[0-9a-f]+: 0002 12d0 not v0,v0
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0023 12d0 nor v0,v1,at
+[ ]*[0-9a-f]+: 0c56 move v0,s6
+[ ]*[0-9a-f]+: 0ec2 move s6,v0
+[ ]*[0-9a-f]+: 0c56 move v0,s6
+[ ]*[0-9a-f]+: 0ec2 move s6,v0
+[ ]*[0-9a-f]+: 4529 or v0,v0,v0
+[ ]*[0-9a-f]+: 4539 or v0,v0,v1
+[ ]*[0-9a-f]+: 4549 or v0,v0,a0
+[ ]*[0-9a-f]+: 4559 or v0,v0,a1
+[ ]*[0-9a-f]+: 4569 or v0,v0,a2
+[ ]*[0-9a-f]+: 4579 or v0,v0,a3
+[ ]*[0-9a-f]+: 4509 or v0,v0,s0
+[ ]*[0-9a-f]+: 4519 or v0,v0,s1
+[ ]*[0-9a-f]+: 45a9 or v1,v1,v0
+[ ]*[0-9a-f]+: 4629 or a0,a0,v0
+[ ]*[0-9a-f]+: 46a9 or a1,a1,v0
+[ ]*[0-9a-f]+: 4729 or a2,a2,v0
+[ ]*[0-9a-f]+: 47a9 or a3,a3,v0
+[ ]*[0-9a-f]+: 4429 or s0,s0,v0
+[ ]*[0-9a-f]+: 44a9 or s1,s1,v0
+[ ]*[0-9a-f]+: 4529 or v0,v0,v0
+[ ]*[0-9a-f]+: 4539 or v0,v0,v1
+[ ]*[0-9a-f]+: 4539 or v0,v0,v1
+[ ]*[0-9a-f]+: 0083 1290 or v0,v1,a0
+[ ]*[0-9a-f]+: 03fe ea90 or sp,s8,ra
+[ ]*[0-9a-f]+: 0082 1290 or v0,v0,a0
+[ ]*[0-9a-f]+: 0082 1290 or v0,v0,a0
+[ ]*[0-9a-f]+: 5043 8000 ori v0,v1,0x8000
+[ ]*[0-9a-f]+: 5043 ffff ori v0,v1,0xffff
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0023 1290 or v0,v1,at
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0023 1290 or v0,v1,at
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0023 1290 or v0,v1,at
+[ ]*[0-9a-f]+: 0c64 move v1,a0
+[ ]*[0-9a-f]+: 5064 7fff ori v1,a0,0x7fff
+[ ]*[0-9a-f]+: 5064 ffff ori v1,a0,0xffff
+[ ]*[0-9a-f]+: 5063 ffff ori v1,v1,0xffff
+[ ]*[0-9a-f]+: 5063 ffff ori v1,v1,0xffff
+[ ]*[0-9a-f]+: 0040 01c0 rdhwr v0,hwr_cpunum
+[ ]*[0-9a-f]+: 0041 01c0 rdhwr v0,hwr_synci_step
+[ ]*[0-9a-f]+: 0042 01c0 rdhwr v0,hwr_cc
+[ ]*[0-9a-f]+: 0043 01c0 rdhwr v0,hwr_ccres
+[ ]*[0-9a-f]+: 0044 01c0 rdhwr v0,\$4
+[ ]*[0-9a-f]+: 0045 01c0 rdhwr v0,\$5
+[ ]*[0-9a-f]+: 0046 01c0 rdhwr v0,\$6
+[ ]*[0-9a-f]+: 0047 01c0 rdhwr v0,\$7
+[ ]*[0-9a-f]+: 0048 01c0 rdhwr v0,\$8
+[ ]*[0-9a-f]+: 0049 01c0 rdhwr v0,\$9
+[ ]*[0-9a-f]+: 004a 01c0 rdhwr v0,\$10
+[ ]*[0-9a-f]+: 0043 e17c rdpgpr v0,v1
+[ ]*[0-9a-f]+: 0042 e17c rdpgpr v0,v0
+[ ]*[0-9a-f]+: 0042 e17c rdpgpr v0,v0
+[ ]*[0-9a-f]+: 0080 11d0 negu v0,a0
+[ ]*[0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ ]*[0-9a-f]+: 0080 09d0 negu at,a0
+[ ]*[0-9a-f]+: 0041 10d0 rorv v0,v0,at
+[ ]*[0-9a-f]+: 0060 11d0 negu v0,v1
+[ ]*[0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ ]*[0-9a-f]+: 0040 11d0 negu v0,v0
+[ ]*[0-9a-f]+: 0062 10d0 rorv v0,v1,v0
+[ ]*[0-9a-f]+: 0043 00c0 ror v0,v1,0x0
+[ ]*[0-9a-f]+: 0043 f8c0 ror v0,v1,0x1f
+[ ]*[0-9a-f]+: 0043 08c0 ror v0,v1,0x1
+[ ]*[0-9a-f]+: 0042 08c0 ror v0,v0,0x1
+[ ]*[0-9a-f]+: 0042 08c0 ror v0,v0,0x1
+[ ]*[0-9a-f]+: 0043 00c0 ror v0,v1,0x0
+[ ]*[0-9a-f]+: 0043 08c0 ror v0,v1,0x1
+[ ]*[0-9a-f]+: 0043 f8c0 ror v0,v1,0x1f
+[ ]*[0-9a-f]+: 0042 f8c0 ror v0,v0,0x1f
+[ ]*[0-9a-f]+: 0042 f8c0 ror v0,v0,0x1f
+[ ]*[0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ ]*[0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ ]*[0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ ]*[0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ ]*[0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ ]*[0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ ]*[0-9a-f]+: 0064 10d0 rorv v0,v1,a0
+[ ]*[0-9a-f]+: 0044 10d0 rorv v0,v0,a0
+[ ]*[0-9a-f]+: 8830 sb zero,0\(v1\)
+[ ]*[0-9a-f]+: 8830 sb zero,0\(v1\)
+[ ]*[0-9a-f]+: 8831 sb zero,1\(v1\)
+[ ]*[0-9a-f]+: 8832 sb zero,2\(v1\)
+[ ]*[0-9a-f]+: 8833 sb zero,3\(v1\)
+[ ]*[0-9a-f]+: 8834 sb zero,4\(v1\)
+[ ]*[0-9a-f]+: 8835 sb zero,5\(v1\)
+[ ]*[0-9a-f]+: 8836 sb zero,6\(v1\)
+[ ]*[0-9a-f]+: 8837 sb zero,7\(v1\)
+[ ]*[0-9a-f]+: 8838 sb zero,8\(v1\)
+[ ]*[0-9a-f]+: 8839 sb zero,9\(v1\)
+[ ]*[0-9a-f]+: 883a sb zero,10\(v1\)
+[ ]*[0-9a-f]+: 883b sb zero,11\(v1\)
+[ ]*[0-9a-f]+: 883c sb zero,12\(v1\)
+[ ]*[0-9a-f]+: 883d sb zero,13\(v1\)
+[ ]*[0-9a-f]+: 883e sb zero,14\(v1\)
+[ ]*[0-9a-f]+: 883f sb zero,15\(v1\)
+[ ]*[0-9a-f]+: 893f sb v0,15\(v1\)
+[ ]*[0-9a-f]+: 89bf sb v1,15\(v1\)
+[ ]*[0-9a-f]+: 8a3f sb a0,15\(v1\)
+[ ]*[0-9a-f]+: 8abf sb a1,15\(v1\)
+[ ]*[0-9a-f]+: 8b3f sb a2,15\(v1\)
+[ ]*[0-9a-f]+: 8bbf sb a3,15\(v1\)
+[ ]*[0-9a-f]+: 88bf sb s1,15\(v1\)
+[ ]*[0-9a-f]+: 88cf sb s1,15\(a0\)
+[ ]*[0-9a-f]+: 88df sb s1,15\(a1\)
+[ ]*[0-9a-f]+: 88ef sb s1,15\(a2\)
+[ ]*[0-9a-f]+: 88ff sb s1,15\(a3\)
+[ ]*[0-9a-f]+: 88af sb s1,15\(v0\)
+[ ]*[0-9a-f]+: 888f sb s1,15\(s0\)
+[ ]*[0-9a-f]+: 889f sb s1,15\(s1\)
+[ ]*[0-9a-f]+: 1860 0004 sb v1,4\(zero\)
+[ ]*[0-9a-f]+: 1860 0004 sb v1,4\(zero\)
+[ ]*[0-9a-f]+: 1860 7fff sb v1,32767\(zero\)
+[ ]*[0-9a-f]+: 1860 8000 sb v1,-32768\(zero\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 1861 ffff sb v1,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ ]*[0-9a-f]+: 1860 8000 sb v1,-32768\(zero\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ ]*[0-9a-f]+: 1860 8001 sb v1,-32767\(zero\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ ]*[0-9a-f]+: 1860 ffff sb v1,-1\(zero\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 1861 5678 sb v1,22136\(at\)
+[ ]*[0-9a-f]+: 1864 0000 sb v1,0\(a0\)
+[ ]*[0-9a-f]+: 1864 0000 sb v1,0\(a0\)
+[ ]*[0-9a-f]+: 1864 7fff sb v1,32767\(a0\)
+[ ]*[0-9a-f]+: 1864 8000 sb v1,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 1861 ffff sb v1,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ ]*[0-9a-f]+: 1864 8000 sb v1,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 1861 0001 sb v1,1\(at\)
+[ ]*[0-9a-f]+: 1864 8001 sb v1,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 1861 0000 sb v1,0\(at\)
+[ ]*[0-9a-f]+: 1864 ffff sb v1,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 1861 5678 sb v1,22136\(at\)
+[ ]*[0-9a-f]+: 6060 b004 sc v1,4\(zero\)
+[ ]*[0-9a-f]+: 6060 b004 sc v1,4\(zero\)
+[ ]*[0-9a-f]+: 6060 b0ff sc v1,255\(zero\)
+[ ]*[0-9a-f]+: 6060 b100 sc v1,-256\(zero\)
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 6061 b1ff sc v1,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ ]*[0-9a-f]+: 3020 8001 li at,-32767
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 6060 b1ff sc v1,-1\(zero\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5600 ori at,at,0x5600
+[ ]*[0-9a-f]+: 6061 b078 sc v1,120\(at\)
+[ ]*[0-9a-f]+: 6064 b000 sc v1,0\(a0\)
+[ ]*[0-9a-f]+: 6064 b000 sc v1,0\(a0\)
+[ ]*[0-9a-f]+: 6064 b0ff sc v1,255\(a0\)
+[ ]*[0-9a-f]+: 6064 b100 sc v1,-256\(a0\)
+[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 6061 b1ff sc v1,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 6061 b001 sc v1,1\(at\)
+[ ]*[0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: 6064 b1ff sc v1,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5600 ori at,at,0x5600
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 6061 b078 sc v1,120\(at\)
+[ ]*[0-9a-f]+: 443b sdbbp
+[ ]*[0-9a-f]+: 443b sdbbp
+[ ]*[0-9a-f]+: 447b sdbbp 0x1
+[ ]*[0-9a-f]+: 44bb sdbbp 0x2
+[ ]*[0-9a-f]+: 44fb sdbbp 0x3
+[ ]*[0-9a-f]+: 453b sdbbp 0x4
+[ ]*[0-9a-f]+: 457b sdbbp 0x5
+[ ]*[0-9a-f]+: 45bb sdbbp 0x6
+[ ]*[0-9a-f]+: 45fb sdbbp 0x7
+[ ]*[0-9a-f]+: 463b sdbbp 0x8
+[ ]*[0-9a-f]+: 467b sdbbp 0x9
+[ ]*[0-9a-f]+: 46bb sdbbp 0xa
+[ ]*[0-9a-f]+: 46fb sdbbp 0xb
+[ ]*[0-9a-f]+: 473b sdbbp 0xc
+[ ]*[0-9a-f]+: 477b sdbbp 0xd
+[ ]*[0-9a-f]+: 47bb sdbbp 0xe
+[ ]*[0-9a-f]+: 47fb sdbbp 0xf
+[ ]*[0-9a-f]+: 0000 db7c sdbbp
+[ ]*[0-9a-f]+: 0000 db7c sdbbp
+[ ]*[0-9a-f]+: 0001 db7c sdbbp 0x1
+[ ]*[0-9a-f]+: 0002 db7c sdbbp 0x2
+[ ]*[0-9a-f]+: 00ff db7c sdbbp 0xff
+[ ]*[0-9a-f]+: 0043 2b3c seb v0,v1
+[ ]*[0-9a-f]+: 0042 2b3c seb v0,v0
+[ ]*[0-9a-f]+: 0042 2b3c seb v0,v0
+[ ]*[0-9a-f]+: 0043 3b3c seh v0,v1
+[ ]*[0-9a-f]+: 0042 3b3c seh v0,v0
+[ ]*[0-9a-f]+: 0042 3b3c seh v0,v0
+[ ]*[0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ ]*[0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ ]*[0-9a-f]+: b043 0001 sltiu v0,v1,1
+[ ]*[0-9a-f]+: b044 0001 sltiu v0,a0,1
+[ ]*[0-9a-f]+: b043 0001 sltiu v0,v1,1
+[ ]*[0-9a-f]+: 7043 0001 xori v0,v1,0x1
+[ ]*[0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ ]*[0-9a-f]+: 3043 0001 addiu v0,v1,1
+[ ]*[0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0023 1310 xor v0,v1,at
+[ ]*[0-9a-f]+: b042 0001 sltiu v0,v0,1
+[ ]*[0-9a-f]+: 0083 1350 slt v0,v1,a0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 9043 0000 slti v0,v1,0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 9043 8000 slti v0,v1,-32768
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 9043 0000 slti v0,v1,0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 9043 7fff slti v0,v1,32767
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0083 1390 sltu v0,v1,a0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: b043 8000 sltiu v0,v1,-32768
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: b043 7fff sltiu v0,v1,32767
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0064 1350 slt v0,a0,v1
+[ ]*[0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ ]*[0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 0064 1390 sltu v0,a0,v1
+[ ]*[0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ ]*[0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: a930 sh v0,0\(v1\)
+[ ]*[0-9a-f]+: a930 sh v0,0\(v1\)
+[ ]*[0-9a-f]+: a931 sh v0,2\(v1\)
+[ ]*[0-9a-f]+: a932 sh v0,4\(v1\)
+[ ]*[0-9a-f]+: a933 sh v0,6\(v1\)
+[ ]*[0-9a-f]+: a934 sh v0,8\(v1\)
+[ ]*[0-9a-f]+: a935 sh v0,10\(v1\)
+[ ]*[0-9a-f]+: a936 sh v0,12\(v1\)
+[ ]*[0-9a-f]+: a937 sh v0,14\(v1\)
+[ ]*[0-9a-f]+: a938 sh v0,16\(v1\)
+[ ]*[0-9a-f]+: a939 sh v0,18\(v1\)
+[ ]*[0-9a-f]+: a93a sh v0,20\(v1\)
+[ ]*[0-9a-f]+: a93b sh v0,22\(v1\)
+[ ]*[0-9a-f]+: a93c sh v0,24\(v1\)
+[ ]*[0-9a-f]+: a93d sh v0,26\(v1\)
+[ ]*[0-9a-f]+: a93e sh v0,28\(v1\)
+[ ]*[0-9a-f]+: a93f sh v0,30\(v1\)
+[ ]*[0-9a-f]+: a94f sh v0,30\(a0\)
+[ ]*[0-9a-f]+: a95f sh v0,30\(a1\)
+[ ]*[0-9a-f]+: a96f sh v0,30\(a2\)
+[ ]*[0-9a-f]+: a97f sh v0,30\(a3\)
+[ ]*[0-9a-f]+: a92f sh v0,30\(v0\)
+[ ]*[0-9a-f]+: a90f sh v0,30\(s0\)
+[ ]*[0-9a-f]+: a91f sh v0,30\(s1\)
+[ ]*[0-9a-f]+: a99f sh v1,30\(s1\)
+[ ]*[0-9a-f]+: aa1f sh a0,30\(s1\)
+[ ]*[0-9a-f]+: aa9f sh a1,30\(s1\)
+[ ]*[0-9a-f]+: ab1f sh a2,30\(s1\)
+[ ]*[0-9a-f]+: ab9f sh a3,30\(s1\)
+[ ]*[0-9a-f]+: a89f sh s1,30\(s1\)
+[ ]*[0-9a-f]+: a81f sh zero,30\(s1\)
+[ ]*[0-9a-f]+: 3860 0004 sh v1,4\(zero\)
+[ ]*[0-9a-f]+: 3860 0004 sh v1,4\(zero\)
+[ ]*[0-9a-f]+: 3860 7fff sh v1,32767\(zero\)
+[ ]*[0-9a-f]+: 3860 8000 sh v1,-32768\(zero\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 3861 ffff sh v1,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ ]*[0-9a-f]+: 3860 8000 sh v1,-32768\(zero\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 3861 0001 sh v1,1\(at\)
+[ ]*[0-9a-f]+: 3860 8001 sh v1,-32767\(zero\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ ]*[0-9a-f]+: 3860 ffff sh v1,-1\(zero\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 3861 5678 sh v1,22136\(at\)
+[ ]*[0-9a-f]+: 3864 0000 sh v1,0\(a0\)
+[ ]*[0-9a-f]+: 3864 0000 sh v1,0\(a0\)
+[ ]*[0-9a-f]+: 3864 7fff sh v1,32767\(a0\)
+[ ]*[0-9a-f]+: 3864 8000 sh v1,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 3861 ffff sh v1,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ ]*[0-9a-f]+: 3864 8000 sh v1,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 3861 0001 sh v1,1\(at\)
+[ ]*[0-9a-f]+: 3864 8001 sh v1,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 3861 0000 sh v1,0\(at\)
+[ ]*[0-9a-f]+: 3864 ffff sh v1,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 3861 5678 sh v1,22136\(at\)
+[ ]*[0-9a-f]+: 0064 1350 slt v0,a0,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0044 1350 slt v0,a0,v0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0064 1390 sltu v0,a0,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 0044 1390 sltu v0,a0,v0
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: 2522 sll v0,v0,1
+[ ]*[0-9a-f]+: 2524 sll v0,v0,2
+[ ]*[0-9a-f]+: 2526 sll v0,v0,3
+[ ]*[0-9a-f]+: 2528 sll v0,v0,4
+[ ]*[0-9a-f]+: 252a sll v0,v0,5
+[ ]*[0-9a-f]+: 252c sll v0,v0,6
+[ ]*[0-9a-f]+: 252e sll v0,v0,7
+[ ]*[0-9a-f]+: 2520 sll v0,v0,8
+[ ]*[0-9a-f]+: 2530 sll v0,v1,8
+[ ]*[0-9a-f]+: 2540 sll v0,a0,8
+[ ]*[0-9a-f]+: 2550 sll v0,a1,8
+[ ]*[0-9a-f]+: 2560 sll v0,a2,8
+[ ]*[0-9a-f]+: 2570 sll v0,a3,8
+[ ]*[0-9a-f]+: 2500 sll v0,s0,8
+[ ]*[0-9a-f]+: 2510 sll v0,s1,8
+[ ]*[0-9a-f]+: 25a0 sll v1,v0,8
+[ ]*[0-9a-f]+: 2620 sll a0,v0,8
+[ ]*[0-9a-f]+: 26a0 sll a1,v0,8
+[ ]*[0-9a-f]+: 2720 sll a2,v0,8
+[ ]*[0-9a-f]+: 27a0 sll a3,v0,8
+[ ]*[0-9a-f]+: 2420 sll s0,v0,8
+[ ]*[0-9a-f]+: 24a0 sll s1,v0,8
+[ ]*[0-9a-f]+: 2522 sll v0,v0,1
+[ ]*[0-9a-f]+: 25b2 sll v1,v1,1
+[ ]*[0-9a-f]+: 0064 1010 sllv v0,v1,a0
+[ ]*[0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ ]*[0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ ]*[0-9a-f]+: 0044 1010 sllv v0,v0,a0
+[ ]*[0-9a-f]+: 0044 0000 sll v0,a0,0x0
+[ ]*[0-9a-f]+: 0044 0800 sll v0,a0,0x1
+[ ]*[0-9a-f]+: 0044 f800 sll v0,a0,0x1f
+[ ]*[0-9a-f]+: 0042 f800 sll v0,v0,0x1f
+[ ]*[0-9a-f]+: 0042 f800 sll v0,v0,0x1f
+[ ]*[0-9a-f]+: 0083 1350 slt v0,v1,a0
+[ ]*[0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ ]*[0-9a-f]+: 0082 1350 slt v0,v0,a0
+[ ]*[0-9a-f]+: 9043 0000 slti v0,v1,0
+[ ]*[0-9a-f]+: 9043 8000 slti v0,v1,-32768
+[ ]*[0-9a-f]+: 9043 0000 slti v0,v1,0
+[ ]*[0-9a-f]+: 9043 7fff slti v0,v1,32767
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: 9064 8000 slti v1,a0,-32768
+[ ]*[0-9a-f]+: 9064 0000 slti v1,a0,0
+[ ]*[0-9a-f]+: 9064 7fff slti v1,a0,32767
+[ ]*[0-9a-f]+: 9064 ffff slti v1,a0,-1
+[ ]*[0-9a-f]+: 9063 ffff slti v1,v1,-1
+[ ]*[0-9a-f]+: 9063 ffff slti v1,v1,-1
+[ ]*[0-9a-f]+: b064 8000 sltiu v1,a0,-32768
+[ ]*[0-9a-f]+: b064 0000 sltiu v1,a0,0
+[ ]*[0-9a-f]+: b064 7fff sltiu v1,a0,32767
+[ ]*[0-9a-f]+: b064 ffff sltiu v1,a0,-1
+[ ]*[0-9a-f]+: b063 ffff sltiu v1,v1,-1
+[ ]*[0-9a-f]+: b063 ffff sltiu v1,v1,-1
+[ ]*[0-9a-f]+: 0083 1390 sltu v0,v1,a0
+[ ]*[0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ ]*[0-9a-f]+: 0082 1390 sltu v0,v0,a0
+[ ]*[0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ ]*[0-9a-f]+: b043 8000 sltiu v0,v1,-32768
+[ ]*[0-9a-f]+: b043 0000 sltiu v0,v1,0
+[ ]*[0-9a-f]+: b043 7fff sltiu v0,v1,32767
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
+[ ]*[0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ ]*[0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ ]*[0-9a-f]+: 0080 1390 sltu v0,zero,a0
+[ ]*[0-9a-f]+: 0060 1390 sltu v0,zero,v1
+[ ]*[0-9a-f]+: 0060 1390 sltu v0,zero,v1
+[ ]*[0-9a-f]+: 7043 0001 xori v0,v1,0x1
+[ ]*[0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ ]*[0-9a-f]+: 3043 0001 addiu v0,v1,1
+[ ]*[0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0023 1310 xor v0,v1,at
+[ ]*[0-9a-f]+: 0040 1390 sltu v0,zero,v0
+[ ]*[0-9a-f]+: 0064 1090 srav v0,v1,a0
+[ ]*[0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ ]*[0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ ]*[0-9a-f]+: 0044 1090 srav v0,v0,a0
+[ ]*[0-9a-f]+: 0044 0080 sra v0,a0,0x0
+[ ]*[0-9a-f]+: 0044 0880 sra v0,a0,0x1
+[ ]*[0-9a-f]+: 0044 f880 sra v0,a0,0x1f
+[ ]*[0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ ]*[0-9a-f]+: 0042 f880 sra v0,v0,0x1f
+[ ]*[0-9a-f]+: 0064 1050 srlv v0,v1,a0
+[ ]*[0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ ]*[0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ ]*[0-9a-f]+: 0044 1050 srlv v0,v0,a0
+[ ]*[0-9a-f]+: 0044 0040 srl v0,a0,0x0
+[ ]*[0-9a-f]+: 2543 srl v0,a0,1
+[ ]*[0-9a-f]+: 0044 f840 srl v0,a0,0x1f
+[ ]*[0-9a-f]+: 0042 f840 srl v0,v0,0x1f
+[ ]*[0-9a-f]+: 0042 f840 srl v0,v0,0x1f
+[ ]*[0-9a-f]+: 2523 srl v0,v0,1
+[ ]*[0-9a-f]+: 2525 srl v0,v0,2
+[ ]*[0-9a-f]+: 2527 srl v0,v0,3
+[ ]*[0-9a-f]+: 2529 srl v0,v0,4
+[ ]*[0-9a-f]+: 252b srl v0,v0,5
+[ ]*[0-9a-f]+: 252d srl v0,v0,6
+[ ]*[0-9a-f]+: 252f srl v0,v0,7
+[ ]*[0-9a-f]+: 2521 srl v0,v0,8
+[ ]*[0-9a-f]+: 2531 srl v0,v1,8
+[ ]*[0-9a-f]+: 2541 srl v0,a0,8
+[ ]*[0-9a-f]+: 2551 srl v0,a1,8
+[ ]*[0-9a-f]+: 2561 srl v0,a2,8
+[ ]*[0-9a-f]+: 2571 srl v0,a3,8
+[ ]*[0-9a-f]+: 2501 srl v0,s0,8
+[ ]*[0-9a-f]+: 2511 srl v0,s1,8
+[ ]*[0-9a-f]+: 2521 srl v0,v0,8
+[ ]*[0-9a-f]+: 25a1 srl v1,v0,8
+[ ]*[0-9a-f]+: 2621 srl a0,v0,8
+[ ]*[0-9a-f]+: 26a1 srl a1,v0,8
+[ ]*[0-9a-f]+: 2721 srl a2,v0,8
+[ ]*[0-9a-f]+: 27a1 srl a3,v0,8
+[ ]*[0-9a-f]+: 2421 srl s0,v0,8
+[ ]*[0-9a-f]+: 24a1 srl s1,v0,8
+[ ]*[0-9a-f]+: 25b3 srl v1,v1,1
+[ ]*[0-9a-f]+: 25b3 srl v1,v1,1
+[ ]*[0-9a-f]+: 0083 1190 sub v0,v1,a0
+[ ]*[0-9a-f]+: 03fe e990 sub sp,s8,ra
+[ ]*[0-9a-f]+: 0082 1190 sub v0,v0,a0
+[ ]*[0-9a-f]+: 0082 1190 sub v0,v0,a0
+[ ]*[0-9a-f]+: 05a5 subu v0,v1,v0
+[ ]*[0-9a-f]+: 05b5 subu v0,v1,v1
+[ ]*[0-9a-f]+: 05c5 subu v0,v1,a0
+[ ]*[0-9a-f]+: 05d5 subu v0,v1,a1
+[ ]*[0-9a-f]+: 05e5 subu v0,v1,a2
+[ ]*[0-9a-f]+: 05f5 subu v0,v1,a3
+[ ]*[0-9a-f]+: 0585 subu v0,v1,s0
+[ ]*[0-9a-f]+: 0595 subu v0,v1,s1
+[ ]*[0-9a-f]+: 0515 subu v0,v0,s1
+[ ]*[0-9a-f]+: 0615 subu v0,a0,s1
+[ ]*[0-9a-f]+: 0695 subu v0,a1,s1
+[ ]*[0-9a-f]+: 0715 subu v0,a2,s1
+[ ]*[0-9a-f]+: 0795 subu v0,a3,s1
+[ ]*[0-9a-f]+: 0415 subu v0,s0,s1
+[ ]*[0-9a-f]+: 0495 subu v0,s1,s1
+[ ]*[0-9a-f]+: 0515 subu v0,v0,s1
+[ ]*[0-9a-f]+: 0517 subu v1,v0,s1
+[ ]*[0-9a-f]+: 0519 subu a0,v0,s1
+[ ]*[0-9a-f]+: 051b subu a1,v0,s1
+[ ]*[0-9a-f]+: 051d subu a2,v0,s1
+[ ]*[0-9a-f]+: 051f subu a3,v0,s1
+[ ]*[0-9a-f]+: 0511 subu s0,v0,s1
+[ ]*[0-9a-f]+: 0513 subu s1,v0,s1
+[ ]*[0-9a-f]+: 07af subu a3,a3,v0
+[ ]*[0-9a-f]+: 07af subu a3,a3,v0
+[ ]*[0-9a-f]+: 0083 11d0 subu v0,v1,a0
+[ ]*[0-9a-f]+: 03fe e9d0 subu sp,s8,ra
+[ ]*[0-9a-f]+: 0082 11d0 subu v0,v0,a0
+[ ]*[0-9a-f]+: 0082 11d0 subu v0,v0,a0
+[ ]*[0-9a-f]+: 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: 3042 ffff addiu v0,v0,-1
+[ ]*[0-9a-f]+: 3042 8001 addiu v0,v0,-32767
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0022 11d0 subu v0,v0,at
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0022 11d0 subu v0,v0,at
+[ ]*[0-9a-f]+: e940 sw v0,0\(a0\)
+[ ]*[0-9a-f]+: e940 sw v0,0\(a0\)
+[ ]*[0-9a-f]+: e941 sw v0,4\(a0\)
+[ ]*[0-9a-f]+: e942 sw v0,8\(a0\)
+[ ]*[0-9a-f]+: e943 sw v0,12\(a0\)
+[ ]*[0-9a-f]+: e944 sw v0,16\(a0\)
+[ ]*[0-9a-f]+: e945 sw v0,20\(a0\)
+[ ]*[0-9a-f]+: e946 sw v0,24\(a0\)
+[ ]*[0-9a-f]+: e947 sw v0,28\(a0\)
+[ ]*[0-9a-f]+: e948 sw v0,32\(a0\)
+[ ]*[0-9a-f]+: e949 sw v0,36\(a0\)
+[ ]*[0-9a-f]+: e94a sw v0,40\(a0\)
+[ ]*[0-9a-f]+: e94b sw v0,44\(a0\)
+[ ]*[0-9a-f]+: e94c sw v0,48\(a0\)
+[ ]*[0-9a-f]+: e94d sw v0,52\(a0\)
+[ ]*[0-9a-f]+: e94e sw v0,56\(a0\)
+[ ]*[0-9a-f]+: e94f sw v0,60\(a0\)
+[ ]*[0-9a-f]+: e95f sw v0,60\(a1\)
+[ ]*[0-9a-f]+: e96f sw v0,60\(a2\)
+[ ]*[0-9a-f]+: e97f sw v0,60\(a3\)
+[ ]*[0-9a-f]+: e90f sw v0,60\(s0\)
+[ ]*[0-9a-f]+: e91f sw v0,60\(s1\)
+[ ]*[0-9a-f]+: e92f sw v0,60\(v0\)
+[ ]*[0-9a-f]+: e93f sw v0,60\(v1\)
+[ ]*[0-9a-f]+: e9bf sw v1,60\(v1\)
+[ ]*[0-9a-f]+: ea3f sw a0,60\(v1\)
+[ ]*[0-9a-f]+: eabf sw a1,60\(v1\)
+[ ]*[0-9a-f]+: eb3f sw a2,60\(v1\)
+[ ]*[0-9a-f]+: ebbf sw a3,60\(v1\)
+[ ]*[0-9a-f]+: e8bf sw s1,60\(v1\)
+[ ]*[0-9a-f]+: e83f sw zero,60\(v1\)
+[ ]*[0-9a-f]+: c800 sw zero,0\(sp\)
+[ ]*[0-9a-f]+: c800 sw zero,0\(sp\)
+[ ]*[0-9a-f]+: c801 sw zero,4\(sp\)
+[ ]*[0-9a-f]+: c802 sw zero,8\(sp\)
+[ ]*[0-9a-f]+: c803 sw zero,12\(sp\)
+[ ]*[0-9a-f]+: c804 sw zero,16\(sp\)
+[ ]*[0-9a-f]+: c805 sw zero,20\(sp\)
+[ ]*[0-9a-f]+: c81e sw zero,120\(sp\)
+[ ]*[0-9a-f]+: c81f sw zero,124\(sp\)
+[ ]*[0-9a-f]+: c85f sw v0,124\(sp\)
+[ ]*[0-9a-f]+: ca3f sw s1,124\(sp\)
+[ ]*[0-9a-f]+: c87f sw v1,124\(sp\)
+[ ]*[0-9a-f]+: c89f sw a0,124\(sp\)
+[ ]*[0-9a-f]+: c8bf sw a1,124\(sp\)
+[ ]*[0-9a-f]+: c8df sw a2,124\(sp\)
+[ ]*[0-9a-f]+: c8ff sw a3,124\(sp\)
+[ ]*[0-9a-f]+: cbff sw ra,124\(sp\)
+[ ]*[0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ ]*[0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ ]*[0-9a-f]+: f860 7fff sw v1,32767\(zero\)
+[ ]*[0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ ]*[0-9a-f]+: f860 8001 sw v1,-32767\(zero\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: f860 ffff sw v1,-1\(zero\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ ]*[0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ ]*[0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ ]*[0-9a-f]+: f864 7fff sw v1,32767\(a0\)
+[ ]*[0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ ]*[0-9a-f]+: f864 8001 sw v1,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: f864 ffff sw v1,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ ]*[0-9a-f]+: 44ca swm s0,ra,48\(sp\)
+[ ]*[0-9a-f]+: 45ca swm s0-s1,ra,48\(sp\)
+[ ]*[0-9a-f]+: 45ca swm s0-s1,ra,48\(sp\)
+[ ]*[0-9a-f]+: 46ca swm s0-s2,ra,48\(sp\)
+[ ]*[0-9a-f]+: 46ca swm s0-s2,ra,48\(sp\)
+[ ]*[0-9a-f]+: 47ca swm s0-s3,ra,48\(sp\)
+[ ]*[0-9a-f]+: 47ca swm s0-s3,ra,48\(sp\)
+[ ]*[0-9a-f]+: 440a swm s0,ra,0\(sp\)
+[ ]*[0-9a-f]+: 440a swm s0,ra,0\(sp\)
+[ ]*[0-9a-f]+: 441a swm s0,ra,4\(sp\)
+[ ]*[0-9a-f]+: 442a swm s0,ra,8\(sp\)
+[ ]*[0-9a-f]+: 443a swm s0,ra,12\(sp\)
+[ ]*[0-9a-f]+: 444a swm s0,ra,16\(sp\)
+[ ]*[0-9a-f]+: 445a swm s0,ra,20\(sp\)
+[ ]*[0-9a-f]+: 446a swm s0,ra,24\(sp\)
+[ ]*[0-9a-f]+: 447a swm s0,ra,28\(sp\)
+[ ]*[0-9a-f]+: 448a swm s0,ra,32\(sp\)
+[ ]*[0-9a-f]+: 449a swm s0,ra,36\(sp\)
+[ ]*[0-9a-f]+: 44aa swm s0,ra,40\(sp\)
+[ ]*[0-9a-f]+: 44ba swm s0,ra,44\(sp\)
+[ ]*[0-9a-f]+: 44ca swm s0,ra,48\(sp\)
+[ ]*[0-9a-f]+: 44da swm s0,ra,52\(sp\)
+[ ]*[0-9a-f]+: 44ea swm s0,ra,56\(sp\)
+[ ]*[0-9a-f]+: 44fa swm s0,ra,60\(sp\)
+[ ]*[0-9a-f]+: 2020 d000 swm s0,0\(zero\)
+[ ]*[0-9a-f]+: 2020 d004 swm s0,4\(zero\)
+[ ]*[0-9a-f]+: 2020 d7ff swm s0,2047\(zero\)
+[ ]*[0-9a-f]+: 2020 d800 swm s0,-2048\(zero\)
+[ ]*[0-9a-f]+: 3020 0800 li at,2048
+[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: 3020 f7ff li at,-2049
+[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: 2025 d000 swm s0,0\(a1\)
+[ ]*[0-9a-f]+: 2025 d7ff swm s0,2047\(a1\)
+[ ]*[0-9a-f]+: 2025 d800 swm s0,-2048\(a1\)
+[ ]*[0-9a-f]+: 3025 0800 addiu at,a1,2048
+[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: 3025 f7ff addiu at,a1,-2049
+[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: 2045 d7ff swm s0-s1,2047\(a1\)
+[ ]*[0-9a-f]+: 2065 d7ff swm s0-s2,2047\(a1\)
+[ ]*[0-9a-f]+: 2085 d7ff swm s0-s3,2047\(a1\)
+[ ]*[0-9a-f]+: 20a5 d7ff swm s0-s4,2047\(a1\)
+[ ]*[0-9a-f]+: 20c5 d7ff swm s0-s5,2047\(a1\)
+[ ]*[0-9a-f]+: 20e5 d7ff swm s0-s6,2047\(a1\)
+[ ]*[0-9a-f]+: 2105 d7ff swm s0-s7,2047\(a1\)
+[ ]*[0-9a-f]+: 2125 d7ff swm s0-s7,s8,2047\(a1\)
+[ ]*[0-9a-f]+: 2205 d7ff swm ra,2047\(a1\)
+[ ]*[0-9a-f]+: 2225 d000 swm s0,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2245 d000 swm s0-s1,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2265 d000 swm s0-s2,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2285 d000 swm s0-s3,ra,0\(a1\)
+[ ]*[0-9a-f]+: 22a5 d000 swm s0-s4,ra,0\(a1\)
+[ ]*[0-9a-f]+: 22c5 d000 swm s0-s5,ra,0\(a1\)
+[ ]*[0-9a-f]+: 22e5 d000 swm s0-s6,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2305 d000 swm s0-s7,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2325 d000 swm s0-s7,s8,ra,0\(a1\)
+[ ]*[0-9a-f]+: 303d 8000 addiu at,sp,-32768
+[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: 303d 7fff addiu at,sp,32767
+[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: 203d d000 swm s0,0\(sp\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 03a1 0950 addu at,at,sp
+[ ]*[0-9a-f]+: 2021 dfff swm s0,-1\(at\)
+[ ]*[0-9a-f]+: 2040 9000 swp v0,0\(zero\)
+[ ]*[0-9a-f]+: 2040 9004 swp v0,4\(zero\)
+[ ]*[0-9a-f]+: 2040 97ff swp v0,2047\(zero\)
+[ ]*[0-9a-f]+: 2040 9800 swp v0,-2048\(zero\)
+[ ]*[0-9a-f]+: 3020 0800 li at,2048
+[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: 3020 f7ff li at,-2049
+[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: 205d 9000 swp v0,0\(sp\)
+[ ]*[0-9a-f]+: 205d 9000 swp v0,0\(sp\)
+[ ]*[0-9a-f]+: 2043 97ff swp v0,2047\(v1\)
+[ ]*[0-9a-f]+: 2043 9800 swp v0,-2048\(v1\)
+[ ]*[0-9a-f]+: 3023 0800 addiu at,v1,2048
+[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: 3023 f7ff addiu at,v1,-2049
+[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: 3023 7fff addiu at,v1,32767
+[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: 3023 8000 addiu at,v1,-32768
+[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: 2043 9000 swp v0,0\(v1\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: 2041 9fff swp v0,-1\(at\)
+[ ]*[0-9a-f]+: 0000 6b7c sync
+[ ]*[0-9a-f]+: 0000 6b7c sync
+[ ]*[0-9a-f]+: 0001 6b7c sync 0x1
+[ ]*[0-9a-f]+: 0002 6b7c sync 0x2
+[ ]*[0-9a-f]+: 0003 6b7c sync 0x3
+[ ]*[0-9a-f]+: 0004 6b7c sync_wmb
+[ ]*[0-9a-f]+: 001e 6b7c sync 0x1e
+[ ]*[0-9a-f]+: 001f 6b7c sync 0x1f
+[ ]*[0-9a-f]+: 4180 0000 synci 0\(zero\)
+[ ]*[0-9a-f]+: 4180 0000 synci 0\(zero\)
+[ ]*[0-9a-f]+: 4180 0000 synci 0\(zero\)
+[ ]*[0-9a-f]+: 4180 07ff synci 2047\(zero\)
+[ ]*[0-9a-f]+: 4180 f800 synci -2048\(zero\)
+[ ]*[0-9a-f]+: 4180 0800 synci 2048\(zero\)
+[ ]*[0-9a-f]+: 4180 f7ff synci -2049\(zero\)
+[ ]*[0-9a-f]+: 4180 7fff synci 32767\(zero\)
+[ ]*[0-9a-f]+: 4180 8000 synci -32768\(zero\)
+[ ]*[0-9a-f]+: 4182 0000 synci 0\(v0\)
+[ ]*[0-9a-f]+: 4183 0000 synci 0\(v1\)
+[ ]*[0-9a-f]+: 4183 07ff synci 2047\(v1\)
+[ ]*[0-9a-f]+: 4183 f800 synci -2048\(v1\)
+[ ]*[0-9a-f]+: 4183 0800 synci 2048\(v1\)
+[ ]*[0-9a-f]+: 4183 f7ff synci -2049\(v1\)
+[ ]*[0-9a-f]+: 4183 7fff synci 32767\(v1\)
+[ ]*[0-9a-f]+: 4183 8000 synci -32768\(v1\)
+[ ]*[0-9a-f]+: 0000 8b7c syscall
+[ ]*[0-9a-f]+: 0000 8b7c syscall
+[ ]*[0-9a-f]+: 0001 8b7c syscall 0x1
+[ ]*[0-9a-f]+: 0002 8b7c syscall 0x2
+[ ]*[0-9a-f]+: 00ff 8b7c syscall 0xff
+[ ]*[0-9a-f]+: 0062 003c teq v0,v1
+[ ]*[0-9a-f]+: 0043 003c teq v1,v0
+[ ]*[0-9a-f]+: 0062 003c teq v0,v1
+[ ]*[0-9a-f]+: 0062 103c teq v0,v1,0x1
+[ ]*[0-9a-f]+: 0062 f03c teq v0,v1,0xf
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0022 003c teq v0,at
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0022 003c teq v0,at
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 0022 003c teq v0,at
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0022 003c teq v0,at
+[ ]*[0-9a-f]+: 0062 023c tge v0,v1
+[ ]*[0-9a-f]+: 0043 023c tge v1,v0
+[ ]*[0-9a-f]+: 0062 023c tge v0,v1
+[ ]*[0-9a-f]+: 0062 123c tge v0,v1,0x1
+[ ]*[0-9a-f]+: 0062 f23c tge v0,v1,0xf
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0022 023c tge v0,at
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0022 023c tge v0,at
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 0022 023c tge v0,at
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0022 023c tge v0,at
+[ ]*[0-9a-f]+: 0062 043c tgeu v0,v1
+[ ]*[0-9a-f]+: 0043 043c tgeu v1,v0
+[ ]*[0-9a-f]+: 0062 043c tgeu v0,v1
+[ ]*[0-9a-f]+: 0062 143c tgeu v0,v1,0x1
+[ ]*[0-9a-f]+: 0062 f43c tgeu v0,v1,0xf
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0022 043c tgeu v0,at
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0022 043c tgeu v0,at
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 0022 043c tgeu v0,at
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0022 043c tgeu v0,at
+[ ]*[0-9a-f]+: 0000 037c tlbp
+[ ]*[0-9a-f]+: 0000 137c tlbr
+[ ]*[0-9a-f]+: 0000 237c tlbwi
+[ ]*[0-9a-f]+: 0000 337c tlbwr
+[ ]*[0-9a-f]+: 0062 083c tlt v0,v1
+[ ]*[0-9a-f]+: 0043 083c tlt v1,v0
+[ ]*[0-9a-f]+: 0062 083c tlt v0,v1
+[ ]*[0-9a-f]+: 0062 183c tlt v0,v1,0x1
+[ ]*[0-9a-f]+: 0062 f83c tlt v0,v1,0xf
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0022 083c tlt v0,at
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0022 083c tlt v0,at
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 0022 083c tlt v0,at
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0022 083c tlt v0,at
+[ ]*[0-9a-f]+: 0062 0a3c tltu v0,v1
+[ ]*[0-9a-f]+: 0043 0a3c tltu v1,v0
+[ ]*[0-9a-f]+: 0062 0a3c tltu v0,v1
+[ ]*[0-9a-f]+: 0062 1a3c tltu v0,v1,0x1
+[ ]*[0-9a-f]+: 0062 fa3c tltu v0,v1,0xf
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: 3020 ffff li at,-1
+[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: 0062 0c3c tne v0,v1
+[ ]*[0-9a-f]+: 0043 0c3c tne v1,v0
+[ ]*[0-9a-f]+: 0062 0c3c tne v0,v1
+[ ]*[0-9a-f]+: 0062 1c3c tne v0,v1,0x1
+[ ]*[0-9a-f]+: 0062 fc3c tne v0,v1,0xf
+[ ]*[0-9a-f]+: 3020 0000 li at,0
+[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: 3020 ffff li at,-1
+[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: 0000 937c wait
+[ ]*[0-9a-f]+: 0000 937c wait
+[ ]*[0-9a-f]+: 0001 937c wait 0x1
+[ ]*[0-9a-f]+: 00ff 937c wait 0xff
+[ ]*[0-9a-f]+: 0043 f17c wrpgpr v0,v1
+[ ]*[0-9a-f]+: 0044 f17c wrpgpr v0,a0
+[ ]*[0-9a-f]+: 0042 f17c wrpgpr v0,v0
+[ ]*[0-9a-f]+: 0042 f17c wrpgpr v0,v0
+[ ]*[0-9a-f]+: 0043 7b3c wsbh v0,v1
+[ ]*[0-9a-f]+: 0044 7b3c wsbh v0,a0
+[ ]*[0-9a-f]+: 0042 7b3c wsbh v0,v0
+[ ]*[0-9a-f]+: 0042 7b3c wsbh v0,v0
+[ ]*[0-9a-f]+: 4528 xor v0,v0,v0
+[ ]*[0-9a-f]+: 4538 xor v0,v0,v1
+[ ]*[0-9a-f]+: 4548 xor v0,v0,a0
+[ ]*[0-9a-f]+: 4558 xor v0,v0,a1
+[ ]*[0-9a-f]+: 4568 xor v0,v0,a2
+[ ]*[0-9a-f]+: 4578 xor v0,v0,a3
+[ ]*[0-9a-f]+: 4508 xor v0,v0,s0
+[ ]*[0-9a-f]+: 4518 xor v0,v0,s1
+[ ]*[0-9a-f]+: 4598 xor v1,v1,s1
+[ ]*[0-9a-f]+: 4618 xor a0,a0,s1
+[ ]*[0-9a-f]+: 4698 xor a1,a1,s1
+[ ]*[0-9a-f]+: 4718 xor a2,a2,s1
+[ ]*[0-9a-f]+: 4798 xor a3,a3,s1
+[ ]*[0-9a-f]+: 4418 xor s0,s0,s1
+[ ]*[0-9a-f]+: 4498 xor s1,s1,s1
+[ ]*[0-9a-f]+: 4538 xor v0,v0,v1
+[ ]*[0-9a-f]+: 4538 xor v0,v0,v1
+[ ]*[0-9a-f]+: 4538 xor v0,v0,v1
+[ ]*[0-9a-f]+: 0083 1310 xor v0,v1,a0
+[ ]*[0-9a-f]+: 03fe eb10 xor sp,s8,ra
+[ ]*[0-9a-f]+: 0082 1310 xor v0,v0,a0
+[ ]*[0-9a-f]+: 0082 1310 xor v0,v0,a0
+[ ]*[0-9a-f]+: 7043 8000 xori v0,v1,0x8000
+[ ]*[0-9a-f]+: 7043 ffff xori v0,v1,0xffff
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0023 1310 xor v0,v1,at
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 0023 1310 xor v0,v1,at
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: 0023 1310 xor v0,v1,at
+[ ]*[0-9a-f]+: 7064 0000 xori v1,a0,0x0
+[ ]*[0-9a-f]+: 7064 7fff xori v1,a0,0x7fff
+[ ]*[0-9a-f]+: 7064 ffff xori v1,a0,0xffff
+[ ]*[0-9a-f]+: 7063 ffff xori v1,v1,0xffff
+[ ]*[0-9a-f]+: 7063 ffff xori v1,v1,0xffff
+[ ]*[0-9a-f]+: 6d01 addiu v0,sp,0
+[ ]*[0-9a-f]+: 6d03 addiu v0,sp,4
+[ ]*[0-9a-f]+: 6d05 addiu v0,sp,8
+[ ]*[0-9a-f]+: 6d07 addiu v0,sp,12
+[ ]*[0-9a-f]+: 6d09 addiu v0,sp,16
+[ ]*[0-9a-f]+: 6d7f addiu v0,sp,252
+[ ]*[0-9a-f]+: 6dff addiu v1,sp,252
+[ ]*[0-9a-f]+: 6e7f addiu a0,sp,252
+[ ]*[0-9a-f]+: 6eff addiu a1,sp,252
+[ ]*[0-9a-f]+: 6f7f addiu a2,sp,252
+[ ]*[0-9a-f]+: 6fff addiu a3,sp,252
+[ ]*[0-9a-f]+: 6c7f addiu s0,sp,252
+[ ]*[0-9a-f]+: 6cff addiu s1,sp,252
+[ ]*[0-9a-f]+: 6d2e addiu v0,v0,-1
+[ ]*[0-9a-f]+: 6d3e addiu v0,v1,-1
+[ ]*[0-9a-f]+: 6d4e addiu v0,a0,-1
+[ ]*[0-9a-f]+: 6d5e addiu v0,a1,-1
+[ ]*[0-9a-f]+: 6d6e addiu v0,a2,-1
+[ ]*[0-9a-f]+: 6d7e addiu v0,a3,-1
+[ ]*[0-9a-f]+: 6d0e addiu v0,s0,-1
+[ ]*[0-9a-f]+: 6d1e addiu v0,s1,-1
+[ ]*[0-9a-f]+: 6d9e addiu v1,s1,-1
+[ ]*[0-9a-f]+: 6e1e addiu a0,s1,-1
+[ ]*[0-9a-f]+: 6e9e addiu a1,s1,-1
+[ ]*[0-9a-f]+: 6f1e addiu a2,s1,-1
+[ ]*[0-9a-f]+: 6f9e addiu a3,s1,-1
+[ ]*[0-9a-f]+: 6c1e addiu s0,s1,-1
+[ ]*[0-9a-f]+: 6c9e addiu s1,s1,-1
+[ ]*[0-9a-f]+: 6c90 addiu s1,s1,1
+[ ]*[0-9a-f]+: 6c92 addiu s1,s1,4
+[ ]*[0-9a-f]+: 6c94 addiu s1,s1,8
+[ ]*[0-9a-f]+: 6c96 addiu s1,s1,12
+[ ]*[0-9a-f]+: 6c98 addiu s1,s1,16
+[ ]*[0-9a-f]+: 6c9a addiu s1,s1,20
+[ ]*[0-9a-f]+: 6c9c addiu s1,s1,24
+[ ]*[0-9a-f]+: 4c05 addiu sp,sp,8
+[ ]*[0-9a-f]+: 4c07 addiu sp,sp,12
+[ ]*[0-9a-f]+: 4dfd addiu sp,sp,1016
+[ ]*[0-9a-f]+: 4dff addiu sp,sp,1020
+[ ]*[0-9a-f]+: 4c01 addiu sp,sp,1024
+[ ]*[0-9a-f]+: 4c03 addiu sp,sp,1028
+[ ]*[0-9a-f]+: 4ffb addiu sp,sp,-12
+[ ]*[0-9a-f]+: 4ff9 addiu sp,sp,-16
+[ ]*[0-9a-f]+: 4e03 addiu sp,sp,-1020
+[ ]*[0-9a-f]+: 4e01 addiu sp,sp,-1024
+[ ]*[0-9a-f]+: 4fff addiu sp,sp,-1028
+[ ]*[0-9a-f]+: 4ffd addiu sp,sp,-1032
+[ ]*[0-9a-f]+: 4c00 addiu zero,zero,0
+[ ]*[0-9a-f]+: 4c40 addiu v0,v0,0
+[ ]*[0-9a-f]+: 4c60 addiu v1,v1,0
+[ ]*[0-9a-f]+: 4fc0 addiu s8,s8,0
+[ ]*[0-9a-f]+: 4fe0 addiu ra,ra,0
+[ ]*[0-9a-f]+: 4fe2 addiu ra,ra,1
+[ ]*[0-9a-f]+: 4fe4 addiu ra,ra,2
+[ ]*[0-9a-f]+: 4fe6 addiu ra,ra,3
+[ ]*[0-9a-f]+: 4fee addiu ra,ra,7
+[ ]*[0-9a-f]+: 4ff4 addiu ra,ra,-6
+[ ]*[0-9a-f]+: 4ff2 addiu ra,ra,-7
+[ ]*[0-9a-f]+: 4ff0 addiu ra,ra,-8
+[ ]*[0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ ]*[0-9a-f]+: f880 0008 sw a0,8\(zero\)
+[ ]*[0-9a-f]+: f860 0004 sw v1,4\(zero\)
+[ ]*[0-9a-f]+: f880 0008 sw a0,8\(zero\)
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: f880 8004 sw a0,-32764\(zero\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ ]*[0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: f880 8004 sw a0,-32764\(zero\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ ]*[0-9a-f]+: f881 0005 sw a0,5\(at\)
+[ ]*[0-9a-f]+: f860 8001 sw v1,-32767\(zero\)
+[ ]*[0-9a-f]+: f880 8005 sw a0,-32763\(zero\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: f860 ffff sw v1,-1\(zero\)
+[ ]*[0-9a-f]+: f880 0003 sw a0,3\(zero\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ ]*[0-9a-f]+: f881 567c sw a0,22140\(at\)
+[ ]*[0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ ]*[0-9a-f]+: f884 0004 sw a0,4\(a0\)
+[ ]*[0-9a-f]+: f864 0000 sw v1,0\(a0\)
+[ ]*[0-9a-f]+: f884 0004 sw a0,4\(a0\)
+[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: f884 8004 sw a0,-32764\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: f861 ffff sw v1,-1\(at\)
+[ ]*[0-9a-f]+: f881 0003 sw a0,3\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: f884 8004 sw a0,-32764\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: f861 0001 sw v1,1\(at\)
+[ ]*[0-9a-f]+: f881 0005 sw a0,5\(at\)
+[ ]*[0-9a-f]+: f864 8001 sw v1,-32767\(a0\)
+[ ]*[0-9a-f]+: f884 8005 sw a0,-32763\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: f864 ffff sw v1,-1\(a0\)
+[ ]*[0-9a-f]+: f884 0003 sw a0,3\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: f861 5678 sw v1,22136\(at\)
+[ ]*[0-9a-f]+: f881 567c sw a0,22140\(at\)
+[ ]*[0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ ]*[0-9a-f]+: fc80 0008 lw a0,8\(zero\)
+[ ]*[0-9a-f]+: fc60 0004 lw v1,4\(zero\)
+[ ]*[0-9a-f]+: fc80 0008 lw a0,8\(zero\)
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: fc80 8004 lw a0,-32764\(zero\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ ]*[0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: fc80 8004 lw a0,-32764\(zero\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: fc61 0001 lw v1,1\(at\)
+[ ]*[0-9a-f]+: fc81 0005 lw a0,5\(at\)
+[ ]*[0-9a-f]+: fc60 8001 lw v1,-32767\(zero\)
+[ ]*[0-9a-f]+: fc80 8005 lw a0,-32763\(zero\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: fc60 ffff lw v1,-1\(zero\)
+[ ]*[0-9a-f]+: fc80 0003 lw a0,3\(zero\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: fc61 5678 lw v1,22136\(at\)
+[ ]*[0-9a-f]+: fc81 567c lw a0,22140\(at\)
+[ ]*[0-9a-f]+: fc64 0000 lw v1,0\(a0\)
+[ ]*[0-9a-f]+: fc84 0004 lw a0,4\(a0\)
+[ ]*[0-9a-f]+: fc64 0000 lw v1,0\(a0\)
+[ ]*[0-9a-f]+: fc84 0004 lw a0,4\(a0\)
+[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: fc84 8004 lw a0,-32764\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: fc61 ffff lw v1,-1\(at\)
+[ ]*[0-9a-f]+: fc81 0003 lw a0,3\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: fc84 8004 lw a0,-32764\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: fc61 0001 lw v1,1\(at\)
+[ ]*[0-9a-f]+: fc81 0005 lw a0,5\(at\)
+[ ]*[0-9a-f]+: fc64 8001 lw v1,-32767\(a0\)
+[ ]*[0-9a-f]+: fc84 8005 lw a0,-32763\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: fc64 ffff lw v1,-1\(a0\)
+[ ]*[0-9a-f]+: fc84 0003 lw a0,3\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: fc61 5678 lw v1,22136\(at\)
+[ ]*[0-9a-f]+: fc81 567c lw a0,22140\(at\)
+[ ]*[0-9a-f]+: 4413 jrcaddiusp 0
+[ ]*[0-9a-f]+: 4433 jrcaddiusp 4
+[ ]*[0-9a-f]+: 4453 jrcaddiusp 8
+[ ]*[0-9a-f]+: 4473 jrcaddiusp 12
+[ ]*[0-9a-f]+: 4493 jrcaddiusp 16
+[ ]*[0-9a-f]+: 44b3 jrcaddiusp 20
+[ ]*[0-9a-f]+: 44d3 jrcaddiusp 24
+[ ]*[0-9a-f]+: 44f3 jrcaddiusp 28
+[ ]*[0-9a-f]+: 4513 jrcaddiusp 32
+[ ]*[0-9a-f]+: 4533 jrcaddiusp 36
+[ ]*[0-9a-f]+: 4553 jrcaddiusp 40
+[ ]*[0-9a-f]+: 47d3 jrcaddiusp 120
+[ ]*[0-9a-f]+: 47f3 jrcaddiusp 124
+[ ]*[0-9a-f]+: 2060 2000 ldc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: 2060 2000 ldc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: 2060 2004 ldc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: 2060 2004 ldc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: 2064 2000 ldc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: 2064 2000 ldc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 27ff ldc2 \$3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 2001 ldc2 \$3,1\(at\)
+[ ]*[0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 2064 27ff ldc2 \$3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5800 ori at,at,0x5800
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 2678 ldc2 \$3,-392\(at\)
+[ ]*[0-9a-f]+: 2060 0000 lwc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: 2060 0000 lwc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: 2060 0004 lwc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: 2060 0004 lwc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: 2064 0000 lwc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: 2064 0000 lwc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 07ff lwc2 \$3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 0001 lwc2 \$3,1\(at\)
+[ ]*[0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 2064 07ff lwc2 \$3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5800 ori at,at,0x5800
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 0678 lwc2 \$3,-392\(at\)
+[ ]*[0-9a-f]+: 00a0 4d3c mfc2 a1,\$0
+[ ]*[0-9a-f]+: 00a1 4d3c mfc2 a1,\$1
+[ ]*[0-9a-f]+: 00a2 4d3c mfc2 a1,\$2
+[ ]*[0-9a-f]+: 00a3 4d3c mfc2 a1,\$3
+[ ]*[0-9a-f]+: 00a4 4d3c mfc2 a1,\$4
+[ ]*[0-9a-f]+: 00a5 4d3c mfc2 a1,\$5
+[ ]*[0-9a-f]+: 00a6 4d3c mfc2 a1,\$6
+[ ]*[0-9a-f]+: 00a7 4d3c mfc2 a1,\$7
+[ ]*[0-9a-f]+: 00a8 4d3c mfc2 a1,\$8
+[ ]*[0-9a-f]+: 00a9 4d3c mfc2 a1,\$9
+[ ]*[0-9a-f]+: 00aa 4d3c mfc2 a1,\$10
+[ ]*[0-9a-f]+: 00ab 4d3c mfc2 a1,\$11
+[ ]*[0-9a-f]+: 00ac 4d3c mfc2 a1,\$12
+[ ]*[0-9a-f]+: 00ad 4d3c mfc2 a1,\$13
+[ ]*[0-9a-f]+: 00ae 4d3c mfc2 a1,\$14
+[ ]*[0-9a-f]+: 00af 4d3c mfc2 a1,\$15
+[ ]*[0-9a-f]+: 00b0 4d3c mfc2 a1,\$16
+[ ]*[0-9a-f]+: 00b1 4d3c mfc2 a1,\$17
+[ ]*[0-9a-f]+: 00b2 4d3c mfc2 a1,\$18
+[ ]*[0-9a-f]+: 00b3 4d3c mfc2 a1,\$19
+[ ]*[0-9a-f]+: 00b4 4d3c mfc2 a1,\$20
+[ ]*[0-9a-f]+: 00b5 4d3c mfc2 a1,\$21
+[ ]*[0-9a-f]+: 00b6 4d3c mfc2 a1,\$22
+[ ]*[0-9a-f]+: 00b7 4d3c mfc2 a1,\$23
+[ ]*[0-9a-f]+: 00b8 4d3c mfc2 a1,\$24
+[ ]*[0-9a-f]+: 00b9 4d3c mfc2 a1,\$25
+[ ]*[0-9a-f]+: 00ba 4d3c mfc2 a1,\$26
+[ ]*[0-9a-f]+: 00bb 4d3c mfc2 a1,\$27
+[ ]*[0-9a-f]+: 00bc 4d3c mfc2 a1,\$28
+[ ]*[0-9a-f]+: 00bd 4d3c mfc2 a1,\$29
+[ ]*[0-9a-f]+: 00be 4d3c mfc2 a1,\$30
+[ ]*[0-9a-f]+: 00bf 4d3c mfc2 a1,\$31
+[ ]*[0-9a-f]+: 00a0 8d3c mfhc2 a1,\$0
+[ ]*[0-9a-f]+: 00a1 8d3c mfhc2 a1,\$1
+[ ]*[0-9a-f]+: 00a2 8d3c mfhc2 a1,\$2
+[ ]*[0-9a-f]+: 00a3 8d3c mfhc2 a1,\$3
+[ ]*[0-9a-f]+: 00a4 8d3c mfhc2 a1,\$4
+[ ]*[0-9a-f]+: 00a5 8d3c mfhc2 a1,\$5
+[ ]*[0-9a-f]+: 00a6 8d3c mfhc2 a1,\$6
+[ ]*[0-9a-f]+: 00a7 8d3c mfhc2 a1,\$7
+[ ]*[0-9a-f]+: 00a8 8d3c mfhc2 a1,\$8
+[ ]*[0-9a-f]+: 00a9 8d3c mfhc2 a1,\$9
+[ ]*[0-9a-f]+: 00aa 8d3c mfhc2 a1,\$10
+[ ]*[0-9a-f]+: 00ab 8d3c mfhc2 a1,\$11
+[ ]*[0-9a-f]+: 00ac 8d3c mfhc2 a1,\$12
+[ ]*[0-9a-f]+: 00ad 8d3c mfhc2 a1,\$13
+[ ]*[0-9a-f]+: 00ae 8d3c mfhc2 a1,\$14
+[ ]*[0-9a-f]+: 00af 8d3c mfhc2 a1,\$15
+[ ]*[0-9a-f]+: 00b0 8d3c mfhc2 a1,\$16
+[ ]*[0-9a-f]+: 00b1 8d3c mfhc2 a1,\$17
+[ ]*[0-9a-f]+: 00b2 8d3c mfhc2 a1,\$18
+[ ]*[0-9a-f]+: 00b3 8d3c mfhc2 a1,\$19
+[ ]*[0-9a-f]+: 00b4 8d3c mfhc2 a1,\$20
+[ ]*[0-9a-f]+: 00b5 8d3c mfhc2 a1,\$21
+[ ]*[0-9a-f]+: 00b6 8d3c mfhc2 a1,\$22
+[ ]*[0-9a-f]+: 00b7 8d3c mfhc2 a1,\$23
+[ ]*[0-9a-f]+: 00b8 8d3c mfhc2 a1,\$24
+[ ]*[0-9a-f]+: 00b9 8d3c mfhc2 a1,\$25
+[ ]*[0-9a-f]+: 00ba 8d3c mfhc2 a1,\$26
+[ ]*[0-9a-f]+: 00bb 8d3c mfhc2 a1,\$27
+[ ]*[0-9a-f]+: 00bc 8d3c mfhc2 a1,\$28
+[ ]*[0-9a-f]+: 00bd 8d3c mfhc2 a1,\$29
+[ ]*[0-9a-f]+: 00be 8d3c mfhc2 a1,\$30
+[ ]*[0-9a-f]+: 00bf 8d3c mfhc2 a1,\$31
+[ ]*[0-9a-f]+: 00a0 5d3c mtc2 a1,\$0
+[ ]*[0-9a-f]+: 00a1 5d3c mtc2 a1,\$1
+[ ]*[0-9a-f]+: 00a2 5d3c mtc2 a1,\$2
+[ ]*[0-9a-f]+: 00a3 5d3c mtc2 a1,\$3
+[ ]*[0-9a-f]+: 00a4 5d3c mtc2 a1,\$4
+[ ]*[0-9a-f]+: 00a5 5d3c mtc2 a1,\$5
+[ ]*[0-9a-f]+: 00a6 5d3c mtc2 a1,\$6
+[ ]*[0-9a-f]+: 00a7 5d3c mtc2 a1,\$7
+[ ]*[0-9a-f]+: 00a8 5d3c mtc2 a1,\$8
+[ ]*[0-9a-f]+: 00a9 5d3c mtc2 a1,\$9
+[ ]*[0-9a-f]+: 00aa 5d3c mtc2 a1,\$10
+[ ]*[0-9a-f]+: 00ab 5d3c mtc2 a1,\$11
+[ ]*[0-9a-f]+: 00ac 5d3c mtc2 a1,\$12
+[ ]*[0-9a-f]+: 00ad 5d3c mtc2 a1,\$13
+[ ]*[0-9a-f]+: 00ae 5d3c mtc2 a1,\$14
+[ ]*[0-9a-f]+: 00af 5d3c mtc2 a1,\$15
+[ ]*[0-9a-f]+: 00b0 5d3c mtc2 a1,\$16
+[ ]*[0-9a-f]+: 00b1 5d3c mtc2 a1,\$17
+[ ]*[0-9a-f]+: 00b2 5d3c mtc2 a1,\$18
+[ ]*[0-9a-f]+: 00b3 5d3c mtc2 a1,\$19
+[ ]*[0-9a-f]+: 00b4 5d3c mtc2 a1,\$20
+[ ]*[0-9a-f]+: 00b5 5d3c mtc2 a1,\$21
+[ ]*[0-9a-f]+: 00b6 5d3c mtc2 a1,\$22
+[ ]*[0-9a-f]+: 00b7 5d3c mtc2 a1,\$23
+[ ]*[0-9a-f]+: 00b8 5d3c mtc2 a1,\$24
+[ ]*[0-9a-f]+: 00b9 5d3c mtc2 a1,\$25
+[ ]*[0-9a-f]+: 00ba 5d3c mtc2 a1,\$26
+[ ]*[0-9a-f]+: 00bb 5d3c mtc2 a1,\$27
+[ ]*[0-9a-f]+: 00bc 5d3c mtc2 a1,\$28
+[ ]*[0-9a-f]+: 00bd 5d3c mtc2 a1,\$29
+[ ]*[0-9a-f]+: 00be 5d3c mtc2 a1,\$30
+[ ]*[0-9a-f]+: 00bf 5d3c mtc2 a1,\$31
+[ ]*[0-9a-f]+: 00a0 9d3c mthc2 a1,\$0
+[ ]*[0-9a-f]+: 00a1 9d3c mthc2 a1,\$1
+[ ]*[0-9a-f]+: 00a2 9d3c mthc2 a1,\$2
+[ ]*[0-9a-f]+: 00a3 9d3c mthc2 a1,\$3
+[ ]*[0-9a-f]+: 00a4 9d3c mthc2 a1,\$4
+[ ]*[0-9a-f]+: 00a5 9d3c mthc2 a1,\$5
+[ ]*[0-9a-f]+: 00a6 9d3c mthc2 a1,\$6
+[ ]*[0-9a-f]+: 00a7 9d3c mthc2 a1,\$7
+[ ]*[0-9a-f]+: 00a8 9d3c mthc2 a1,\$8
+[ ]*[0-9a-f]+: 00a9 9d3c mthc2 a1,\$9
+[ ]*[0-9a-f]+: 00aa 9d3c mthc2 a1,\$10
+[ ]*[0-9a-f]+: 00ab 9d3c mthc2 a1,\$11
+[ ]*[0-9a-f]+: 00ac 9d3c mthc2 a1,\$12
+[ ]*[0-9a-f]+: 00ad 9d3c mthc2 a1,\$13
+[ ]*[0-9a-f]+: 00ae 9d3c mthc2 a1,\$14
+[ ]*[0-9a-f]+: 00af 9d3c mthc2 a1,\$15
+[ ]*[0-9a-f]+: 00b0 9d3c mthc2 a1,\$16
+[ ]*[0-9a-f]+: 00b1 9d3c mthc2 a1,\$17
+[ ]*[0-9a-f]+: 00b2 9d3c mthc2 a1,\$18
+[ ]*[0-9a-f]+: 00b3 9d3c mthc2 a1,\$19
+[ ]*[0-9a-f]+: 00b4 9d3c mthc2 a1,\$20
+[ ]*[0-9a-f]+: 00b5 9d3c mthc2 a1,\$21
+[ ]*[0-9a-f]+: 00b6 9d3c mthc2 a1,\$22
+[ ]*[0-9a-f]+: 00b7 9d3c mthc2 a1,\$23
+[ ]*[0-9a-f]+: 00b8 9d3c mthc2 a1,\$24
+[ ]*[0-9a-f]+: 00b9 9d3c mthc2 a1,\$25
+[ ]*[0-9a-f]+: 00ba 9d3c mthc2 a1,\$26
+[ ]*[0-9a-f]+: 00bb 9d3c mthc2 a1,\$27
+[ ]*[0-9a-f]+: 00bc 9d3c mthc2 a1,\$28
+[ ]*[0-9a-f]+: 00bd 9d3c mthc2 a1,\$29
+[ ]*[0-9a-f]+: 00be 9d3c mthc2 a1,\$30
+[ ]*[0-9a-f]+: 00bf 9d3c mthc2 a1,\$31
+[ ]*[0-9a-f]+: 2060 a000 sdc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: 2060 a000 sdc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: 2060 a004 sdc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: 2060 a004 sdc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: 2064 a000 sdc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: 2064 a000 sdc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 a7ff sdc2 \$3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 a001 sdc2 \$3,1\(at\)
+[ ]*[0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 2064 a7ff sdc2 \$3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5800 ori at,at,0x5800
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 a678 sdc2 \$3,-392\(at\)
+[ ]*[0-9a-f]+: 2060 8000 swc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: 2060 8000 swc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: 2060 8004 swc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: 2060 8004 swc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: 2064 8000 swc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: 2064 8000 swc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 87ff swc2 \$3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 8001 swc2 \$3,1\(at\)
+[ ]*[0-9a-f]+: 3024 8001 addiu at,a0,-32767
+[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: 2064 87ff swc2 \$3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5800 ori at,at,0x5800
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 2061 8678 swc2 \$3,-392\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2041 1000 lwp v0,0\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: 3043 0000 addiu v0,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 6042 3000 ll v0,0\(v0\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 6041 b000 sc v0,0\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2021 5000 lwm s0,0\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2201 0000 lwc2 \$16,0\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2201 8000 swc2 \$16,0\(at\)
+[ ]*[0-9a-f]+: 03ff db7c sdbbp 0x3ff
+[ ]*[0-9a-f]+: 03ff 937c wait 0x3ff
+[ ]*[0-9a-f]+: 03ff 8b7c syscall 0x3ff
+[ ]*[0-9a-f]+: 03ff fffa cop2 0x7fffff
+
+[ 0-9a-f]+ <fp_test>:
+[ ]*[0-9a-f]+: 5401 037b abs.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 037b abs.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 037b abs.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5442 037b abs.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 237b abs.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 237b abs.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 237b abs.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5442 237b abs.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5441 0030 add.s \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: 57fe e830 add.s \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: 57dd e830 add.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 57dd e830 add.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 5441 0130 add.d \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: 57fe e930 add.d \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: 57dd e930 add.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 57dd e930 add.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 5401 533b ceil.l.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 533b ceil.l.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 533b ceil.l.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 133b ceil.l.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 133b ceil.l.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 133b ceil.l.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 5b3b ceil.w.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 5b3b ceil.w.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 5b3b ceil.w.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 1b3b ceil.w.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 1b3b ceil.w.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 1b3b ceil.w.s \$f2,\$f2
+[ ]*[0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ ]*[0-9a-f]+: 54a1 103b cfc1 a1,\$1
+[ ]*[0-9a-f]+: 54a2 103b cfc1 a1,\$2
+[ ]*[0-9a-f]+: 54a3 103b cfc1 a1,\$3
+[ ]*[0-9a-f]+: 54a4 103b cfc1 a1,\$4
+[ ]*[0-9a-f]+: 54a5 103b cfc1 a1,\$5
+[ ]*[0-9a-f]+: 54a6 103b cfc1 a1,\$6
+[ ]*[0-9a-f]+: 54a7 103b cfc1 a1,\$7
+[ ]*[0-9a-f]+: 54a8 103b cfc1 a1,\$8
+[ ]*[0-9a-f]+: 54a9 103b cfc1 a1,\$9
+[ ]*[0-9a-f]+: 54aa 103b cfc1 a1,\$10
+[ ]*[0-9a-f]+: 54ab 103b cfc1 a1,\$11
+[ ]*[0-9a-f]+: 54ac 103b cfc1 a1,\$12
+[ ]*[0-9a-f]+: 54ad 103b cfc1 a1,\$13
+[ ]*[0-9a-f]+: 54ae 103b cfc1 a1,\$14
+[ ]*[0-9a-f]+: 54af 103b cfc1 a1,\$15
+[ ]*[0-9a-f]+: 54b0 103b cfc1 a1,\$16
+[ ]*[0-9a-f]+: 54b1 103b cfc1 a1,\$17
+[ ]*[0-9a-f]+: 54b2 103b cfc1 a1,\$18
+[ ]*[0-9a-f]+: 54b3 103b cfc1 a1,\$19
+[ ]*[0-9a-f]+: 54b4 103b cfc1 a1,\$20
+[ ]*[0-9a-f]+: 54b5 103b cfc1 a1,\$21
+[ ]*[0-9a-f]+: 54b6 103b cfc1 a1,\$22
+[ ]*[0-9a-f]+: 54b7 103b cfc1 a1,\$23
+[ ]*[0-9a-f]+: 54b8 103b cfc1 a1,\$24
+[ ]*[0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ ]*[0-9a-f]+: 54ba 103b cfc1 a1,\$26
+[ ]*[0-9a-f]+: 54bb 103b cfc1 a1,\$27
+[ ]*[0-9a-f]+: 54bc 103b cfc1 a1,\$28
+[ ]*[0-9a-f]+: 54bd 103b cfc1 a1,\$29
+[ ]*[0-9a-f]+: 54be 103b cfc1 a1,\$30
+[ ]*[0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ ]*[0-9a-f]+: 54a0 103b cfc1 a1,\$0
+[ ]*[0-9a-f]+: 54a1 103b cfc1 a1,\$1
+[ ]*[0-9a-f]+: 54a2 103b cfc1 a1,\$2
+[ ]*[0-9a-f]+: 54a3 103b cfc1 a1,\$3
+[ ]*[0-9a-f]+: 54a4 103b cfc1 a1,\$4
+[ ]*[0-9a-f]+: 54a5 103b cfc1 a1,\$5
+[ ]*[0-9a-f]+: 54a6 103b cfc1 a1,\$6
+[ ]*[0-9a-f]+: 54a7 103b cfc1 a1,\$7
+[ ]*[0-9a-f]+: 54a8 103b cfc1 a1,\$8
+[ ]*[0-9a-f]+: 54a9 103b cfc1 a1,\$9
+[ ]*[0-9a-f]+: 54aa 103b cfc1 a1,\$10
+[ ]*[0-9a-f]+: 54ab 103b cfc1 a1,\$11
+[ ]*[0-9a-f]+: 54ac 103b cfc1 a1,\$12
+[ ]*[0-9a-f]+: 54ad 103b cfc1 a1,\$13
+[ ]*[0-9a-f]+: 54ae 103b cfc1 a1,\$14
+[ ]*[0-9a-f]+: 54af 103b cfc1 a1,\$15
+[ ]*[0-9a-f]+: 54b0 103b cfc1 a1,\$16
+[ ]*[0-9a-f]+: 54b1 103b cfc1 a1,\$17
+[ ]*[0-9a-f]+: 54b2 103b cfc1 a1,\$18
+[ ]*[0-9a-f]+: 54b3 103b cfc1 a1,\$19
+[ ]*[0-9a-f]+: 54b4 103b cfc1 a1,\$20
+[ ]*[0-9a-f]+: 54b5 103b cfc1 a1,\$21
+[ ]*[0-9a-f]+: 54b6 103b cfc1 a1,\$22
+[ ]*[0-9a-f]+: 54b7 103b cfc1 a1,\$23
+[ ]*[0-9a-f]+: 54b8 103b cfc1 a1,\$24
+[ ]*[0-9a-f]+: 54b9 103b cfc1 a1,\$25
+[ ]*[0-9a-f]+: 54ba 103b cfc1 a1,\$26
+[ ]*[0-9a-f]+: 54bb 103b cfc1 a1,\$27
+[ ]*[0-9a-f]+: 54bc 103b cfc1 a1,\$28
+[ ]*[0-9a-f]+: 54bd 103b cfc1 a1,\$29
+[ ]*[0-9a-f]+: 54be 103b cfc1 a1,\$30
+[ ]*[0-9a-f]+: 54bf 103b cfc1 a1,\$31
+[ ]*[0-9a-f]+: 00a0 cd3c cfc2 a1,\$0
+[ ]*[0-9a-f]+: 00a1 cd3c cfc2 a1,\$1
+[ ]*[0-9a-f]+: 00a2 cd3c cfc2 a1,\$2
+[ ]*[0-9a-f]+: 00a3 cd3c cfc2 a1,\$3
+[ ]*[0-9a-f]+: 00a4 cd3c cfc2 a1,\$4
+[ ]*[0-9a-f]+: 00a5 cd3c cfc2 a1,\$5
+[ ]*[0-9a-f]+: 00a6 cd3c cfc2 a1,\$6
+[ ]*[0-9a-f]+: 00a7 cd3c cfc2 a1,\$7
+[ ]*[0-9a-f]+: 00a8 cd3c cfc2 a1,\$8
+[ ]*[0-9a-f]+: 00a9 cd3c cfc2 a1,\$9
+[ ]*[0-9a-f]+: 00aa cd3c cfc2 a1,\$10
+[ ]*[0-9a-f]+: 00ab cd3c cfc2 a1,\$11
+[ ]*[0-9a-f]+: 00ac cd3c cfc2 a1,\$12
+[ ]*[0-9a-f]+: 00ad cd3c cfc2 a1,\$13
+[ ]*[0-9a-f]+: 00ae cd3c cfc2 a1,\$14
+[ ]*[0-9a-f]+: 00af cd3c cfc2 a1,\$15
+[ ]*[0-9a-f]+: 00b0 cd3c cfc2 a1,\$16
+[ ]*[0-9a-f]+: 00b1 cd3c cfc2 a1,\$17
+[ ]*[0-9a-f]+: 00b2 cd3c cfc2 a1,\$18
+[ ]*[0-9a-f]+: 00b3 cd3c cfc2 a1,\$19
+[ ]*[0-9a-f]+: 00b4 cd3c cfc2 a1,\$20
+[ ]*[0-9a-f]+: 00b5 cd3c cfc2 a1,\$21
+[ ]*[0-9a-f]+: 00b6 cd3c cfc2 a1,\$22
+[ ]*[0-9a-f]+: 00b7 cd3c cfc2 a1,\$23
+[ ]*[0-9a-f]+: 00b8 cd3c cfc2 a1,\$24
+[ ]*[0-9a-f]+: 00b9 cd3c cfc2 a1,\$25
+[ ]*[0-9a-f]+: 00ba cd3c cfc2 a1,\$26
+[ ]*[0-9a-f]+: 00bb cd3c cfc2 a1,\$27
+[ ]*[0-9a-f]+: 00bc cd3c cfc2 a1,\$28
+[ ]*[0-9a-f]+: 00bd cd3c cfc2 a1,\$29
+[ ]*[0-9a-f]+: 00be cd3c cfc2 a1,\$30
+[ ]*[0-9a-f]+: 00bf cd3c cfc2 a1,\$31
+[ ]*[0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ ]*[0-9a-f]+: 54a1 183b ctc1 a1,\$1
+[ ]*[0-9a-f]+: 54a2 183b ctc1 a1,\$2
+[ ]*[0-9a-f]+: 54a3 183b ctc1 a1,\$3
+[ ]*[0-9a-f]+: 54a4 183b ctc1 a1,\$4
+[ ]*[0-9a-f]+: 54a5 183b ctc1 a1,\$5
+[ ]*[0-9a-f]+: 54a6 183b ctc1 a1,\$6
+[ ]*[0-9a-f]+: 54a7 183b ctc1 a1,\$7
+[ ]*[0-9a-f]+: 54a8 183b ctc1 a1,\$8
+[ ]*[0-9a-f]+: 54a9 183b ctc1 a1,\$9
+[ ]*[0-9a-f]+: 54aa 183b ctc1 a1,\$10
+[ ]*[0-9a-f]+: 54ab 183b ctc1 a1,\$11
+[ ]*[0-9a-f]+: 54ac 183b ctc1 a1,\$12
+[ ]*[0-9a-f]+: 54ad 183b ctc1 a1,\$13
+[ ]*[0-9a-f]+: 54ae 183b ctc1 a1,\$14
+[ ]*[0-9a-f]+: 54af 183b ctc1 a1,\$15
+[ ]*[0-9a-f]+: 54b0 183b ctc1 a1,\$16
+[ ]*[0-9a-f]+: 54b1 183b ctc1 a1,\$17
+[ ]*[0-9a-f]+: 54b2 183b ctc1 a1,\$18
+[ ]*[0-9a-f]+: 54b3 183b ctc1 a1,\$19
+[ ]*[0-9a-f]+: 54b4 183b ctc1 a1,\$20
+[ ]*[0-9a-f]+: 54b5 183b ctc1 a1,\$21
+[ ]*[0-9a-f]+: 54b6 183b ctc1 a1,\$22
+[ ]*[0-9a-f]+: 54b7 183b ctc1 a1,\$23
+[ ]*[0-9a-f]+: 54b8 183b ctc1 a1,\$24
+[ ]*[0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ ]*[0-9a-f]+: 54ba 183b ctc1 a1,\$26
+[ ]*[0-9a-f]+: 54bb 183b ctc1 a1,\$27
+[ ]*[0-9a-f]+: 54bc 183b ctc1 a1,\$28
+[ ]*[0-9a-f]+: 54bd 183b ctc1 a1,\$29
+[ ]*[0-9a-f]+: 54be 183b ctc1 a1,\$30
+[ ]*[0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ ]*[0-9a-f]+: 54a0 183b ctc1 a1,\$0
+[ ]*[0-9a-f]+: 54a1 183b ctc1 a1,\$1
+[ ]*[0-9a-f]+: 54a2 183b ctc1 a1,\$2
+[ ]*[0-9a-f]+: 54a3 183b ctc1 a1,\$3
+[ ]*[0-9a-f]+: 54a4 183b ctc1 a1,\$4
+[ ]*[0-9a-f]+: 54a5 183b ctc1 a1,\$5
+[ ]*[0-9a-f]+: 54a6 183b ctc1 a1,\$6
+[ ]*[0-9a-f]+: 54a7 183b ctc1 a1,\$7
+[ ]*[0-9a-f]+: 54a8 183b ctc1 a1,\$8
+[ ]*[0-9a-f]+: 54a9 183b ctc1 a1,\$9
+[ ]*[0-9a-f]+: 54aa 183b ctc1 a1,\$10
+[ ]*[0-9a-f]+: 54ab 183b ctc1 a1,\$11
+[ ]*[0-9a-f]+: 54ac 183b ctc1 a1,\$12
+[ ]*[0-9a-f]+: 54ad 183b ctc1 a1,\$13
+[ ]*[0-9a-f]+: 54ae 183b ctc1 a1,\$14
+[ ]*[0-9a-f]+: 54af 183b ctc1 a1,\$15
+[ ]*[0-9a-f]+: 54b0 183b ctc1 a1,\$16
+[ ]*[0-9a-f]+: 54b1 183b ctc1 a1,\$17
+[ ]*[0-9a-f]+: 54b2 183b ctc1 a1,\$18
+[ ]*[0-9a-f]+: 54b3 183b ctc1 a1,\$19
+[ ]*[0-9a-f]+: 54b4 183b ctc1 a1,\$20
+[ ]*[0-9a-f]+: 54b5 183b ctc1 a1,\$21
+[ ]*[0-9a-f]+: 54b6 183b ctc1 a1,\$22
+[ ]*[0-9a-f]+: 54b7 183b ctc1 a1,\$23
+[ ]*[0-9a-f]+: 54b8 183b ctc1 a1,\$24
+[ ]*[0-9a-f]+: 54b9 183b ctc1 a1,\$25
+[ ]*[0-9a-f]+: 54ba 183b ctc1 a1,\$26
+[ ]*[0-9a-f]+: 54bb 183b ctc1 a1,\$27
+[ ]*[0-9a-f]+: 54bc 183b ctc1 a1,\$28
+[ ]*[0-9a-f]+: 54bd 183b ctc1 a1,\$29
+[ ]*[0-9a-f]+: 54be 183b ctc1 a1,\$30
+[ ]*[0-9a-f]+: 54bf 183b ctc1 a1,\$31
+[ ]*[0-9a-f]+: 00a0 dd3c ctc2 a1,\$0
+[ ]*[0-9a-f]+: 00a1 dd3c ctc2 a1,\$1
+[ ]*[0-9a-f]+: 00a2 dd3c ctc2 a1,\$2
+[ ]*[0-9a-f]+: 00a3 dd3c ctc2 a1,\$3
+[ ]*[0-9a-f]+: 00a4 dd3c ctc2 a1,\$4
+[ ]*[0-9a-f]+: 00a5 dd3c ctc2 a1,\$5
+[ ]*[0-9a-f]+: 00a6 dd3c ctc2 a1,\$6
+[ ]*[0-9a-f]+: 00a7 dd3c ctc2 a1,\$7
+[ ]*[0-9a-f]+: 00a8 dd3c ctc2 a1,\$8
+[ ]*[0-9a-f]+: 00a9 dd3c ctc2 a1,\$9
+[ ]*[0-9a-f]+: 00aa dd3c ctc2 a1,\$10
+[ ]*[0-9a-f]+: 00ab dd3c ctc2 a1,\$11
+[ ]*[0-9a-f]+: 00ac dd3c ctc2 a1,\$12
+[ ]*[0-9a-f]+: 00ad dd3c ctc2 a1,\$13
+[ ]*[0-9a-f]+: 00ae dd3c ctc2 a1,\$14
+[ ]*[0-9a-f]+: 00af dd3c ctc2 a1,\$15
+[ ]*[0-9a-f]+: 00b0 dd3c ctc2 a1,\$16
+[ ]*[0-9a-f]+: 00b1 dd3c ctc2 a1,\$17
+[ ]*[0-9a-f]+: 00b2 dd3c ctc2 a1,\$18
+[ ]*[0-9a-f]+: 00b3 dd3c ctc2 a1,\$19
+[ ]*[0-9a-f]+: 00b4 dd3c ctc2 a1,\$20
+[ ]*[0-9a-f]+: 00b5 dd3c ctc2 a1,\$21
+[ ]*[0-9a-f]+: 00b6 dd3c ctc2 a1,\$22
+[ ]*[0-9a-f]+: 00b7 dd3c ctc2 a1,\$23
+[ ]*[0-9a-f]+: 00b8 dd3c ctc2 a1,\$24
+[ ]*[0-9a-f]+: 00b9 dd3c ctc2 a1,\$25
+[ ]*[0-9a-f]+: 00ba dd3c ctc2 a1,\$26
+[ ]*[0-9a-f]+: 00bb dd3c ctc2 a1,\$27
+[ ]*[0-9a-f]+: 00bc dd3c ctc2 a1,\$28
+[ ]*[0-9a-f]+: 00bd dd3c ctc2 a1,\$29
+[ ]*[0-9a-f]+: 00be dd3c ctc2 a1,\$30
+[ ]*[0-9a-f]+: 00bf dd3c ctc2 a1,\$31
+[ ]*[0-9a-f]+: 5401 537b cvt.d.l \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 537b cvt.d.l \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 537b cvt.d.l \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 137b cvt.d.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 137b cvt.d.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 137b cvt.d.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 337b cvt.d.w \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 337b cvt.d.w \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 337b cvt.d.w \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 013b cvt.l.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 013b cvt.l.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 013b cvt.l.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 413b cvt.l.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 413b cvt.l.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 413b cvt.l.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 5b7b cvt.s.l \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 5b7b cvt.s.l \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 5b7b cvt.s.l \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 1b7b cvt.s.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 1b7b cvt.s.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 1b7b cvt.s.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 3b7b cvt.s.w \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 3b7b cvt.s.w \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 3b7b cvt.s.w \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 213b cvt.s.pl \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 213b cvt.s.pl \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 213b cvt.s.pl \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 293b cvt.s.pu \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 293b cvt.s.pu \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 293b cvt.s.pu \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 093b cvt.w.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 093b cvt.w.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 093b cvt.w.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 493b cvt.w.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 493b cvt.w.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 493b cvt.w.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5441 01f0 div.d \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: 57fe e9f0 div.d \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: 57dd e9f0 div.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 57dd e9f0 div.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 5441 00f0 div.s \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: 57fe e8f0 div.s \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: 57dd e8f0 div.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 57dd e8f0 div.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 5401 433b floor.l.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 433b floor.l.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 433b floor.l.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 033b floor.l.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 033b floor.l.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 033b floor.l.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 4b3b floor.w.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 4b3b floor.w.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 4b3b floor.w.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 0b3b floor.w.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 0b3b floor.w.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 0b3b floor.w.s \$f2,\$f2
+[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: bc61 ffff ldc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: bc61 0001 ldc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: bc64 8001 ldc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: bc64 ffff ldc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: bc61 5678 ldc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: bc61 ffff ldc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: bc61 0001 ldc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: bc64 8001 ldc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: bc64 ffff ldc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: bc61 5678 ldc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: 54a0 203b mfc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 203b mfc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 203b mfc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 203b mfc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 203b mfc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 203b mfc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 203b mfc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 203b mfc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 203b mfc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 203b mfc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 203b mfc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 203b mfc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 203b mfc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 203b mfc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 203b mfc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 203b mfc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 203b mfc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 203b mfc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 203b mfc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 203b mfc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 203b mfc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 203b mfc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 203b mfc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 203b mfc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 203b mfc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 203b mfc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 203b mfc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 203b mfc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 203b mfc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 203b mfc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 203b mfc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 203b mfc1 a1,\$f31
+[ ]*[0-9a-f]+: 54a0 203b mfc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 203b mfc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 203b mfc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 203b mfc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 203b mfc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 203b mfc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 203b mfc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 203b mfc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 203b mfc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 203b mfc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 203b mfc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 203b mfc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 203b mfc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 203b mfc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 203b mfc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 203b mfc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 203b mfc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 203b mfc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 203b mfc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 203b mfc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 203b mfc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 203b mfc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 203b mfc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 203b mfc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 203b mfc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 203b mfc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 203b mfc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 203b mfc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 203b mfc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 203b mfc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 203b mfc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 203b mfc1 a1,\$f31
+[ ]*[0-9a-f]+: 54a0 303b mfhc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 303b mfhc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 303b mfhc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 303b mfhc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 303b mfhc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 303b mfhc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 303b mfhc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 303b mfhc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 303b mfhc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 303b mfhc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 303b mfhc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 303b mfhc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 303b mfhc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 303b mfhc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 303b mfhc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 303b mfhc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 303b mfhc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 303b mfhc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 303b mfhc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 303b mfhc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 303b mfhc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 303b mfhc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 303b mfhc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 303b mfhc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 303b mfhc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 303b mfhc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 303b mfhc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 303b mfhc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 303b mfhc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 303b mfhc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 303b mfhc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 303b mfhc1 a1,\$f31
+[ ]*[0-9a-f]+: 54a0 303b mfhc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 303b mfhc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 303b mfhc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 303b mfhc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 303b mfhc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 303b mfhc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 303b mfhc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 303b mfhc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 303b mfhc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 303b mfhc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 303b mfhc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 303b mfhc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 303b mfhc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 303b mfhc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 303b mfhc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 303b mfhc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 303b mfhc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 303b mfhc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 303b mfhc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 303b mfhc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 303b mfhc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 303b mfhc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 303b mfhc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 303b mfhc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 303b mfhc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 303b mfhc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 303b mfhc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 303b mfhc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 303b mfhc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 303b mfhc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 303b mfhc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 303b mfhc1 a1,\$f31
+[ ]*[0-9a-f]+: 5401 207b mov.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 207b mov.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5401 007b mov.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 007b mov.s \$f30,\$f31
+[ ]*[0-9a-f]+: 54a0 283b mtc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 283b mtc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 283b mtc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 283b mtc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 283b mtc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 283b mtc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 283b mtc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 283b mtc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 283b mtc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 283b mtc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 283b mtc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 283b mtc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 283b mtc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 283b mtc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 283b mtc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 283b mtc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 283b mtc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 283b mtc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 283b mtc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 283b mtc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 283b mtc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 283b mtc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 283b mtc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 283b mtc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 283b mtc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 283b mtc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 283b mtc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 283b mtc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 283b mtc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 283b mtc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 283b mtc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 283b mtc1 a1,\$f31
+[ ]*[0-9a-f]+: 54a0 283b mtc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 283b mtc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 283b mtc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 283b mtc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 283b mtc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 283b mtc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 283b mtc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 283b mtc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 283b mtc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 283b mtc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 283b mtc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 283b mtc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 283b mtc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 283b mtc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 283b mtc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 283b mtc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 283b mtc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 283b mtc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 283b mtc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 283b mtc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 283b mtc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 283b mtc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 283b mtc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 283b mtc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 283b mtc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 283b mtc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 283b mtc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 283b mtc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 283b mtc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 283b mtc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 283b mtc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 283b mtc1 a1,\$f31
+[ ]*[0-9a-f]+: 54a0 383b mthc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 383b mthc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 383b mthc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 383b mthc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 383b mthc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 383b mthc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 383b mthc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 383b mthc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 383b mthc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 383b mthc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 383b mthc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 383b mthc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 383b mthc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 383b mthc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 383b mthc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 383b mthc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 383b mthc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 383b mthc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 383b mthc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 383b mthc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 383b mthc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 383b mthc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 383b mthc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 383b mthc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 383b mthc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 383b mthc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 383b mthc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 383b mthc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 383b mthc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 383b mthc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 383b mthc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 383b mthc1 a1,\$f31
+[ ]*[0-9a-f]+: 54a0 383b mthc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 383b mthc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 383b mthc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 383b mthc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 383b mthc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 383b mthc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 383b mthc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 383b mthc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 383b mthc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 383b mthc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 383b mthc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 383b mthc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 383b mthc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 383b mthc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 383b mthc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 383b mthc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 383b mthc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 383b mthc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 383b mthc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 383b mthc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 383b mthc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 383b mthc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 383b mthc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 383b mthc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 383b mthc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 383b mthc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 383b mthc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 383b mthc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 383b mthc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 383b mthc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 383b mthc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 383b mthc1 a1,\$f31
+[ ]*[0-9a-f]+: 5441 00b0 mul.s \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: 57fe e8b0 mul.s \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: 57dd e8b0 mul.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 57dd e8b0 mul.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 5441 01b0 mul.d \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: 57fe e9b0 mul.d \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: 57dd e9b0 mul.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 57dd e9b0 mul.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 5401 0b7b neg.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 0b7b neg.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 0b7b neg.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5442 0b7b neg.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 2b7b neg.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 2b7b neg.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 2b7b neg.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5442 2b7b neg.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 123b recip.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 123b recip.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 123b recip.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 523b recip.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 523b recip.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 523b recip.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 333b round.l.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 333b round.l.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 333b round.l.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 733b round.l.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 733b round.l.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 733b round.l.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 3b3b round.w.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 3b3b round.w.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 3b3b round.w.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 7b3b round.w.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 7b3b round.w.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 7b3b round.w.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 023b rsqrt.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 023b rsqrt.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 023b rsqrt.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 423b rsqrt.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 423b rsqrt.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 423b rsqrt.d \$f2,\$f2
+[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: b861 ffff sdc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: b861 0001 sdc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: b864 8001 sdc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: b864 ffff sdc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: b861 5678 sdc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: b861 ffff sdc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: b861 0001 sdc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: b864 8001 sdc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: b864 ffff sdc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: b861 5678 sdc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 5401 0a3b sqrt.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 0a3b sqrt.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 0a3b sqrt.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 4a3b sqrt.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 4a3b sqrt.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 4a3b sqrt.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5441 0070 sub.s \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: 57fe e870 sub.s \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: 57dd e870 sub.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 57dd e870 sub.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 5441 0170 sub.d \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: 57fe e970 sub.d \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: 57dd e970 sub.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 57dd e970 sub.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: 5401 233b trunc.l.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 233b trunc.l.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 233b trunc.l.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 633b trunc.l.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 633b trunc.l.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 633b trunc.l.d \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 2b3b trunc.w.s \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 2b3b trunc.w.s \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 2b3b trunc.w.s \$f2,\$f2
+[ ]*[0-9a-f]+: 5401 6b3b trunc.w.d \$f0,\$f1
+[ ]*[0-9a-f]+: 57df 6b3b trunc.w.d \$f30,\$f31
+[ ]*[0-9a-f]+: 5442 6b3b trunc.w.d \$f2,\$f2
+
+[ 0-9a-f]+ <test_mips64>:
+[ ]*[0-9a-f]+: 0c43 move v0,v1
+[ ]*[0-9a-f]+: f463 fffe bgezc v1,31ea <.*>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_4
+[ ]*[0-9a-f]+: 5860 1190 dneg v0,v1
+
+[ 0-9a-f]+ <\.L\^\_4>:
+[ ]*[0-9a-f]+: f442 fffe bgezc v0,31f2 <\.L\^\_4>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_5
+[ ]*[0-9a-f]+: 5840 1190 dneg v0,v0
+
+[ 0-9a-f]+ <\.L\^\_5>:
+[ ]*[0-9a-f]+: f442 fffe bgezc v0,31fa <\.L\^\_5>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_6
+[ ]*[0-9a-f]+: 5840 1190 dneg v0,v0
+
+[ 0-9a-f]+ <\.L\^\_6>:
+[ ]*[0-9a-f]+: 5883 1110 dadd v0,v1,a0
+[ ]*[0-9a-f]+: 5bfe e910 dadd sp,s8,ra
+[ ]*[0-9a-f]+: 5862 1110 dadd v0,v0,v1
+[ ]*[0-9a-f]+: 5862 1110 dadd v0,v0,v1
+[ ]*[0-9a-f]+: 5c43 0000 daddiu v0,v1,0
+[ ]*[0-9a-f]+: 5c43 8000 daddiu v0,v1,-32768
+[ ]*[0-9a-f]+: 5c43 7fff daddiu v0,v1,32767
+[ ]*[0-9a-f]+: 5c42 7fff daddiu v0,v0,32767
+[ ]*[0-9a-f]+: 5c42 7fff daddiu v0,v0,32767
+[ ]*[0-9a-f]+: 5883 1150 daddu v0,v1,a0
+[ ]*[0-9a-f]+: 5bfe e950 daddu sp,s8,ra
+[ ]*[0-9a-f]+: 5862 1150 daddu v0,v0,v1
+[ ]*[0-9a-f]+: 5862 1150 daddu v0,v0,v1
+[ ]*[0-9a-f]+: 5803 1150 move v0,v1
+[ ]*[0-9a-f]+: 5c43 0000 daddiu v0,v1,0
+[ ]*[0-9a-f]+: 5c43 0001 daddiu v0,v1,1
+[ ]*[0-9a-f]+: 5c43 7fff daddiu v0,v1,32767
+[ ]*[0-9a-f]+: 5c43 8000 daddiu v0,v1,-32768
+[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: 5823 1150 daddu v0,v1,at
+[ ]*[0-9a-f]+: 5843 4b3c dclo v0,v1
+[ ]*[0-9a-f]+: 5862 4b3c dclo v1,v0
+[ ]*[0-9a-f]+: 5843 5b3c dclz v0,v1
+[ ]*[0-9a-f]+: 5862 5b3c dclz v1,v0
+[ ]*[0-9a-f]+: 5862 0118 ddiv zero,v0,v1
+[ ]*[0-9a-f]+: 5bfe 0118 ddiv zero,s8,ra
+[ ]*[0-9a-f]+: 5803 1118 ddiv v0,v1,zero
+[ ]*[0-9a-f]+: 5883 1118 ddiv v0,v1,a0
+[ ]*[0-9a-f]+: 5862 0198 ddivu zero,v0,v1
+[ ]*[0-9a-f]+: 5bfe 0198 ddivu zero,s8,ra
+[ ]*[0-9a-f]+: 5803 1198 ddivu v0,v1,zero
+[ ]*[0-9a-f]+: 5883 1198 ddivu v0,v1,a0
+[ ]*[0-9a-f]+: 5843 07ec dext v0,v1,0x1f,0x1
+[ ]*[0-9a-f]+: 5843 f82c dext v0,v1,0x0,0x20
+[ ]*[0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21
+[ ]*[0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21
+[ ]*[0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa
+[ ]*[0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa
+[ ]*[0-9a-f]+: 5843 ffcc dins v0,v1,0x1f,0x1
+[ ]*[0-9a-f]+: 5843 f80c dins v0,v1,0x0,0x20
+[ ]*[0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21
+[ ]*[0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21
+[ ]*[0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa
+[ ]*[0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa
+[ ]*[0-9a-f]+: 1040 0000 lui v0,0x0
+ [0-9a-f]+: R_MICROMIPS_HI16 test
+[ ]*[0-9a-f]+: 3042 0000 addiu v0,v0,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 1040 0000 lui v0,0x0
+ [0-9a-f]+: R_MICROMIPS_HI16 test
+[ ]*[0-9a-f]+: 3042 0000 addiu v0,v0,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 3040 8000 li v0,-32768
+[ ]*[0-9a-f]+: 3040 7fff li v0,32767
+[ ]*[0-9a-f]+: 5040 ffff li v0,0xffff
+[ ]*[0-9a-f]+: 1040 1234 lui v0,0x1234
+[ ]*[0-9a-f]+: 5042 5678 ori v0,v0,0x5678
+[ ]*[0-9a-f]+: 5840 00fc dmfc0 v0,c0_index
+[ ]*[0-9a-f]+: 5841 00fc dmfc0 v0,c0_random
+[ ]*[0-9a-f]+: 5842 00fc dmfc0 v0,c0_entrylo0
+[ ]*[0-9a-f]+: 5843 00fc dmfc0 v0,c0_entrylo1
+[ ]*[0-9a-f]+: 5844 00fc dmfc0 v0,c0_context
+[ ]*[0-9a-f]+: 5845 00fc dmfc0 v0,c0_pagemask
+[ ]*[0-9a-f]+: 5846 00fc dmfc0 v0,c0_wired
+[ ]*[0-9a-f]+: 5847 00fc dmfc0 v0,c0_hwrena
+[ ]*[0-9a-f]+: 5848 00fc dmfc0 v0,c0_badvaddr
+[ ]*[0-9a-f]+: 5849 00fc dmfc0 v0,c0_count
+[ ]*[0-9a-f]+: 584a 00fc dmfc0 v0,c0_entryhi
+[ ]*[0-9a-f]+: 584b 00fc dmfc0 v0,c0_compare
+[ ]*[0-9a-f]+: 584c 00fc dmfc0 v0,c0_status
+[ ]*[0-9a-f]+: 584d 00fc dmfc0 v0,c0_cause
+[ ]*[0-9a-f]+: 584e 00fc dmfc0 v0,c0_epc
+[ ]*[0-9a-f]+: 584f 00fc dmfc0 v0,c0_prid
+[ ]*[0-9a-f]+: 5850 00fc dmfc0 v0,c0_config
+[ ]*[0-9a-f]+: 5851 00fc dmfc0 v0,c0_lladdr
+[ ]*[0-9a-f]+: 5852 00fc dmfc0 v0,c0_watchlo
+[ ]*[0-9a-f]+: 5853 00fc dmfc0 v0,c0_watchhi
+[ ]*[0-9a-f]+: 5854 00fc dmfc0 v0,c0_xcontext
+[ ]*[0-9a-f]+: 5855 00fc dmfc0 v0,\$21
+[ ]*[0-9a-f]+: 5856 00fc dmfc0 v0,\$22
+[ ]*[0-9a-f]+: 5857 00fc dmfc0 v0,c0_debug
+[ ]*[0-9a-f]+: 5858 00fc dmfc0 v0,c0_depc
+[ ]*[0-9a-f]+: 5859 00fc dmfc0 v0,c0_perfcnt
+[ ]*[0-9a-f]+: 585a 00fc dmfc0 v0,c0_errctl
+[ ]*[0-9a-f]+: 585b 00fc dmfc0 v0,c0_cacheerr
+[ ]*[0-9a-f]+: 585c 00fc dmfc0 v0,c0_taglo
+[ ]*[0-9a-f]+: 585d 00fc dmfc0 v0,c0_taghi
+[ ]*[0-9a-f]+: 585e 00fc dmfc0 v0,c0_errorepc
+[ ]*[0-9a-f]+: 585f 00fc dmfc0 v0,c0_desave
+[ ]*[0-9a-f]+: 5840 00fc dmfc0 v0,c0_index
+[ ]*[0-9a-f]+: 5840 08fc dmfc0 v0,c0_mvpcontrol
+[ ]*[0-9a-f]+: 5840 10fc dmfc0 v0,c0_mvpconf0
+[ ]*[0-9a-f]+: 5840 18fc dmfc0 v0,c0_mvpconf1
+[ ]*[0-9a-f]+: 5840 20fc dmfc0 v0,\$0,4
+[ ]*[0-9a-f]+: 5840 28fc dmfc0 v0,\$0,5
+[ ]*[0-9a-f]+: 5840 30fc dmfc0 v0,\$0,6
+[ ]*[0-9a-f]+: 5840 38fc dmfc0 v0,\$0,7
+[ ]*[0-9a-f]+: 5841 00fc dmfc0 v0,c0_random
+[ ]*[0-9a-f]+: 5841 08fc dmfc0 v0,c0_vpecontrol
+[ ]*[0-9a-f]+: 5841 10fc dmfc0 v0,c0_vpeconf0
+[ ]*[0-9a-f]+: 5841 18fc dmfc0 v0,c0_vpeconf1
+[ ]*[0-9a-f]+: 5841 20fc dmfc0 v0,c0_yqmask
+[ ]*[0-9a-f]+: 5841 28fc dmfc0 v0,c0_vpeschedule
+[ ]*[0-9a-f]+: 5841 30fc dmfc0 v0,c0_vpeschefback
+[ ]*[0-9a-f]+: 5841 38fc dmfc0 v0,\$1,7
+[ ]*[0-9a-f]+: 5842 00fc dmfc0 v0,c0_entrylo0
+[ ]*[0-9a-f]+: 5842 08fc dmfc0 v0,c0_tcstatus
+[ ]*[0-9a-f]+: 5842 10fc dmfc0 v0,c0_tcbind
+[ ]*[0-9a-f]+: 5842 18fc dmfc0 v0,c0_tcrestart
+[ ]*[0-9a-f]+: 5842 20fc dmfc0 v0,c0_tchalt
+[ ]*[0-9a-f]+: 5842 28fc dmfc0 v0,c0_tccontext
+[ ]*[0-9a-f]+: 5842 30fc dmfc0 v0,c0_tcschedule
+[ ]*[0-9a-f]+: 5842 38fc dmfc0 v0,c0_tcschefback
+[ ]*[0-9a-f]+: 5840 02fc dmtc0 v0,c0_index
+[ ]*[0-9a-f]+: 5841 02fc dmtc0 v0,c0_random
+[ ]*[0-9a-f]+: 5842 02fc dmtc0 v0,c0_entrylo0
+[ ]*[0-9a-f]+: 5843 02fc dmtc0 v0,c0_entrylo1
+[ ]*[0-9a-f]+: 5844 02fc dmtc0 v0,c0_context
+[ ]*[0-9a-f]+: 5845 02fc dmtc0 v0,c0_pagemask
+[ ]*[0-9a-f]+: 5846 02fc dmtc0 v0,c0_wired
+[ ]*[0-9a-f]+: 5847 02fc dmtc0 v0,c0_hwrena
+[ ]*[0-9a-f]+: 5848 02fc dmtc0 v0,c0_badvaddr
+[ ]*[0-9a-f]+: 5849 02fc dmtc0 v0,c0_count
+[ ]*[0-9a-f]+: 584a 02fc dmtc0 v0,c0_entryhi
+[ ]*[0-9a-f]+: 584b 02fc dmtc0 v0,c0_compare
+[ ]*[0-9a-f]+: 584c 02fc dmtc0 v0,c0_status
+[ ]*[0-9a-f]+: 584d 02fc dmtc0 v0,c0_cause
+[ ]*[0-9a-f]+: 584e 02fc dmtc0 v0,c0_epc
+[ ]*[0-9a-f]+: 584f 02fc dmtc0 v0,c0_prid
+[ ]*[0-9a-f]+: 5850 02fc dmtc0 v0,c0_config
+[ ]*[0-9a-f]+: 5851 02fc dmtc0 v0,c0_lladdr
+[ ]*[0-9a-f]+: 5852 02fc dmtc0 v0,c0_watchlo
+[ ]*[0-9a-f]+: 5853 02fc dmtc0 v0,c0_watchhi
+[ ]*[0-9a-f]+: 5854 02fc dmtc0 v0,c0_xcontext
+[ ]*[0-9a-f]+: 5855 02fc dmtc0 v0,\$21
+[ ]*[0-9a-f]+: 5856 02fc dmtc0 v0,\$22
+[ ]*[0-9a-f]+: 5857 02fc dmtc0 v0,c0_debug
+[ ]*[0-9a-f]+: 5858 02fc dmtc0 v0,c0_depc
+[ ]*[0-9a-f]+: 5859 02fc dmtc0 v0,c0_perfcnt
+[ ]*[0-9a-f]+: 585a 02fc dmtc0 v0,c0_errctl
+[ ]*[0-9a-f]+: 585b 02fc dmtc0 v0,c0_cacheerr
+[ ]*[0-9a-f]+: 585c 02fc dmtc0 v0,c0_taglo
+[ ]*[0-9a-f]+: 585d 02fc dmtc0 v0,c0_taghi
+[ ]*[0-9a-f]+: 585e 02fc dmtc0 v0,c0_errorepc
+[ ]*[0-9a-f]+: 585f 02fc dmtc0 v0,c0_desave
+[ ]*[0-9a-f]+: 5840 02fc dmtc0 v0,c0_index
+[ ]*[0-9a-f]+: 5840 0afc dmtc0 v0,c0_mvpcontrol
+[ ]*[0-9a-f]+: 5840 12fc dmtc0 v0,c0_mvpconf0
+[ ]*[0-9a-f]+: 5840 1afc dmtc0 v0,c0_mvpconf1
+[ ]*[0-9a-f]+: 5840 22fc dmtc0 v0,\$0,4
+[ ]*[0-9a-f]+: 5840 2afc dmtc0 v0,\$0,5
+[ ]*[0-9a-f]+: 5840 32fc dmtc0 v0,\$0,6
+[ ]*[0-9a-f]+: 5840 3afc dmtc0 v0,\$0,7
+[ ]*[0-9a-f]+: 5841 02fc dmtc0 v0,c0_random
+[ ]*[0-9a-f]+: 5841 0afc dmtc0 v0,c0_vpecontrol
+[ ]*[0-9a-f]+: 5841 12fc dmtc0 v0,c0_vpeconf0
+[ ]*[0-9a-f]+: 5841 1afc dmtc0 v0,c0_vpeconf1
+[ ]*[0-9a-f]+: 5841 22fc dmtc0 v0,c0_yqmask
+[ ]*[0-9a-f]+: 5841 2afc dmtc0 v0,c0_vpeschedule
+[ ]*[0-9a-f]+: 5841 32fc dmtc0 v0,c0_vpeschefback
+[ ]*[0-9a-f]+: 5841 3afc dmtc0 v0,\$1,7
+[ ]*[0-9a-f]+: 5842 02fc dmtc0 v0,c0_entrylo0
+[ ]*[0-9a-f]+: 5842 0afc dmtc0 v0,c0_tcstatus
+[ ]*[0-9a-f]+: 5842 12fc dmtc0 v0,c0_tcbind
+[ ]*[0-9a-f]+: 5842 1afc dmtc0 v0,c0_tcrestart
+[ ]*[0-9a-f]+: 5842 22fc dmtc0 v0,c0_tchalt
+[ ]*[0-9a-f]+: 5842 2afc dmtc0 v0,c0_tccontext
+[ ]*[0-9a-f]+: 5842 32fc dmtc0 v0,c0_tcschedule
+[ ]*[0-9a-f]+: 5842 3afc dmtc0 v0,c0_tcschefback
+[ ]*[0-9a-f]+: 54a0 243b dmfc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 243b dmfc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 243b dmfc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 243b dmfc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 243b dmfc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 243b dmfc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 243b dmfc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 243b dmfc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 243b dmfc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 243b dmfc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 243b dmfc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 243b dmfc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 243b dmfc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 243b dmfc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 243b dmfc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 243b dmfc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 243b dmfc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 243b dmfc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 243b dmfc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 243b dmfc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 243b dmfc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 243b dmfc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 243b dmfc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 243b dmfc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 243b dmfc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 243b dmfc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 243b dmfc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 243b dmfc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 243b dmfc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 243b dmfc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
+[ ]*[0-9a-f]+: 54a0 243b dmfc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 243b dmfc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 243b dmfc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 243b dmfc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 243b dmfc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 243b dmfc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 243b dmfc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 243b dmfc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 243b dmfc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 243b dmfc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 243b dmfc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 243b dmfc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 243b dmfc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 243b dmfc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 243b dmfc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 243b dmfc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 243b dmfc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 243b dmfc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 243b dmfc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 243b dmfc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 243b dmfc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 243b dmfc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 243b dmfc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 243b dmfc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 243b dmfc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 243b dmfc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 243b dmfc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 243b dmfc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 243b dmfc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 243b dmfc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
+[ ]*[0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
+[ ]*[0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
+[ ]*[0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
+[ ]*[0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
+[ ]*[0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
+[ ]*[0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
+[ ]*[0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
+[ ]*[0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
+[ ]*[0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
+[ ]*[0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
+[ ]*[0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
+[ ]*[0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
+[ ]*[0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
+[ ]*[0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
+[ ]*[0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
+[ ]*[0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
+[ ]*[0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
+[ ]*[0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
+[ ]*[0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
+[ ]*[0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
+[ ]*[0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
+[ ]*[0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
+[ ]*[0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
+[ ]*[0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
+[ ]*[0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
+[ ]*[0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
+[ ]*[0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
+[ ]*[0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
+[ ]*[0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
+[ ]*[0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
+[ ]*[0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
+[ ]*[0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
+[ ]*[0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
+[ ]*[0-9a-f]+: 0040 6d3c dmfc2 v0,\$0
+[ ]*[0-9a-f]+: 0041 6d3c dmfc2 v0,\$1
+[ ]*[0-9a-f]+: 0042 6d3c dmfc2 v0,\$2
+[ ]*[0-9a-f]+: 0043 6d3c dmfc2 v0,\$3
+[ ]*[0-9a-f]+: 0044 6d3c dmfc2 v0,\$4
+[ ]*[0-9a-f]+: 0045 6d3c dmfc2 v0,\$5
+[ ]*[0-9a-f]+: 0046 6d3c dmfc2 v0,\$6
+[ ]*[0-9a-f]+: 0047 6d3c dmfc2 v0,\$7
+[ ]*[0-9a-f]+: 0048 6d3c dmfc2 v0,\$8
+[ ]*[0-9a-f]+: 0049 6d3c dmfc2 v0,\$9
+[ ]*[0-9a-f]+: 004a 6d3c dmfc2 v0,\$10
+[ ]*[0-9a-f]+: 004b 6d3c dmfc2 v0,\$11
+[ ]*[0-9a-f]+: 004c 6d3c dmfc2 v0,\$12
+[ ]*[0-9a-f]+: 004d 6d3c dmfc2 v0,\$13
+[ ]*[0-9a-f]+: 004e 6d3c dmfc2 v0,\$14
+[ ]*[0-9a-f]+: 004f 6d3c dmfc2 v0,\$15
+[ ]*[0-9a-f]+: 0050 6d3c dmfc2 v0,\$16
+[ ]*[0-9a-f]+: 0051 6d3c dmfc2 v0,\$17
+[ ]*[0-9a-f]+: 0052 6d3c dmfc2 v0,\$18
+[ ]*[0-9a-f]+: 0053 6d3c dmfc2 v0,\$19
+[ ]*[0-9a-f]+: 0054 6d3c dmfc2 v0,\$20
+[ ]*[0-9a-f]+: 0055 6d3c dmfc2 v0,\$21
+[ ]*[0-9a-f]+: 0056 6d3c dmfc2 v0,\$22
+[ ]*[0-9a-f]+: 0057 6d3c dmfc2 v0,\$23
+[ ]*[0-9a-f]+: 0058 6d3c dmfc2 v0,\$24
+[ ]*[0-9a-f]+: 0059 6d3c dmfc2 v0,\$25
+[ ]*[0-9a-f]+: 005a 6d3c dmfc2 v0,\$26
+[ ]*[0-9a-f]+: 005b 6d3c dmfc2 v0,\$27
+[ ]*[0-9a-f]+: 005c 6d3c dmfc2 v0,\$28
+[ ]*[0-9a-f]+: 005d 6d3c dmfc2 v0,\$29
+[ ]*[0-9a-f]+: 005e 6d3c dmfc2 v0,\$30
+[ ]*[0-9a-f]+: 005f 6d3c dmfc2 v0,\$31
+[ ]*[0-9a-f]+: 0040 7d3c dmtc2 v0,\$0
+[ ]*[0-9a-f]+: 0041 7d3c dmtc2 v0,\$1
+[ ]*[0-9a-f]+: 0042 7d3c dmtc2 v0,\$2
+[ ]*[0-9a-f]+: 0043 7d3c dmtc2 v0,\$3
+[ ]*[0-9a-f]+: 0044 7d3c dmtc2 v0,\$4
+[ ]*[0-9a-f]+: 0045 7d3c dmtc2 v0,\$5
+[ ]*[0-9a-f]+: 0046 7d3c dmtc2 v0,\$6
+[ ]*[0-9a-f]+: 0047 7d3c dmtc2 v0,\$7
+[ ]*[0-9a-f]+: 0048 7d3c dmtc2 v0,\$8
+[ ]*[0-9a-f]+: 0049 7d3c dmtc2 v0,\$9
+[ ]*[0-9a-f]+: 004a 7d3c dmtc2 v0,\$10
+[ ]*[0-9a-f]+: 004b 7d3c dmtc2 v0,\$11
+[ ]*[0-9a-f]+: 004c 7d3c dmtc2 v0,\$12
+[ ]*[0-9a-f]+: 004d 7d3c dmtc2 v0,\$13
+[ ]*[0-9a-f]+: 004e 7d3c dmtc2 v0,\$14
+[ ]*[0-9a-f]+: 004f 7d3c dmtc2 v0,\$15
+[ ]*[0-9a-f]+: 0050 7d3c dmtc2 v0,\$16
+[ ]*[0-9a-f]+: 0051 7d3c dmtc2 v0,\$17
+[ ]*[0-9a-f]+: 0052 7d3c dmtc2 v0,\$18
+[ ]*[0-9a-f]+: 0053 7d3c dmtc2 v0,\$19
+[ ]*[0-9a-f]+: 0054 7d3c dmtc2 v0,\$20
+[ ]*[0-9a-f]+: 0055 7d3c dmtc2 v0,\$21
+[ ]*[0-9a-f]+: 0056 7d3c dmtc2 v0,\$22
+[ ]*[0-9a-f]+: 0057 7d3c dmtc2 v0,\$23
+[ ]*[0-9a-f]+: 0058 7d3c dmtc2 v0,\$24
+[ ]*[0-9a-f]+: 0059 7d3c dmtc2 v0,\$25
+[ ]*[0-9a-f]+: 005a 7d3c dmtc2 v0,\$26
+[ ]*[0-9a-f]+: 005b 7d3c dmtc2 v0,\$27
+[ ]*[0-9a-f]+: 005c 7d3c dmtc2 v0,\$28
+[ ]*[0-9a-f]+: 005d 7d3c dmtc2 v0,\$29
+[ ]*[0-9a-f]+: 005e 7d3c dmtc2 v0,\$30
+[ ]*[0-9a-f]+: 005f 7d3c dmtc2 v0,\$31
+[ ]*[0-9a-f]+: 5883 1018 dmul v0,v1,a0
+[ ]*[0-9a-f]+: 5880 11d0 dnegu v0,a0
+[ ]*[0-9a-f]+: 5862 10d0 drorv v0,v1,v0
+[ ]*[0-9a-f]+: 5880 09d0 dnegu at,a0
+[ ]*[0-9a-f]+: 5841 10d0 drorv v0,v0,at
+[ ]*[0-9a-f]+: 5843 e0c8 dror32 v0,v1,0x1c
+[ ]*[0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ ]*[0-9a-f]+: 5843 20c0 dror v0,v1,0x4
+[ ]*[0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ ]*[0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ ]*[0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ ]*[0-9a-f]+: 5880 11d0 dnegu v0,a0
+[ ]*[0-9a-f]+: 5862 10d0 drorv v0,v1,v0
+[ ]*[0-9a-f]+: 5880 09d0 dnegu at,a0
+[ ]*[0-9a-f]+: 5841 10d0 drorv v0,v0,at
+[ ]*[0-9a-f]+: 5843 e0c8 dror32 v0,v1,0x1c
+[ ]*[0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ ]*[0-9a-f]+: 5843 20c0 dror v0,v1,0x4
+[ ]*[0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ ]*[0-9a-f]+: 5864 10d0 drorv v0,v1,a0
+[ ]*[0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
+[ ]*[0-9a-f]+: 5843 7b3c dsbh v0,v1
+[ ]*[0-9a-f]+: 5842 7b3c dsbh v0,v0
+[ ]*[0-9a-f]+: 5842 7b3c dsbh v0,v0
+[ ]*[0-9a-f]+: 5843 fb3c dshd v0,v1
+[ ]*[0-9a-f]+: 5842 fb3c dshd v0,v0
+[ ]*[0-9a-f]+: 5842 fb3c dshd v0,v0
+[ ]*[0-9a-f]+: 5864 1010 dsllv v0,v1,a0
+[ ]*[0-9a-f]+: 5843 f808 dsll32 v0,v1,0x1f
+[ ]*[0-9a-f]+: 5864 1010 dsllv v0,v1,a0
+[ ]*[0-9a-f]+: 5843 f808 dsll32 v0,v1,0x1f
+[ ]*[0-9a-f]+: 5843 f800 dsll v0,v1,0x1f
+[ ]*[0-9a-f]+: 5864 1090 dsrav v0,v1,a0
+[ ]*[0-9a-f]+: 5843 2088 dsra32 v0,v1,0x4
+[ ]*[0-9a-f]+: 5864 1090 dsrav v0,v1,a0
+[ ]*[0-9a-f]+: 5843 2088 dsra32 v0,v1,0x4
+[ ]*[0-9a-f]+: 5843 2080 dsra v0,v1,0x4
+[ ]*[0-9a-f]+: 5864 1050 dsrlv v0,v1,a0
+[ ]*[0-9a-f]+: 5843 f848 dsrl32 v0,v1,0x1f
+[ ]*[0-9a-f]+: 5864 1050 dsrlv v0,v1,a0
+[ ]*[0-9a-f]+: 5843 2048 dsrl32 v0,v1,0x4
+[ ]*[0-9a-f]+: 5843 2040 dsrl v0,v1,0x4
+[ ]*[0-9a-f]+: 5883 1190 dsub v0,v1,a0
+[ ]*[0-9a-f]+: 5bfe e990 dsub sp,s8,ra
+[ ]*[0-9a-f]+: 5862 1190 dsub v0,v0,v1
+[ ]*[0-9a-f]+: 5862 1190 dsub v0,v0,v1
+[ ]*[0-9a-f]+: 5883 11d0 dsubu v0,v1,a0
+[ ]*[0-9a-f]+: 5bfe e9d0 dsubu sp,s8,ra
+[ ]*[0-9a-f]+: 5862 11d0 dsubu v0,v0,v1
+[ ]*[0-9a-f]+: 5862 11d0 dsubu v0,v0,v1
+[ ]*[0-9a-f]+: 5c43 edcc daddiu v0,v1,-4660
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5678 ori at,at,0x5678
+[ ]*[0-9a-f]+: 5823 11d0 dsubu v0,v1,at
+[ ]*[0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ ]*[0-9a-f]+: dc40 0004 ld v0,4\(zero\)
+[ ]*[0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ ]*[0-9a-f]+: dc40 0000 ld v0,0\(zero\)
+[ ]*[0-9a-f]+: dc40 0004 ld v0,4\(zero\)
+[ ]*[0-9a-f]+: dc43 0004 ld v0,4\(v1\)
+[ ]*[0-9a-f]+: dc43 8000 ld v0,-32768\(v1\)
+[ ]*[0-9a-f]+: dc43 7fff ld v0,32767\(v1\)
+[ ]*[0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ ]*[0-9a-f]+: 6040 7004 lld v0,4\(zero\)
+[ ]*[0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ ]*[0-9a-f]+: 6040 7000 lld v0,0\(zero\)
+[ ]*[0-9a-f]+: 6040 7004 lld v0,4\(zero\)
+[ ]*[0-9a-f]+: 6043 7004 lld v0,4\(v1\)
+[ ]*[0-9a-f]+: 6043 7100 lld v0,-256\(v1\)
+[ ]*[0-9a-f]+: 6043 70ff lld v0,255\(v1\)
+[ ]*[0-9a-f]+: 3043 8000 addiu v0,v1,-32768
+[ ]*[0-9a-f]+: 6042 7000 lld v0,0\(v0\)
+[ ]*[0-9a-f]+: 1040 1234 lui v0,0x1234
+[ ]*[0-9a-f]+: 5042 5600 ori v0,v0,0x5600
+[ ]*[0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ ]*[0-9a-f]+: 6042 7078 lld v0,120\(v0\)
+[ ]*[0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ ]*[0-9a-f]+: 6040 e004 lwu v0,4\(zero\)
+[ ]*[0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ ]*[0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
+[ ]*[0-9a-f]+: 6040 e004 lwu v0,4\(zero\)
+[ ]*[0-9a-f]+: 6043 e004 lwu v0,4\(v1\)
+[ ]*[0-9a-f]+: 6043 ee00 lwu v0,-512\(v1\)
+[ ]*[0-9a-f]+: 6043 e1ff lwu v0,511\(v1\)
+[ ]*[0-9a-f]+: 3043 8000 addiu v0,v1,-32768
+[ ]*[0-9a-f]+: 6042 e000 lwu v0,0\(v0\)
+[ ]*[0-9a-f]+: 1040 1234 lui v0,0x1234
+[ ]*[0-9a-f]+: 5042 5000 ori v0,v0,0x5000
+[ ]*[0-9a-f]+: 0062 1150 addu v0,v0,v1
+[ ]*[0-9a-f]+: 6042 e678 lwu v0,1656\(v0\)
+[ ]*[0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ ]*[0-9a-f]+: 6040 f004 scd v0,4\(zero\)
+[ ]*[0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ ]*[0-9a-f]+: 6040 f000 scd v0,0\(zero\)
+[ ]*[0-9a-f]+: 6040 f004 scd v0,4\(zero\)
+[ ]*[0-9a-f]+: 6043 f004 scd v0,4\(v1\)
+[ ]*[0-9a-f]+: 6043 f100 scd v0,-256\(v1\)
+[ ]*[0-9a-f]+: 6043 f0ff scd v0,255\(v1\)
+[ ]*[0-9a-f]+: 3023 8000 addiu at,v1,-32768
+[ ]*[0-9a-f]+: 6041 f000 scd v0,0\(at\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5600 ori at,at,0x5600
+[ ]*[0-9a-f]+: 0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: 6041 f078 scd v0,120\(at\)
+[ ]*[0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ ]*[0-9a-f]+: d840 0004 sd v0,4\(zero\)
+[ ]*[0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ ]*[0-9a-f]+: d840 0000 sd v0,0\(zero\)
+[ ]*[0-9a-f]+: d840 0004 sd v0,4\(zero\)
+[ ]*[0-9a-f]+: d843 0004 sd v0,4\(v1\)
+[ ]*[0-9a-f]+: d843 8000 sd v0,-32768\(v1\)
+[ ]*[0-9a-f]+: d843 7fff sd v0,32767\(v1\)
+[ ]*[0-9a-f]+: 2020 7000 ldm s0,0\(zero\)
+[ ]*[0-9a-f]+: 2020 7004 ldm s0,4\(zero\)
+[ ]*[0-9a-f]+: 2025 7000 ldm s0,0\(a1\)
+[ ]*[0-9a-f]+: 2025 77ff ldm s0,2047\(a1\)
+[ ]*[0-9a-f]+: 2045 77ff ldm s0-s1,2047\(a1\)
+[ ]*[0-9a-f]+: 2065 77ff ldm s0-s2,2047\(a1\)
+[ ]*[0-9a-f]+: 2085 77ff ldm s0-s3,2047\(a1\)
+[ ]*[0-9a-f]+: 20a5 77ff ldm s0-s4,2047\(a1\)
+[ ]*[0-9a-f]+: 20c5 77ff ldm s0-s5,2047\(a1\)
+[ ]*[0-9a-f]+: 20e5 77ff ldm s0-s6,2047\(a1\)
+[ ]*[0-9a-f]+: 2105 77ff ldm s0-s7,2047\(a1\)
+[ ]*[0-9a-f]+: 2125 77ff ldm s0-s7,s8,2047\(a1\)
+[ ]*[0-9a-f]+: 2205 77ff ldm ra,2047\(a1\)
+[ ]*[0-9a-f]+: 2225 7000 ldm s0,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2245 7000 ldm s0-s1,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2265 7000 ldm s0-s2,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2285 7000 ldm s0-s3,ra,0\(a1\)
+[ ]*[0-9a-f]+: 22a5 7000 ldm s0-s4,ra,0\(a1\)
+[ ]*[0-9a-f]+: 22c5 7000 ldm s0-s5,ra,0\(a1\)
+[ ]*[0-9a-f]+: 22e5 7000 ldm s0-s6,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2305 7000 ldm s0-s7,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2325 7000 ldm s0-s7,s8,ra,0\(a1\)
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ ]*[0-9a-f]+: 2020 7000 ldm s0,0\(zero\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ ]*[0-9a-f]+: 303d 8000 addiu at,sp,-32768
+[ ]*[0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ ]*[0-9a-f]+: 303d 7fff addiu at,sp,32767
+[ ]*[0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ ]*[0-9a-f]+: 203d 7000 ldm s0,0\(sp\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 03a1 0950 addu at,at,sp
+[ ]*[0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ ]*[0-9a-f]+: 03a1 0950 addu at,at,sp
+[ ]*[0-9a-f]+: 2021 7678 ldm s0,1656\(at\)
+[ ]*[0-9a-f]+: 2040 4000 ldp v0,0\(zero\)
+[ ]*[0-9a-f]+: 2040 4004 ldp v0,4\(zero\)
+[ ]*[0-9a-f]+: 205d 4000 ldp v0,0\(sp\)
+[ ]*[0-9a-f]+: 205d 4000 ldp v0,0\(sp\)
+[ ]*[0-9a-f]+: 2043 4800 ldp v0,-2048\(v1\)
+[ ]*[0-9a-f]+: 2043 47ff ldp v0,2047\(v1\)
+[ ]*[0-9a-f]+: 3023 8000 addiu at,v1,-32768
+[ ]*[0-9a-f]+: 2041 4000 ldp v0,0\(at\)
+[ ]*[0-9a-f]+: 3023 7fff addiu at,v1,32767
+[ ]*[0-9a-f]+: 2041 4000 ldp v0,0\(at\)
+[ ]*[0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: 2041 4fff ldp v0,-1\(at\)
+[ ]*[0-9a-f]+: 3060 8000 li v1,-32768
+[ ]*[0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
+[ ]*[0-9a-f]+: 3060 7fff li v1,32767
+[ ]*[0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
+[ ]*[0-9a-f]+: 1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: 2043 4fff ldp v0,-1\(v1\)
+[ ]*[0-9a-f]+: 1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: 5063 5000 ori v1,v1,0x5000
+[ ]*[0-9a-f]+: 2043 4678 ldp v0,1656\(v1\)
+[ ]*[0-9a-f]+: 2020 f000 sdm s0,0\(zero\)
+[ ]*[0-9a-f]+: 2020 f004 sdm s0,4\(zero\)
+[ ]*[0-9a-f]+: 2025 f000 sdm s0,0\(a1\)
+[ ]*[0-9a-f]+: 2025 f7ff sdm s0,2047\(a1\)
+[ ]*[0-9a-f]+: 2045 f7ff sdm s0-s1,2047\(a1\)
+[ ]*[0-9a-f]+: 2065 f7ff sdm s0-s2,2047\(a1\)
+[ ]*[0-9a-f]+: 2085 f7ff sdm s0-s3,2047\(a1\)
+[ ]*[0-9a-f]+: 20a5 f7ff sdm s0-s4,2047\(a1\)
+[ ]*[0-9a-f]+: 20c5 f7ff sdm s0-s5,2047\(a1\)
+[ ]*[0-9a-f]+: 20e5 f7ff sdm s0-s6,2047\(a1\)
+[ ]*[0-9a-f]+: 2105 f7ff sdm s0-s7,2047\(a1\)
+[ ]*[0-9a-f]+: 2125 f7ff sdm s0-s7,s8,2047\(a1\)
+[ ]*[0-9a-f]+: 2205 f7ff sdm ra,2047\(a1\)
+[ ]*[0-9a-f]+: 2225 f000 sdm s0,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2245 f000 sdm s0-s1,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2265 f000 sdm s0-s2,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2285 f000 sdm s0-s3,ra,0\(a1\)
+[ ]*[0-9a-f]+: 22a5 f000 sdm s0-s4,ra,0\(a1\)
+[ ]*[0-9a-f]+: 22c5 f000 sdm s0-s5,ra,0\(a1\)
+[ ]*[0-9a-f]+: 22e5 f000 sdm s0-s6,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2305 f000 sdm s0-s7,ra,0\(a1\)
+[ ]*[0-9a-f]+: 2325 f000 sdm s0-s7,s8,ra,0\(a1\)
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ ]*[0-9a-f]+: 2020 f000 sdm s0,0\(zero\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ ]*[0-9a-f]+: 303d 8000 addiu at,sp,-32768
+[ ]*[0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ ]*[0-9a-f]+: 303d 7fff addiu at,sp,32767
+[ ]*[0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ ]*[0-9a-f]+: 203d f000 sdm s0,0\(sp\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 03a1 0950 addu at,at,sp
+[ ]*[0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ ]*[0-9a-f]+: 03a1 0950 addu at,at,sp
+[ ]*[0-9a-f]+: 2021 f678 sdm s0,1656\(at\)
+[ ]*[0-9a-f]+: 2040 c000 sdp v0,0\(zero\)
+[ ]*[0-9a-f]+: 2040 c004 sdp v0,4\(zero\)
+[ ]*[0-9a-f]+: 205d c000 sdp v0,0\(sp\)
+[ ]*[0-9a-f]+: 205d c000 sdp v0,0\(sp\)
+[ ]*[0-9a-f]+: 2043 c800 sdp v0,-2048\(v1\)
+[ ]*[0-9a-f]+: 2043 c7ff sdp v0,2047\(v1\)
+[ ]*[0-9a-f]+: 3023 8000 addiu at,v1,-32768
+[ ]*[0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ ]*[0-9a-f]+: 3023 7fff addiu at,v1,32767
+[ ]*[0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ ]*[0-9a-f]+: 2043 c000 sdp v0,0\(v1\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ ]*[0-9a-f]+: 3020 8000 li at,-32768
+[ ]*[0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ ]*[0-9a-f]+: 3020 7fff li at,32767
+[ ]*[0-9a-f]+: 2041 c000 sdp v0,0\(at\)
+[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
+[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: 5021 5000 ori at,at,0x5000
+[ ]*[0-9a-f]+: 2041 c678 sdp v0,1656\(at\)
+[ ]*[0-9a-f]+: 3203 0000 addiu s0,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 6210 7000 lld s0,0\(s0\)
+[ ]*[0-9a-f]+: 3203 0000 addiu s0,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 6210 e000 lwu s0,0\(s0\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 6201 f000 scd s0,0\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2021 7000 ldm s0,0\(at\)
+[ ]*[0-9a-f]+: 3223 0000 addiu s1,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2211 4000 ldp s0,0\(s1\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2021 f000 sdm s0,0\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2201 c000 sdp s0,0\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2201 2000 ldc2 \$16,0\(at\)
+[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
+ [0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: 2201 a000 sdc2 \$16,0\(at\)
+
+[ 0-9a-f]+ <test_delay_slot>:
+[ ]*[0-9a-f]+: b3fe 0000 sltiu ra,s8,0
+ [0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
+[ ]*[0-9a-f]+: c063 fffe bgezalc v1,3ba2 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ ]*[0-9a-f]+: e063 fffe bltzalc v1,3ba6 <.*>
+ [0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ ]*[0-9a-f]+: b3fe 0000 sltiu ra,s8,0
+ [0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
+[ ]*[0-9a-f]+: 444b jalrc v0
+[ ]*[0-9a-f]+: 03e2 0f3c jalrc v0
+[ ]*[0-9a-f]+: 0c00 nop
+[ ]*[0-9a-f]+: 4443 jrc v0
+[ ]*[0-9a-f]+: 8002 0000 jrc v0
+[ ]*[0-9a-f]+: 03e2 1f3c jalrc.hb v0
+[ ]*[0-9a-f]+: 0002 1f3c jrc.hb v0
+[ ]*[0-9a-f]+: b3fe 0000 sltiu ra,s8,0
+ [0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
+[ ]*[0-9a-f]+: 444b jalrc v0
+[ ]*[0-9a-f]+: 03e2 0f3c jalrc v0
+
+[ 0-9a-f]+ <test_spec102>:
+[ ]*[0-9a-f]+: 6540 lw v0,-256\(gp\)
+[ ]*[0-9a-f]+: 65c0 lw v1,-256\(gp\)
+[ ]*[0-9a-f]+: 6640 lw a0,-256\(gp\)
+[ ]*[0-9a-f]+: 66c0 lw a1,-256\(gp\)
+[ ]*[0-9a-f]+: 6740 lw a2,-256\(gp\)
+[ ]*[0-9a-f]+: 67c0 lw a3,-256\(gp\)
+[ ]*[0-9a-f]+: 6440 lw s0,-256\(gp\)
+[ ]*[0-9a-f]+: 64c0 lw s1,-256\(gp\)
+[ ]*[0-9a-f]+: 64c1 lw s1,-252\(gp\)
+[ ]*[0-9a-f]+: 64ff lw s1,-4\(gp\)
+[ ]*[0-9a-f]+: 6480 lw s1,0\(gp\)
+[ ]*[0-9a-f]+: 6481 lw s1,4\(gp\)
+[ ]*[0-9a-f]+: 64be lw s1,248\(gp\)
+[ ]*[0-9a-f]+: 64bf lw s1,252\(gp\)
+[ ]*[0-9a-f]+: fe3c 0100 lw s1,256\(gp\)
+[ ]*[0-9a-f]+: fe3c fefc lw s1,-260\(gp\)
+[ ]*[0-9a-f]+: fe3c 0001 lw s1,1\(gp\)
+[ ]*[0-9a-f]+: fe3c 0002 lw s1,2\(gp\)
+[ ]*[0-9a-f]+: fe3c 0003 lw s1,3\(gp\)
+[ ]*[0-9a-f]+: fe3c ffff lw s1,-1\(gp\)
+[ ]*[0-9a-f]+: fe3c fffe lw s1,-2\(gp\)
+[ ]*[0-9a-f]+: fe3c fffd lw s1,-3\(gp\)
+[ ]*[0-9a-f]+: fe3b 0000 lw s1,0\(k1\)
+[ ]*[0-9a-f]+: 7840 0000 lapc v0,3c0c <.*>
+[ ]*[0-9a-f]+: 7860 0000 lapc v1,3c10 <.*>
+[ ]*[0-9a-f]+: 7880 0000 lapc a0,3c14 <.*>
+[ ]*[0-9a-f]+: 78a0 0000 lapc a1,3c18 <.*>
+[ ]*[0-9a-f]+: 78c0 0000 lapc a2,3c1c <.*>
+[ ]*[0-9a-f]+: 78e0 0000 lapc a3,3c20 <.*>
+[ ]*[0-9a-f]+: 7a00 0000 lapc s0,3c24 <.*>
+[ ]*[0-9a-f]+: 7a20 0000 lapc s1,3c28 <.*>
+[ ]*[0-9a-f]+: 7a23 ffff lapc s1,103c28 <.*>
+[ ]*[0-9a-f]+: 7a24 0000 lapc s1,fff03c30 <.*>
+[ ]*[0-9a-f]+: 7840 0000 lapc v0,3c34 <.*>
+[ ]*[0-9a-f]+: 7860 0000 lapc v1,3c38 <.*>
+[ ]*[0-9a-f]+: 7880 0000 lapc a0,3c3c <.*>
+[ ]*[0-9a-f]+: 78a0 0000 lapc a1,3c40 <.*>
+[ ]*[0-9a-f]+: 78c0 0000 lapc a2,3c44 <.*>
+[ ]*[0-9a-f]+: 78e0 0000 lapc a3,3c48 <.*>
+[ ]*[0-9a-f]+: 7a00 0000 lapc s0,3c4c <.*>
+[ ]*[0-9a-f]+: 7a20 0000 lapc s1,3c50 <.*>
+[ ]*[0-9a-f]+: 7a23 ffff lapc s1,103c50 <.*>
+[ ]*[0-9a-f]+: 7a24 0000 lapc s1,fff03c58 <.*>
+
+[ 0-9a-f]+ <test_spec107>:
+[ ]*[0-9a-f]+: 4404 movep a1,a2,zero,zero
+[ ]*[0-9a-f]+: 4484 movep a1,a3,zero,zero
+[ ]*[0-9a-f]+: 4504 movep a2,a3,zero,zero
+[ ]*[0-9a-f]+: 4584 movep a0,s5,zero,zero
+[ ]*[0-9a-f]+: 4604 movep a0,s6,zero,zero
+[ ]*[0-9a-f]+: 4684 movep a0,a1,zero,zero
+[ ]*[0-9a-f]+: 4704 movep a0,a2,zero,zero
+[ ]*[0-9a-f]+: 4784 movep a0,a3,zero,zero
+[ ]*[0-9a-f]+: 4785 movep a0,a3,s1,zero
+[ ]*[0-9a-f]+: 4786 movep a0,a3,v0,zero
+[ ]*[0-9a-f]+: 4787 movep a0,a3,v1,zero
+[ ]*[0-9a-f]+: 478c movep a0,a3,s0,zero
+[ ]*[0-9a-f]+: 478d movep a0,a3,s2,zero
+[ ]*[0-9a-f]+: 478e movep a0,a3,s3,zero
+[ ]*[0-9a-f]+: 478f movep a0,a3,s4,zero
+[ ]*[0-9a-f]+: 479f movep a0,a3,s4,s1
+[ ]*[0-9a-f]+: 47af movep a0,a3,s4,v0
+[ ]*[0-9a-f]+: 47bf movep a0,a3,s4,v1
+[ ]*[0-9a-f]+: 47cf movep a0,a3,s4,s0
+[ ]*[0-9a-f]+: 47df movep a0,a3,s4,s2
+[ ]*[0-9a-f]+: 47ef movep a0,a3,s4,s3
+[ ]*[0-9a-f]+: 47ff movep a0,a3,s4,s4
+[ ]*[0-9a-f]+: 0c00 nop
+[ ]*[0-9a-f]+: 0000 0000 nop
+#pass
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips32-cp2.d b/gas/testsuite/gas/mips/micromipsr6@mips32-cp2.d
new file mode 100644
index 00000000000..12681a4d90d
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips32-cp2.d
@@ -0,0 +1,16 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS32 cop2 instructions
+#source: micromips@mips32-cp2.s
+#as: -32
+
+# Check MIPS32 cop2 instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0022 cd3c cfc2 at,\$2
+[0-9a-f]+ <[^>]*> 0009 1a2a cop2 0x12345
+[0-9a-f]+ <[^>]*> 0043 dd3c ctc2 v0,\$3
+[0-9a-f]+ <[^>]*> 0064 4d3c mfc2 v1,\$4
+[0-9a-f]+ <[^>]*> 00c7 5d3c mtc2 a2,\$7
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips32-dsp.d b/gas/testsuite/gas/mips/micromipsr6@mips32-dsp.d
new file mode 100644
index 00000000000..a6a2ac222d7
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips32-dsp.d
@@ -0,0 +1,148 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE for MIPS32
+#as: -mdspr3 -32
+#source: mips32-dsp.s
+
+# Check MIPS DSP ASE for MIPS32 Instruction Assembly (microMIPS)
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> 0041 000d addq\.ph zero,at,v0
+0+0004 <[^>]*> 0062 0c0d addq_s\.ph at,v0,v1
+0+0008 <[^>]*> 0083 1305 addq_s\.w v0,v1,a0
+0+000c <[^>]*> 00a4 18cd addu\.qb v1,a0,a1
+0+0010 <[^>]*> 00c5 24cd addu_s\.qb a0,a1,a2
+0+0014 <[^>]*> 00e6 2a0d subq\.ph a1,a2,a3
+0+0018 <[^>]*> 0107 360d subq_s\.ph a2,a3,t0
+0+001c <[^>]*> 0128 3b45 subq_s\.w a3,t0,t1
+0+0020 <[^>]*> 0149 42cd subu\.qb t0,t1,t2
+0+0024 <[^>]*> 016a 4ecd subu_s\.qb t1,t2,t3
+0+0028 <[^>]*> 018b 5385 addsc t2,t3,t4
+0+002c <[^>]*> 01ac 5bc5 addwc t3,t4,t5
+0+0030 <[^>]*> 01cd 6295 modsub t4,t5,t6
+0+0034 <[^>]*> 01ae f13c raddu\.w\.qb t5,t6
+0+0038 <[^>]*> 01cf 113c absq_s\.ph t6,t7
+0+003c <[^>]*> 01f0 213c absq_s\.w t7,s0
+0+0040 <[^>]*> 0251 80ad precrq\.qb\.ph s0,s1,s2
+0+0044 <[^>]*> 0272 88ed precrq\.ph\.w s1,s2,s3
+0+0048 <[^>]*> 0293 912d precrq_rs\.ph\.w s2,s3,s4
+0+004c <[^>]*> 02b4 996d precrqu_s\.qb\.ph s3,s4,s5
+0+0050 <[^>]*> 0295 513c preceq\.w\.phl s4,s5
+0+0054 <[^>]*> 02b6 613c preceq\.w\.phr s5,s6
+0+0058 <[^>]*> 02d7 713c precequ\.ph\.qbl s6,s7
+0+005c <[^>]*> 02f8 913c precequ\.ph\.qbr s7,t8
+0+0060 <[^>]*> 0319 733c precequ\.ph\.qbla t8,t9
+0+0064 <[^>]*> 033a 933c precequ\.ph\.qbra t9,k0
+0+0068 <[^>]*> 035b b13c preceu\.ph\.qbl k0,k1
+0+006c <[^>]*> 037c d13c preceu\.ph\.qbr k1,gp
+0+0070 <[^>]*> 039d b33c preceu\.ph\.qbla gp,sp
+0+0074 <[^>]*> 03be d33c preceu\.ph\.qbra sp,s8
+0+0078 <[^>]*> 03df 087c shll\.qb s8,ra,0x0
+0+007c <[^>]*> 03df e87c shll\.qb s8,ra,0x7
+0+0080 <[^>]*> 0001 fb95 shllv\.qb ra,zero,at
+0+0084 <[^>]*> 0001 03b5 shll\.ph zero,at,0x0
+0+0088 <[^>]*> 0001 f3b5 shll\.ph zero,at,0xf
+0+008c <[^>]*> 0043 0b8d shllv\.ph at,v0,v1
+0+0090 <[^>]*> 0043 0bb5 shll_s\.ph v0,v1,0x0
+0+0094 <[^>]*> 0043 fbb5 shll_s\.ph v0,v1,0xf
+0+0098 <[^>]*> 0085 1f8d shllv_s\.ph v1,a0,a1
+0+009c <[^>]*> 0085 03f5 shll_s\.w a0,a1,0x0
+0+00a0 <[^>]*> 0085 fbf5 shll_s\.w a0,a1,0x1f
+0+00a4 <[^>]*> 00c7 2bd5 shllv_s\.w a1,a2,a3
+0+00a8 <[^>]*> 00c7 187c shrl\.qb a2,a3,0x0
+0+00ac <[^>]*> 00c7 f87c shrl\.qb a2,a3,0x7
+0+00b0 <[^>]*> 0109 3b55 shrlv\.qb a3,t0,t1
+0+00b4 <[^>]*> 0109 0335 shra\.ph t0,t1,0x0
+0+00b8 <[^>]*> 0109 f335 shra\.ph t0,t1,0xf
+0+00bc <[^>]*> 014b 498d shrav\.ph t1,t2,t3
+0+00c0 <[^>]*> 014b 0735 shra_r\.ph t2,t3,0x0
+0+00c4 <[^>]*> 014b f735 shra_r\.ph t2,t3,0xf
+0+00c8 <[^>]*> 018d 5d8d shrav_r\.ph t3,t4,t5
+0+00cc <[^>]*> 018d 02f5 shra_r\.w t4,t5,0x0
+0+00d0 <[^>]*> 018d faf5 shra_r\.w t4,t5,0x1f
+0+00d4 <[^>]*> 01cf 6ad5 shrav_r\.w t5,t6,t7
+0+00d8 <[^>]*> 020f 7095 muleu_s\.ph\.qbl t6,t7,s0
+0+00dc <[^>]*> 0230 78d5 muleu_s\.ph\.qbr t7,s0,s1
+0+00e0 <[^>]*> 0251 8115 mulq_rs\.ph s0,s1,s2
+0+00e4 <[^>]*> 0272 8825 muleq_s\.w\.phl s1,s2,s3
+0+00e8 <[^>]*> 0293 9065 muleq_s\.w\.phr s2,s3,s4
+0+00ec <[^>]*> 0293 20bc dpau\.h\.qbl \$ac0,s3,s4
+0+00f0 <[^>]*> 02b4 70bc dpau\.h\.qbr \$ac1,s4,s5
+0+00f4 <[^>]*> 02d5 a4bc dpsu\.h\.qbl \$ac2,s5,s6
+0+00f8 <[^>]*> 02f6 f4bc dpsu\.h\.qbr \$ac3,s6,s7
+0+00fc <[^>]*> 0317 02bc dpaq_s\.w\.ph \$ac0,s7,t8
+0+0100 <[^>]*> 0338 46bc dpsq_s\.w\.ph \$ac1,t8,t9
+0+0104 <[^>]*> 0359 bcbc mulsaq_s\.w\.ph \$ac2,t9,k0
+0+0108 <[^>]*> 037a d2bc dpaq_sa.l\.w \$ac3,k0,k1
+0+010c <[^>]*> 039b 16bc dpsq_sa.l\.w \$ac0,k1,gp
+0+0110 <[^>]*> 03bc 5a7c maq_s\.w\.phl \$ac1,gp,sp
+0+0114 <[^>]*> 03dd 8a7c maq_s\.w\.phr \$ac2,sp,s8
+0+0118 <[^>]*> 03fe fa7c maq_sa\.w\.phl \$ac3,s8,ra
+0+011c <[^>]*> 001f 2a7c maq_sa\.w\.phr \$ac0,ra,zero
+0+0120 <[^>]*> 0001 313c bitrev zero,at
+0+0124 <[^>]*> 0022 413c insv at,v0
+0+0128 <[^>]*> 0040 05fc repl\.qb v0,0x0
+0+012c <[^>]*> 005f e5fc repl\.qb v0,0xff
+0+0130 <[^>]*> 0064 133c replv\.qb v1,a0
+0+0134 <[^>]*> 0200 203d repl\.ph a0,-512
+0+0138 <[^>]*> 01ff 203d repl\.ph a0,511
+0+013c <[^>]*> 00a6 033c replv\.ph a1,a2
+0+0140 <[^>]*> 00e6 0245 cmpu\.eq\.qb a2,a3
+0+0144 <[^>]*> 0107 0285 cmpu\.lt\.qb a3,t0
+0+0148 <[^>]*> 0128 02c5 cmpu\.le\.qb t0,t1
+0+014c <[^>]*> 016a 48c5 cmpgu\.eq\.qb t1,t2,t3
+0+0150 <[^>]*> 018b 5105 cmpgu\.lt\.qb t2,t3,t4
+0+0154 <[^>]*> 01ac 5945 cmpgu\.le\.qb t3,t4,t5
+0+0158 <[^>]*> 01ac 0005 cmp\.eq\.ph t4,t5
+0+015c <[^>]*> 01cd 0045 cmp\.lt\.ph t5,t6
+0+0160 <[^>]*> 01ee 0085 cmp\.le\.ph t6,t7
+0+0164 <[^>]*> 0230 79ed pick\.qb t7,s0,s1
+0+0168 <[^>]*> 0251 822d pick\.ph s0,s1,s2
+0+016c <[^>]*> 0272 89ad packrl\.ph s1,s2,s3
+0+0170 <[^>]*> 0240 4e7c extr\.w s2,\$ac1,0x0
+0+0174 <[^>]*> 025f 4e7c extr\.w s2,\$ac1,0x1f
+0+0178 <[^>]*> 0260 9e7c extr_r\.w s3,\$ac2,0x0
+0+017c <[^>]*> 027f 9e7c extr_r\.w s3,\$ac2,0x1f
+0+0180 <[^>]*> 0280 ee7c extr_rs\.w s4,\$ac3,0x0
+0+0184 <[^>]*> 029f ee7c extr_rs\.w s4,\$ac3,0x1f
+0+0188 <[^>]*> 02a0 3e7c extr_s\.h s5,\$ac0,0x0
+0+018c <[^>]*> 02bf 3e7c extr_s\.h s5,\$ac0,0x1f
+0+0190 <[^>]*> 02d7 7ebc extrv_s\.h s6,\$ac1,s7
+0+0194 <[^>]*> 02f8 8ebc extrv\.w s7,\$ac2,t8
+0+0198 <[^>]*> 0319 debc extrv_r\.w t8,\$ac3,t9
+0+019c <[^>]*> 033a 2ebc extrv_rs\.w t9,\$ac0,k0
+0+01a0 <[^>]*> 0340 667c extp k0,\$ac1,0x0
+0+01a4 <[^>]*> 035f 667c extp k0,\$ac1,0x1f
+0+01a8 <[^>]*> 037c a8bc extpv k1,\$ac2,gp
+0+01ac <[^>]*> 0380 f67c extpdp gp,\$ac3,0x0
+0+01b0 <[^>]*> 039f f67c extpdp gp,\$ac3,0x1f
+0+01b4 <[^>]*> 03be 38bc extpdpv sp,\$ac0,s8
+0+01b8 <[^>]*> 0020 401d shilo \$ac1,-32
+0+01bc <[^>]*> 001f 401d shilo \$ac1,31
+0+01c0 <[^>]*> 001e 927c shilov \$ac2,s8
+0+01c4 <[^>]*> 001f c27c mthlip ra,\$ac3
+0+01c8 <[^>]*> 0000 007c mfhi zero,\$ac0
+0+01cc <[^>]*> 0001 507c mflo at,\$ac1
+0+01d0 <[^>]*> 0002 a07c mthi v0,\$ac2
+0+01d4 <[^>]*> 0003 f07c mtlo v1,\$ac3
+0+01d8 <[^>]*> 0080 167c wrdsp a0,0x0
+0+01dc <[^>]*> 008f d67c wrdsp a0
+0+01e0 <[^>]*> 00af d67c wrdsp a1
+0+01e4 <[^>]*> 00c0 067c rddsp a2,0x0
+0+01e8 <[^>]*> 00cf c67c rddsp a2
+0+01ec <[^>]*> 00ef c67c rddsp a3
+0+01f0 <[^>]*> 012a 4225 lbux t0,t1\(t2\)
+0+01f4 <[^>]*> 014b 4965 lhx t1,t2\(t3\)
+0+01f8 <[^>]*> 016c 51a5 lwx t2,t3\(t4\)
+0+01fc <[^>]*> 4320 fffe bposge32c 000001fc <text_label\+0x1fc>
+ 1fc: R_MICROMIPS_PC16_S1 text_label
+0+0200 <[^>]*> 0c00 nop
+0+0202 <[^>]*> 018b 8abc madd \$ac2,t3,t4
+0+0206 <[^>]*> 01ac dabc maddu \$ac3,t4,t5
+0+020a <[^>]*> 01cd 2abc msub \$ac0,t5,t6
+0+020e <[^>]*> 01ee 7abc msubu \$ac1,t6,t7
+0+0212 <[^>]*> 02d5 ccbc mult \$ac3,s5,s6
+0+0216 <[^>]*> 02f6 1cbc multu \$ac0,s6,s7
+0+021a <[^>]*> 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips32-dspr2.d b/gas/testsuite/gas/mips/micromipsr6@mips32-dspr2.d
new file mode 100644
index 00000000000..18b5c0ea1b9
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips32-dspr2.d
@@ -0,0 +1,74 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE Rev2 for MIPS32
+#as: -mdspr3 -32
+#source: mips32-dspr2.s
+
+# Check MIPS DSP ASE Rev2 for MIPS32 Instruction Assembly (microMIPS)
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+0+0000 <[^>]*> 0001 013c absq_s\.qb zero,at
+0+0004 <[^>]*> 0062 090d addu\.ph at,v0,v1
+0+0008 <[^>]*> 0083 150d addu_s\.ph v0,v1,a0
+0+000c <[^>]*> 00a4 194d adduh\.qb v1,a0,a1
+0+0010 <[^>]*> 00c5 254d adduh_r\.qb a0,a1,a2
+0+0014 <[^>]*> 00a6 0215 append a1,a2,0x0
+0+0018 <[^>]*> 00a6 fa15 append a1,a2,0x1f
+0+001c <[^>]*> 0c00 nop
+0+001e <[^>]*> 00c7 48bc balign a2,a3,0x1
+0+0022 <[^>]*> 00e6 31ad packrl\.ph a2,a2,a3
+0+0026 <[^>]*> 00c7 c8bc balign a2,a3,0x3
+0+002a <[^>]*> 0107 3185 cmpgdu\.eq\.qb a2,a3,t0
+0+002e <[^>]*> 0128 39c5 cmpgdu\.lt\.qb a3,t0,t1
+0+0032 <[^>]*> 0149 4205 cmpgdu\.le\.qb t0,t1,t2
+0+0036 <[^>]*> 0149 00bc dpa\.w\.ph \$ac0,t1,t2
+0+003a <[^>]*> 016a 44bc dps\.w\.ph \$ac1,t2,t3
+0+003e <[^>]*> 018b 8abc madd \$ac2,t3,t4
+0+0042 <[^>]*> 01ac dabc maddu \$ac3,t4,t5
+0+0046 <[^>]*> 01cd 2abc msub \$ac0,t5,t6
+0+004a <[^>]*> 01ee 7abc msubu \$ac1,t6,t7
+0+004e <[^>]*> 0230 782d mul\.ph t7,s0,s1
+0+0052 <[^>]*> 0251 842d mul_s\.ph s0,s1,s2
+0+0056 <[^>]*> 0272 8995 mulq_rs\.w s1,s2,s3
+0+005a <[^>]*> 0293 9155 mulq_s\.ph s2,s3,s4
+0+005e <[^>]*> 02b4 99d5 mulq_s\.w s3,s4,s5
+0+0062 <[^>]*> 02b4 acbc mulsa\.w\.ph \$ac2,s4,s5
+0+0066 <[^>]*> 02d5 ccbc mult \$ac3,s5,s6
+0+006a <[^>]*> 02f6 1cbc multu \$ac0,s6,s7
+0+006e <[^>]*> 0338 b86d precr\.qb\.ph s7,t8,t9
+0+0072 <[^>]*> 0319 03cd precr_sra\.ph\.w t8,t9,0x0
+0+0076 <[^>]*> 0319 fbcd precr_sra\.ph\.w t8,t9,0x1f
+0+007a <[^>]*> 033a 07cd precr_sra_r\.ph\.w t9,k0,0x0
+0+007e <[^>]*> 033a ffcd precr_sra_r\.ph\.w t9,k0,0x1f
+0+0082 <[^>]*> 035b 0255 prepend k0,k1,0x0
+0+0086 <[^>]*> 035b fa55 prepend k0,k1,0x1f
+0+008a <[^>]*> 037c 01fc shra\.qb k1,gp,0x0
+0+008e <[^>]*> 037c e1fc shra\.qb k1,gp,0x7
+0+0092 <[^>]*> 039d 11fc shra_r\.qb gp,sp,0x0
+0+0096 <[^>]*> 039d f1fc shra_r\.qb gp,sp,0x7
+0+009a <[^>]*> 03df e9cd shrav\.qb sp,s8,ra
+0+009e <[^>]*> 03e0 f5cd shrav_r\.qb s8,ra,zero
+0+00a2 <[^>]*> 03e0 03fc shrl\.ph ra,zero,0x0
+0+00a6 <[^>]*> 03e0 f3fc shrl\.ph ra,zero,0xf
+0+00aa <[^>]*> 0022 0315 shrlv\.ph zero,at,v0
+0+00ae <[^>]*> 0062 0b0d subu\.ph at,v0,v1
+0+00b2 <[^>]*> 0083 170d subu_s\.ph v0,v1,a0
+0+00b6 <[^>]*> 00a4 1b4d subuh\.qb v1,a0,a1
+0+00ba <[^>]*> 00c5 274d subuh_r\.qb a0,a1,a2
+0+00be <[^>]*> 00e6 284d addqh\.ph a1,a2,a3
+0+00c2 <[^>]*> 0107 344d addqh_r\.ph a2,a3,t0
+0+00c6 <[^>]*> 0128 388d addqh\.w a3,t0,t1
+0+00ca <[^>]*> 0149 448d addqh_r\.w t0,t1,t2
+0+00ce <[^>]*> 016a 4a4d subqh\.ph t1,t2,t3
+0+00d2 <[^>]*> 018b 564d subqh_r\.ph t2,t3,t4
+0+00d6 <[^>]*> 01ac 5a8d subqh\.w t3,t4,t5
+0+00da <[^>]*> 01cd 668d subqh_r\.w t4,t5,t6
+0+00de <[^>]*> 01cd 50bc dpax\.w\.ph \$ac1,t5,t6
+0+00e2 <[^>]*> 01ee 94bc dpsx\.w\.ph \$ac2,t6,t7
+0+00e6 <[^>]*> 020f e2bc dpaqx_s\.w\.ph \$ac3,t7,s0
+0+00ea <[^>]*> 0230 32bc dpaqx_sa\.w\.ph \$ac0,s0,s1
+0+00ee <[^>]*> 0251 66bc dpsqx_s\.w\.ph \$ac1,s1,s2
+0+00f2 <[^>]*> 0272 b6bc dpsqx_sa\.w\.ph \$ac2,s2,s3
+0+00f6 <[^>]*> 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips32-dspr3.d b/gas/testsuite/gas/mips/micromipsr6@mips32-dspr3.d
new file mode 100644
index 00000000000..e126180596a
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips32-dspr3.d
@@ -0,0 +1,23 @@
+#objdump: -pdr --prefix-addresses --show-raw-insn
+#name: MIPS DSP ASE Rev3 for MIPS32
+#source: mips32-dspr3.s
+#as: -mdspr3 -32
+
+# Check MIPS DSP ASE Rev3 for MIPS32 Instruction Assembly
+
+.*: +file format .*mips.*
+#...
+ASEs:
+#...
+ DSP ASE
+ DSP R2 ASE
+ DSP R3 ASE
+#...
+FLAGS 1: .*
+FLAGS 2: .*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 4320 fffe bposge32c 00000000 <text_label>
+.*0: R_MICROMIPS_PC16_S1 text_label
+
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips32-sf32.d b/gas/testsuite/gas/mips/micromipsr6@mips32-sf32.d
new file mode 100644
index 00000000000..ae63e8368de
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips32-sf32.d
@@ -0,0 +1,20 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS32 odd single-precision float registers
+#source: mips32-sf32.s
+#as: -32
+
+# Check MIPS32 instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1020 3f80 lui \$1,0x3f80
+[0-9a-f]+ <[^>]*> 5421 283b mtc1 \$1,\$f1
+[0-9a-f]+ <[^>]*> 9c7c 0000 lwc1 \$f3,0\(\$28\)
+[ ]*[0-9a-f]+: R_MICROMIPS_LITERAL \.lit4
+[0-9a-f]+ <[^>]*> 5461 2830 add\.s \$f5,\$f1,\$f3
+[0-9a-f]+ <[^>]*> 5507 137b cvt\.d\.s \$f8,\$f7
+[0-9a-f]+ <[^>]*> 5507 337b cvt\.d\.w \$f8,\$f7
+[0-9a-f]+ <[^>]*> 54e8 1b7b cvt\.s\.d \$f7,\$f8
+[0-9a-f]+ <[^>]*> 54e8 6b3b trunc\.w\.d \$f7,\$f8
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips32.d b/gas/testsuite/gas/mips/micromipsr6@mips32.d
new file mode 100644
index 00000000000..f783ec28f78
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips32.d
@@ -0,0 +1,32 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS MIPS32 instructions
+#source: mips32.s
+#as: -32
+
+# Check MIPS32 instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0022 4b3c clo at,v0
+[0-9a-f]+ <[^>]*> 0064 5b3c clz v1,a0
+[0-9a-f]+ <[^>]*> 01ee 6818 mul t5,t6,t7
+[0-9a-f]+ <[^>]*> 6090 2000 pref 0x4,0\(s0\)
+[0-9a-f]+ <[^>]*> 0000 0800 ssnop
+[0-9a-f]+ <[^>]*> 20a1 6000 cache 0x5,0\(at\)
+[0-9a-f]+ <[^>]*> 0000 f37c eret
+[0-9a-f]+ <[^>]*> 0000 037c tlbp
+[0-9a-f]+ <[^>]*> 0000 137c tlbr
+[0-9a-f]+ <[^>]*> 0000 237c tlbwi
+[0-9a-f]+ <[^>]*> 0000 337c tlbwr
+[0-9a-f]+ <[^>]*> 0000 937c wait
+[0-9a-f]+ <[^>]*> 0000 937c wait
+[0-9a-f]+ <[^>]*> 0345 937c wait 0x345
+[0-9a-f]+ <[^>]*> 441b break
+[0-9a-f]+ <[^>]*> 441b break
+[0-9a-f]+ <[^>]*> 0345 0007 break 0x345
+[0-9a-f]+ <[^>]*> 0048 d147 break 0x48,0x345
+[0-9a-f]+ <[^>]*> 443b sdbbp
+[0-9a-f]+ <[^>]*> 443b sdbbp
+[0-9a-f]+ <[^>]*> 0345 db7c sdbbp 0x345
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips32r2.d b/gas/testsuite/gas/mips/micromipsr6@mips32r2.d
new file mode 100644
index 00000000000..5c81def8e12
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips32r2.d
@@ -0,0 +1,49 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS MIPS32r2 non-fp instructions
+#source: mips32r2.s
+#as: -32
+
+# Check MIPS32 Release 2 (mips32r2) *non-fp* instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0000 1800 ehb
+[0-9a-f]+ <[^>]*> 0085 39ac ext \$4,\$5,0x6,0x8
+[0-9a-f]+ <[^>]*> 0085 698c ins \$4,\$5,0x6,0x8
+[0-9a-f]+ <[^>]*> 03e8 1f3c jalrc\.hb \$8
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0289 1f3c jalrc\.hb \$20,\$9
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0008 1f3c jrc\.hb \$8
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0140 01c0 rdhwr \$10,\$0
+[0-9a-f]+ <[^>]*> 0161 01c0 rdhwr \$11,\$1
+[0-9a-f]+ <[^>]*> 0182 01c0 rdhwr \$12,\$2
+[0-9a-f]+ <[^>]*> 01a3 01c0 rdhwr \$13,\$3
+[0-9a-f]+ <[^>]*> 01c4 01c0 rdhwr \$14,\$4
+[0-9a-f]+ <[^>]*> 01e5 01c0 rdhwr \$15,\$5
+[0-9a-f]+ <[^>]*> 032a e0c0 ror \$25,\$10,0x1c
+[0-9a-f]+ <[^>]*> 032a 20c0 ror \$25,\$10,0x4
+[0-9a-f]+ <[^>]*> 0080 c9d0 negu \$25,\$4
+[0-9a-f]+ <[^>]*> 0159 c8d0 rorv \$25,\$10,\$25
+[0-9a-f]+ <[^>]*> 0144 c8d0 rorv \$25,\$10,\$4
+[0-9a-f]+ <[^>]*> 0144 c8d0 rorv \$25,\$10,\$4
+[0-9a-f]+ <[^>]*> 00e7 2b3c seb \$7,\$7
+[0-9a-f]+ <[^>]*> 010a 2b3c seb \$8,\$10
+[0-9a-f]+ <[^>]*> 00e7 3b3c seh \$7,\$7
+[0-9a-f]+ <[^>]*> 010a 3b3c seh \$8,\$10
+[0-9a-f]+ <[^>]*> 418a 5555 synci 21845\(\$10\)
+[0-9a-f]+ <[^>]*> 00e7 7b3c wsbh \$7,\$7
+[0-9a-f]+ <[^>]*> 010a 7b3c wsbh \$8,\$10
+[0-9a-f]+ <[^>]*> 0000 477c di
+[0-9a-f]+ <[^>]*> 0000 477c di
+[0-9a-f]+ <[^>]*> 000a 477c di \$10
+[0-9a-f]+ <[^>]*> 0000 577c ei
+[0-9a-f]+ <[^>]*> 0000 577c ei
+[0-9a-f]+ <[^>]*> 000a 577c ei \$10
+[0-9a-f]+ <[^>]*> 0159 e17c rdpgpr \$10,\$25
+[0-9a-f]+ <[^>]*> 0159 f17c wrpgpr \$10,\$25
+[0-9a-f]+ <[^>]*> 0000 2800 pause
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips4-fp.d b/gas/testsuite/gas/mips/micromipsr6@mips4-fp.d
new file mode 100644
index 00000000000..a81a4233c9f
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips4-fp.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses
+#name: MIPS mips4 fp
+
+# Test mips4 fp instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> recip.d \$f4,\$f6
+[0-9a-f]+ <[^>]*> recip.s \$f4,\$f6
+[0-9a-f]+ <[^>]*> rsqrt.d \$f4,\$f6
+[0-9a-f]+ <[^>]*> rsqrt.s \$f4,\$f6
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips4-fp.s b/gas/testsuite/gas/mips/micromipsr6@mips4-fp.s
new file mode 100644
index 00000000000..4d124e5327a
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips4-fp.s
@@ -0,0 +1,11 @@
+# Source file used to test -mips4 fp instructions.
+
+text_label:
+ recip.d $f4,$f6
+ recip.s $f4,$f6
+ rsqrt.d $f4,$f6
+ rsqrt.s $f4,$f6
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
+ .space 8
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips4.d b/gas/testsuite/gas/mips/micromipsr6@mips4.d
new file mode 100644
index 00000000000..8bb7b575870
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips4.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS mips4 non-fp
+#source: mips4.s
+
+# Test mips4 *non-fp* instructions (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 6084 2000 pref 0x4,0\(a0\)
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips5-fp.d b/gas/testsuite/gas/mips/micromipsr6@mips5-fp.d
new file mode 100644
index 00000000000..1d526b12982
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips5-fp.d
@@ -0,0 +1,11 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M reg-names=numeric
+#name: MIPS mips5 instructions
+
+# Check MIPS V instruction assembly
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 5612 213b cvt\.s\.pl \$f16,\$f18
+[0-9a-f]+ <[^>]*> 5654 293b cvt\.s\.pu \$f18,\$f20
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@mips5-fp.s b/gas/testsuite/gas/mips/micromipsr6@mips5-fp.s
new file mode 100644
index 00000000000..6bee111a4a4
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@mips5-fp.s
@@ -0,0 +1,8 @@
+# Source file used to test -mips5 instructions.
+
+text_label:
+ cvt.s.pl $f16, $f18
+ cvt.s.pu $f18, $f20
+
+# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .space 8
diff --git a/gas/testsuite/gas/mips/micromipsr6@pcrel-reloc-4-r6.d b/gas/testsuite/gas/mips/micromipsr6@pcrel-reloc-4-r6.d
new file mode 100644
index 00000000000..d81a68e061c
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@pcrel-reloc-4-r6.d
@@ -0,0 +1,69 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS local PC-relative relocations 4
+#as: -32
+#source: pcrel-reloc-4.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> cfff bc 00000000 <foo>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 bar
+[0-9a-f]+ <[^>]*> cfff bc 00000002 <foo\+0x2>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 bar
+[0-9a-f]+ <[^>]*> cfff bc 00000004 <foo\+0x4>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 bar
+[0-9a-f]+ <[^>]*> cfff bc 00000006 <foo\+0x6>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 bar
+[0-9a-f]+ <[^>]*> cfff bc 00000008 <foo\+0x8>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 bar
+[0-9a-f]+ <[^>]*> cfff bc 0000000a <foo\+0xa>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 bar
+[0-9a-f]+ <[^>]*> cfff bc 0000000c <foo\+0xc>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 bar
+[0-9a-f]+ <[^>]*> cfff bc 0000000e <foo\+0xe>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 bar
+[0-9a-f]+ <[^>]*> 8d7f beqzc v0,00000010 <foo\+0x10>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 bar
+[0-9a-f]+ <[^>]*> 8d7f beqzc v0,00000012 <foo\+0x12>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 bar
+[0-9a-f]+ <[^>]*> 8d7f beqzc v0,00000014 <foo\+0x14>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 bar
+[0-9a-f]+ <[^>]*> 8d7f beqzc v0,00000016 <foo\+0x16>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 bar
+[0-9a-f]+ <[^>]*> 7848 0000 lwpc v0,00000018 <foo\+0x18>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC19_S2 bar
+[0-9a-f]+ <[^>]*> 7848 0000 lwpc v0,0000001c <foo\+0x1c>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC19_S2 bar
+[0-9a-f]+ <[^>]*> 7848 0000 lwpc v0,00000020 <foo\+0x20>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC19_S2 bar
+[0-9a-f]+ <[^>]*> 7848 0000 lwpc v0,00000024 <foo\+0x24>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC19_S2 bar
+[0-9a-f]+ <[^>]*> 7858 0000 ldpc v0,00000028 <foo\+0x28>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC18_S3 bar
+[0-9a-f]+ <[^>]*> 7858 0000 ldpc v0,00000028 <foo\+0x28>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC18_S3 bar
+[0-9a-f]+ <[^>]*> 7858 0000 ldpc v0,00000030 <foo\+0x30>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC18_S3 bar
+[0-9a-f]+ <[^>]*> 7858 0000 ldpc v0,00000030 <foo\+0x30>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC18_S3 bar
+[0-9a-f]+ <[^>]*> 785f 0000 aluipc v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_PCHI16 \.text
+[0-9a-f]+ <[^>]*> 3057 0000 addiu v0,s7,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PCLO16 \.text
+[0-9a-f]+ <[^>]*> 785f 0000 aluipc v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_PCHI16 \.text
+[0-9a-f]+ <[^>]*> 3057 0000 addiu v0,s7,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PCLO16 \.text
+[0-9a-f]+ <[^>]*> 785f 0000 aluipc v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_PCHI16 \.text
+[0-9a-f]+ <[^>]*> 3057 0000 addiu v0,s7,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PCLO16 \.text
+[0-9a-f]+ <[^>]*> 785f 0000 aluipc v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_PCHI16 \.text
+[0-9a-f]+ <[^>]*> 3057 0000 addiu v0,s7,0
+[ ]*[0-9a-f]+: R_MICROMIPS_PCLO16 \.text
+ \.\.\.
+[0-9a-f]+ <[^>]*> 001f 0f3c jrc ra
+ \.\.\.
+[0-9a-f]+ <[^>]*> 001f 0f3c jrc ra
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@pref.d b/gas/testsuite/gas/mips/micromipsr6@pref.d
new file mode 100644
index 00000000000..9ea32f02b6d
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@pref.d
@@ -0,0 +1,13 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS PREF instruction
+#as: -32 --defsym micromips=1 --defsym tpref=1
+#source: cache.s
+
+# Check MIPS CACHE instruction assembly (microMIPS).
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 60a2 20ff pref 0x5,255\(v0\)
+[0-9a-f]+ <[^>]*> 60a3 2100 pref 0x5,-256\(v1\)
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@r5.d b/gas/testsuite/gas/mips/micromipsr6@r5.d
new file mode 100644
index 00000000000..bf0e2f71ed0
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@r5.d
@@ -0,0 +1,9 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#source: r5.s
+#name: Test MIPS32r5 instructions
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 0001 f37c eretnc
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@r6-branch-constraints.l b/gas/testsuite/gas/mips/micromipsr6@r6-branch-constraints.l
new file mode 100644
index 00000000000..c9926486e08
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@r6-branch-constraints.l
@@ -0,0 +1,21 @@
+.*: Assembler messages:
+.*:2: Error: the source register must not be \$0 `blezc \$0,.'
+.*:3: Error: the source register must not be \$0 `bgezc \$0,.'
+.*:4: Error: the source register must not be \$0 `bgtzc \$0,.'
+.*:5: Error: the source register must not be \$0 `bltzc \$0,.'
+.*:6: Error: the source register must not be \$0 `beqzc \$0,.'
+.*:7: Error: the source register must not be \$0 `bnezc \$0,.'
+.*:8: Error: the source register must not be \$0 `bgec \$0,\$2,.'
+.*:9: Error: invalid operands `bgec \$2,\$0,.'
+.*:10: Error: invalid operands `bgec \$2,\$2,.'
+.*:11: Error: the source register must not be \$0 `bgeuc \$0,\$2,.'
+.*:12: Error: invalid operands `bgeuc \$2,\$0,.'
+.*:13: Error: invalid operands `bgeuc \$2,\$2,.'
+.*:14: Error: the source register must not be \$0 `bltc \$0,\$2,.'
+.*:15: Error: invalid operands `bltc \$2,\$0,.'
+.*:16: Error: invalid operands `bltc \$2,\$2,.'
+.*:17: Error: the source register must not be \$0 `bltuc \$0,\$2,.'
+.*:18: Error: invalid operands `bltuc \$2,\$0,.'
+.*:19: Error: invalid operands `bltuc \$2,\$2,.'
+.*:20: Error: invalid operands `beqc \$2,\$2,.'
+.*:21: Error: invalid operands `bnec \$2,\$2,.'
diff --git a/gas/testsuite/gas/mips/micromipsr6@r6-branch-constraints.s b/gas/testsuite/gas/mips/micromipsr6@r6-branch-constraints.s
new file mode 100644
index 00000000000..70bc5550547
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@r6-branch-constraints.s
@@ -0,0 +1,21 @@
+ .text
+ blezc $0,.
+ bgezc $0,.
+ bgtzc $0,.
+ bltzc $0,.
+ beqzc $0,.
+ bnezc $0,.
+ bgec $0,$2,.
+ bgec $2,$0,.
+ bgec $2,$2,.
+ bgeuc $0,$2,.
+ bgeuc $2,$0,.
+ bgeuc $2,$2,.
+ bltc $0,$2,.
+ bltc $2,$0,.
+ bltc $2,$2,.
+ bltuc $0,$2,.
+ bltuc $2,$0,.
+ bltuc $2,$2,.
+ beqc $2,$2,.
+ bnec $2,$2,.
diff --git a/gas/testsuite/gas/mips/micromipsr6@relax-swap3.d b/gas/testsuite/gas/mips/micromipsr6@relax-swap3.d
new file mode 100644
index 00000000000..2f639518410
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@relax-swap3.d
@@ -0,0 +1,20 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS relaxed macro with branch swapping
+#as: -32
+#source: relax-swap3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 1040 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 bar
+[0-9a-f]+ <[^>]*> 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 bar
+[0-9a-f]+ <[^>]*> 4463 jrc v1
+[0-9a-f]+ <[^>]*> 1040 0000 lui v0,0x0
+[ ]*[0-9a-f]+: R_MICROMIPS_HI16 bar
+[0-9a-f]+ <[^>]*> 3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: R_MICROMIPS_LO16 bar
+[0-9a-f]+ <[^>]*> 8dff beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .*
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/micromipsr6@rfe.d b/gas/testsuite/gas/mips/micromipsr6@rfe.d
new file mode 100644
index 00000000000..6e87e4ee5d1
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@rfe.d
@@ -0,0 +1,5 @@
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS RFE instruction
+#as: -32
+#source: rfe.s
+#error_output: micromipsr6@rfe.l
diff --git a/gas/testsuite/gas/mips/micromipsr6@rfe.l b/gas/testsuite/gas/mips/micromipsr6@rfe.l
new file mode 100644
index 00000000000..a119f6b40a1
--- /dev/null
+++ b/gas/testsuite/gas/mips/micromipsr6@rfe.l
@@ -0,0 +1,2 @@
+.*: Assembler messages:
+.*:4: Error: unrecognized opcode `rfe'
diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 118ad6a489b..0003dc91ff1 100644
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -344,6 +344,9 @@ proc run_dump_test_arch { name opts arch } {
if { [ string match "mips*r6" $proparch ]} {
lappend prefixes mipsr6@
}
+ if { [ string match "micromipsr6" $proparch ]} {
+ lappend prefixes micromips@
+ }
foreach prefix ${prefixes} {
set archname ${prefix}${name}
if { [file exists "$srcdir/$subdir/${archname}.d"] } {
@@ -403,6 +406,9 @@ proc run_list_test_arch { name opts arch } {
if { [ string match "mips*r6" $proparch ]} {
lappend prefixes mipsr6@
}
+ if { [ string match "micromipsr6" $proparch ]} {
+ lappend prefixes micromips@
+ }
foreach prefix ${prefixes} {
set archname ${prefix}${name}
if { [file exists "$srcdir/$subdir/${archname}.l"] } {
@@ -509,6 +515,8 @@ mips_arch_create mips16e2-64 64 mips16e-64 { mips16e2-32 } \
{ -mmips:isa64r2 }
mips_arch_create micromips 64 mips64r2 {} \
{ -march=mips64r2 -mmicromips } {}
+mips_arch_create micromipsr6 64 mips64r6 {} \
+ { -march=mips64r6 -mmicromips --defsym r6= --defsym compact_branches=} {}
mips_arch_create r3000 32 mips1 {} \
{ -march=r3000 -mtune=r3000 } { -mmips:3000 }
mips_arch_create r3900 32 mips1 { gpr_ilocks } \
@@ -602,7 +610,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "bgeu" [mips_arch_list_matching mips1]
run_dump_test_arches "blt" [mips_arch_list_matching mips1]
run_dump_test_arches "bltu" [mips_arch_list_matching mips1]
- run_dump_test_arches "branch-likely" [mips_arch_list_matching mips2 !mips32r6]
+ run_dump_test_arches "branch-likely" [mips_arch_list_matching mips2 \
+ !mips32r6 !micromipsr6]
run_dump_test_arches "branch-misc-1" [mips_arch_list_matching mips1]
run_dump_test_arches "branch-misc-2" [mips_arch_list_matching mips1]
run_dump_test_arches "branch-misc-2pic" [mips_arch_list_matching mips1]
@@ -705,8 +714,10 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "branch-absolute-addend-n64"
}
- run_dump_test_arches "nal-1" [mips_arch_list_matching mips1 !micromips]
- run_dump_test_arches "nal-2" [mips_arch_list_matching mips1 !micromips]
+ run_dump_test_arches "nal-1" [mips_arch_list_matching mips1 !micromips \
+ !micromipsr6]
+ run_dump_test_arches "nal-2" [mips_arch_list_matching mips1 !micromips \
+ !micromipsr6]
run_dump_test "compact-eh-eb-1"
run_dump_test "compact-eh-eb-2"
@@ -738,8 +749,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "dli" [mips_arch_list_matching mips3]
}
run_dump_test_arches "jal" [mips_arch_list_matching mips1]
- run_dump_test_arches "jal-mask-11" [mips_arch_list_matching mips1]
- run_dump_test_arches "jal-mask-12" [mips_arch_list_matching mips1]
+ run_dump_test_arches "jal-mask-11" [mips_arch_list_matching mips1 !micromipsr6]
+ run_dump_test_arches "jal-mask-12" [mips_arch_list_matching mips1 !micromipsr6]
run_dump_test_arches "jal-mask-21" [mips_arch_list_matching micromips]
run_dump_test_arches "jal-mask-22" [mips_arch_list_matching micromips]
run_dump_test "eret-1"
@@ -783,7 +794,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "jal-svr4pic${imips}" \
[mips_arch_list_matching mips1]
run_dump_test_arches "jal-svr4pic-noreorder${imips}" \
- [mips_arch_list_matching mips1]
+ [mips_arch_list_matching mips1 !micromipsr6]
run_dump_test_arches "jal-svr4pic-local${imips}" \
[mips_arch_list_matching mips1]
if $has_newabi {
@@ -1274,22 +1285,22 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "tls-relw"
run_dump_test "jalr2${imips}"
run_dump_test_arches "jalr3" [mips_arch_list_matching mips1 \
- !micromips]
+ !micromips !micromipsr6]
run_dump_test_arches "jalr4" [mips_arch_list_matching mips1 \
- !micromips]
+ !micromips !micromipsr6]
if $has_newabi {
run_dump_test_arches "jalr3-n32" \
[mips_arch_list_matching mips3 \
- !micromips]
+ !micromips !micromipsr6]
run_dump_test_arches "jalr4-n32" \
[mips_arch_list_matching mips3 \
- !micromips]
+ !micromips !micromipsr6]
run_dump_test_arches "jalr3-n64" \
[mips_arch_list_matching mips3 \
- !micromips]
+ !micromips !micromipsr6]
run_dump_test_arches "jalr4-n64" \
[mips_arch_list_matching mips3 \
- !micromips]
+ !micromips !micromipsr6]
}
run_dump_test_arches "aent" [mips_arch_list_matching mips1]
@@ -1298,10 +1309,14 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "aent-mdebug-2" \
[mips_arch_list_matching mips1]
- run_dump_test_arches "loc-swap" [mips_arch_list_all]
- run_dump_test_arches "loc-swap-dis" [mips_arch_list_all]
- run_dump_test_arches "loc-swap-2" [mips_arch_list_all]
- run_dump_test_arches "loc-swap-3" [mips_arch_list_all]
+ set all_not_micromipsr6 [lsort -dictionary -unique [concat \
+ [mips_arch_list_matching mips1 !micromipsr6] \
+ [mips_arch_list_matching mips16-32] ] ]
+
+ run_dump_test_arches "loc-swap" $all_not_micromipsr6
+ run_dump_test_arches "loc-swap-dis" $all_not_micromipsr6
+ run_dump_test_arches "loc-swap-2" $all_not_micromipsr6
+ run_dump_test_arches "loc-swap-3" $all_not_micromipsr6
run_dump_test "nan-legacy-1"
run_dump_test "nan-legacy-2"
@@ -1322,8 +1337,10 @@ if { [istarget mips*-*-vxworks*] } {
}
# tests of objdump's ability to disassemble the move mnemonic
- run_dump_test_arches "move" [mips_arch_list_matching mips64 !micromips]
+ run_dump_test_arches "move" [mips_arch_list_matching mips64 !micromips \
+ !micromipsr6]
run_dump_test_arches "micromips32-move" [mips_arch_list_matching micromips]
+ run_dump_test_arches "micromips32-move" [mips_arch_list_matching micromipsr6]
# tests of objdump's ability to disassemble using different
# register names.
@@ -1502,7 +1519,8 @@ if { [istarget mips*-*-vxworks*] } {
[mips_arch_list_matching mips16e-32] \
[mips_arch_list_matching interaptiv-mr2]]]
run_dump_test_arches "save-sub" [lsort -dictionary -unique [concat \
- [mips_arch_list_matching mips1 !micromips] \
+ [mips_arch_list_matching mips1 !micromips \
+ !micromipsr6] \
[mips_arch_list_matching mips16-32]]]
run_dump_test "mips16-dwarf2"
@@ -1591,10 +1609,14 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "reginfo-2-n32"
}
- run_dump_test "micromips"
+ set any_micromips [lsort -dictionary -unique [concat \
+ [mips_arch_list_matching micromips] \
+ [mips_arch_list_matching micromipsr6]]]
+
+ run_dump_test_arches "micromips" $any_micromips
run_dump_test "micromips-trap"
run_dump_test "micromips-compact"
- run_dump_test "micromips-insn32"
+ run_dump_test_arches "micromips-insn32" $any_micromips
run_dump_test "micromips-noinsn32"
run_list_test "micromips" "-mips32r2 -32 -mfp64 -minsn32" \
"microMIPS for MIPS32r2 (instructions invalid in insn32 mode)"
@@ -1676,12 +1698,15 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "l_d-reloc"
run_list_test "bltzal"
- run_dump_test_arches "msa" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "msa" [mips_arch_list_matching mips32r2 \
+ !micromipsr6]
if { $has_newabi } {
- run_dump_test_arches "msa64" [mips_arch_list_matching mips64r2]
+ run_dump_test_arches "msa64" [mips_arch_list_matching mips64r2 \
+ !micromipsr6]
}
run_dump_test_arches "msa-relax" [mips_arch_list_matching mips32r2 !mips32r6]
- run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2]
+ run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2 \
+ !micromipsr6]
run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2]
run_dump_test_arches "xpa-err" [mips_arch_list_matching mips32r2]
@@ -1704,7 +1729,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "pcrel-reloc-3"
run_dump_test "pcrel-reloc-3-r6"
run_dump_test "pcrel-reloc-4"
- run_dump_test "pcrel-reloc-4-r6"
+ run_dump_test_arches "pcrel-reloc-4-r6" [mips_arch_list_matching mips64r6]
run_dump_test "pcrel-reloc-5"
run_dump_test "pcrel-reloc-5-r6"
run_dump_test "pcrel-reloc-6"
@@ -2133,7 +2158,8 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "option-pic-relax-4"
run_dump_test "option-pic-relax-5"
- run_dump_test_arches "isa-override-1" "" [mips_arch_list_matching mips1]
+ run_dump_test_arches "isa-override-1" "" [mips_arch_list_matching mips1 \
+ !micromipsr6]
run_dump_test_arches "isa-override-2" "" [mips_arch_list_matching mips1]
run_dump_test "debug-label-end-1"
@@ -2155,30 +2181,39 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test_arches "stabs-symbol-type" [mips_arch_list_all]
- run_dump_test_arches "r6" [mips_arch_list_matching mips32r6]
+ run_dump_test_arches "r6" [mips_arch_list_matching mips32r6 \
+ !micromipsr6]
if $has_newabi {
- run_dump_test_arches "r6-n32" [mips_arch_list_matching mips64r6]
- run_dump_test_arches "r6-n64" [mips_arch_list_matching mips64r6]
- run_dump_test_arches "r6-64-n32" [mips_arch_list_matching mips64r6]
- run_dump_test_arches "r6-64-n64" [mips_arch_list_matching mips64r6]
+ run_dump_test_arches "r6-n32" [mips_arch_list_matching mips64r6 \
+ !micromipsr6]
+ run_dump_test_arches "r6-n64" [mips_arch_list_matching mips64r6 \
+ !micromipsr6]
+ run_dump_test_arches "r6-64-n32" [mips_arch_list_matching mips64r6 \
+ !micromipsr6]
+ run_dump_test_arches "r6-64-n64" [mips_arch_list_matching mips64r6 \
+ !micromipsr6]
run_list_test_arches "ldpc-unalign" "-64" [mips_arch_list_matching mips64r6]
}
- run_list_test_arches "r6-removed" "-32" [mips_arch_list_matching mips32r6]
- run_list_test_arches "r6-64-removed" [mips_arch_list_matching mips64r6]
+ run_list_test_arches "r6-removed" "-32" [mips_arch_list_matching mips32r6 \
+ !micromipsr6]
+ run_list_test_arches "r6-64-removed" [mips_arch_list_matching mips64r6 \
+ !micromipsr6]
run_list_test_arches "r6-reg-constraints" "-32" \
[mips_arch_list_matching mips32r6]
- run_dump_test_arches "crc" [mips_arch_list_matching mips32r6]
- run_dump_test_arches "crc-err" [mips_arch_list_matching mips32r6]
- run_dump_test_arches "crc64" [mips_arch_list_matching mips64r6]
- run_dump_test_arches "crc64-err" [mips_arch_list_matching mips64r6]
+ run_dump_test_arches "crc" [mips_arch_list_matching mips32r6 !micromipsr6]
+ run_dump_test_arches "crc-err" [mips_arch_list_matching mips32r6 !micromipsr6]
+ run_dump_test_arches "crc64" [mips_arch_list_matching mips64r6 !micromipsr6]
+ run_dump_test_arches "crc64-err" [mips_arch_list_matching mips64r6 !micromipsr6]
- run_dump_test_arches "ginv" [mips_arch_list_matching mips32r6]
- run_dump_test_arches "ginv-err" [mips_arch_list_matching mips32r6]
+ run_dump_test_arches "ginv" [mips_arch_list_matching mips32r6 !micromipsr6]
+ run_dump_test_arches "ginv-err" [mips_arch_list_matching mips32r6 !micromipsr6]
- run_dump_test_arches "llpscp-32" [mips_arch_list_matching mips32r6]
+ run_dump_test_arches "llpscp-32" [mips_arch_list_matching mips32r6 !micromipsr6]
+ run_dump_test "llpscp-32-micromips"
run_dump_test_arch "llpscp-64" "" mips64r6
+ run_dump_test "llpscp-64-micromips"
run_dump_test "pr14798${imips}"
run_dump_test "insn-isa-mode"
diff --git a/gas/testsuite/gas/mips/mips32r2.d b/gas/testsuite/gas/mips/mips32r2.d
index 0b04de62e78..5ad9f797574 100644
--- a/gas/testsuite/gas/mips/mips32r2.d
+++ b/gas/testsuite/gas/mips/mips32r2.d
@@ -11,34 +11,37 @@ Disassembly of section .text:
0+0004 <[^>]*> 7ca43980 ext \$4,\$5,0x6,0x8
0+0008 <[^>]*> 7ca46984 ins \$4,\$5,0x6,0x8
0+000c <[^>]*> 0100fc09 jalr.hb \$8
-0+0010 <[^>]*> 0120a409 jalr.hb \$20,\$9
-0+0014 <[^>]*> 01000408 jr.hb \$8
-0+0018 <[^>]*> 7c0a003b rdhwr \$10,\$0
-0+001c <[^>]*> 7c0b083b rdhwr \$11,\$1
-0+0020 <[^>]*> 7c0c103b rdhwr \$12,\$2
-0+0024 <[^>]*> 7c0d183b rdhwr \$13,\$3
-0+0028 <[^>]*> 7c0e203b rdhwr \$14,\$4
-0+002c <[^>]*> 7c0f283b rdhwr \$15,\$5
-0+0030 <[^>]*> 002acf02 ror \$25,\$10,0x1c
-0+0034 <[^>]*> 002ac902 ror \$25,\$10,0x4
-0+0038 <[^>]*> 0004c823 negu \$25,\$4
-0+003c <[^>]*> 032ac846 rorv \$25,\$10,\$25
-0+0040 <[^>]*> 008ac846 rorv \$25,\$10,\$4
-0+0044 <[^>]*> 008ac846 rorv \$25,\$10,\$4
-0+0048 <[^>]*> 7c073c20 seb \$7,\$7
-0+004c <[^>]*> 7c0a4420 seb \$8,\$10
-0+0050 <[^>]*> 7c073e20 seh \$7,\$7
-0+0054 <[^>]*> 7c0a4620 seh \$8,\$10
-0+0058 <[^>]*> 055f5555 synci 21845\(\$10\)
-0+005c <[^>]*> 7c0738a0 wsbh \$7,\$7
-0+0060 <[^>]*> 7c0a40a0 wsbh \$8,\$10
-0+0064 <[^>]*> 41606000 di
-0+0068 <[^>]*> 41606000 di
-0+006c <[^>]*> 416a6000 di \$10
-0+0070 <[^>]*> 41606020 ei
-0+0074 <[^>]*> 41606020 ei
-0+0078 <[^>]*> 416a6020 ei \$10
-0+007c <[^>]*> 41595000 rdpgpr \$10,\$25
-0+0080 <[^>]*> 41d95000 wrpgpr \$10,\$25
-0+0084 <[^>]*> 00000140 pause
+0+0010 <[^>]*> 00000000 nop
+0+0014 <[^>]*> 0120a409 jalr.hb \$20,\$9
+0+0018 <[^>]*> 00000000 nop
+0+001c <[^>]*> 01000408 jr.hb \$8
+0+0020 <[^>]*> 00000000 nop
+0+0024 <[^>]*> 7c0a003b rdhwr \$10,\$0
+0+0028 <[^>]*> 7c0b083b rdhwr \$11,\$1
+0+002c <[^>]*> 7c0c103b rdhwr \$12,\$2
+0+0030 <[^>]*> 7c0d183b rdhwr \$13,\$3
+0+0034 <[^>]*> 7c0e203b rdhwr \$14,\$4
+0+0038 <[^>]*> 7c0f283b rdhwr \$15,\$5
+0+003c <[^>]*> 002acf02 ror \$25,\$10,0x1c
+0+0040 <[^>]*> 002ac902 ror \$25,\$10,0x4
+0+0044 <[^>]*> 0004c823 negu \$25,\$4
+0+0048 <[^>]*> 032ac846 rorv \$25,\$10,\$25
+0+004c <[^>]*> 008ac846 rorv \$25,\$10,\$4
+0+0050 <[^>]*> 008ac846 rorv \$25,\$10,\$4
+0+0054 <[^>]*> 7c073c20 seb \$7,\$7
+0+0058 <[^>]*> 7c0a4420 seb \$8,\$10
+0+005c <[^>]*> 7c073e20 seh \$7,\$7
+0+0060 <[^>]*> 7c0a4620 seh \$8,\$10
+0+0064 <[^>]*> 055f5555 synci 21845\(\$10\)
+0+0068 <[^>]*> 7c0738a0 wsbh \$7,\$7
+0+006c <[^>]*> 7c0a40a0 wsbh \$8,\$10
+0+0070 <[^>]*> 41606000 di
+0+0074 <[^>]*> 41606000 di
+0+0078 <[^>]*> 416a6000 di \$10
+0+007c <[^>]*> 41606020 ei
+0+0080 <[^>]*> 41606020 ei
+0+0084 <[^>]*> 416a6020 ei \$10
+0+0088 <[^>]*> 41595000 rdpgpr \$10,\$25
+0+008c <[^>]*> 41d95000 wrpgpr \$10,\$25
+0+0090 <[^>]*> 00000140 pause
...
diff --git a/gas/testsuite/gas/mips/mips32r2.s b/gas/testsuite/gas/mips/mips32r2.s
index a91a8fc9964..6a270330787 100644
--- a/gas/testsuite/gas/mips/mips32r2.s
+++ b/gas/testsuite/gas/mips/mips32r2.s
@@ -15,9 +15,13 @@ text_label:
ins $4, $5, 6, 8
jalr.hb $8
+ nop
+
jalr.hb $20, $9
+ nop
jr.hb $8
+ nop
# Note, further testing of rdhwr is done in hwr-names-mips32r2.d
rdhwr $10, $0
@@ -66,4 +70,5 @@ text_label:
pause
# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ...
+ .align 2
.space 8
diff --git a/gas/testsuite/gas/mips/mipsr6@mips32r2.d b/gas/testsuite/gas/mips/mipsr6@mips32r2.d
index dbf680c8849..2b256b66ea6 100644
--- a/gas/testsuite/gas/mips/mipsr6@mips32r2.d
+++ b/gas/testsuite/gas/mips/mipsr6@mips32r2.d
@@ -12,34 +12,37 @@ Disassembly of section .text:
0+0004 <[^>]*> 7ca43980 ext \$4,\$5,0x6,0x8
0+0008 <[^>]*> 7ca46984 ins \$4,\$5,0x6,0x8
0+000c <[^>]*> 0100fc09 jalr.hb \$8
-0+0010 <[^>]*> 0120a409 jalr.hb \$20,\$9
-0+0014 <[^>]*> 01000409 jr.hb \$8
-0+0018 <[^>]*> 7c0a003b rdhwr \$10,\$0
-0+001c <[^>]*> 7c0b083b rdhwr \$11,\$1
-0+0020 <[^>]*> 7c0c103b rdhwr \$12,\$2
-0+0024 <[^>]*> 7c0d183b rdhwr \$13,\$3
-0+0028 <[^>]*> 7c0e203b rdhwr \$14,\$4
-0+002c <[^>]*> 7c0f283b rdhwr \$15,\$5
-0+0030 <[^>]*> 002acf02 ror \$25,\$10,0x1c
-0+0034 <[^>]*> 002ac902 ror \$25,\$10,0x4
-0+0038 <[^>]*> 0004c823 negu \$25,\$4
-0+003c <[^>]*> 032ac846 rorv \$25,\$10,\$25
-0+0040 <[^>]*> 008ac846 rorv \$25,\$10,\$4
-0+0044 <[^>]*> 008ac846 rorv \$25,\$10,\$4
-0+0048 <[^>]*> 7c073c20 seb \$7,\$7
-0+004c <[^>]*> 7c0a4420 seb \$8,\$10
-0+0050 <[^>]*> 7c073e20 seh \$7,\$7
-0+0054 <[^>]*> 7c0a4620 seh \$8,\$10
-0+0058 <[^>]*> 055f5555 synci 21845\(\$10\)
-0+005c <[^>]*> 7c0738a0 wsbh \$7,\$7
-0+0060 <[^>]*> 7c0a40a0 wsbh \$8,\$10
-0+0064 <[^>]*> 41606000 di
-0+0068 <[^>]*> 41606000 di
-0+006c <[^>]*> 416a6000 di \$10
-0+0070 <[^>]*> 41606020 ei
-0+0074 <[^>]*> 41606020 ei
-0+0078 <[^>]*> 416a6020 ei \$10
-0+007c <[^>]*> 41595000 rdpgpr \$10,\$25
-0+0080 <[^>]*> 41d95000 wrpgpr \$10,\$25
-0+0084 <[^>]*> 00000140 pause
+0+0010 <[^>]*> 00000000 nop
+0+0014 <[^>]*> 0120a409 jalr.hb \$20,\$9
+0+0018 <[^>]*> 00000000 nop
+0+001c <[^>]*> 01000409 jr.hb \$8
+0+0020 <[^>]*> 00000000 nop
+0+0024 <[^>]*> 7c0a003b rdhwr \$10,\$0
+0+0028 <[^>]*> 7c0b083b rdhwr \$11,\$1
+0+002c <[^>]*> 7c0c103b rdhwr \$12,\$2
+0+0030 <[^>]*> 7c0d183b rdhwr \$13,\$3
+0+0034 <[^>]*> 7c0e203b rdhwr \$14,\$4
+0+0038 <[^>]*> 7c0f283b rdhwr \$15,\$5
+0+003c <[^>]*> 002acf02 ror \$25,\$10,0x1c
+0+0040 <[^>]*> 002ac902 ror \$25,\$10,0x4
+0+0044 <[^>]*> 0004c823 negu \$25,\$4
+0+0048 <[^>]*> 032ac846 rorv \$25,\$10,\$25
+0+004c <[^>]*> 008ac846 rorv \$25,\$10,\$4
+0+0050 <[^>]*> 008ac846 rorv \$25,\$10,\$4
+0+0054 <[^>]*> 7c073c20 seb \$7,\$7
+0+0058 <[^>]*> 7c0a4420 seb \$8,\$10
+0+005c <[^>]*> 7c073e20 seh \$7,\$7
+0+0060 <[^>]*> 7c0a4620 seh \$8,\$10
+0+0064 <[^>]*> 055f5555 synci 21845\(\$10\)
+0+0068 <[^>]*> 7c0738a0 wsbh \$7,\$7
+0+006c <[^>]*> 7c0a40a0 wsbh \$8,\$10
+0+0070 <[^>]*> 41606000 di
+0+0074 <[^>]*> 41606000 di
+0+0078 <[^>]*> 416a6000 di \$10
+0+007c <[^>]*> 41606020 ei
+0+0080 <[^>]*> 41606020 ei
+0+0084 <[^>]*> 416a6020 ei \$10
+0+0088 <[^>]*> 41595000 rdpgpr \$10,\$25
+0+008c <[^>]*> 41d95000 wrpgpr \$10,\$25
+0+0090 <[^>]*> 00000140 pause
...
diff --git a/gas/testsuite/gas/mips/pcrel-reloc-4-r6.d b/gas/testsuite/gas/mips/pcrel-reloc-4-r6.d
index 32619cd0f13..67073ce9731 100644
--- a/gas/testsuite/gas/mips/pcrel-reloc-4-r6.d
+++ b/gas/testsuite/gas/mips/pcrel-reloc-4-r6.d
@@ -1,6 +1,6 @@
-#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa64r6
+#objdump: -dr --prefix-addresses --show-raw-insn
#name: MIPS local PC-relative relocations 4
-#as: -32 -mips32r6
+#as: -32
#source: pcrel-reloc-4.s
.*: +file format .*mips.*
diff --git a/gas/testsuite/gas/mips/pcrel-reloc-4.s b/gas/testsuite/gas/mips/pcrel-reloc-4.s
index d6906ae5022..a3df607b3c5 100644
--- a/gas/testsuite/gas/mips/pcrel-reloc-4.s
+++ b/gas/testsuite/gas/mips/pcrel-reloc-4.s
@@ -23,7 +23,9 @@ bar:
.align 4, 0
.globl foo
.ent foo
+ .ifndef compact_branches
.set noreorder
+ .endif
foo:
b bar
b bar
diff --git a/gas/testsuite/gas/mips/ur6-64-removed.l b/gas/testsuite/gas/mips/ur6-64-removed.l
new file mode 100644
index 00000000000..61fb7f28bcf
--- /dev/null
+++ b/gas/testsuite/gas/mips/ur6-64-removed.l
@@ -0,0 +1,8 @@
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `daddi \$23,\$24,1023'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `dmult \$2,\$3'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `dmultu \$2,\$3'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `ldl \$2,1\(\$3\)'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `ldr \$2,1\(\$3\)'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `sdl \$2,1\(\$3\)'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `sdr \$2,1\(\$3\)'
diff --git a/gas/testsuite/gas/mips/ur6-64-removed.s b/gas/testsuite/gas/mips/ur6-64-removed.s
new file mode 100644
index 00000000000..db949138e75
--- /dev/null
+++ b/gas/testsuite/gas/mips/ur6-64-removed.s
@@ -0,0 +1,10 @@
+ .set reorder
+ .set micromips
+foo:
+ daddi $23,$24,1023
+ dmult $2,$3
+ dmultu $2,$3
+ ldl $2, 1($3)
+ ldr $2, 1($3)
+ sdl $2, 1($3)
+ sdr $2, 1($3)
diff --git a/gas/testsuite/gas/mips/ur6-ctc-err.l b/gas/testsuite/gas/mips/ur6-ctc-err.l
new file mode 100644
index 00000000000..0a36dffc237
--- /dev/null
+++ b/gas/testsuite/gas/mips/ur6-ctc-err.l
@@ -0,0 +1,63 @@
+.*.s: Assembler messages:
+.*.s:6: Error: unable to convert `b' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:8: Error: unable to convert `b' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:10: Error: unable to convert `b' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:13: Error: unable to convert `bal' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:16: Error: unable to convert `beqz' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:18: Error: unable to convert `beqz' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:21: Error: unable to convert `beq' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:23: Error: unable to convert `beq' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:25: Error: unable to convert `beq' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:27: Error: unable to convert `beq' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:29: Error: unable to convert `beq' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:31: Error: unable to convert `beq' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:33: Error: unable to convert `beqz' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:37: Error: unable to convert `bnez' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:39: Error: unable to convert `bnez' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:41: Error: unable to convert `bne' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:43: Error: unable to convert `bne' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:45: Error: unable to convert `bne' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:47: Error: unable to convert `bne' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:49: Error: unable to convert `bne' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:51: Error: unable to convert `bnez' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:56: Error: unable to convert `bgez' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:58: Error: unable to convert `bltz' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:60: Error: unable to convert `bltzal' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:63: Error: unable to convert `j' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:65: Error: unable to convert `jr' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:70: Error: unable to convert `j' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:72: Error: unable to convert `j' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:77: Error: unable to convert `jal' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:80: Error: unable to convert `j' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:82: Error: unable to convert `jr' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:85: Error: unable to convert `jalr' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:87: Error: unable to convert `jalr' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:89: Error: unable to convert `jalr' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:91: Error: unable to convert `jalr' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:94: Error: unable to convert `jalr' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:96: Error: unable to convert `jalr' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:98: Error: unable to convert `jalr' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:101: Error: unable to convert `jr.hb' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:103: Error: unable to convert `jalr.hb' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:105: Error: unable to convert `jalr.hb' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:107: Error: unable to convert `jalr.hb' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:118: Error: unable to convert `j' to its compact form because it has a non NOP instruction \(`li'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:123: Error: unable to convert `jal' to its compact form because it has a non NOP instruction \(`sh'\) in its delay slot. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:130: Error: operand 2 must be an immediate expression `beq \$3,\$3,ext'
+.*.s:131: Error: operand 2 must be an immediate expression `bne \$3,\$3,ext'
+.*.s:133: Error: the source register must not be \$0 `beqz \$0,1b'
+.*.s:134: Error: the source register must not be \$0 `bnez \$0,1b'
+.*.s:136: Error: the source register must not be \$0 `bgez \$0,1b'
+.*.s:137: Error: the source register must not be \$0 `bltz \$0,1b'
+.*.s:138: Error: the source register must not be \$0 `bltzal \$0,1b'
+.*.s:142: Error: unable to convert `bal' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:146: Error: unable to convert `bgezal' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:150: Error: unable to convert `bltzal' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:154: Error: unable to convert `jal' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:158: Error: unable to convert `jalr' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:160: Error: unable to convert `jalr' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:162: Error: unable to convert `jalr' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:164: Error: unable to convert `jalr' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:167: Error: unable to convert `jalr' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:169: Error: unable to convert `jalr' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
+.*.s:171: Error: unable to convert `jalr' to its compact form because the link register would have a different value. Please move the delay slot instruction before the branch and disable noreorder.
diff --git a/gas/testsuite/gas/mips/ur6-ctc-err.s b/gas/testsuite/gas/mips/ur6-ctc-err.s
new file mode 100644
index 00000000000..b69c5708af9
--- /dev/null
+++ b/gas/testsuite/gas/mips/ur6-ctc-err.s
@@ -0,0 +1,179 @@
+ .text
+ .set micromips
+ .set noreorder
+noreorder:
+ b 1f # bc16
+ li $2, 0x1
+ b16 1f # bc16
+ li $2, 0x1
+ b32 1f # bc32 (pre-r6 beq32)
+ li $2, 0x1
+
+ bal 1f # balc
+ li $2, 0x1
+
+ beqz $2,1f # beqzc16 v0,1f [PC7]
+ li $2, 0x1
+ beqz16 $2,1f # beqzc16 v0,1f
+ li $2, 0x1
+
+ beq16 $3,$0,ext # beqzc16 v1,ext [PC7]
+ li $2, 0x1
+ beq16 $0,$3,ext # beqzc16 v1,ext
+ li $2, 0x1
+ beq $3,$0,ext # beqzc v1,ext [PC21]
+ li $2, 0x1
+ beq $0,$3,ext # beqzc v1,ext
+ li $2, 0x1
+ beq $3,$2,ext # beqc v0,v1,ext [PC16]
+ li $2, 0x1
+ beq $2,$3,ext # beqc v0,v1,ext
+ li $2, 0x1
+ beqz16 $3,ext # beqzc16 v1,ext [PC7]
+ li $2, 0x1
+ beqzc $3,ext # compact, no error should be reported
+ li $2, 0x1
+ bnez $2,1f # bnezc16 v0,1f [PC7]
+ li $2, 0x1
+ bnez16 $2,1f # bnezc16 v0,1f
+ li $2, 0x1
+ bne16 $3,$0,ext # bnezc16 v1,ext [PC7]
+ li $2, 0x1
+ bne16 $0,$3,ext # bnezc16 v1,ext
+ li $2, 0x1
+ bne $3,$0,ext # bnezc v1,ext [PC21]
+ li $2, 0x1
+ bne $3,$2,ext # bnec v0,v1,ext [PC16]
+ li $2, 0x1
+ bne $2,$3,ext # bnec v0,v1,ext
+ li $2, 0x1
+ bnez16 $3,ext # bnezc16 v1,ext [PC7]
+ li $2, 0x1
+ bnezc $3,ext # compact, no error should be reported
+ li $2, 0x1
+
+ bgez $2, ext # bgezc v0,ext
+ li $2, 0x1
+ bltz $2, ext # bgezc v0,ext
+ li $2, 0x1
+ bltzal $2, ext # bgezc v0,ext
+ li $2, 0x1
+
+ j16 $4 # jrc16 a0
+ li $2, 0x1
+ jr $2 # jrc16 v0
+ li $2, 0x1
+ li $2, 0x1
+
+
+ j 1f # bc32
+ li $2, 0x1
+ j32 1f # bc32
+ li $2, 0x1
+
+ jal 1f # balc
+
+f:
+ li $2, 0x1
+
+ j32 $4 # jalrc32/jrc a0
+ li $2, 0x1
+ jr32 $4 # jalrc32/jrc a0
+ li $2, 0x1
+
+ jalr $4 # jalrc16 a0
+ li $2, 0x1
+ jalr32 $4 # jalrc a0
+ li $2, 0x1
+ jalr $4,$5 # jalrc a0,a1
+ li $2, 0x1
+ jalr32 $4,$5 # jalrc a0,a1
+ li $2, 0x1
+
+ jalr $2 # jalrc16 v0
+ li $2, 0x1
+ jalr16 $2 # jalrc16 v0
+ li $2, 0x1
+ jalr16 $31,$2 # jalrc16 v0
+ li $2, 0x1
+
+ jr.hb $4 # jrc.hb a0
+ li $2, 0x1
+ jalr.hb $4 # jalrc.hb a0
+ li $2, 0x1
+ jalr.hb $4,$5 # jalrc.hb a0,a1
+ li $2, 0x1
+ jalr.hb $4,$5 # jalrc.hb a0,a1
+ li $2, 0x1
+
+text_label:
+ .set noreorder
+ j text_label
+ .set reorder
+ nop
+
+ .set noreorder
+ j text_label
+ .set reorder
+ li $2, 0x1
+
+ .set noreorder
+ .set nomacro
+ jal func1
+ sh $2,36($17)
+ .set macro
+ .set reorder
+1:
+ nop
+
+# Impossible mappings
+ beq $3, $3, ext # rs must not be equal to rt -> beqzalc
+ bne $3, $3, ext # as above but bnezalc
+
+ beqz $0, 1b
+ bnez $0, 1b
+
+ bgez $0, 1b
+ bltz $0, 1b
+ bltzal $0, 1b
+
+ .set noreorder
+ bal 2f
+ nop
+
+2:
+ bgezal $3, 3f
+ nop
+
+3:
+ bltzal $3, 4f
+ nop
+
+4:
+ jal 5f
+ nop
+
+5:
+ jalr $4 # jalrc16 a0
+ nop
+ jalr32 $4 # jalrc a0
+ nop
+ jalr $4,$5 # jalrc a0,a1
+ nop
+ jalr32 $4,$5 # jalrc a0,a1
+ nop
+
+ jalr $2 # jalrc16 v0
+ nop
+ jalr16 $2 # jalrc16 v0
+ nop
+ jalr16 $31,$2 # jalrc16 v0
+ nop
+
+ jalr.hb $4 # jalrc.hb a0
+ nop
+ jalr.hb $4,$5 # jalrc.hb a0,a1
+ nop
+
+ .align 2
+ .space 8
diff --git a/gas/testsuite/gas/mips/ur6-ctc.d b/gas/testsuite/gas/mips/ur6-ctc.d
new file mode 100644
index 00000000000..3f347ecc334
--- /dev/null
+++ b/gas/testsuite/gas/mips/ur6-ctc.d
@@ -0,0 +1,193 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS microMIPS pre-R6 to R6 mapping
+#as: -32
+
+# Check mapping of microMIPS pre-R6 to R6 translation
+
+.*.o: file format elf32-trad.*mips
+
+
+Disassembly of section .text:
+[0-9a-f]+ <[^>]*> cfff bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .L1\x021
+[0-9a-f]+ <[^>]*> cfff bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 97ff fffe bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 .L1\x021
+[0-9a-f]+ <[^>]*> b7ff fffe balc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 805f fffe beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 805f fffe beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 8d7f beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 8dff beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> 8dff beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> 807f fffe beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> 807f fffe beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> 7462 fffe beqc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7462 fffe beqc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 8dff beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> 807f fffe beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> a05f fffe bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 .L1\x021
+[0-9a-f]+ <[^>]*> a05f fffe bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 .L1\x021
+[0-9a-f]+ <[^>]*> ad7f bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .L1\x021
+[0-9a-f]+ <[^>]*> adff bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> adff bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> a07f fffe bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> a07f fffe bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> 7c62 fffe bnec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7c62 fffe bnec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> adff bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> a07f fffe bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> f442 fffe bgezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> d442 fffe bltzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> e042 fffe bltzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> c042 fffe bgezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 4483 jrc a0
+[0-9a-f]+ <[^>]*> 4443 jrc v0
+[0-9a-f]+ <[^>]*> 8002 0000 jrc v0
+[0-9a-f]+ <[^>]*> 97ff fffe bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 97ff fffe bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 .L1\x021
+[0-9a-f]+ <[^>]*> b7ff fffe balc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 8004 0000 jrc a0
+[0-9a-f]+ <[^>]*> 8004 0000 jrc a0
+[0-9a-f]+ <[^>]*> 448b jalrc a0
+[0-9a-f]+ <[^>]*> 03e4 0f3c jalrc a0
+[0-9a-f]+ <[^>]*> 0085 0f3c jalrc a0,a1
+[0-9a-f]+ <[^>]*> 0085 0f3c jalrc a0,a1
+[0-9a-f]+ <[^>]*> 444b jalrc v0
+[0-9a-f]+ <[^>]*> 444b jalrc v0
+[0-9a-f]+ <[^>]*> 444b jalrc v0
+[0-9a-f]+ <[^>]*> 0004 1f3c jrc.hb a0
+[0-9a-f]+ <[^>]*> 03e4 1f3c jalrc.hb a0
+[0-9a-f]+ <[^>]*> 0085 1f3c jalrc.hb a0,a1
+[0-9a-f]+ <[^>]*> 4513 jrcaddiusp 32
+[0-9a-f]+ <[^>]*> cfff bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> cfff bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 97ff fffe bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 805f fffe beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 805f fffe beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8d7f beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8dff beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8dff beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 807f fffe beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 807f fffe beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 7462 fffe beqc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 7462 fffe beqc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8dff beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 807f fffe beqzc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ad7f bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> a05f fffe bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> ad7f bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> adff bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> adff bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> a07f fffe bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 7c62 fffe bnec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 7c62 fffe bnec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> adff bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> a07f fffe bnezc v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> f442 fffe bgezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> d442 fffe bltzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4483 jrc a0
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4443 jrc v0
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8002 0000 jrc v0
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 97ff fffe bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 97ff fffe bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8004 0000 jrc a0
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 8004 0000 jrc a0
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0004 1f3c jrc.hb a0
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 4513 jrcaddiusp 32
+[0-9a-f]+ <[^>]*> ed0f li v0,15
+[0-9a-f]+ <[^>]*> 0c00 nop
+[0-9a-f]+ <[^>]*> 0c00 nop
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/ur6-ctc.s b/gas/testsuite/gas/mips/ur6-ctc.s
new file mode 100644
index 00000000000..78bca815b6b
--- /dev/null
+++ b/gas/testsuite/gas/mips/ur6-ctc.s
@@ -0,0 +1,157 @@
+ .text
+ .set micromips
+
+ .set reorder
+reorder:
+ b 1f # bc16
+ b16 1f # bc16
+ b32 1f # bc32 (pre-r6 beq32)
+
+ bal 1f # balc
+
+ beqz $2,1f # beqzc16 v0,1f [PC7]
+ beqz32 $2,1f # beqzc32 v0,1f
+ beqz16 $2,1f # beqzc16 v0,1f
+
+ beq16 $3,$0,ext # beqzc16 v1,ext [PC7]
+ beq16 $0,$3,ext # beqzc16 v1,ext
+ beq $3,$0,ext # beqzc v1,ext [PC21]
+ beq $0,$3,ext # beqzc v1,ext
+ beq $3,$2,ext # beqc v0,v1,ext [PC16]
+ beq $2,$3,ext # beqc v0,v1,ext
+ beqz16 $3,ext # beqzc16 v1,ext [PC7]
+ beqzc $3,ext # beqzc v1,ext [new reloc=PC21]
+
+ bnez $2,1f # bnezc16 v0,1f [PC7]
+ bnez32 $2,1f # bnezc32 v0,1f [PC7]
+ bnez16 $2,1f # bnezc16 v0,1f
+
+ bne16 $3,$0,ext # bnezc16 v1,ext [PC7]
+ bne16 $0,$3,ext # bnezc16 v1,ext
+ bne $3,$0,ext # bnezc v1,ext [PC21]
+ bne $0,$3,ext # bnezc v1,ext [PC21]
+ bne $3,$2,ext # bnec v0,v1,ext [PC16]
+ bne $2,$3,ext # bnec v0,v1,ext
+ bnez16 $3,ext # bnezc16 v1,ext [PC7]
+ bnezc $3,ext # bnezc v1,ext [new reloc=PC21]
+
+ bgez $2, ext # bgezc v0,ext
+ bltz $2, ext # bgezc v0,ext
+ bltzal $2, ext # bltzalc v0,ext
+ bgezal $2, ext # bgezalc v0,ext
+
+ j16 $4 # jrc16 a0
+ jr $2 # jrc16 v0
+ jrc32 $2 # jic v0,0
+
+
+ j 1f # bc32
+ j32 1f # bc32
+
+ jal 1f # balc
+
+ j32 $4 # jic a0,0
+ jr32 $4 # jic a0,0
+
+ jalr $4 # jalrc16 a0
+ jalr32 $4 # jalrc a0
+ jalr $4,$5 # jalrc a0,a1
+ jalr32 $4,$5 # jalrc a0,a1
+
+ jalr $2 # jalrc16 v0
+ jalr16 $2 # jalrc16 v0
+ jalr16 $31,$2 # jalrc16 v0
+
+ jr.hb $4 # jrc.hb a0
+ jalr.hb $4 # jalrc.hb a0
+ jalr.hb $4,$5 # jalrc.hb a0,a1
+
+ jraddiusp 32 # jrcaddiusp
+
+ .set noreorder
+noreorder:
+ b 1f # bc
+ nop
+ b16 1f # bc16
+ nop
+ b32 1f # bc32 (pre-r6 beq32)
+ nop
+
+ beqz $2,1f # beqzc16 v0,1f [PC7]
+ nop
+ beqz32 $2,1f # beqzc32 v0,1f
+ nop
+ beqz16 $2,1f # beqzc16 v0,1f
+ nop
+
+ beq16 $3,$0,ext # beqzc16 v1,ext [PC7]
+ nop
+ beq16 $0,$3,ext # beqzc16 v1,ext
+ nop
+ beq $3,$0,ext # beqzc v1,ext [PC21]
+ nop
+ beq $0,$3,ext # beqzc v1,ext
+ nop
+ beq $3,$2,ext # beqc v0,v1,ext [PC16]
+ nop
+ beq $2,$3,ext # beqc v0,v1,ext
+ nop
+ beqz16 $3,ext # beqzc16 v1,ext [PC7]
+ nop
+ beqzc $3,ext # beqzc v1,ext [new reloc=PC21]
+ nop
+
+ bnez $2,1f # bnezc16 v0,1f [PC7]
+ nop
+ bnez32 $2,1f # bnezc32 v0,1f [PC7]
+ nop
+ bnez16 $2,1f # bnezc16 v0,1f
+ nop
+
+ bne16 $3,$0,ext # bnezc16 v1,ext [PC7]
+ nop
+ bne16 $0,$3,ext # bnezc16 v1,ext
+ nop
+ bne $3,$0,ext # bnezc v1,ext [PC21]
+ nop
+ bne $3,$2,ext # bnec v0,v1,ext [PC16]
+ nop
+ bne $2,$3,ext # bnec v0,v1,ext
+ nop
+ bnez16 $3,ext # bnezc16 v1,ext [PC7]
+ nop
+ bnezc $3,ext # bnezc v1,ext [new reloc=PC21]
+ nop
+
+ bgez $2, ext # bgezc v0,ext
+ nop
+ bltz $2, ext # bgezc v0,ext
+ nop
+
+ j16 $4 # jrc16 a0
+ nop
+ jr $2 # jrc16 v0
+ nop
+ jrc32 $2 # jic v0,0
+ nop
+
+ j 1f # bc32
+ nop
+ j32 1f # bc32
+ nop
+
+ j32 $4 # jic a0,0
+ nop
+ jr32 $4 # jic a0,0
+ nop
+
+ jr.hb $4 # jrc.hb a0
+ nop
+
+ jraddiusp 32 # jrcaddiusp
+ li $2, 0xf # jraddiusp has no DS
+
+1:
+ nop
+ .align 2
+ .space 8
diff --git a/gas/testsuite/gas/mips/ur6-removed.l b/gas/testsuite/gas/mips/ur6-removed.l
new file mode 100644
index 00000000000..66b4e47f0f0
--- /dev/null
+++ b/gas/testsuite/gas/mips/ur6-removed.l
@@ -0,0 +1,186 @@
+.*.s: Assembler messages:
+.*.s:3: Error: opcode not supported on this processor: .* \(.*\) `abs.ps \$f0,\$f2'
+.*.s:4: Error: opcode not supported on this processor: .* \(.*\) `add.ps \$f0,\$f2,\$f2'
+.*.s:5: Error: opcode not supported on this processor: .* \(.*\) `addi \$15,\$16,256'
+.*.s:6: Error: opcode not supported on this processor: .* \(.*\) `alnv.ps \$f0,\$f2,\$f2,\$3'
+.*.s:7: Error: opcode not supported on this processor: .* \(.*\) `bc1f 1f'
+.*.s:8: Error: opcode not supported on this processor: .* \(.*\) `bc1fl 1f'
+.*.s:9: Error: opcode not supported on this processor: .* \(.*\) `bc1t 1f'
+.*.s:10: Error: opcode not supported on this processor: .* \(.*\) `bc1tl 1f'
+.*.s:11: Error: opcode not supported on this processor: .* \(.*\) `bc2f 1f'
+.*.s:12: Error: opcode not supported on this processor: .* \(.*\) `bc2fl 1f'
+.*.s:13: Error: opcode not supported on this processor: .* \(.*\) `bc2t 1f'
+.*.s:14: Error: opcode not supported on this processor: .* \(.*\) `bc2tl 1f'
+.*.s:15: Error: opcode not supported on this processor: .* \(.*\) `beql \$28,\$29,1f'
+.*.s:16: Error: opcode not supported on this processor: .* \(.*\) `bgezall \$28,1f'
+.*.s:17: Error: opcode not supported on this processor: .* \(.*\) `bgezl \$28,1f'
+.*.s:18: Error: opcode not supported on this processor: .* \(.*\) `bgtzl \$28,1f'
+.*.s:19: Error: opcode not supported on this processor: .* \(.*\) `blezl \$28,1f'
+.*.s:21: Error: opcode not supported on this processor: .* \(.*\) `bltzall \$28,1f'
+.*.s:22: Error: opcode not supported on this processor: .* \(.*\) `bltzl \$28,1f'
+.*.s:23: Error: opcode not supported on this processor: .* \(.*\) `bnel \$28,\$29,1f'
+.*.s:24: Error: opcode not supported on this processor: .* \(.*\) `c.f.s \$f0,\$f2'
+.*.s:25: Error: opcode not supported on this processor: .* \(.*\) `c.un.s \$f0,\$f2'
+.*.s:26: Error: opcode not supported on this processor: .* \(.*\) `c.eq.s \$f0,\$f2'
+.*.s:27: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.s \$f0,\$f2'
+.*.s:28: Error: opcode not supported on this processor: .* \(.*\) `c.olt.s \$f0,\$f2'
+.*.s:29: Error: opcode not supported on this processor: .* \(.*\) `c.ult.s \$f0,\$f2'
+.*.s:30: Error: opcode not supported on this processor: .* \(.*\) `c.ole.s \$f0,\$f2'
+.*.s:31: Error: opcode not supported on this processor: .* \(.*\) `c.ule.s \$f0,\$f2'
+.*.s:32: Error: opcode not supported on this processor: .* \(.*\) `c.sf.s \$f0,\$f2'
+.*.s:33: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.s \$f0,\$f2'
+.*.s:34: Error: opcode not supported on this processor: .* \(.*\) `c.seq.s \$f0,\$f2'
+.*.s:35: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.s \$f0,\$f2'
+.*.s:36: Error: opcode not supported on this processor: .* \(.*\) `c.lt.s \$f0,\$f2'
+.*.s:37: Error: opcode not supported on this processor: .* \(.*\) `c.nge.s \$f0,\$f2'
+.*.s:38: Error: opcode not supported on this processor: .* \(.*\) `c.le.s \$f0,\$f2'
+.*.s:39: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.s \$f0,\$f2'
+.*.s:40: Error: opcode not supported on this processor: .* \(.*\) `c.f.ps \$f0,\$f2'
+.*.s:41: Error: opcode not supported on this processor: .* \(.*\) `c.un.ps \$f0,\$f2'
+.*.s:42: Error: opcode not supported on this processor: .* \(.*\) `c.eq.ps \$f0,\$f2'
+.*.s:43: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.ps \$f0,\$f2'
+.*.s:44: Error: opcode not supported on this processor: .* \(.*\) `c.olt.ps \$f0,\$f2'
+.*.s:45: Error: opcode not supported on this processor: .* \(.*\) `c.ult.ps \$f0,\$f2'
+.*.s:46: Error: opcode not supported on this processor: .* \(.*\) `c.ole.ps \$f0,\$f2'
+.*.s:47: Error: opcode not supported on this processor: .* \(.*\) `c.ule.ps \$f0,\$f2'
+.*.s:48: Error: opcode not supported on this processor: .* \(.*\) `c.sf.ps \$f0,\$f2'
+.*.s:49: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.ps \$f0,\$f2'
+.*.s:50: Error: opcode not supported on this processor: .* \(.*\) `c.seq.ps \$f0,\$f2'
+.*.s:51: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.ps \$f0,\$f2'
+.*.s:52: Error: opcode not supported on this processor: .* \(.*\) `c.lt.ps \$f0,\$f2'
+.*.s:53: Error: opcode not supported on this processor: .* \(.*\) `c.nge.ps \$f0,\$f2'
+.*.s:54: Error: opcode not supported on this processor: .* \(.*\) `c.le.ps \$f0,\$f2'
+.*.s:55: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.ps \$f0,\$f2'
+.*.s:56: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f0,\$f2'
+.*.s:57: Error: opcode not supported on this processor: .* \(.*\) `c.un.d \$f0,\$f2'
+.*.s:58: Error: opcode not supported on this processor: .* \(.*\) `c.eq.d \$f0,\$f2'
+.*.s:59: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.d \$f0,\$f2'
+.*.s:60: Error: opcode not supported on this processor: .* \(.*\) `c.olt.d \$f0,\$f2'
+.*.s:61: Error: opcode not supported on this processor: .* \(.*\) `c.ult.d \$f0,\$f2'
+.*.s:62: Error: opcode not supported on this processor: .* \(.*\) `c.ole.d \$f0,\$f2'
+.*.s:63: Error: opcode not supported on this processor: .* \(.*\) `c.ule.d \$f0,\$f2'
+.*.s:64: Error: opcode not supported on this processor: .* \(.*\) `c.sf.d \$f0,\$f2'
+.*.s:65: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.d \$f0,\$f2'
+.*.s:66: Error: opcode not supported on this processor: .* \(.*\) `c.seq.d \$f0,\$f2'
+.*.s:67: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.d \$f0,\$f2'
+.*.s:68: Error: opcode not supported on this processor: .* \(.*\) `c.lt.d \$f0,\$f2'
+.*.s:69: Error: opcode not supported on this processor: .* \(.*\) `c.nge.d \$f0,\$f2'
+.*.s:70: Error: opcode not supported on this processor: .* \(.*\) `c.le.d \$f0,\$f2'
+.*.s:71: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.d \$f0,\$f2'
+.*.s:72: Error: opcode not supported on this processor: .* \(.*\) `c.f.s \$fcc2,\$f0,\$f2'
+.*.s:73: Error: opcode not supported on this processor: .* \(.*\) `c.un.s \$fcc2,\$f0,\$f2'
+.*.s:74: Error: opcode not supported on this processor: .* \(.*\) `c.eq.s \$fcc2,\$f0,\$f2'
+.*.s:75: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.s \$fcc2,\$f0,\$f2'
+.*.s:76: Error: opcode not supported on this processor: .* \(.*\) `c.olt.s \$fcc2,\$f0,\$f2'
+.*.s:77: Error: opcode not supported on this processor: .* \(.*\) `c.ult.s \$fcc2,\$f0,\$f2'
+.*.s:78: Error: opcode not supported on this processor: .* \(.*\) `c.ole.s \$fcc2,\$f0,\$f2'
+.*.s:79: Error: opcode not supported on this processor: .* \(.*\) `c.ule.s \$fcc2,\$f0,\$f2'
+.*.s:80: Error: opcode not supported on this processor: .* \(.*\) `c.sf.s \$fcc2,\$f0,\$f2'
+.*.s:81: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.s \$fcc2,\$f0,\$f2'
+.*.s:82: Error: opcode not supported on this processor: .* \(.*\) `c.seq.s \$fcc2,\$f0,\$f2'
+.*.s:83: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.s \$fcc2,\$f0,\$f2'
+.*.s:84: Error: opcode not supported on this processor: .* \(.*\) `c.lt.s \$fcc2,\$f0,\$f2'
+.*.s:85: Error: opcode not supported on this processor: .* \(.*\) `c.nge.s \$fcc2,\$f0,\$f2'
+.*.s:86: Error: opcode not supported on this processor: .* \(.*\) `c.le.s \$fcc2,\$f0,\$f2'
+.*.s:87: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.s \$fcc2,\$f0,\$f2'
+.*.s:88: Error: opcode not supported on this processor: .* \(.*\) `c.f.ps \$fcc2,\$f0,\$f2'
+.*.s:89: Error: opcode not supported on this processor: .* \(.*\) `c.un.ps \$fcc2,\$f0,\$f2'
+.*.s:90: Error: opcode not supported on this processor: .* \(.*\) `c.eq.ps \$fcc2,\$f0,\$f2'
+.*.s:91: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.ps \$fcc2,\$f0,\$f2'
+.*.s:92: Error: opcode not supported on this processor: .* \(.*\) `c.olt.ps \$fcc2,\$f0,\$f2'
+.*.s:93: Error: opcode not supported on this processor: .* \(.*\) `c.ult.ps \$fcc2,\$f0,\$f2'
+.*.s:94: Error: opcode not supported on this processor: .* \(.*\) `c.ole.ps \$fcc2,\$f0,\$f2'
+.*.s:95: Error: opcode not supported on this processor: .* \(.*\) `c.ule.ps \$fcc2,\$f0,\$f2'
+.*.s:96: Error: opcode not supported on this processor: .* \(.*\) `c.sf.ps \$fcc2,\$f0,\$f2'
+.*.s:97: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.ps \$fcc2,\$f0,\$f2'
+.*.s:98: Error: opcode not supported on this processor: .* \(.*\) `c.seq.ps \$fcc2,\$f0,\$f2'
+.*.s:99: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.ps \$fcc2,\$f0,\$f2'
+.*.s:100: Error: opcode not supported on this processor: .* \(.*\) `c.lt.ps \$fcc2,\$f0,\$f2'
+.*.s:101: Error: opcode not supported on this processor: .* \(.*\) `c.nge.ps \$fcc2,\$f0,\$f2'
+.*.s:102: Error: opcode not supported on this processor: .* \(.*\) `c.le.ps \$fcc2,\$f0,\$f2'
+.*.s:103: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.ps \$fcc2,\$f0,\$f2'
+.*.s:104: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc2,\$f0,\$f2'
+.*.s:105: Error: opcode not supported on this processor: .* \(.*\) `c.un.d \$fcc2,\$f0,\$f2'
+.*.s:106: Error: opcode not supported on this processor: .* \(.*\) `c.eq.d \$fcc2,\$f0,\$f2'
+.*.s:107: Error: opcode not supported on this processor: .* \(.*\) `c.ueq.d \$fcc2,\$f0,\$f2'
+.*.s:108: Error: opcode not supported on this processor: .* \(.*\) `c.olt.d \$fcc2,\$f0,\$f2'
+.*.s:109: Error: opcode not supported on this processor: .* \(.*\) `c.ult.d \$fcc2,\$f0,\$f2'
+.*.s:110: Error: opcode not supported on this processor: .* \(.*\) `c.ole.d \$fcc2,\$f0,\$f2'
+.*.s:111: Error: opcode not supported on this processor: .* \(.*\) `c.ule.d \$fcc2,\$f0,\$f2'
+.*.s:112: Error: opcode not supported on this processor: .* \(.*\) `c.sf.d \$fcc2,\$f0,\$f2'
+.*.s:113: Error: opcode not supported on this processor: .* \(.*\) `c.ngle.d \$fcc2,\$f0,\$f2'
+.*.s:114: Error: opcode not supported on this processor: .* \(.*\) `c.seq.d \$fcc2,\$f0,\$f2'
+.*.s:115: Error: opcode not supported on this processor: .* \(.*\) `c.ngl.d \$fcc2,\$f0,\$f2'
+.*.s:116: Error: opcode not supported on this processor: .* \(.*\) `c.lt.d \$fcc2,\$f0,\$f2'
+.*.s:117: Error: opcode not supported on this processor: .* \(.*\) `c.nge.d \$fcc2,\$f0,\$f2'
+.*.s:118: Error: opcode not supported on this processor: .* \(.*\) `c.le.d \$fcc2,\$f0,\$f2'
+.*.s:119: Error: opcode not supported on this processor: .* \(.*\) `c.ngt.d \$fcc2,\$f0,\$f2'
+.*.s:120: Error: opcode not supported on this processor: .* \(.*\) `cvt.ps.s \$f2,\$f3,\$f4'
+.*.s:121: Error: opcode not supported on this processor: .* \(.*\) `jalx 1f'
+.*.s:122: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f0,\$0\(\$2\)'
+.*.s:123: Error: opcode not supported on this processor: .* \(.*\) `luxc1 \$f0,\$0\(\$2\)'
+.*.s:124: Error: opcode not supported on this processor: .* \(.*\) `lwl \$2,1\(\$3\)'
+.*.s:125: Error: opcode not supported on this processor: .* \(.*\) `lwle \$4,0\(\$6\)'
+.*.s:126: Error: opcode not supported on this processor: .* \(.*\) `lwr \$2,1\(\$3\)'
+.*.s:127: Error: opcode not supported on this processor: .* \(.*\) `lwre \$4,0\(\$6\)'
+.*.s:128: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f0,\$0\(\$2\)'
+.*.s:129: Error: opcode not supported on this processor: .* \(.*\) `madd \$2,\$3'
+.*.s:130: Error: opcode not supported on this processor: .* \(.*\) `maddu \$2,\$3'
+.*.s:131: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f5,\$f6,\$f7,\$f8'
+.*.s:132: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f6,\$f8,\$f10,\$f12'
+.*.s:133: Error: opcode not supported on this processor: .* \(.*\) `madd.ps \$f6,\$f8,\$f10,\$f12'
+.*.s:134: Error: opcode not supported on this processor: .* \(.*\) `mfhi \$2'
+.*.s:135: Error: opcode not supported on this processor: .* \(.*\) `mflo \$2'
+.*.s:136: Error: opcode not supported on this processor: .* \(.*\) `mov.ps \$f10,\$f20'
+.*.s:137: Error: opcode not supported on this processor: .* \(.*\) `movf \$8,\$9,\$fcc0'
+.*.s:138: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f8,\$f9,\$fcc0'
+.*.s:139: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f8,\$f10,\$fcc0'
+.*.s:140: Error: opcode not supported on this processor: .* \(.*\) `movf.ps \$f8,\$f10,\$fcc0'
+.*.s:141: Error: opcode not supported on this processor: .* \(.*\) `movn \$2,\$3,\$4'
+.*.s:142: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f0,\$f2,\$10'
+.*.s:143: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f0,\$f2,\$10'
+.*.s:144: Error: opcode not supported on this processor: .* \(.*\) `movn.ps \$f0,\$f2,\$10'
+.*.s:145: Error: opcode not supported on this processor: .* \(.*\) `movt \$10,\$11,\$fcc2'
+.*.s:146: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f20,\$f21,\$fcc2'
+.*.s:147: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f20,\$f22,\$fcc2'
+.*.s:148: Error: opcode not supported on this processor: .* \(.*\) `movt.ps \$f20,\$f22,\$fcc2'
+.*.s:149: Error: opcode not supported on this processor: .* \(.*\) `movz \$5,\$6,\$7'
+.*.s:150: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f0,\$f2,\$10'
+.*.s:151: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f0,\$f2,\$10'
+.*.s:152: Error: opcode not supported on this processor: .* \(.*\) `movz.ps \$f0,\$f2,\$10'
+.*.s:153: Error: opcode not supported on this processor: .* \(.*\) `msub \$2,\$3'
+.*.s:154: Error: opcode not supported on this processor: .* \(.*\) `msubu \$2,\$3'
+.*.s:155: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f5,\$f6,\$f7,\$f8'
+.*.s:156: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f6,\$f8,\$f10,\$f12'
+.*.s:157: Error: opcode not supported on this processor: .* \(.*\) `msub.ps \$f6,\$f8,\$f10,\$f12'
+.*.s:158: Error: opcode not supported on this processor: .* \(.*\) `mthi32 \$2'
+.*.s:159: Error: opcode not supported on this processor: .* \(.*\) `mtlo32 \$2'
+.*.s:160: Error: opcode not supported on this processor: .* \(.*\) `mul.ps \$f10,\$f20,\$f22'
+.*.s:161: Error: opcode not supported on this processor: .* \(.*\) `mult \$2,\$3'
+.*.s:162: Error: opcode not supported on this processor: .* \(.*\) `multu \$2,\$3'
+.*.s:163: Error: opcode not supported on this processor: .* \(.*\) `neg.ps \$f22,\$f24'
+.*.s:164: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f5,\$f6,\$f7,\$f8'
+.*.s:165: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f6,\$f8,\$f10,\$f12'
+.*.s:166: Error: opcode not supported on this processor: .* \(.*\) `nmadd.ps \$f6,\$f8,\$f10,\$f12'
+.*.s:167: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f5,\$f6,\$f7,\$f8'
+.*.s:168: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f6,\$f8,\$f10,\$f12'
+.*.s:169: Error: opcode not supported on this processor: .* \(.*\) `nmsub.ps \$f6,\$f8,\$f10,\$f12'
+.*.s:170: Error: opcode not supported on this processor: .* \(.*\) `pll.ps \$f24,\$f20,\$f26'
+.*.s:171: Error: opcode not supported on this processor: .* \(.*\) `plu.ps \$f24,\$f20,\$f26'
+.*.s:172: Error: opcode not supported on this processor: .* \(.*\) `pul.ps \$f24,\$f20,\$f26'
+.*.s:173: Error: opcode not supported on this processor: .* \(.*\) `puu.ps \$f24,\$f20,\$f26'
+.*.s:174: Error: opcode not supported on this processor: .* \(.*\) `prefx 5,\$3\(\$5\)'
+.*.s:175: Error: opcode not supported on this processor: .* \(.*\) `sub.ps \$f20,\$f28,\$f26'
+.*.s:176: Error: opcode not supported on this processor: .* \(.*\) `suxc1 \$f0,\$0\(\$2\)'
+.*.s:177: Error: opcode not supported on this processor: .* \(.*\) `swl \$2,1\(\$3\)'
+.*.s:178: Error: opcode not supported on this processor: .* \(.*\) `swle \$4,0\(\$6\)'
+.*.s:179: Error: opcode not supported on this processor: .* \(.*\) `swr \$2,1\(\$3\)'
+.*.s:180: Error: opcode not supported on this processor: .* \(.*\) `swre \$4,0\(\$6\)'
+.*.s:181: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f0,\$0\(\$2\)'
+.*.s:182: Error: opcode not supported on this processor: .* \(.*\) `teqi \$11,1024'
+.*.s:183: Error: opcode not supported on this processor: .* \(.*\) `tgei \$11,1024'
+.*.s:184: Error: opcode not supported on this processor: .* \(.*\) `tgeiu \$11,1024'
+.*.s:185: Error: opcode not supported on this processor: .* \(.*\) `tlti \$11,1024'
+.*.s:186: Error: opcode not supported on this processor: .* \(.*\) `tltiu \$11,1024'
+.*.s:187: Error: opcode not supported on this processor: .* \(.*\) `tnei \$11,1024'
+.*.s:188: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f0,\$0\(\$0\)'
diff --git a/gas/testsuite/gas/mips/ur6-removed.s b/gas/testsuite/gas/mips/ur6-removed.s
new file mode 100644
index 00000000000..f63b03a0acc
--- /dev/null
+++ b/gas/testsuite/gas/mips/ur6-removed.s
@@ -0,0 +1,192 @@
+ .set reorder
+foo:
+ abs.ps $f0,$f2
+ add.ps $f0,$f2,$f2
+ addi $15,$16,256
+ alnv.ps $f0,$f2,$f2,$3
+ bc1f 1f
+ bc1fl 1f
+ bc1t 1f
+ bc1tl 1f
+ bc2f 1f
+ bc2fl 1f
+ bc2t 1f
+ bc2tl 1f
+ beql $28,$29,1f
+ bgezall $28,1f
+ bgezl $28,1f
+ bgtzl $28,1f
+ blezl $28,1f
+ bltzal $4,1f
+ bltzall $28,1f
+ bltzl $28,1f
+ bnel $28,$29,1f
+ c.f.s $f0,$f2
+ c.un.s $f0,$f2
+ c.eq.s $f0,$f2
+ c.ueq.s $f0,$f2
+ c.olt.s $f0,$f2
+ c.ult.s $f0,$f2
+ c.ole.s $f0,$f2
+ c.ule.s $f0,$f2
+ c.sf.s $f0,$f2
+ c.ngle.s $f0,$f2
+ c.seq.s $f0,$f2
+ c.ngl.s $f0,$f2
+ c.lt.s $f0,$f2
+ c.nge.s $f0,$f2
+ c.le.s $f0,$f2
+ c.ngt.s $f0,$f2
+ c.f.ps $f0,$f2
+ c.un.ps $f0,$f2
+ c.eq.ps $f0,$f2
+ c.ueq.ps $f0,$f2
+ c.olt.ps $f0,$f2
+ c.ult.ps $f0,$f2
+ c.ole.ps $f0,$f2
+ c.ule.ps $f0,$f2
+ c.sf.ps $f0,$f2
+ c.ngle.ps $f0,$f2
+ c.seq.ps $f0,$f2
+ c.ngl.ps $f0,$f2
+ c.lt.ps $f0,$f2
+ c.nge.ps $f0,$f2
+ c.le.ps $f0,$f2
+ c.ngt.ps $f0,$f2
+ c.f.d $f0,$f2
+ c.un.d $f0,$f2
+ c.eq.d $f0,$f2
+ c.ueq.d $f0,$f2
+ c.olt.d $f0,$f2
+ c.ult.d $f0,$f2
+ c.ole.d $f0,$f2
+ c.ule.d $f0,$f2
+ c.sf.d $f0,$f2
+ c.ngle.d $f0,$f2
+ c.seq.d $f0,$f2
+ c.ngl.d $f0,$f2
+ c.lt.d $f0,$f2
+ c.nge.d $f0,$f2
+ c.le.d $f0,$f2
+ c.ngt.d $f0,$f2
+ c.f.s $fcc2, $f0,$f2
+ c.un.s $fcc2, $f0,$f2
+ c.eq.s $fcc2, $f0,$f2
+ c.ueq.s $fcc2, $f0,$f2
+ c.olt.s $fcc2, $f0,$f2
+ c.ult.s $fcc2, $f0,$f2
+ c.ole.s $fcc2, $f0,$f2
+ c.ule.s $fcc2, $f0,$f2
+ c.sf.s $fcc2, $f0,$f2
+ c.ngle.s $fcc2, $f0,$f2
+ c.seq.s $fcc2, $f0,$f2
+ c.ngl.s $fcc2, $f0,$f2
+ c.lt.s $fcc2, $f0,$f2
+ c.nge.s $fcc2, $f0,$f2
+ c.le.s $fcc2, $f0,$f2
+ c.ngt.s $fcc2, $f0,$f2
+ c.f.ps $fcc2, $f0,$f2
+ c.un.ps $fcc2, $f0,$f2
+ c.eq.ps $fcc2, $f0,$f2
+ c.ueq.ps $fcc2, $f0,$f2
+ c.olt.ps $fcc2, $f0,$f2
+ c.ult.ps $fcc2, $f0,$f2
+ c.ole.ps $fcc2, $f0,$f2
+ c.ule.ps $fcc2, $f0,$f2
+ c.sf.ps $fcc2, $f0,$f2
+ c.ngle.ps $fcc2, $f0,$f2
+ c.seq.ps $fcc2, $f0,$f2
+ c.ngl.ps $fcc2, $f0,$f2
+ c.lt.ps $fcc2, $f0,$f2
+ c.nge.ps $fcc2, $f0,$f2
+ c.le.ps $fcc2, $f0,$f2
+ c.ngt.ps $fcc2, $f0,$f2
+ c.f.d $fcc2, $f0,$f2
+ c.un.d $fcc2, $f0,$f2
+ c.eq.d $fcc2, $f0,$f2
+ c.ueq.d $fcc2, $f0,$f2
+ c.olt.d $fcc2, $f0,$f2
+ c.ult.d $fcc2, $f0,$f2
+ c.ole.d $fcc2, $f0,$f2
+ c.ule.d $fcc2, $f0,$f2
+ c.sf.d $fcc2, $f0,$f2
+ c.ngle.d $fcc2, $f0,$f2
+ c.seq.d $fcc2, $f0,$f2
+ c.ngl.d $fcc2, $f0,$f2
+ c.lt.d $fcc2, $f0,$f2
+ c.nge.d $fcc2, $f0,$f2
+ c.le.d $fcc2, $f0,$f2
+ c.ngt.d $fcc2, $f0,$f2
+ cvt.ps.s $f2,$f3,$f4
+ jalx 1f
+ ldxc1 $f0,$0($2)
+ luxc1 $f0,$0($2)
+ lwl $2, 1($3)
+ lwle $4,0($6)
+ lwr $2, 1($3)
+ lwre $4,0($6)
+ lwxc1 $f0,$0($2)
+ madd $2,$3
+ maddu $2,$3
+ madd.s $f5,$f6,$f7,$f8
+ madd.d $f6,$f8,$f10,$f12
+ madd.ps $f6,$f8,$f10,$f12
+ mfhi $2
+ mflo $2
+ mov.ps $f10,$f20
+ movf $8,$9,$fcc0
+ movf.s $f8,$f9,$fcc0
+ movf.d $f8,$f10,$fcc0
+ movf.ps $f8,$f10,$fcc0
+ movn $2,$3,$4
+ movn.s $f0,$f2,$10
+ movn.d $f0,$f2,$10
+ movn.ps $f0,$f2,$10
+ movt $10,$11,$fcc2
+ movt.s $f20,$f21,$fcc2
+ movt.d $f20,$f22,$fcc2
+ movt.ps $f20,$f22,$fcc2
+ movz $5,$6,$7
+ movz.s $f0,$f2,$10
+ movz.d $f0,$f2,$10
+ movz.ps $f0,$f2,$10
+ msub $2,$3
+ msubu $2,$3
+ msub.s $f5,$f6,$f7,$f8
+ msub.d $f6,$f8,$f10,$f12
+ msub.ps $f6,$f8,$f10,$f12
+ mthi32 $2
+ mtlo32 $2
+ mul.ps $f10,$f20,$f22
+ mult $2,$3
+ multu $2,$3
+ neg.ps $f22,$f24
+ nmadd.s $f5,$f6,$f7,$f8
+ nmadd.d $f6,$f8,$f10,$f12
+ nmadd.ps $f6,$f8,$f10,$f12
+ nmsub.s $f5,$f6,$f7,$f8
+ nmsub.d $f6,$f8,$f10,$f12
+ nmsub.ps $f6,$f8,$f10,$f12
+ pll.ps $f24,$f20,$f26
+ plu.ps $f24,$f20,$f26
+ pul.ps $f24,$f20,$f26
+ puu.ps $f24,$f20,$f26
+ prefx 5, $3($5)
+ sub.ps $f20,$f28,$f26
+ suxc1 $f0,$0($2)
+ swl $2, 1($3)
+ swle $4,0($6)
+ swr $2, 1($3)
+ swre $4,0($6)
+ swxc1 $f0,$0($2)
+ teqi $11,1024
+ tgei $11,1024
+ tgeiu $11,1024
+ tlti $11,1024
+ tltiu $11,1024
+ tnei $11,1024
+ sdxc1 $f0, $0($0)
+1:
+ .insn
+ .align 2
+ .space 8
diff --git a/gas/testsuite/gas/mips/ur6.d b/gas/testsuite/gas/mips/ur6.d
new file mode 100644
index 00000000000..826cb576c18
--- /dev/null
+++ b/gas/testsuite/gas/mips/ur6.d
@@ -0,0 +1,419 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: MIPS microMIPS R6 instructions
+#as: -32
+
+# Check microMIPS R6 instructions
+
+.*: +file format .*mips.*
+
+
+Disassembly of section .text:
+[0-9a-f]+ <[^>]*> 5441 01b8 maddf.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 54a4 1bb8 maddf.d \$f3,\$f4,\$f5
+[0-9a-f]+ <[^>]*> 5507 31f8 msubf.s \$f6,\$f7,\$f8
+[0-9a-f]+ <[^>]*> 556a 4bf8 msubf.d \$f9,\$f10,\$f11
+[0-9a-f]+ <[^>]*> 5441 0005 cmp.af.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0015 cmp.af.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0045 cmp.un.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0055 cmp.un.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0085 cmp.eq.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0095 cmp.eq.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 00c5 cmp.ueq.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 00d5 cmp.ueq.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0105 cmp.lt.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0115 cmp.lt.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0145 cmp.ult.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0155 cmp.ult.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0185 cmp.le.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0195 cmp.le.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 01c5 cmp.ule.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 01d5 cmp.ule.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0205 cmp.saf.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0215 cmp.saf.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0245 cmp.sun.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0255 cmp.sun.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0285 cmp.seq.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0295 cmp.seq.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 02c5 cmp.sueq.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 02d5 cmp.sueq.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0305 cmp.slt.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0315 cmp.slt.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0345 cmp.sult.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0355 cmp.sult.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0385 cmp.sle.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0395 cmp.sle.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 03c5 cmp.sule.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 03d5 cmp.sule.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0445 cmp.or.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0455 cmp.or.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0485 cmp.une.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0495 cmp.une.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 04c5 cmp.ne.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 04d5 cmp.ne.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0645 cmp.sor.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0655 cmp.sor.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0685 cmp.sune.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0695 cmp.sune.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 06c5 cmp.sne.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 06d5 cmp.sne.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 4100 fffe bc1eqzc \$f0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 411f fffe bc1eqzc \$f31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 411f fffe bc1eqzc \$f31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 new
+[0-9a-f]+ <[^>]*> 411f fffe bc1eqzc \$f31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 4120 fffe bc1nezc \$f0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 413f fffe bc1nezc \$f31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 413f fffe bc1nezc \$f31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 new
+[0-9a-f]+ <[^>]*> 413f fffe bc1nezc \$f31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 4140 fffe bc2eqzc \$0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 415f fffe bc2eqzc \$31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 415f fffe bc2eqzc \$31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 new
+[0-9a-f]+ <[^>]*> 415f fffe bc2eqzc \$31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 4160 fffe bc2nezc \$0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 417f fffe bc2nezc \$31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 417f fffe bc2nezc \$31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 new
+[0-9a-f]+ <[^>]*> 417f fffe bc2nezc \$31,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 external_label
+[0-9a-f]+ <[^>]*> 5441 00b8 sel.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 02b8 sel.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0038 seleqz.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0238 seleqz.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0078 selnez.s \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 5441 0278 selnez.d \$f0,\$f1,\$f2
+[0-9a-f]+ <[^>]*> 0083 1140 seleqz v0,v1,a0
+[0-9a-f]+ <[^>]*> 0083 1180 selnez v0,v1,a0
+[0-9a-f]+ <[^>]*> 0083 1018 mul v0,v1,a0
+[0-9a-f]+ <[^>]*> 0083 1058 muh v0,v1,a0
+[0-9a-f]+ <[^>]*> 0083 1098 mulu v0,v1,a0
+[0-9a-f]+ <[^>]*> 0083 10d8 muhu v0,v1,a0
+[0-9a-f]+ <[^>]*> 0083 1118 div v0,v1,a0
+[0-9a-f]+ <[^>]*> 0083 1158 mod v0,v1,a0
+[0-9a-f]+ <[^>]*> 0083 1198 divu v0,v1,a0
+[0-9a-f]+ <[^>]*> 0083 11d8 modu v0,v1,a0
+[0-9a-f]+ <[^>]*> 0083 100f lsa v0,v1,a0,0x1
+[0-9a-f]+ <[^>]*> 0083 160f lsa v0,v1,a0,0x4
+[0-9a-f]+ <[^>]*> 0062 201f align a0,v0,v1,0
+[0-9a-f]+ <[^>]*> 0062 221f align a0,v0,v1,1
+[0-9a-f]+ <[^>]*> 0062 241f align a0,v0,v1,2
+[0-9a-f]+ <[^>]*> 0062 261f align a0,v0,v1,3
+[0-9a-f]+ <[^>]*> 0044 0b3c bitswap a0,v0
+[0-9a-f]+ <[^>]*> 7400 fffe bovc zero,zero,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7402 fffe bovc v0,zero,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7402 fffe bovc v0,zero,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7444 fffe bovc a0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7444 fffe bovc a0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7444 8000 bovc a0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7444 7fff bovc a0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7444 fffe bovc a0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 7442 fffe bovc v0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7442 8000 bovc v0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7440 fffe beqzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7440 8000 beqzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7440 7fff beqzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7440 fffe beqzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 7462 fffe beqc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7462 fffe beqc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7462 8000 beqc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7462 7fff beqc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7462 fffe beqc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 7c00 fffe bnvc zero,zero,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7c02 fffe bnvc v0,zero,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7c02 fffe bnvc v0,zero,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7c44 fffe bnvc a0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7c44 fffe bnvc a0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7c44 8000 bnvc a0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7c44 7fff bnvc a0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7c44 fffe bnvc a0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 7c42 fffe bnvc v0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7c42 8000 bnvc v0,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7c40 fffe bnezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7c40 8000 bnezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7c40 7fff bnezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7c40 fffe bnezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 7c62 fffe bnec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7c62 fffe bnec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> 7c62 8000 bnec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7c62 7fff bnec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> 7c62 fffe bnec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> f440 fffe blezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> f440 8000 blezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> f440 7fff blezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> f440 fffe blezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> f442 fffe bgezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> f442 8000 bgezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> f442 7fff bgezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> f442 fffe bgezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 f
+[0-9a-f]+ <[^>]*> f462 fffe bgec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> f462 8000 bgec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> f462 7fff bgec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> f462 fffe bgec v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> f443 fffe bgec v1,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> d440 fffe bgtzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> d440 8000 bgtzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> d440 7fff bgtzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> d440 fffe bgtzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> d442 fffe bltzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> d442 8000 bltzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> d442 7fff bltzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> d442 fffe bltzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> d462 fffe bltc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> d462 8000 bltc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> d462 7fff bltc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> d462 fffe bltc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> d443 fffe bltc v1,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> c040 fffe blezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> c040 8000 blezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> c040 7fff blezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> c040 fffe blezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> c042 fffe bgezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> c042 8000 bgezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> c042 7fff bgezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> c042 fffe bgezalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> c062 fffe bgeuc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> c062 8000 bgeuc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> c062 7fff bgeuc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> c062 fffe bgeuc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> c043 fffe bgeuc v1,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> e040 fffe bgtzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> e040 8000 bgtzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> e040 7fff bgtzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> e040 fffe bgtzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> e042 fffe bltzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> e042 8000 bltzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> e042 7fff bltzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> e042 fffe bltzalc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> e062 fffe bltuc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 ext
+[0-9a-f]+ <[^>]*> e062 8000 bltuc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> e062 7fff bltuc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 L0\x01
+[0-9a-f]+ <[^>]*> e062 fffe bltuc v0,v1,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> e043 fffe bltuc v1,v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 97ff fffe bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 ext
+[0-9a-f]+ <[^>]*> 9600 0000 bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 L0\x01
+[0-9a-f]+ <[^>]*> 95ff ffff bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 L0\x01
+[0-9a-f]+ <[^>]*> cfff bc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .L1\x021
+[0-9a-f]+ <[^>]*> b7ff fffe balc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 ext
+[0-9a-f]+ <[^>]*> b600 0000 balc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 L0\x01
+[0-9a-f]+ <[^>]*> b5ff ffff balc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 L0\x01
+[0-9a-f]+ <[^>]*> b7ff fffe balc [0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 8d40 beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 L0\x01
+[0-9a-f]+ <[^>]*> 8d3f beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 L0\x01
+[0-9a-f]+ <[^>]*> 805f fffe beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> 8050 0000 beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 L0\x01
+[0-9a-f]+ <[^>]*> 804f ffff beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 L0\x01
+[0-9a-f]+ <[^>]*> 805f fffe beqzc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 .L1\x021
+[0-9a-f]+ <[^>]*> 8003 8000 jic v1,-[0-9]+
+[0-9a-f]+ <[^>]*> 8003 7fff jic v1,[0-9]+
+[0-9a-f]+ <[^>]*> 47e3 jrc ra
+[0-9a-f]+ <[^>]*> ad40 bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 L0\x01
+[0-9a-f]+ <[^>]*> ad3f bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 L0\x01
+[0-9a-f]+ <[^>]*> a05f fffe bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 ext
+[0-9a-f]+ <[^>]*> a050 0000 bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 L0\x01
+[0-9a-f]+ <[^>]*> a04f ffff bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 L0\x01
+[0-9a-f]+ <[^>]*> a05f fffe bnezc v0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 .L1\x021
+[0-9a-f]+ <[^>]*> a003 8000 jialc v1,-[0-9]+
+[0-9a-f]+ <[^>]*> a003 7fff jialc v1,[0-9]+
+[0-9a-f]+ <[^>]*> 1062 ffff aui v1,v0,0xffff
+[0-9a-f]+ <[^>]*> 7884 0000 lapc a0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC19_S2 L0\x01
+[0-9a-f]+ <[^>]*> 7883 ffff lapc a0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC19_S2 L0\x01
+[0-9a-f]+ <[^>]*> 7884 0000 lapc a0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 7883 ffff lapc a0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 7904 0000 lapc t0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 7903 ffff lapc t0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 787e ffff auipc v1,0xffff
+[0-9a-f]+ <[^>]*> 787f ffff aluipc v1,0xffff
+[0-9a-f]+ <[^>]*> 7888 0000 lwpc a0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC19_S2 .L1\x021
+[0-9a-f]+ <[^>]*> 788c 0000 lwpc a0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC19_S2 L0\x01
+[0-9a-f]+ <[^>]*> 788b ffff lwpc a0,[0-9a-f]+ <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC19_S2 L0\x01
+[0-9a-f]+ <[^>]*> 788c 0000 lwpc a0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 788b ffff lwpc a0,[0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 5462 0020 rint.s \$f2,\$f3
+[0-9a-f]+ <[^>]*> 5462 0220 rint.d \$f2,\$f3
+[0-9a-f]+ <[^>]*> 5462 0060 class.s \$f2,\$f3
+[0-9a-f]+ <[^>]*> 5462 0260 class.d \$f2,\$f3
+[0-9a-f]+ <[^>]*> 5483 1003 min.s \$f2,\$f3,\$f4
+[0-9a-f]+ <[^>]*> 5483 1203 min.d \$f2,\$f3,\$f4
+[0-9a-f]+ <[^>]*> 5483 100b max.s \$f2,\$f3,\$f4
+[0-9a-f]+ <[^>]*> 5483 120b max.d \$f2,\$f3,\$f4
+[0-9a-f]+ <[^>]*> 5483 1023 mina.s \$f2,\$f3,\$f4
+[0-9a-f]+ <[^>]*> 5483 1223 mina.d \$f2,\$f3,\$f4
+[0-9a-f]+ <[^>]*> 5483 102b maxa.s \$f2,\$f3,\$f4
+[0-9a-f]+ <[^>]*> 5483 122b maxa.d \$f2,\$f3,\$f4
+[0-9a-f]+ <[^>]*> 0002 0100 lwxs zero,zero\(v0\)
+[0-9a-f]+ <[^>]*> 4180 ffff synci -1\(zero\)
+[0-9a-f]+ <[^>]*> 1040 ffff lui v0,0xffff
+[0-9a-f]+ <[^>]*> 4530 not v0,v1
+[0-9a-f]+ <[^>]*> 4538 xor v0,v0,v1
+[0-9a-f]+ <[^>]*> 4531 and v0,v0,v1
+[0-9a-f]+ <[^>]*> 4539 or v0,v0,v1
+[0-9a-f]+ <[^>]*> 2225 5000 lwm s0,ra,0\(a1\)
+[0-9a-f]+ <[^>]*> 2225 d000 swm s0,ra,0\(a1\)
+[0-9a-f]+ <[^>]*> 4463 jrc v1
+[0-9a-f]+ <[^>]*> 444b jalrc v0
+[0-9a-f]+ <[^>]*> 4433 jrcaddiusp 4
+[0-9a-f]+ <[^>]*> 469b break 0xa
+[0-9a-f]+ <[^>]*> 443b sdbbp
+[0-9a-f]+ <[^>]*> 443b sdbbp
+[0-9a-f]+ <[^>]*> 447b sdbbp 0x1
+[0-9a-f]+ <[^>]*> 47fb sdbbp 0xf
+[0-9a-f]+ <[^>]*> 001f 1f3c jrc.hb ra
+[0-9a-f]+ <[^>]*> 03e0 1f3c jalrc.hb zero
+[0-9a-f]+ <[^>]*> 001f 1f3c jrc.hb ra
+[0-9a-f]+ <[^>]*> 005f 1f3c jalrc.hb v0,ra
+[0-9a-f]+ <[^>]*> 0002 1f3c jrc.hb v0
+[0-9a-f]+ <[^>]*> 000a 1f3c jrc.hb t2
+[0-9a-f]+ <[^>]*> 60a6 1040 llwp a1,a0,a2
+[0-9a-f]+ <[^>]*> 60a6 9040 scwp a1,a0,a2
+[0-9a-f]+ <[^>]*> 6085 b000 sc a0,0\(a1\)
+[0-9a-f]+ <[^>]*> cfff bc 000003d4 <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .L1.1
+[0-9a-f]+ <[^>]*> 6085 b000 sc a0,0\(a1\)
+[0-9a-f]+ <[^>]*> cfff bc 000003da <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .L1.1
+[0-9a-f]+ <[^>]*> 60a6 6440 llwpe a1,a0,a2
+[0-9a-f]+ <[^>]*> 60a6 a040 scwpe a1,a0,a2
+[0-9a-f]+ <[^>]*> 6085 ac00 sce a0,0\(a1\)
+[0-9a-f]+ <[^>]*> cfff bc 000003e8 <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .L1.1
+[0-9a-f]+ <[^>]*> 6085 ac00 sce a0,0\(a1\)
+[0-9a-f]+ <[^>]*> cfff bc 000003ee <[^>]*>
+[ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 .L1.1
+[0-9a-f]+ <[^>]*> 0004 01c0 rdhwr zero,\$4
+[0-9a-f]+ <[^>]*> 0004 09c0 rdhwr zero,\$4,1
+[0-9a-f]+ <[^>]*> 0004 11c0 rdhwr zero,\$4,2
+[0-9a-f]+ <[^>]*> 0004 19c0 rdhwr zero,\$4,3
+[0-9a-f]+ <[^>]*> 0004 21c0 rdhwr zero,\$4,4
+[0-9a-f]+ <[^>]*> 0004 29c0 rdhwr zero,\$4,5
+[0-9a-f]+ <[^>]*> 0004 31c0 rdhwr zero,\$4,6
+[0-9a-f]+ <[^>]*> 0004 39c0 rdhwr zero,\$4,7
+[0-9a-f]+ <[^>]*> 0000 003f sigrie 0x0
+[0-9a-f]+ <[^>]*> 003f ffff sigrie 0xffff
+ \.\.\.
diff --git a/gas/testsuite/gas/mips/ur6.s b/gas/testsuite/gas/mips/ur6.s
new file mode 100644
index 00000000000..f0e06e2d63d
--- /dev/null
+++ b/gas/testsuite/gas/mips/ur6.s
@@ -0,0 +1,306 @@
+ .text
+ .set reorder
+ .set micromips
+foo:
+ maddf.s $f0,$f1,$f2
+ maddf.d $f3,$f4,$f5
+ msubf.s $f6,$f7,$f8
+ msubf.d $f9,$f10,$f11
+
+ cmp.af.s $f0,$f1,$f2
+ cmp.af.d $f0,$f1,$f2
+ cmp.un.s $f0,$f1,$f2
+ cmp.un.d $f0,$f1,$f2
+ cmp.eq.s $f0,$f1,$f2
+ cmp.eq.d $f0,$f1,$f2
+ cmp.ueq.s $f0,$f1,$f2
+ cmp.ueq.d $f0,$f1,$f2
+ cmp.lt.s $f0,$f1,$f2
+ cmp.lt.d $f0,$f1,$f2
+ cmp.ult.s $f0,$f1,$f2
+ cmp.ult.d $f0,$f1,$f2
+ cmp.le.s $f0,$f1,$f2
+ cmp.le.d $f0,$f1,$f2
+ cmp.ule.s $f0,$f1,$f2
+ cmp.ule.d $f0,$f1,$f2
+ cmp.saf.s $f0,$f1,$f2
+ cmp.saf.d $f0,$f1,$f2
+ cmp.sun.s $f0,$f1,$f2
+ cmp.sun.d $f0,$f1,$f2
+ cmp.seq.s $f0,$f1,$f2
+ cmp.seq.d $f0,$f1,$f2
+ cmp.sueq.s $f0,$f1,$f2
+ cmp.sueq.d $f0,$f1,$f2
+ cmp.slt.s $f0,$f1,$f2
+ cmp.slt.d $f0,$f1,$f2
+ cmp.sult.s $f0,$f1,$f2
+ cmp.sult.d $f0,$f1,$f2
+ cmp.sle.s $f0,$f1,$f2
+ cmp.sle.d $f0,$f1,$f2
+ cmp.sule.s $f0,$f1,$f2
+ cmp.sule.d $f0,$f1,$f2
+ cmp.or.s $f0,$f1,$f2
+ cmp.or.d $f0,$f1,$f2
+ cmp.une.s $f0,$f1,$f2
+ cmp.une.d $f0,$f1,$f2
+ cmp.ne.s $f0,$f1,$f2
+ cmp.ne.d $f0,$f1,$f2
+ cmp.sor.s $f0,$f1,$f2
+ cmp.sor.d $f0,$f1,$f2
+ cmp.sune.s $f0,$f1,$f2
+ cmp.sune.d $f0,$f1,$f2
+ cmp.sne.s $f0,$f1,$f2
+ cmp.sne.d $f0,$f1,$f2
+
+ bc1eqzc $f0,1f
+ bc1eqzc $f31,1f
+ bc1eqzc $f31,new
+ bc1eqzc $f31,external_label
+ bc1nezc $f0,1f
+ bc1nezc $f31,1f
+ bc1nezc $f31,new
+ bc1nezc $f31,external_label
+ bc2eqzc $0,1f
+ bc2eqzc $31,1f
+ bc2eqzc $31,new
+ bc2eqzc $31,external_label
+ bc2nezc $0,1f
+ bc2nezc $31,1f
+ bc2nezc $31,new
+ bc2nezc $31,external_label
+ sel.s $f0,$f1,$f2
+ sel.d $f0,$f1,$f2
+ seleqz.s $f0,$f1,$f2
+ seleqz.d $f0,$f1,$f2
+ selnez.s $f0,$f1,$f2
+ selnez.d $f0,$f1,$f2
+ seleqz $2,$3,$4
+ selnez $2,$3,$4
+ mul $2,$3,$4
+ muh $2,$3,$4
+ mulu $2,$3,$4
+ muhu $2,$3,$4
+ div $2,$3,$4
+ mod $2,$3,$4
+ divu $2,$3,$4
+ modu $2,$3,$4
+ lsa $2,$3,$4,1
+ lsa $2,$3,$4,4
+
+ align $4, $2, $3, 0
+ align $4, $2, $3, 1
+ align $4, $2, $3, 2
+ align $4, $2, $3, 3
+
+ bitswap $4, $2
+
+ bovc $0, $0, ext
+ bovc $2, $0, ext
+ bovc $0, $2, ext
+ bovc $2, $4, ext
+ bovc $4, $2, ext
+ bovc $2, $4, . + 4 + (-32768 << 1)
+ bovc $2, $4, . + 4 + (32767 << 1)
+ bovc $2, $4, 1f
+ bovc $2, $2, ext
+ bovc $2, $2, . + 4 + (-32768 << 1)
+ beqzalc $2, ext
+ beqzalc $2, . + 4 + (-32768 << 1)
+ beqzalc $2, . + 4 + (32767 << 1)
+ beqzalc $2, 1f
+ beqc $3, $2, ext
+ beqc $2, $3, ext
+ beqc $3, $2, . + 4 + (-32768 << 1)
+ beqc $3, $2, . + 4 + (32767 << 1)
+ beqc $3, $2, 1f
+
+ bnvc $0, $0, ext
+ bnvc $2, $0, ext
+ bnvc $0, $2, ext
+ bnvc $2, $4, ext
+ bnvc $4, $2, ext
+ bnvc $2, $4, . + 4 + (-32768 << 1)
+ bnvc $2, $4, . + 4 + (32767 << 1)
+ bnvc $2, $4, 1f
+ bnvc $2, $2, ext
+ bnvc $2, $2, . + 4 + (-32768 << 1)
+ bnezalc $2, ext
+ bnezalc $2, . + 4 + (-32768 << 1)
+ bnezalc $2, . + 4 + (32767 << 1)
+ bnezalc $2, 1f
+ bnec $3, $2, ext
+ bnec $2, $3, ext
+ bnec $3, $2, . + 4 + (-32768 << 1)
+ bnec $3, $2, . + 4 + (32767 << 1)
+ bnec $3, $2, 1f
+
+ blezc $2, ext
+ blezc $2, . + 4 + (-32768 << 1)
+ blezc $2, . + 4 + (32767 << 1)
+ blezc $2, 1f
+ bgezc $2, ext
+ bgezc $2, . + 4 + (-32768 << 1)
+ bgezc $2, . + 4 + (32767 << 1)
+ bgezc $2, f
+ bgec $2, $3, ext
+ bgec $2, $3, . + 4 + (-32768 << 1)
+ bgec $2, $3, . + 4 + (32767 << 1)
+ bgec $2, $3, 1f
+ bgec $3, $2, 1f
+
+ bgtzc $2, ext
+ bgtzc $2, . + 4 + (-32768 << 1)
+ bgtzc $2, . + 4 + (32767 << 1)
+ bgtzc $2, 1f
+ bltzc $2, ext
+ bltzc $2, . + 4 + (-32768 << 1)
+ bltzc $2, . + 4 + (32767 << 1)
+ bltzc $2, 1f
+ bltc $2, $3, ext
+ bltc $2, $3, . + 4 + (-32768 << 1)
+ bltc $2, $3, . + 4 + (32767 << 1)
+ bltc $2, $3, 1f
+ bltc $3, $2, 1f
+
+ blezalc $2, ext
+ blezalc $2, . + 4 + (-32768 << 1)
+ blezalc $2, . + 4 + (32767 << 1)
+ blezalc $2, 1f
+ bgezalc $2, ext
+ bgezalc $2, . + 4 + (-32768 << 1)
+ bgezalc $2, . + 4 + (32767 << 1)
+ bgezalc $2, 1f
+ bgeuc $2, $3, ext
+ bgeuc $2, $3, . + 4 + (-32768 << 1)
+ bgeuc $2, $3, . + 4 + (32767 << 1)
+ bgeuc $2, $3, 1f
+ bgeuc $3, $2, 1f
+
+ bgtzalc $2, ext
+ bgtzalc $2, . + 4 + (-32768 << 1)
+ bgtzalc $2, . + 4 + (32767 << 1)
+ bgtzalc $2, 1f
+ bltzalc $2, ext
+ bltzalc $2, . + 4 + (-32768 << 1)
+ bltzalc $2, . + 4 + (32767 << 1)
+ bltzalc $2, 1f
+ bltuc $2, $3, ext
+ bltuc $2, $3, . + 4 + (-32768 << 1)
+ bltuc $2, $3, . + 4 + (32767 << 1)
+ bltuc $2, $3, 1f
+ bltuc $3, $2, 1f
+
+ bc ext
+ bc . + 4 + (-33554432 << 1)
+ bc . + 4 + (33554431 << 1)
+ bc 1f
+ balc ext
+ balc . + 4 + (-33554432 << 1)
+ balc . + 4 + (33554431 << 1)
+ balc 1f
+
+ beqzc16 $2, . + 2 + (-64 << 1)
+ beqzc16 $2, . + 2 + (63 << 1)
+
+ beqzc $2, ext
+ beqzc $2, . + 4 + (-1048576 << 1)
+ beqzc $2, . + 4 + (1048575 << 1)
+ beqzc $2, 1f
+ jic $3,-32768
+ jic $3,32767
+ jrc $31
+
+ bnezc16 $2, . + 2 + (-64 << 1)
+ bnezc16 $2, . + 2 + (63 << 1)
+
+ bnezc $2, ext
+ bnezc $2, . + 4 + (-1048576 << 1)
+ bnezc $2, . + 4 + (1048575 << 1)
+ bnezc $2, 1f
+ jialc $3,-32768
+ jialc $3,32767
+
+ aui $3, $2, 0xffff
+ lapc $4, .+(-262144 << 2)
+ lapc $4, .+(262143 << 2)
+ addiupc $4, (-262144 << 2)
+ addiupc $4, (262143 << 2)
+ addiu $8,$pc, (-262144 << 2)
+ addiu $8,$pc, (262143 << 2)
+ auipc $3, 0xffff
+ aluipc $3, 0xffff
+ lwpc $4, 1f
+ lwpc $4, .+(-262144 << 2)
+ lwpc $4, .+(262143 << 2)
+ lw $4, (-262144 << 2)($pc)
+ lw $4, (262143 << 2)($pc)
+
+ rint.s $f2,$f3
+ rint.d $f2,$f3
+ class.s $f2,$f3
+ class.d $f2,$f3
+ min.s $f2,$f3,$f4
+ min.d $f2,$f3,$f4
+ max.s $f2,$f3,$f4
+ max.d $f2,$f3,$f4
+ mina.s $f2,$f3,$f4
+ mina.d $f2,$f3,$f4
+ maxa.s $f2,$f3,$f4
+ maxa.d $f2,$f3,$f4
+
+ lwxs $0,$0($2)
+ synci 0xffff
+ lui $2,0xffff
+ not16 $2,$3
+ xor16 $2,$3
+ and16 $2,$3
+ or16 $2,$3
+ lwm $s0,$ra, ($5)
+ swm $s0,$ra, ($5)
+ jrc16 $3
+ jalrc16 $2
+ jrcaddiusp 4
+ break16 10
+ sdbbp16
+ sdbbp16 0
+ sdbbp16 1
+ sdbbp16 15
+
+ jrc.hb $31
+ jalrc.hb $31, $0
+ jalrc.hb $0, $31
+ jalrc.hb $2, $31
+ jalrc.hb $0, $v0
+ jrc.hb $10
+1:
+ llwp $5, $4, $6
+ scwp $5, $4, $6
+ sc $4, 0($5)
+ b 1b
+ sc $4, 0($5)
+ b 1b
+
+ .set push
+ .set eva
+ llwpe $5, $4, $6
+ scwpe $5, $4, $6
+ sce $4, 0($5)
+ b 1b
+ sce $4, 0($5)
+ b 1b
+ .set pop
+1:
+ rdhwr $0, $4, 0
+ rdhwr $0, $4, 1
+ rdhwr $0, $4, 2
+ rdhwr $0, $4, 3
+ rdhwr $0, $4, 4
+ rdhwr $0, $4, 5
+ rdhwr $0, $4, 6
+ rdhwr $0, $4, 7
+
+ sigrie 0
+ sigrie 0xffff
+
+ .align 2
+ .space 8
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index bd247ffd0f0..dc625334bf3 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -245,6 +245,11 @@ struct mips_operand
/* The operand occupies SIZE bits of the instruction, starting at LSB. */
unsigned short size;
unsigned short lsb;
+
+ /* These are used to split a value across two different
+ parts of the instruction encoding. */
+ unsigned int size_top;
+ unsigned int lsb_top;
};
/* Describes an integer operand with a regular encoding pattern. */
@@ -386,10 +391,15 @@ mips_insert_operand (const struct mips_operand *operand, unsigned int insn,
unsigned int uval)
{
unsigned int mask;
+ unsigned int size_bottom = operand->size - operand->size_top;
- mask = (1 << operand->size) - 1;
+ mask = (1 << size_bottom) - 1;
insn &= ~(mask << operand->lsb);
insn |= (uval & mask) << operand->lsb;
+
+ mask = (1 << operand->size_top) - 1;
+ insn &= ~(mask << operand->lsb_top);
+ insn |= ((uval & (mask << size_bottom)) >> size_bottom) << operand->lsb_top;
return insn;
}
@@ -398,7 +408,13 @@ mips_insert_operand (const struct mips_operand *operand, unsigned int insn,
static inline unsigned int
mips_extract_operand (const struct mips_operand *operand, unsigned int insn)
{
- return (insn >> operand->lsb) & ((1 << operand->size) - 1);
+ unsigned int uval;
+ unsigned int size_bottom = operand->size - operand->size_top;
+
+ uval = (insn >> operand->lsb_top) & ((1 << operand->size_top) - 1);
+ uval <<= size_bottom;
+ uval |= (insn >> operand->lsb) & ((1 << size_bottom) - 1);
+ return uval;
}
/* UVAL is the value encoded by OPERAND. Return it in signed form. */
@@ -1874,32 +1890,61 @@ extern const int bfd_mips16_num_opcodes;
microMIPS Enhanced VA Scheme:
"+j" 9-bit signed offset in bit 0.
+ microMIPS R6:
+ "+:" 11-bit mask at bit 0
+ "+'" 26-bit PC relative branch target address
+ "+"" 21-bit PC relative branch target address
+ "+;" 5-bit same register in both OP_*_RS and OP_*_RT
+ "+D" 5-bit destination floating point register
+ "+I" 2-bit unsigned bit position at bit 9
+ "+K" 4-bit immediate (0 .. 15) at bit 6
+ "+L" 4-bit immediate (0 .. 15) << 2 at bit 4
+ "+M" 16-bit unsigned immediate at bit 6
+ "+N" 2-bit immediate (0 .. 3) for register list at bit 8
+ "+O" 3-bit unsigned bit position at bit 9
+ "+P" 5-bit immediate (0 .. 31) << 2 at bit 5
+ "+S" 5-bit fs source 1 floating point register
+ "+s" 5-bit source register specifier (MICROMIPSOP_*_RS) at 21
+ "+t" 5-bit target register (MICROMIPSOP_*_RT) at bit 16
+ "-a" (-262144 .. 262143) << 2 at bit 0
+ "-b" (-131072 .. 131071) << 3 at bit 0
+ "-s" 5-bit source register specifier (OP_*_RS) not $0
+ "-t" 5-bit source register specifier (OP_*_RT) not $0
+ "-u" 5-bit target register specifier (OP_*_RT) less than OP_*_RS
+ "-v" 5-bit target register specifier (OP_*_RT) not $0 different than OP_*_RS
+ "-w" 5-bit target register specifier (OP_*_RT) greater than OP_*_RS
+ "-x" 5-bit source register specifier (OP_*_RS) less than OP_*_RT
+ "-y" 5-bit source register specifier (OP_*_RS) greater than OP_*_RT
+ "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
+ "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
+
MSA Extension:
- "+d" 5-bit MSA register at bit 6 (FD).
- "+e" 5-bit MSA register at bit 11 (FS).
- "+h" 5-bit MSA register at bit 16 (FT).
- "+k" 5-bit GPR at bit 6.
- "+l" 5-bit MSA control register at bit 6.
- "+n" 5-bit MSA control register at bit 11.
- "+o" 4-bit vector element index at bit 16.
- "+u" 3-bit vector element index at bit 16.
- "+v" 2-bit vector element index at bit 16.
- "+w" 1-bit vector element index at bit 16.
- "+x" 5-bit shift amount at bit 16.
- "+T" (-512 .. 511) << 0 at bit 16.
- "+U" (-512 .. 511) << 1 at bit 16.
- "+V" (-512 .. 511) << 2 at bit 16.
- "+W" (-512 .. 511) << 3 at bit 16.
- "+~" 2-bit LSA/DLSA shift amount from 1 to 4 at bit 6.
- "+!" 3-bit unsigned bit position at bit 16.
- "+@" 4-bit unsigned bit position at bit 16.
- "+#" 6-bit unsigned bit position at bit 16.
- "+$" 5-bit unsigned immediate at bit 16.
- "+%" 5-bit signed immediate at bit 16.
- "+^" 10-bit signed immediate at bit 11.
- "+&" 0 vector element index.
- "+*" 5-bit register vector element index at bit 16.
- "+|" 8-bit mask at bit 16.
+ "+d" 5-bit MSA register (FD)
+ "+e" 5-bit MSA register (FS)
+ "+h" 5-bit MSA register (FT)
+ "+k" 5-bit GPR at bit 6
+ "+l" 5-bit MSA control register at bit 6
+ "+n" 5-bit MSA control register at bit 11
+ "+o" 4-bit vector element index at bit 16
+ "+u" 3-bit vector element index at bit 16
+ "+v" 2-bit vector element index at bit 16
+ "+w" 1-bit vector element index at bit 16
+ "+x" 5-bit shift amount at bit 16
+ "+T" (-512 .. 511) << 0 at bit 16
+ "+U" (-512 .. 511) << 1 at bit 16
+ "+V" (-512 .. 511) << 2 at bit 16
+ "+W" (-512 .. 511) << 3 at bit 16
+ "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+ "+!" 3 bit unsigned bit position at bit 16
+ "+@" 4 bit unsigned bit position at bit 16
+ "+#" 6 bit unsigned bit position at bit 16
+ "+$" 5 bit unsigned immediate at bit 16
+ "+%" 5 bit signed immediate at bit 16
+ "+^" 10 bit signed immediate at bit 11
+ "+&" 0 vector element index
+ "+*" 5-bit register vector element index at bit 16
+ "+|" 8-bit mask at bit 16
+ "+." microMIPS R6: 2-bit LSA/DLSA shift amount from 1 to 4 at bit 9
MT ASE usage:
"!" 1-bit usermode flag at bit 10.
@@ -1922,6 +1967,13 @@ extern const int bfd_mips16_num_opcodes;
"ABCDEFGHIJKLMN RST V "
"abcd fghijklmnopqrstuvwxyz"
+ Extension character sequences used so far ("+" followed by the
+ following), for quick reference when adding more:
+ ""
+ "~!@#$%^&*|'":;"
+ "ABCDEFGHIJKLMNOP STUVW "
+ " de hijkl no uvwx "
+
Extension character sequences used so far ("m" followed by the
following), for quick reference when adding more:
""
@@ -1940,7 +1992,8 @@ extern const int bfd_mips16_num_opcodes;
following), for quick reference when adding more:
""
""
- <none so far>
+ "AB "
+ "ab stuvwyx "
*/
extern const struct mips_operand *decode_micromips_operand (const char *);
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-r6.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-r6.od
new file mode 100644
index 00000000000..f58b2e511da
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-r6.od
@@ -0,0 +1,103 @@
+
+.* file format .*
+
+
+Disassembly of section \.plt:
+
+10100000 <_PROCEDURE_LINKAGE_TABLE_>:
+.*: 3c1c1020 lui \$28,0x1020
+.*: 8f990000 lw \$25,0\(\$28\)
+.*: 279c0000 addiu \$28,\$28,0
+.*: 031cc023 subu \$24,\$24,\$28
+.*: 03e07821 move \$15,\$31
+.*: 0018c082 srl \$24,\$24,0x2
+.*: 2718fffe addiu \$24,\$24,-2
+.*: f8190000 jalrc \$25
+
+10100020 <f_lo_iu@plt>:
+.*: 3c0f1020 lui \$15,0x1020
+.*: 8df90008 lw \$25,8\(\$15\)
+.*: 25f80008 addiu \$24,\$15,8
+.*: d8190000 jrc \$25
+
+10100030 <f_du@plt>:
+.*: 3c0f1020 lui \$15,0x1020
+.*: 8df9000c lw \$25,12\(\$15\)
+.*: 25f8000c addiu \$24,\$15,12
+.*: d8190000 jrc \$25
+
+10100040 <f_iu_du@plt>:
+.*: 3c0f1020 lui \$15,0x1020
+.*: 8df90010 lw \$25,16\(\$15\)
+.*: 25f80010 addiu \$24,\$15,16
+.*: d8190000 jrc \$25
+
+10100050 <f_lo_iu_du@plt>:
+.*: 3c0f1020 lui \$15,0x1020
+.*: 8df90014 lw \$25,20\(\$15\)
+.*: 25f80014 addiu \$24,\$15,20
+.*: d8190000 jrc \$25
+
+10100060 <f_lo_du@plt>:
+.*: 3c0f1020 lui \$15,0x1020
+.*: 8df90018 lw \$25,24\(\$15\)
+.*: 25f80018 addiu \$24,\$15,24
+.*: d8190000 jrc \$25
+
+10100070 <f_lo@plt>:
+.*: 3c0f1020 lui \$15,0x1020
+.*: 8df9001c lw \$25,28\(\$15\)
+.*: 25f8001c addiu \$24,\$15,28
+.*: d8190000 jrc \$25
+
+Disassembly of section \.MIPS\.stubs:
+
+10101000 <_MIPS_STUBS_>:
+# Lazy-binding stub for f_iu.
+.*: 8f998010 lw \$25,-32752\(\$28\)
+.*: 03e07821 move \$15,\$31
+.*: 24180009 li \$24,9
+.*: f8190000 jalrc \$25
+ \.\.\.
+
+Disassembly of section \.text\.b:
+
+10102000 <testu>:
+.*: ........ jal [0-9a-f]+ <f_du@plt>
+.*: 00000000 nop
+.*: ........ j [0-9a-f]+ <f_du@plt>
+.*: 00000000 nop
+.*: 8c628024 lw \$2,-32732\(\$3\)
+# ^ global GOT entry for f_iu
+.*: ........ jal [0-9a-f]+ <f_iu_du@plt>
+.*: 00000000 nop
+.*: ........ j [0-9a-f]+ <f_iu_du@plt>
+.*: 00000000 nop
+.*: 8c628018 lw \$2,-32744\(\$3\)
+# ^ local GOT entry for f_iu_du@plt
+.*: ........ jal [0-9a-f]+ <f_lo_du@plt>
+.*: 00000000 nop
+.*: ........ j [0-9a-f]+ <f_lo_du@plt>
+.*: 00000000 nop
+.*: 8c62801c lw \$2,-32740\(\$3\)
+# ^ local GOT entry for f_lo_iu@plt
+.*: ........ jal [0-9a-f]+ <f_lo_iu_du@plt>
+.*: 00000000 nop
+.*: ........ j [0-9a-f]+ <f_lo_iu_du@plt>
+.*: 00000000 nop
+.*: 8c628020 lw \$2,-32736\(\$3\)
+# ^ local GOT entry for f_lo_iu_du@plt
+.*: 03e00009 jr \$31
+
+Disassembly of section \.text\.c:
+
+10103000 <testlo>:
+.*: 24020070 li \$2,112
+# ^ low 16 bits of f_lo@plt
+.*: 24020060 li \$2,96
+# ^ low 16 bits of f_lo_du@plt
+.*: 24020020 li \$2,32
+# ^ low 16 bits of f_lo_iu@plt
+.*: 24020050 li \$2,80
+# ^ low 16 bits of f_lo_iu_du@plt
+
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-r6.rd b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-r6.rd
new file mode 100644
index 00000000000..fa23221f8bb
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-r6.rd
@@ -0,0 +1,79 @@
+
+Dynamic section .*
+#...
+ 0x00000003 \(PLTGOT\) 0x10201000
+#...
+ 0x70000013 \(MIPS_GOTSYM\) 0x9
+ 0x00000014 \(PLTREL\) REL
+ 0x00000017 \(JMPREL\) 0x10004000
+ 0x00000002 \(PLTRELSZ\) 48 \(bytes\)
+ 0x70000032 \(MIPS_PLTGOT\) 0x10200000
+#...
+Relocation section '\.rel\.plt' .*
+ Offset Info Type Sym\.Value Sym\. Name
+10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100020 f_lo_iu
+1020000c [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_du
+10200010 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_iu_du
+10200014 [^ ]+ R_MIPS_JUMP_SLOT 10100050 f_lo_iu_du
+10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100060 f_lo_du
+1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100070 f_lo
+
+Symbol table '\.dynsym' .*
+ Num: Value Size Type Bind Vis Ndx Name
+ 0: 00000000 0 NOTYPE LOCAL DEFAULT UND
+# _lo symbols have their address taken, so their PLT symbols need to have
+# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish
+# them from old-style lazy-binding stubs. Non-_lo symbols are only called,
+# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation.
+ .*: 10100020 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu
+#...
+ .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_du
+ .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_iu_du
+ .*: 10100050 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_iu_du
+ .*: 10100060 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_du
+#...
+ .*: 10100070 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo
+# The start of the GOT-mapped area. This should only contain functions that
+# are accessed purely via the traditional psABI scheme. The symbol value
+# is the address of the lazy-binding stub.
+ 9: 10101000 0 FUNC GLOBAL DEFAULT UND f_iu
+
+Symbol table '\.symtab' .*
+#...
+Primary GOT:
+ Canonical gp value: 10208ff0
+
+ Reserved entries:
+ Address Access Initial Purpose
+ 10201000 -32752\(gp\) 00000000 Lazy resolver
+ 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+# See the disassembly output for the meaning of each entry.
+ Local entries:
+ Address Access Initial
+ 10201008 -32744\(gp\) 10100040
+ 1020100c -32740\(gp\) 10100020
+ 10201010 -32736\(gp\) 10100050
+
+ Global entries:
+ Address Access Initial Sym\.Val\. Type Ndx Name
+ 10201014 -32732\(gp\) 10101000 10101000 FUNC UND f_iu
+
+
+PLT GOT:
+
+ Reserved entries:
+ Address Initial Purpose
+ 10200000 00000000 PLT lazy resolver
+ 10200004 00000000 Module pointer
+
+ Entries:
+ Address Initial Sym\.Val\. Type Ndx Name
+ 10200008 10100000 10100020 FUNC UND f_lo_iu
+ 1020000c 10100000 00000000 FUNC UND f_du
+ 10200010 10100000 00000000 FUNC UND f_iu_du
+ 10200014 10100000 10100050 FUNC UND f_lo_iu_du
+ 10200018 10100000 10100060 FUNC UND f_lo_du
+ 1020001c 10100000 10100070 FUNC UND f_lo
+
+
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-insn32-only.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-insn32-only.od
new file mode 100644
index 00000000000..a95a2606f16
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-insn32-only.od
@@ -0,0 +1,105 @@
+
+.* file format .*
+
+
+Disassembly of section \.plt:
+
+# All entries must be microMIPS.
+10100000 <_PROCEDURE_LINKAGE_TABLE_>:
+.*: 41bc 1020 lui \$28,0x1020
+.*: ff3c 0000 lw \$25,0\(\$28\)
+.*: 339c 0000 addiu \$28,\$28,0
+.*: 0398 c1d0 subu \$24,\$24,\$28
+.*: 001f 7a90 move \$15,\$31
+.*: 0318 1040 srl \$24,\$24,0x2
+.*: 03f9 0f3c jalr \$25
+.*: 3318 fffe addiu \$24,\$24,-2
+
+
+10100020 <f_lo_ic@micromipsplt>:
+.*: 41af 1020 lui \$15,0x1020
+.*: ff2f 0008 lw \$25,8\(\$15\)
+.*: 0019 0f3c jr \$25
+.*: 330f 0008 addiu \$24,\$15,8
+
+10100030 <f_lo_dc@micromipsplt>:
+.*: 41af 1020 lui \$15,0x1020
+.*: ff2f 000c lw \$25,12\(\$15\)
+.*: 0019 0f3c jr \$25
+.*: 330f 000c addiu \$24,\$15,12
+
+10100040 <f_dc@micromipsplt>:
+.*: 41af 1020 lui \$15,0x1020
+.*: ff2f 0010 lw \$25,16\(\$15\)
+.*: 0019 0f3c jr \$25
+.*: 330f 0010 addiu \$24,\$15,16
+
+10100050 <f_ic_dc@micromipsplt>:
+.*: 41af 1020 lui \$15,0x1020
+.*: ff2f 0014 lw \$25,20\(\$15\)
+.*: 0019 0f3c jr \$25
+.*: 330f 0014 addiu \$24,\$15,20
+
+10100060 <f_lo_ic_dc@micromipsplt>:
+.*: 41af 1020 lui \$15,0x1020
+.*: ff2f 0018 lw \$25,24\(\$15\)
+.*: 0019 0f3c jr \$25
+.*: 330f 0018 addiu \$24,\$15,24
+
+10100070 <f_lo@micromipsplt>:
+.*: 41af 1020 lui \$15,0x1020
+.*: ff2f 001c lw \$25,28\(\$15\)
+.*: 0019 0f3c jr \$25
+.*: 330f 001c addiu \$24,\$15,28
+
+Disassembly of section \.MIPS\.stubs:
+
+10101000 <_MIPS_STUBS_>:
+# Lazy-binding stub for f_ic.
+.*: ff3c 8010 lw \$25,-32752\(\$28\)
+.*: 001f 7a90 move \$15,\$31
+.*: 03f9 0f3c jalr \$25
+.*: 3300 0009 li \$24,9
+ \.\.\.
+
+Disassembly of section \.text\.a:
+
+10102000 <testc>:
+.*: .... .... jal [0-9a-f]+ <f_dc@micromipsplt>
+.*: 0000 0000 nop
+.*: .... .... j [0-9a-f]+ <f_dc@micromipsplt>
+.*: 0c00 nop
+.*: fc43 8024 lw \$2,-32732\(\$3\)
+# ^ global GOT entry for f_ic
+.*: .... .... jal [0-9a-f]+ <f_ic_dc@micromipsplt>
+.*: 0000 0000 nop
+.*: .... .... j [0-9a-f]+ <f_ic_dc@micromipsplt>
+.*: 0c00 nop
+.*: fc43 8018 lw \$2,-32744\(\$3\)
+# ^ local GOT entry for f_ic_dc@micromipsplt
+.*: .... .... jal [0-9a-f]+ <f_lo_dc@micromipsplt>
+.*: 0000 0000 nop
+.*: .... .... j [0-9a-f]+ <f_lo_dc@micromipsplt>
+.*: 0c00 nop
+.*: fc43 801c lw \$2,-32740\(\$3\)
+# ^ local GOT entry for f_lo_ic@micromipsplt
+.*: .... .... jal [0-9a-f]+ <f_lo_ic_dc@micromipsplt>
+.*: 0000 0000 nop
+.*: .... .... j [0-9a-f]+ <f_lo_ic_dc@micromipsplt>
+.*: 0c00 nop
+.*: fc43 8020 lw \$2,-32736\(\$3\)
+# ^ local GOT entry for f_lo_ic_dc@micromipsplt
+.*: 459f jr \$31
+
+Disassembly of section \.text\.c:
+
+10103000 <testlo>:
+.*: 3040 0071 li \$2,113
+# ^ low 16 bits of f_lo@micromipsplt
+.*: 3040 0031 li \$2,49
+# ^ low 16 bits of f_lo_dc@micromipsplt
+.*: 3040 0021 li \$2,33
+# ^ low 16 bits of f_lo_ic@micromipsplt
+.*: 3040 0061 li \$2,97
+# ^ low 16 bits of f_lo_ic_dc@micromipsplt
+
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-insn32-only.rd b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-insn32-only.rd
new file mode 100644
index 00000000000..e2f8368bfe8
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umips-insn32-only.rd
@@ -0,0 +1,81 @@
+
+Dynamic section .*
+#...
+ 0x00000003 \(PLTGOT\) 0x10201000
+#...
+ 0x70000013 \(MIPS_GOTSYM\) 0x9
+ 0x00000014 \(PLTREL\) REL
+ 0x00000017 \(JMPREL\) 0x10004000
+ 0x00000002 \(PLTRELSZ\) 48 \(bytes\)
+ 0x70000032 \(MIPS_PLTGOT\) 0x10200000
+#...
+Relocation section '\.rel\.plt' .*
+ Offset Info Type Sym\.Value Sym\. Name
+10200008 [^ ]+ R_MIPS_JUMP_SLOT 10100021 f_lo_ic
+1020000c [^ ]+ R_MIPS_JUMP_SLOT 10100031 f_lo_dc
+10200010 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc
+10200014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc
+10200018 [^ ]+ R_MIPS_JUMP_SLOT 10100061 f_lo_ic_dc
+1020001c [^ ]+ R_MIPS_JUMP_SLOT 10100071 f_lo
+
+Symbol table '\.dynsym' .*
+ Num: Value Size Type Bind Vis Ndx Name
+ 0: 00000000 0 NOTYPE LOCAL DEFAULT UND
+# _lo symbols have their address taken, so their PLT symbols need to have
+# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish
+# them from old-style lazy-binding stubs. Non-_lo symbols are only called,
+# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation.
+#
+# All PLTs should be microMIPS.
+#...
+ .*: 10100021 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic
+ .*: 10100031 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc
+ .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc
+ .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc
+#...
+ .*: 10100061 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc
+ .*: 10100071 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo
+# The start of the GOT-mapped area. This should only contain functions that
+# are accessed purely via the traditional psABI scheme. The symbol value
+# is the address of the lazy-binding stub.
+ 9: 10101001 0 FUNC GLOBAL DEFAULT UND f_ic
+
+Symbol table '\.symtab' .*
+#...
+Primary GOT:
+ Canonical gp value: 10208ff0
+
+ Reserved entries:
+ Address Access Initial Purpose
+ 10201000 -32752\(gp\) 00000000 Lazy resolver
+ 10201004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+# See the disassembly output for the meaning of each entry.
+ Local entries:
+ Address Access Initial
+ 10201008 -32744\(gp\) 10100051
+ 1020100c -32740\(gp\) 10100021
+ 10201010 -32736\(gp\) 10100061
+
+ Global entries:
+ Address Access Initial Sym\.Val\. Type Ndx Name
+ 10201014 -32732\(gp\) 10101001 10101001 FUNC UND f_ic
+
+
+PLT GOT:
+
+ Reserved entries:
+ Address Initial Purpose
+ 10200000 00000000 PLT lazy resolver
+ 10200004 00000000 Module pointer
+
+ Entries:
+ Address Initial Sym\.Val\. Type Ndx Name
+ 10200008 10100001 10100021 FUNC UND f_lo_ic
+ 1020000c 10100001 10100031 FUNC UND f_lo_dc
+ 10200010 10100001 00000000 FUNC UND f_dc
+ 10200014 10100001 00000000 FUNC UND f_ic_dc
+ 10200018 10100001 10100061 FUNC UND f_lo_ic_dc
+ 1020001c 10100001 10100071 FUNC UND f_lo
+
+
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-insn32-only.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-insn32-only.od
new file mode 100644
index 00000000000..8e6c5304ee3
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-insn32-only.od
@@ -0,0 +1,96 @@
+
+.* file format .*
+
+
+Disassembly of section \.plt:
+
+# All entries must be microMIPS.
+01010000 <_PROCEDURE_LINKAGE_TABLE_>:
+.*: 1380 0102 lui \$28,0x102
+.*: ff3c 0000 lw \$25,0\(\$28\)
+.*: 339c 0000 addiu \$28,\$28,0
+.*: 0398 c1d0 subu \$24,\$24,\$28
+.*: 001f 7a90 move \$15,\$31
+.*: 0318 1040 srl \$24,\$24,0x2
+.*: 3318 fffe addiu \$24,\$24,-2
+.*: 03f9 0f3c jalrc \$25
+
+01010020 <f_lo_ic@micromipsplt>:
+.*: 11e0 0102 lui \$15,0x102
+.*: ff2f 0008 lw \$25,8\(\$15\)
+.*: 330f 0008 addiu \$24,\$15,8
+.*: 8019 0000 jrc \$25
+
+01010030 <f_lo_dc@micromipsplt>:
+.*: 11e0 0102 lui \$15,0x102
+.*: ff2f 000c lw \$25,12\(\$15\)
+.*: 330f 000c addiu \$24,\$15,12
+.*: 8019 0000 jrc \$25
+
+01010040 <f_dc@micromipsplt>:
+.*: 11e0 0102 lui \$15,0x102
+.*: ff2f 0010 lw \$25,16\(\$15\)
+.*: 330f 0010 addiu \$24,\$15,16
+.*: 8019 0000 jrc \$25
+
+01010050 <f_ic_dc@micromipsplt>:
+.*: 11e0 0102 lui \$15,0x102
+.*: ff2f 0014 lw \$25,20\(\$15\)
+.*: 330f 0014 addiu \$24,\$15,20
+.*: 8019 0000 jrc \$25
+
+01010060 <f_lo_ic_dc@micromipsplt>:
+.*: 11e0 0102 lui \$15,0x102
+.*: ff2f 0018 lw \$25,24\(\$15\)
+.*: 330f 0018 addiu \$24,\$15,24
+.*: 8019 0000 jrc \$25
+
+01010070 <f_lo@micromipsplt>:
+.*: 11e0 0102 lui \$15,0x102
+.*: ff2f 001c lw \$25,28\(\$15\)
+.*: 330f 001c addiu \$24,\$15,28
+.*: 8019 0000 jrc \$25
+
+Disassembly of section \.MIPS\.stubs:
+
+01011000 <_MIPS_STUBS_>:
+# Lazy-binding stub for f_ic.
+.*: ff3c 8010 lw \$25,-32752\(\$28\)
+.*: 001f 7a90 move \$15,\$31
+.*: 3300 0009 li \$24,9
+.*: 03f9 0f3c jalrc \$25
+ \.\.\.
+
+Disassembly of section \.text\.a:
+
+01012000 <testc>:
+.*: .... .... balc [0-9a-f]+ <f_dc@micromipsplt>
+.*: .... .... bc [0-9a-f]+ <f_dc@micromipsplt>
+.*: fc43 8024 lw \$2,-32732\(\$3\)
+# ^ global GOT entry for f_ic
+.*: .... .... balc [0-9a-f]+ <f_ic_dc@micromipsplt>
+.*: .... .... bc [0-9a-f]+ <f_ic_dc@micromipsplt>
+.*: fc43 8018 lw \$2,-32744\(\$3\)
+# ^ local GOT entry for f_ic_dc@micromipsplt
+.*: .... .... balc [0-9a-f]+ <f_lo_dc@micromipsplt>
+.*: .... .... bc [0-9a-f]+ <f_lo_dc@micromipsplt>
+.*: fc43 801c lw \$2,-32740\(\$3\)
+# ^ local GOT entry for f_lo_ic@micromipsplt
+.*: .... .... balc [0-9a-f]+ <f_lo_ic_dc@micromipsplt>
+.*: .... .... bc [0-9a-f]+ <f_lo_ic_dc@micromipsplt>
+.*: fc43 8020 lw \$2,-32736\(\$3\)
+# ^ local GOT entry for f_lo_ic_dc@micromipsplt
+.*: 47e3 jrc \$31
+
+Disassembly of section \.text\.c:
+
+01013000 <testlo>:
+.*: 3040 0071 li \$2,113
+# ^ low 16 bits of f_lo@micromipsplt
+.*: 3040 0031 li \$2,49
+# ^ low 16 bits of f_lo_dc@micromipsplt
+.*: 3040 0021 li \$2,33
+# ^ low 16 bits of f_lo_ic@micromipsplt
+.*: 3040 0061 li \$2,97
+# ^ low 16 bits of f_lo_ic_dc@micromipsplt
+
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-insn32-only.rd b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-insn32-only.rd
new file mode 100644
index 00000000000..ff9b425ef16
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-insn32-only.rd
@@ -0,0 +1,81 @@
+
+Dynamic section .*
+#...
+ 0x00000003 \(PLTGOT\) 0x1021000
+#...
+ 0x70000013 \(MIPS_GOTSYM\) 0x9
+ 0x00000014 \(PLTREL\) REL
+ 0x00000017 \(JMPREL\) 0x1004000
+ 0x00000002 \(PLTRELSZ\) 48 \(bytes\)
+ 0x70000032 \(MIPS_PLTGOT\) 0x1020000
+#...
+Relocation section '\.rel\.plt' .*
+ Offset Info Type Sym\.Value Sym\. Name
+01020008 [^ ]+ R_MIPS_JUMP_SLOT 01010021 f_lo_ic
+0102000c [^ ]+ R_MIPS_JUMP_SLOT 01010031 f_lo_dc
+01020010 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc
+01020014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc
+01020018 [^ ]+ R_MIPS_JUMP_SLOT 01010061 f_lo_ic_dc
+0102001c [^ ]+ R_MIPS_JUMP_SLOT 01010071 f_lo
+
+Symbol table '\.dynsym' .*
+ Num: Value Size Type Bind Vis Ndx Name
+ 0: 00000000 0 NOTYPE LOCAL DEFAULT UND
+# _lo symbols have their address taken, so their PLT symbols need to have
+# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish
+# them from old-style lazy-binding stubs. Non-_lo symbols are only called,
+# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation.
+#
+# All PLTs should be microMIPS.
+#...
+ .*: 01010021 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic
+ .*: 01010031 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc
+ .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc
+ .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc
+#...
+ .*: 01010061 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc
+ .*: 01010071 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo
+# The start of the GOT-mapped area. This should only contain functions that
+# are accessed purely via the traditional psABI scheme. The symbol value
+# is the address of the lazy-binding stub.
+ 9: 01011001 0 FUNC GLOBAL DEFAULT UND f_ic
+
+Symbol table '\.symtab' .*
+#...
+Primary GOT:
+ Canonical gp value: 01028ff0
+
+ Reserved entries:
+ Address Access Initial Purpose
+ 01021000 -32752\(gp\) 00000000 Lazy resolver
+ 01021004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+# See the disassembly output for the meaning of each entry.
+ Local entries:
+ Address Access Initial
+ 01021008 -32744\(gp\) 01010051
+ 0102100c -32740\(gp\) 01010021
+ 01021010 -32736\(gp\) 01010061
+
+ Global entries:
+ Address Access Initial Sym\.Val\. Type Ndx Name
+ 01021014 -32732\(gp\) 01011001 01011001 FUNC UND f_ic
+
+
+PLT GOT:
+
+ Reserved entries:
+ Address Initial Purpose
+ 01020000 00000000 PLT lazy resolver
+ 01020004 00000000 Module pointer
+
+ Entries:
+ Address Initial Sym\.Val\. Type Ndx Name
+ 01020008 01010001 01010021 FUNC UND f_lo_ic
+ 0102000c 01010001 01010031 FUNC UND f_lo_dc
+ 01020010 01010001 00000000 FUNC UND f_dc
+ 01020014 01010001 00000000 FUNC UND f_ic_dc
+ 01020018 01010001 01010061 FUNC UND f_lo_ic_dc
+ 0102001c 01010001 01010071 FUNC UND f_lo
+
+
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-only.od b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-only.od
new file mode 100644
index 00000000000..07fc33e26fb
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-only.od
@@ -0,0 +1,103 @@
+
+.* file format .*
+
+
+Disassembly of section \.plt:
+
+# All entries must be microMIPS.
+01010000 <_PROCEDURE_LINKAGE_TABLE_>:
+.*: 7860 4000 lapc \$3,1020000 <.*>
+.*: ff23 0000 lw \$25,0\(\$3\)
+.*: 0535 subu \$2,\$2,\$3
+.*: 2525 srl \$2,\$2,2
+.*: 3302 fffe addiu \$24,\$2,-2
+.*: 0dff move \$15,\$31
+.*: 0f83 move \$28,\$3
+.*: 472b jalrc \$25
+.*: 0c00 nop
+
+01010018 <f_lo_ic@micromipsplt>:
+.*: 7840 3ffc lapc \$2,1020008 <.*>
+# ^ 0x1020008
+.*: ff22 0000 lw \$25,0\(\$2\)
+.*: 0f02 move \$24,\$2
+.*: 4723 jrc \$25
+
+01010024 <f_lo_dc@micromipsplt>:
+.*: 7840 3ffa lapc \$2,102000c <.*>
+# ^ 0x102000c
+.*: ff22 0000 lw \$25,0\(\$2\)
+.*: 0f02 move \$24,\$2
+.*: 4723 jrc \$25
+
+01010030 <f_dc@micromipsplt>:
+.*: 7840 3ff8 lapc \$2,1020010 <.*>
+# ^ 0x1020010
+.*: ff22 0000 lw \$25,0\(\$2\)
+.*: 0f02 move \$24,\$2
+.*: 4723 jrc \$25
+
+0101003c <f_ic_dc@micromipsplt>:
+.*: 7840 3ff6 lapc \$2,1020014 <.*>
+# ^ 0x1020014
+.*: ff22 0000 lw \$25,0\(\$2\)
+.*: 0f02 move \$24,\$2
+.*: 4723 jrc \$25
+
+01010048 <f_lo_ic_dc@micromipsplt>:
+.*: 7840 3ff4 lapc \$2,1020018 <.*>
+# ^ 0x1020018
+.*: ff22 0000 lw \$25,0\(\$2\)
+.*: 0f02 move \$24,\$2
+.*: 4723 jrc \$25
+
+01010054 <f_lo@micromipsplt>:
+.*: 7840 3ff2 lapc \$2,102001c <.*>
+# ^ 0x102001c
+.*: ff22 0000 lw \$25,0\(\$2\)
+.*: 0f02 move \$24,\$2
+.*: 4723 jrc \$25
+
+Disassembly of section \.MIPS\.stubs:
+
+01011000 <_MIPS_STUBS_>:
+# Lazy-binding stub for f_ic.
+.*: ff3c 8010 lw \$25,-32752\(\$28\)
+.*: 0dff move \$15,\$31
+.*: 3300 0009 li \$24,9
+.*: 472b jalrc \$25
+ \.\.\.
+
+Disassembly of section \.text\.a:
+
+01012000 <testc>:
+.*: .... .... balc [0-9a-f]+ <f_dc@micromipsplt>
+.*: .... .... bc [0-9a-f]+ <f_dc@micromipsplt>
+.*: fc43 8024 lw \$2,-32732\(\$3\)
+# ^ global GOT entry for f_ic
+.*: .... .... balc [0-9a-f]+ <f_ic_dc@micromipsplt>
+.*: .... .... bc [0-9a-f]+ <f_ic_dc@micromipsplt>
+.*: fc43 8018 lw \$2,-32744\(\$3\)
+# ^ local GOT entry for f_ic_dc@micromipsplt
+.*: .... .... balc [0-9a-f]+ <f_lo_dc@micromipsplt>
+.*: .... .... bc [0-9a-f]+ <f_lo_dc@micromipsplt>
+.*: fc43 801c lw \$2,-32740\(\$3\)
+# ^ local GOT entry for f_lo_ic@micromipsplt
+.*: .... .... balc [0-9a-f]+ <f_lo_ic_dc@micromipsplt>
+.*: .... .... bc [0-9a-f]+ <f_lo_ic_dc@micromipsplt>
+.*: fc43 8020 lw \$2,-32736\(\$3\)
+# ^ local GOT entry for f_lo_ic_dc@micromipsplt
+.*: 47e3 jrc \$31
+
+Disassembly of section \.text\.c:
+
+01013000 <testlo>:
+.*: 3040 0055 li \$2,85
+# ^ low 16 bits of f_lo@micromipsplt
+.*: 3040 0025 li \$2,37
+# ^ low 16 bits of f_lo_dc@micromipsplt
+.*: 3040 0019 li \$2,25
+# ^ low 16 bits of f_lo_ic@micromipsplt
+.*: 3040 0049 li \$2,73
+# ^ low 16 bits of f_lo_ic_dc@micromipsplt
+
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-only.rd b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-only.rd
new file mode 100644
index 00000000000..03c53585527
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-o32-umipsr6-only.rd
@@ -0,0 +1,81 @@
+
+Dynamic section .*
+#...
+ 0x00000003 \(PLTGOT\) 0x1021000
+#...
+ 0x70000013 \(MIPS_GOTSYM\) 0x9
+ 0x00000014 \(PLTREL\) REL
+ 0x00000017 \(JMPREL\) 0x1004000
+ 0x00000002 \(PLTRELSZ\) 48 \(bytes\)
+ 0x70000032 \(MIPS_PLTGOT\) 0x1020000
+#...
+Relocation section '\.rel\.plt' .*
+ Offset Info Type Sym\.Value Sym\. Name
+01020008 [^ ]+ R_MIPS_JUMP_SLOT 01010019 f_lo_ic
+0102000c [^ ]+ R_MIPS_JUMP_SLOT 01010025 f_lo_dc
+01020010 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_dc
+01020014 [^ ]+ R_MIPS_JUMP_SLOT 00000000 f_ic_dc
+01020018 [^ ]+ R_MIPS_JUMP_SLOT 01010049 f_lo_ic_dc
+0102001c [^ ]+ R_MIPS_JUMP_SLOT 01010055 f_lo
+
+Symbol table '\.dynsym' .*
+ Num: Value Size Type Bind Vis Ndx Name
+ 0: 00000000 0 NOTYPE LOCAL DEFAULT UND
+# _lo symbols have their address taken, so their PLT symbols need to have
+# a nonzero value. They must also have STO_MIPS_PLT in order to distinguish
+# them from old-style lazy-binding stubs. Non-_lo symbols are only called,
+# so their PLT symbols should have a zero value and no STO_MIPS_PLT annotation.
+#
+# All PLTs should be microMIPS.
+#...
+ .*: 01010019 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic
+ .*: 01010025 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_dc
+ .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_dc
+ .*: 00000000 0 FUNC GLOBAL DEFAULT UND f_ic_dc
+#...
+ .*: 01010049 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo_ic_dc
+ .*: 01010055 0 FUNC GLOBAL DEFAULT \[MIPS PLT\] UND f_lo
+# The start of the GOT-mapped area. This should only contain functions that
+# are accessed purely via the traditional psABI scheme. The symbol value
+# is the address of the lazy-binding stub.
+ 9: 01011001 0 FUNC GLOBAL DEFAULT UND f_ic
+
+Symbol table '\.symtab' .*
+#...
+Primary GOT:
+ Canonical gp value: 01028ff0
+
+ Reserved entries:
+ Address Access Initial Purpose
+ 01021000 -32752\(gp\) 00000000 Lazy resolver
+ 01021004 -32748\(gp\) 80000000 Module pointer \(GNU extension\)
+
+# See the disassembly output for the meaning of each entry.
+ Local entries:
+ Address Access Initial
+ 01021008 -32744\(gp\) 0101003d
+ 0102100c -32740\(gp\) 01010019
+ 01021010 -32736\(gp\) 01010049
+
+ Global entries:
+ Address Access Initial Sym\.Val\. Type Ndx Name
+ 01021014 -32732\(gp\) 01011001 01011001 FUNC UND f_ic
+
+
+PLT GOT:
+
+ Reserved entries:
+ Address Initial Purpose
+ 01020000 00000000 PLT lazy resolver
+ 01020004 00000000 Module pointer
+
+ Entries:
+ Address Initial Sym\.Val\. Type Ndx Name
+ 01020008 01010001 01010019 FUNC UND f_lo_ic
+ 0102000c 01010001 01010025 FUNC UND f_lo_dc
+ 01020010 01010001 00000000 FUNC UND f_dc
+ 01020014 01010001 00000000 FUNC UND f_ic_dc
+ 01020018 01010001 01010049 FUNC UND f_lo_ic_dc
+ 0102001c 01010001 01010055 FUNC UND f_lo
+
+
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1-umipsr6.ld b/ld/testsuite/ld-mips-elf/compressed-plt-1-umipsr6.ld
new file mode 100644
index 00000000000..5b9024c1bb6
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1-umipsr6.ld
@@ -0,0 +1,40 @@
+SECTIONS
+{
+ . = 0x1000000;
+ .interp : { *(.interp) }
+ .reginfo : { *(.reginfo) }
+ .hash : { *(.hash) }
+ . = ALIGN(0x1000);
+ .dynsym : { *(.dynsym) }
+ . = ALIGN(0x1000);
+ .dynstr : { *(.dynstr) }
+ . = ALIGN(0x1000);
+ .dynamic : { *(.dynamic) }
+ . = ALIGN(0x1000);
+ .rel.dyn : { *(.rel.dyn) }
+ . = ALIGN(0x1000);
+ .rel.plt : { *(.rel.plt) }
+ . = 0x1010000;
+ .plt : { *(.plt) }
+ . = ALIGN(0x1000);
+ .MIPS.stubs : { *(.MIPS.stubs) }
+ . = ALIGN(0x1000);
+ .text.a : { *(.text.a) }
+ . = ALIGN(0x1000);
+ .text.b : { *(.text.b) }
+ . = ALIGN(0x1000);
+ .text.c : { *(.text.c) }
+ . = ALIGN(0x1000);
+ .text.d : { *(.text.d) }
+ . = 0x1020000;
+ .got.plt : { *(.got.plt) }
+ . = ALIGN(0x1000);
+ .data : { *(.data) }
+ . = ALIGN(0x1000);
+ _gp = . + 0x7ff0;
+ .got : { *(.got) }
+ . = ALIGN(0x1000);
+ .rld_map : { *(.rld_map) }
+
+ /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) }
+}
diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1a.s b/ld/testsuite/ld-mips-elf/compressed-plt-1a.s
index ad2ae7922f3..02a462448ec 100644
--- a/ld/testsuite/ld-mips-elf/compressed-plt-1a.s
+++ b/ld/testsuite/ld-mips-elf/compressed-plt-1a.s
@@ -7,10 +7,17 @@
.macro test_one, name, types
.if (\types) & DC
+ .if micromips & 2
+ balc \name
+ .else
jal \name
nop
- .if micromips
+ .endif
.ifdef o32
+ .if micromips & 2
+ bc \name
+ .endif
+ .if micromips & 1
j \name
nop
.endif
diff --git a/ld/testsuite/ld-mips-elf/mips-elf.exp b/ld/testsuite/ld-mips-elf/mips-elf.exp
index 818238d0d58..7ce7c35c082 100644
--- a/ld/testsuite/ld-mips-elf/mips-elf.exp
+++ b/ld/testsuite/ld-mips-elf/mips-elf.exp
@@ -561,6 +561,13 @@ if { $linux_gnu } {
{{objdump -dr pic-and-nonpic-1-micromips-rel.dd}
{readelf --symbols pic-and-nonpic-1-micromips-rel.nd}}
"pic-and-nonpic-1-micromips-rel.o"}
+ {"PIC and non-PIC test 1, microMIPS R6 (relocatable)"
+ "-r -melf32btsmip" ""
+ "-32 -EB -mips32r6"
+ {pic-and-nonpic-1a-micromipsr6.s pic-and-nonpic-1b-micromips.s}
+ {{objdump -dr pic-and-nonpic-1-micromipsr6-rel.dd}
+ {readelf --symbols pic-and-nonpic-1-micromipsr6-rel.nd}}
+ "pic-and-nonpic-1-micromipsr6-rel.o"}
{"PIC and non-PIC test 1, microMIPS (static 1)"
"-melf32btsmip -Tpic-and-nonpic-1.ld" ""
"-32 -EB -mips2"
@@ -568,6 +575,13 @@ if { $linux_gnu } {
{{objdump -dr pic-and-nonpic-1-micromips.dd}
{readelf --symbols pic-and-nonpic-1-micromips.nd}}
"pic-and-nonpic-1-micromips-static1.o"}
+ {"PIC and non-PIC test 1, microMIPS R6 (static 1)"
+ "-melf32btsmip -Tpic-and-nonpic-1.ld" ""
+ "-32 -EB -mips32r6"
+ {pic-and-nonpic-1a-micromipsr6.s pic-and-nonpic-1b-micromips.s}
+ {{objdump -dr pic-and-nonpic-1-micromipsr6.dd}
+ {readelf --symbols pic-and-nonpic-1-micromipsr6.nd}}
+ "pic-and-nonpic-1-micromips-static1.o"}
}
# The final executable produced with the following test is supposed
# to be the same as one produced with the preceding test, however
@@ -810,6 +824,10 @@ run_dump_test_o32 "undefweak-overflow"
run_dump_test_n32 "undefweak-overflow" [list [list name (n32)]]
run_dump_test_n64 "undefweak-overflow" [list [list name (n64)]]
+run_dump_test "undefweak-overflow-r6" [list [list as $abi_asflags(o32)] \
+ [list ld $abi_ldflags(o32)]]
+
+
run_dump_test_n32 "jalbal" noarch
run_dump_test "mode-change-error-1"
@@ -1265,10 +1283,22 @@ proc run_mips_plt_test { name abi filter micromips suffix {extra {}} } {
set as_flags "$abi_asflags($abi) --defsym filter=$filter"
append as_flags " --defsym micromips=$micromips --defsym $abi=1"
- if {[string equal $abi o32]} {
+ if { $micromips & 2} {
+ append as_flags " -mips32r6"
+ } elseif {[string equal $abi o32]} {
append as_flags " -march=mips2"
}
- set ld_flags "$abi_ldflags($abi) -T compressed-plt-1.ld"
+
+ if { $micromips & 2} {
+ set ld_flags "$abi_ldflags($abi) -T compressed-plt-1-umipsr6.ld"
+ } else {
+ set ld_flags "$abi_ldflags($abi) -T compressed-plt-1.ld"
+ }
+
+ if { $micromips & 4} {
+ append ld_flags " --insn32"
+ }
+
set dynobj "tmpdir/compressed-plt-1-${abi}-dyn.so"
set files [list]
if { $filter & 7 } {
@@ -1302,6 +1332,11 @@ if { $linux_gnu && $has_abi(o32) } {
run_mips_plt_test "o32 PLTs for MIPS16 encoding" o32 69 0 mips16-only
run_mips_plt_test "o32 PLTs for MIPS16 branches" o32 2 0 mips16-bronly
run_mips_plt_test "o32 PLTs for microMIPS encoding" o32 69 1 umips-only
+ run_mips_plt_test "o32 PLTs for microMIPS encoding (insn32)" \
+ o32 69 5 umips-insn32-only
+ run_mips_plt_test "o32 PLTs for microMIPS R6 encoding" o32 69 2 umipsr6-only
+ run_mips_plt_test "o32 PLTs for microMIPS R6 encoding (insn32)" \
+ o32 69 6 umipsr6-insn32-only
run_mips_plt_test "o32 PLTs for microMIPS branches" o32 2 1 umips-bronly
run_mips_plt_test "o32 PLTs for mixed MIPS and MIPS16" \
o32 109 0 mips16
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6-rel.dd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6-rel.dd
new file mode 100644
index 00000000000..87ac6fd5858
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6-rel.dd
@@ -0,0 +1,39 @@
+
+.*
+
+Disassembly of section \.text:
+
+00000000 <f1>:
+ 0: 1380 0000 lui gp,0x0
+ 0: R_MICROMIPS_HI16 _gp_disp
+ 4: 339c 0000 addiu gp,gp,0
+ 4: R_MICROMIPS_LO16 _gp_disp
+ 8: 033c e150 addu gp,gp,t9
+ c: b7ff fffe balc c .*
+ c: R_MICROMIPS_PC26_S1 f3
+ 10: 47e3 jrc ra
+
+00000012 <f2>:
+ 12: 1380 0000 lui gp,0x0
+ 12: R_MICROMIPS_HI16 _gp_disp
+ 16: 339c 0000 addiu gp,gp,0
+ 16: R_MICROMIPS_LO16 _gp_disp
+ 1a: 033c e150 addu gp,gp,t9
+ 1e: 47e3 jrc ra
+
+00000020 <f3>:
+ 20: 1380 0000 lui gp,0x0
+ 20: R_MICROMIPS_HI16 _gp_disp
+ 24: 339c 0000 addiu gp,gp,0
+ 24: R_MICROMIPS_LO16 _gp_disp
+ 28: 033c e150 addu gp,gp,t9
+ 2c: 0000 0000 nop
+
+00000030 <__start>:
+ 30: b7ff fffe balc 30 .*
+ 30: R_MICROMIPS_PC26_S1 f1
+ 34: b7ff fffe balc 34 .*
+ 34: R_MICROMIPS_PC26_S1 f2
+ 38: b7ff fffe balc 38 .*
+ 38: R_MICROMIPS_PC26_S1 f3
+ 3c: 0000 0000 nop
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6-rel.nd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6-rel.nd
new file mode 100644
index 00000000000..5cdafc3f7c2
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6-rel.nd
@@ -0,0 +1,5 @@
+#...
+.*: 00000020 +12 +FUNC +GLOBAL +DEFAULT +\[MICROMIPS, MIPS PIC\] .* f3
+.*: 00000030 +12 +FUNC +GLOBAL +DEFAULT +\[MICROMIPS\] .* __start
+.*: 00000012 +14 +FUNC +GLOBAL +DEFAULT +\[MICROMIPS, MIPS PIC\] .* f2
+.*: 00000000 +18 +FUNC +GLOBAL +DEFAULT +\[MICROMIPS, MIPS PIC\] .* f1
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6.dd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6.dd
new file mode 100644
index 00000000000..7bdf06116cf
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6.dd
@@ -0,0 +1,45 @@
+
+.*
+
+Disassembly of section \.text:
+
+00041000 <\.pic\.f3>:
+ 41000: 1320 0004 lui t9,0x4
+ 41004: 3339 1051 addiu t9,t9,4177
+ 41008: 9400 0022 bc 41050 <f3>
+ 4100c: 0000 0000 nop
+
+00041010 <\.pic\.f2>:
+ 41010: 1320 0004 lui t9,0x4
+ 41014: 3339 1043 addiu t9,t9,4163
+ 41018: 9400 0013 bc 41042 <f2>
+ \.\.\.
+
+00041028 <\.pic\.f1>:
+ 41028: 1320 0004 lui t9,0x4
+ 4102c: 3339 1031 addiu t9,t9,4145
+
+00041030 <f1>:
+ 41030: 1380 0002 lui gp,0x2
+ 41034: 339c 6fcf addiu gp,gp,28623
+ 41038: 033c e150 addu gp,gp,t9
+ 4103c: b400 0008 balc 41050 <f3>
+ 41040: 47e3 jrc ra
+
+00041042 <f2>:
+ 41042: 1380 0002 lui gp,0x2
+ 41046: 339c 6fbd addiu gp,gp,28605
+ 4104a: 033c e150 addu gp,gp,t9
+ 4104e: 47e3 jrc ra
+
+00041050 <f3>:
+ 41050: 1380 0002 lui gp,0x2
+ 41054: 339c 6faf addiu gp,gp,28591
+ 41058: 033c e150 addu gp,gp,t9
+ 4105c: 0000 0000 nop
+
+00041060 <__start>:
+ 41060: b7ff ffe2 balc 41028 <\.pic\.f1>
+ 41064: b7ff ffd4 balc 41010 <\.pic\.f2>
+ 41068: b7ff ffca balc 41000 <\.pic\.f3>
+ 4106c: 0000 0000 nop
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6.nd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6.nd
new file mode 100644
index 00000000000..6156c3b4160
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-1-micromipsr6.nd
@@ -0,0 +1,8 @@
+#...
+.*: 00068000 +0 +NOTYPE +LOCAL +DEFAULT +ABS _gp
+.*: 00041028 +8 +FUNC +LOCAL +DEFAULT +\[MICROMIPS\] .* .pic.f1
+.*: 00041010 +16 +FUNC +LOCAL +DEFAULT +\[MICROMIPS\] .* .pic.f2
+.*: 00041050 +12 +FUNC +GLOBAL +DEFAULT .* f3
+.*: 00041060 +12 +FUNC +GLOBAL +DEFAULT +\[MICROMIPS\] .* __start
+.*: 00041042 +14 +FUNC +GLOBAL +DEFAULT +\[MICROMIPS\] .* f2
+.*: 00041030 +18 +FUNC +GLOBAL +DEFAULT +\[MICROMIPS\] .* f1
diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-1a-micromipsr6.s b/ld/testsuite/ld-mips-elf/pic-and-nonpic-1a-micromipsr6.s
new file mode 100644
index 00000000000..3a6a6527d4a
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-1a-micromipsr6.s
@@ -0,0 +1,30 @@
+ .abicalls
+ .global f1
+ .global f2
+ .global f3
+ .set micromips
+ .ent f1
+f1:
+ .set noreorder
+ .cpload $25
+ .set reorder
+ .option pic0
+ jal f3
+ .option pic2
+ jr $31
+ .end f1
+
+ .ent f2
+f2:
+ .set noreorder
+ .cpload $25
+ .set reorder
+ jr $31
+ .end f2
+
+ .ent f3
+f3:
+ .set noreorder
+ .cpload $25
+ .set reorder
+ .end f3
diff --git a/ld/testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d b/ld/testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d
index 9ce02b486f0..eeec1172dd8 100644
--- a/ld/testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d
+++ b/ld/testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d
@@ -1,4 +1,5 @@
#name: MIPSr6 link branch to unaligned symbol 1 (ignore branch ISA)
+#as: -EB -n32 -march=mips64r6 --no-warn
#ld: -Ttext 0x1c000000 -e 0x1c000000 --ignore-branch-isa
#source: ../../../gas/testsuite/gas/mips/unaligned-branch-r6-3.s
#error: \A[^\n]*: in function `foo':\n
@@ -20,19 +21,11 @@
#error: \(\.text\+0x10ac\): branch to a non-instruction-aligned address\n
#error: \(\.text\+0x10b4\): branch to a non-instruction-aligned address\n
#error: \(\.text\+0x10bc\): branch to a non-instruction-aligned address\n
-#error: \(\.text\+0x10dc\): cannot convert a branch to JALX for a non-word-aligned address\n
-#error: \(\.text\+0x10e4\): cannot convert a branch to JALX for a non-word-aligned address\n
-#error: \(\.text\+0x10f4\): cannot convert a branch to JALX for a non-word-aligned address\n
-#error: \(\.text\+0x10fc\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x1104\): cannot convert a branch to JALX for a non-word-aligned address\n
-#error: \(\.text\+0x110c\): cannot convert a branch to JALX for a non-word-aligned address\n
-#error: \(\.text\+0x1114\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x1124\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x112c\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x1134\): cannot convert a branch to JALX for a non-word-aligned address\n
-#error: \(\.text\+0x113c\): cannot convert a branch to JALX for a non-word-aligned address\n
-#error: \(\.text\+0x1144\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x114c\): cannot convert a branch to JALX for a non-word-aligned address\n
-#error: \(\.text\+0x1164\): cannot convert a branch to JALX for a non-word-aligned address\n
-#error: \(\.text\+0x116c\): cannot convert a branch to JALX for a non-word-aligned address\n
-#error: \(\.text\+0x1174\): cannot convert a branch to JALX for a non-word-aligned address\Z
+#error: \(\.text\+0x1154\): cannot convert a branch to JALX for a non-word-aligned address\n
+#error: \(\.text\+0x115c\): cannot convert a branch to JALX for a non-word-aligned address\n
+#error: \(\.text\+0x1164\): cannot convert a branch to JALX for a non-word-aligned address\Z
diff --git a/ld/testsuite/ld-mips-elf/unaligned-branch-r6-1.d b/ld/testsuite/ld-mips-elf/unaligned-branch-r6-1.d
index 5f38f2e6183..9436ee546f6 100644
--- a/ld/testsuite/ld-mips-elf/unaligned-branch-r6-1.d
+++ b/ld/testsuite/ld-mips-elf/unaligned-branch-r6-1.d
@@ -1,4 +1,5 @@
#name: MIPSr6 link branch to unaligned symbol 1
+#as: -EB -n32 -march=mips64r6 --no-warn
#ld: -Ttext 0x1c000000 -e 0x1c000000
#source: ../../../gas/testsuite/gas/mips/unaligned-branch-r6-3.s
#error: \A[^\n]*: in function `foo':\n
@@ -20,20 +21,14 @@
#error: \(\.text\+0x10ac\): branch to a non-instruction-aligned address\n
#error: \(\.text\+0x10b4\): branch to a non-instruction-aligned address\n
#error: \(\.text\+0x10bc\): branch to a non-instruction-aligned address\n
-#error: \(\.text\+0x10dc\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x10dc\): unsupported branch between ISA modes\n
-#error: \(\.text\+0x10e4\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x10e4\): unsupported branch between ISA modes\n
#error: \(\.text\+0x10ec\): unsupported branch between ISA modes\n
-#error: \(\.text\+0x10f4\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x10f4\): unsupported branch between ISA modes\n
-#error: \(\.text\+0x10fc\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x10fc\): unsupported branch between ISA modes\n
#error: \(\.text\+0x1104\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x1104\): unsupported branch between ISA modes\n
-#error: \(\.text\+0x110c\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x110c\): unsupported branch between ISA modes\n
-#error: \(\.text\+0x1114\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x1114\): unsupported branch between ISA modes\n
#error: \(\.text\+0x111c\): unsupported branch between ISA modes\n
#error: \(\.text\+0x1124\): cannot convert a branch to JALX for a non-word-aligned address\n
@@ -42,18 +37,16 @@
#error: \(\.text\+0x112c\): unsupported branch between ISA modes\n
#error: \(\.text\+0x1134\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x1134\): unsupported branch between ISA modes\n
-#error: \(\.text\+0x113c\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x113c\): unsupported branch between ISA modes\n
-#error: \(\.text\+0x1144\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x1144\): unsupported branch between ISA modes\n
#error: \(\.text\+0x114c\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x114c\): unsupported branch between ISA modes\n
+#error: \(\.text\+0x1154\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x1154\): unsupported branch between ISA modes\n
+#error: \(\.text\+0x115c\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x115c\): unsupported branch between ISA modes\n
#error: \(\.text\+0x1164\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x1164\): unsupported branch between ISA modes\n
-#error: \(\.text\+0x116c\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x116c\): unsupported branch between ISA modes\n
-#error: \(\.text\+0x1174\): cannot convert a branch to JALX for a non-word-aligned address\n
#error: \(\.text\+0x1174\): unsupported branch between ISA modes\n
#error: \(\.text\+0x117c\): unsupported branch between ISA modes\Z
diff --git a/ld/testsuite/ld-mips-elf/undefweak-overflow-r6.d b/ld/testsuite/ld-mips-elf/undefweak-overflow-r6.d
new file mode 100644
index 00000000000..85574bc71f7
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/undefweak-overflow-r6.d
@@ -0,0 +1,30 @@
+#name: undefined weak symbol overflow R6
+#source: undefweak-overflow-r6.s
+#ld: -Ttext=0x20000000 -e start
+#objdump: -dr --show-raw-insn
+#...
+[0-9a-f]+ <_ftext>:
+[ 0-9a-f]+: d85fffff beqzc v0,20000000 <_ftext>
+[ 0-9a-f]+: 00000000 nop
+[ 0-9a-f]+: f85ffffd bnezc v0,20000000 <_ftext>
+[ 0-9a-f]+: ec4ffffd lwpc v0,20000000 <_ftext>
+[ 0-9a-f]+: ec5bfffe ldpc v0,20000000 <_ftext>
+[ 0-9a-f]+: cbfffffa bc 20000000 <_ftext>
+[ 0-9a-f]+: ec9ee000 auipc a0,0xe000
+[ 0-9a-f]+: 2484ffe8 addiu a0,a0,-24
+[ 0-9a-f]+: 1000fff7 b 20000000 <_ftext>
+[ 0-9a-f]+: 00000000 nop
+[ 0-9a-f]+: 0411fff5 bal 20000000 <_ftext>
+[ 0-9a-f]+: 3c...... lui a0,0x....
+[ 0-9a-f]+: 0c000000 jal 20000000 <_ftext>
+[ 0-9a-f]+: 00000000 nop
+[ 0-9a-f]+: 08000000 j 20000000 <_ftext>
+[ 0-9a-f]+: 00000000 nop
+
+[0-9a-f]+ <micro>:
+[ 0-9a-f]+: 8e5f beqzc a0,20000000 <_ftext>
+[ 0-9a-f]+: 805d 0000 beqzc v0,1ffa0046 <_ftext-0x5ffba>
+[ 0-9a-f]+: cfdc bc 20000000 <_ftext>
+[ 0-9a-f]+: 93da 0000 slti s8,k0,0
+[ 0-9a-f]+: b3d8 0000 sltiu s8,t8,0
+#pass
\ No newline at end of file
diff --git a/ld/testsuite/ld-mips-elf/undefweak-overflow-r6.s b/ld/testsuite/ld-mips-elf/undefweak-overflow-r6.s
new file mode 100644
index 00000000000..4942608441f
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/undefweak-overflow-r6.s
@@ -0,0 +1,34 @@
+# relocs against undefined weak symbols should not be treated as
+# overflowing
+
+ .module mips64r6
+ .globl start
+ .weak foo
+start:
+ .set noreorder
+ beqzc $2, foo
+ nop
+ bnezc $2, foo
+ lwpc $2, foo
+ ldpc $2, foo
+ bc foo
+ auipc $4, %pcrel_hi(foo)
+ addiu $4, $4, %pcrel_lo(foo+4)
+
+ b foo
+ nop
+ bal foo
+ lui $4, %gp_rel(foo)
+
+ jal foo
+ nop
+ j foo
+ nop
+
+ .set micromips
+micro:
+ beqzc16 $4, foo
+ beqzc $4, foo
+ bc16 foo
+ bc foo
+ balc foo
diff --git a/ld/testsuite/ld-mips-elf/undefweak-overflow.d b/ld/testsuite/ld-mips-elf/undefweak-overflow.d
index 72fcc65cb70..eb03e18052c 100644
--- a/ld/testsuite/ld-mips-elf/undefweak-overflow.d
+++ b/ld/testsuite/ld-mips-elf/undefweak-overflow.d
@@ -4,15 +4,9 @@
#objdump: -dr --show-raw-insn
#...
[0-9a-f]+ <start>:
-[ 0-9a-f]+: d85fffff beqzc v0,20000000 <start>
+[ 0-9a-f]+: 1000ffff b 20000000 <start>
[ 0-9a-f]+: 00000000 nop
-[ 0-9a-f]+: f85ffffd bnezc v0,20000000 <start>
-[ 0-9a-f]+: ec4ffffd lwpc v0,20000000 <start>
-[ 0-9a-f]+: ec5bfffe ldpc v0,20000000 <start>
-[ 0-9a-f]+: cbfffffa bc 20000000 <start>
-[ 0-9a-f]+: 1000fff9 b 20000000 <start>
-[ 0-9a-f]+: 00000000 nop
-[ 0-9a-f]+: 0411fff7 bal 20000000 <start>
+[ 0-9a-f]+: 0411fffd bal 20000000 <start>
[ 0-9a-f]+: 3c...... lui a0,0x....
[ 0-9a-f]+: 0c000000 jal 20000000 <start>
[ 0-9a-f]+: 00000000 nop
@@ -20,13 +14,13 @@
[ 0-9a-f]+: 00000000 nop
[0-9a-f]+ <micro>:
-[ 0-9a-f]+: 8e63 beqz a0,20000000 <start>
+[ 0-9a-f]+: 8e6f beqz a0,20000000 <start>
[ 0-9a-f]+: 0c00 nop
-[ 0-9a-f]+: cfe1 b 20000000 <start>
+[ 0-9a-f]+: cfed b 20000000 <start>
[ 0-9a-f]+: 0c00 nop
-[ 0-9a-f]+: 9400 ffde b 20000000 <start>
+[ 0-9a-f]+: 9400 ffea b 20000000 <start>
[ 0-9a-f]+: 0c00 nop
-[ 0-9a-f]+: 4060 ffdb bal 20000000 <start>
+[ 0-9a-f]+: 4060 ffe7 bal 20000000 <start>
[ 0-9a-f]+: 0000 0000 nop
[ 0-9a-f]+: f400 0000 jal 20000000 <start>
[ 0-9a-f]+: 0000 0000 nop
@@ -34,7 +28,7 @@
[ 0-9a-f]+: 0c00 nop
[0-9a-f]+ <mips16>:
-[ 0-9a-f]+: f7df 1010 b 20000000 <start>
+[ 0-9a-f]+: f7df 101c b 20000000 <start>
[ 0-9a-f]+: 1800 0000 jal 20000000 <start>
[ 0-9a-f]+: 6500 nop
-#pass
+#pass
\ No newline at end of file
diff --git a/ld/testsuite/ld-mips-elf/undefweak-overflow.s b/ld/testsuite/ld-mips-elf/undefweak-overflow.s
index a8370ac6a57..8bad481b687 100644
--- a/ld/testsuite/ld-mips-elf/undefweak-overflow.s
+++ b/ld/testsuite/ld-mips-elf/undefweak-overflow.s
@@ -1,19 +1,12 @@
# relocs against undefined weak symbols should not be treated as
# overflowing
- .module mips64r6
+ .module mips64r2
.globl start
.type start, @function
.weak foo
start:
.set noreorder
- .set mips64r6
- beqzc $2, foo
- nop
- bnezc $2, foo
- lwpc $2, foo
- ldpc $2, foo
- bc foo
b foo
nop
@@ -25,7 +18,6 @@ start:
j foo
nop
- .set mips32r2
.set micromips
micro:
beqz16 $4, foo
diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c
index 699124aa3e6..a4b43504c75 100644
--- a/opcodes/micromips-opc.c
+++ b/opcodes/micromips-opc.c
@@ -97,17 +97,48 @@ decode_micromips_operand (const char *p)
}
break;
+ case '-':
+ switch (p[1])
+ {
+ case 'A': PCREL (19, 0, true, 2, 2, false, false);
+ case 'B': PCREL (18, 0, true, 3, 3, false, false);
+
+ case 'a': INT_ADJ (19, 0, 262143, 2, false);
+ case 'b': INT_ADJ (18, 0, 131071, 3, false);
+ case 'd': MAPPED_REG (3, 1, GP, reg_m16_map);
+ case 'e': OPTIONAL_MAPPED_REG (3, 7, GP, reg_m16_map);
+ case 'm': SPLIT_MAPPED_REG (3, 0, 1, 3, GP, reg_mn_map);
+ case 'p': REG (5, 4, GP);
+ case 's': SPECIAL (5, 16, NON_ZERO_REG);
+ case 't': SPECIAL (5, 21, NON_ZERO_REG);
+ case 'u': PREV_CHECK (5, 21, true, false, false, false);
+ case 'v': PREV_CHECK (5, 21, true, true, false, false);
+ case 'w': PREV_CHECK (5, 21, false, true, true, true);
+ case 'x': PREV_CHECK (5, 16, true, false, false, true);
+ case 'y': PREV_CHECK (5, 16, false, true, false, false);
+ }
+ break;
+
case '+':
switch (p[1])
{
case 'A': BIT (5, 6, 0); /* (0 .. 31) */
case 'B': MSB (5, 11, 1, true, 32); /* (1 .. 32), 32-bit op */
case 'C': MSB (5, 11, 1, false, 32); /* (1 .. 32), 32-bit op */
+ case 'D': REG (5, 16, FP);
case 'E': BIT (5, 6, 32); /* (32 .. 63) */
case 'F': MSB (5, 11, 33, true, 64); /* (33 .. 64), 64-bit op */
case 'G': MSB (5, 11, 33, false, 64); /* (33 .. 64), 64-bit op */
case 'H': MSB (5, 11, 1, false, 64); /* (1 .. 32), 64-bit op */
+ case 'I': UINT (2, 9);
case 'J': HINT (10, 16);
+ case 'K': HINT (4, 6);
+ case 'L': INT_ADJ (4, 4, 15, 2, false); /* (0 .. 15) << 2 */
+ case 'M': HINT (16, 6);
+ case 'N': SPECIAL (2, 8, LWM_SWM_LIST);
+ case 'O': UINT (3, 8);
+ case 'P': INT_ADJ (5, 5, 31, 2, false); /* (0 .. 31) << 2 */
+ case 'S': REG (5, 21, FP);
case 'T': INT_ADJ (10, 16, 511, 0, false); /* (-512 .. 511) << 0 */
case 'U': INT_ADJ (10, 16, 511, 1, false); /* (-512 .. 511) << 1 */
case 'V': INT_ADJ (10, 16, 511, 2, false); /* (-512 .. 511) << 2 */
@@ -122,6 +153,8 @@ decode_micromips_operand (const char *p)
case 'l': REG (5, 6, MSA_CTRL);
case 'n': REG (5, 11, MSA_CTRL);
case 'o': SPECIAL (4, 16, IMM_INDEX);
+ case 's': REG (5, 21, GP);
+ case 't': REG (5, 16, GP);
case 'u': SPECIAL (3, 16, IMM_INDEX);
case 'v': SPECIAL (2, 16, IMM_INDEX);
case 'w': SPECIAL (1, 16, IMM_INDEX);
@@ -137,6 +170,11 @@ decode_micromips_operand (const char *p)
case '&': SPECIAL (0, 0, IMM_INDEX);
case '*': SPECIAL (5, 16, REG_INDEX);
case '|': BIT (8, 16, 0); /* (0 .. 255) */
+ case '\'': BRANCH (26, 0, 1);
+ case '"': BRANCH (21, 0, 1);
+ case ':': SINT (11, 0);
+ case '.': BIT (2, 9, 1); /* (1 .. 4) */
+ case ';': SPECIAL (10, 16, SAME_RS_RT);
}
break;
@@ -196,8 +234,8 @@ decode_micromips_operand (const char *p)
case 'u': HINT (16, 0);
case 'v': OPTIONAL_REG (5, 16, GP);
case 'w': OPTIONAL_REG (5, 21, GP);
- case 'x': REG (5, 6, GP);
- case 'y': REG (5, 21, CONTROL);
+ case 'y': REG (5, 6, GP);
+ case 'x': REG (5, 21, CONTROL);
case 'z': MAPPED_REG (0, 0, GP, reg_0_map);
}
return 0;
@@ -232,6 +270,7 @@ decode_micromips_operand (const char *p)
#define WR_sp INSN2_WRITE_SP
#define RD_31 INSN2_READ_GPR_31
#define RD_pc INSN2_READ_PC
+#define CTC INSN2_CONVERTED_TO_COMPACT
/* For 32-bit microMIPS instructions. */
#define WR_31 INSN_WRITE_GPR_31
@@ -263,6 +302,8 @@ decode_micromips_operand (const char *p)
#define I1 INSN_ISA1
#define I3 INSN_ISA3
#define I36 INSN_ISA32R5
+#define I37 INSN_ISA32R6
+#define I69 INSN_ISA64R6
/* MIPS DSP ASE support. */
#define WR_a WR_HILO /* Write DSP accumulators (reuse WR_HILO). */
@@ -271,6 +312,7 @@ decode_micromips_operand (const char *p)
#define DSP_VOLA INSN_NO_DELAY_SLOT
#define D32 ASE_DSP
#define D33 ASE_DSPR2
+#define D34 ASE_DSPR3
/* MIPS MT ASE support. */
#define MT32 ASE_MT
@@ -280,6 +322,7 @@ decode_micromips_operand (const char *p)
/* MIPS Enhanced VA Scheme. */
#define EVA ASE_EVA
+#define EVAR6 ASE_EVA_R6
/* TLB invalidate instruction support. */
#define TLBINV ASE_EVA
@@ -302,63 +345,77 @@ const struct mips_opcode micromips_opcodes[] =
them first. The assemblers uses a hash table based on the
instruction name anyhow. */
/* name, args, match, mask, pinfo, pinfo2, membership, ase, exclusions */
-{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_3|LM, 0, I1, 0, 0 },
+{"pref", "k,~(b)", 0x60002000, 0xfc00f000, RD_3|LM, 0, I1, 0, I37 },
+{"pref", "k,+j(b)", 0x60002000, 0xfc00fe00, RD_3|LM, 0, I37, 0, 0 },
{"pref", "k,A(b)", 0, (int) M_PREF_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 },
-{"nop", "", 0x0c00, 0xffff, 0, AL, I1, 0, 0 },
-{"nop", "", 0x00000000, 0xffffffff, 0, AL, I1, 0, 0 }, /* sll */
-{"ssnop", "", 0x00000800, 0xffffffff, 0, AL, I1, 0, 0 }, /* sll */
-{"ehb", "", 0x00001800, 0xffffffff, 0, AL, I1, 0, 0 }, /* sll */
-{"pause", "", 0x00002800, 0xffffffff, 0, AL, I1, 0, 0 }, /* sll */
+{"prefx", "h,t(b)", 0x540001a0, 0xfc0007ff, RD_2|RD_3|FP_S|LM, 0, I1, 0, I37 },
+{"nop", "", 0x0c00, 0xffff, 0, INSN2_ALIAS, I1, 0, 0 },
+{"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */
+{"ssnop", "", 0x00000800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */
+{"ehb", "", 0x00001800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */
+{"pause", "", 0x00002800, 0xffffffff, 0, INSN2_ALIAS, I1, 0, 0 }, /* sll */
+{"lapc", "t,-A", 0x78000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
{"li", "md,mI", 0xec00, 0xfc00, WR_1, 0, I1, 0, 0 },
-{"li", "t,j", 0x30000000, 0xfc1f0000, WR_1, AL, I1, 0, 0 }, /* addiu */
-{"li", "t,i", 0x50000000, 0xfc1f0000, WR_1, AL, I1, 0, 0 }, /* ori */
+{"li", "t,j", 0x30000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* addiu */
+{"li", "t,i", 0x50000000, 0xfc1f0000, WR_1, INSN2_ALIAS, I1, 0, 0 }, /* ori */
{"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1, 0, 0 },
{"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1, 0, 0 },
{"move", "mp,mj", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 },
-{"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, AL, I1, 0, 0 }, /* or */
-{"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, AL, I3, 0, 0 }, /* daddu */
-{"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, AL, I1, 0, 0 }, /* addu */
-{"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, 0 },
-{"b", "p", 0x94000000, 0xffff0000, UBD, AL, I1, 0, 0 }, /* beq 0, 0 */
-{"b", "p", 0x40400000, 0xffff0000, UBD, AL, I1, 0, 0 }, /* bgez 0 */
+{"move", "d,s", 0x00000290, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* or */
+{"move", "d,s", 0x58000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I3, 0, 0 }, /* daddu */
+{"move", "d,s", 0x00000150, 0xffe007ff, WR_1|RD_2, INSN2_ALIAS, I1, 0, 0 }, /* addu */
+{"b", "mD", 0xcc00, 0xfc00, UBD, 0, I1, 0, I37 },
+{"b", "mD", 0xcc00, 0xfc00, 0, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* bc */
+{"b", "p", 0x94000000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, I37 }, /* beq 0, 0 */
+{"b", "+'", 0x94000000, 0xfc000000, 0, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* bc */
+{"b", "p", 0x40400000, 0xffff0000, UBD, INSN2_ALIAS, I1, 0, I37 }, /* bgez 0 */
/* BC is next to B so that we easily find it when converting a normal
branch to a compact one. */
-{"bc", "p", 0x40e00000, 0xffff0000, NODS, UBR|AL, I1, 0, 0 }, /* beqzc 0 */
-{"bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, BD32|AL, I1, 0, 0 }, /* bgezal 0 */
-{"bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, BD16|AL, I1, 0, 0 }, /* bgezals 0 */
+{"bc", "mD", 0xcc00, 0xfc00, 0, UBR, I37, 0, 0 },
+{"bc", "+'", 0x94000000, 0xfc000000, 0, UBR, I37, 0, 0 },
+{"bc", "p", 0x40e00000, 0xffff0000, NODS, INSN2_ALIAS|UBR, I1, 0, I37 }, /* beqzc 0 */
+{"bal", "+'", 0xb4000000, 0xfc000000, WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* balc */
+{"bal", "p", 0x40600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD32, I1, 0, I37 }, /* bgezal 0 */
+{"balc", "+'", 0xb4000000, 0xfc000000, WR_31, UBR, I37, 0, 0 },
+{"bals", "p", 0x42600000, 0xffff0000, WR_31|UBD, INSN2_ALIAS|BD16, I1, 0, I37 }, /* bgezals 0 */
+
{"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1, 0, 0 },
{"abs.d", "T,V", 0x5400237b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"abs.s", "T,V", 0x5400037b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
-{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
+{"abs.ps", "T,V", 0x5400437b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, I37 },
{"aclr", "\\,~(b)", 0x2000b000, 0xff00f000, RD_3|LM|SM|NODS, 0, 0, MC, 0 },
{"aclr", "\\,A(b)", 0, (int) M_ACLR_AB, INSN_MACRO, 0, 0, MC, 0 },
{"add", "d,v,t", 0x00000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1, 0, 0 },
{"add.d", "D,V,T", 0x54000130, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
{"add.s", "D,V,T", 0x54000030, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 },
-{"add.ps", "D,V,T", 0x54000230, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
-{"addi", "t,r,j", 0x10000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
+{"add.ps", "D,V,T", 0x54000230, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
+{"addi", "t,r,j", 0x10000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, I37 },
{"addiu", "mp,mj,mZ", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */
{"addiu", "md,ms,mW", 0x6c01, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, /* addiur1sp */
{"addiu", "md,mc,mB", 0x6c00, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 }, /* addiur2 */
{"addiu", "ms,mt,mY", 0x4c01, 0xfc01, MOD_1, 0, I1, 0, 0 }, /* addiusp */
{"addiu", "mp,mt,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 }, /* addius5 */
-{"addiu", "mb,mr,mQ", 0x78000000, 0xfc000000, WR_1, RD_pc, I1, 0, 0 }, /* addiupc */
+{"addiu", "mb,mr,mQ", 0x78000000, 0xfc000000, WR_1, RD_pc, I1, 0, I37 }, /* addiupc */
{"addiu", "t,r,j", 0x30000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
-{"addiupc", "mb,mQ", 0x78000000, 0xfc000000, WR_1, RD_pc, I1, 0, 0 },
+{"addiu", "t,mr,-a", 0x78000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
+{"addiupc", "t,-a", 0x78000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
+{"addiupc", "mb,mQ", 0x78000000, 0xfc000000, WR_1, RD_pc, I1, 0, I37 },
{"addiur1sp", "md,mW", 0x6c01, 0xfc01, WR_1, RD_sp, I1, 0, 0 },
{"addiur2", "md,mc,mB", 0x6c00, 0xfc01, WR_1|RD_2, 0, I1, 0, 0 },
{"addiusp", "mY", 0x4c01, 0xfc01, 0, WR_sp|RD_sp, I1, 0, 0 },
{"addius5", "mp,mX", 0x4c00, 0xfc01, MOD_1, 0, I1, 0, 0 },
{"addu", "mp,mj,mz", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */
{"addu", "mp,mz,mj", 0x0c00, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, /* move */
-{"addu", "md,me,ml", 0x0400, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
+{"addu", "-d,-e,ml", 0x0400, 0xfc01, WR_1|RD_2|RD_3, 0, I37, 0, 0 },
+{"addu", "md,me,ml", 0x0400, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, I37 },
{"addu", "d,v,t", 0x00000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1, 0, 0 },
-{"alnv.ps", "D,V,T,x", 0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
-{"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 },
-{"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 },
+{"alnv.ps", "D,V,T,y", 0x54000019, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, I37 },
+{"and", "md,mt,ml", 0x4401, 0xfc0f, MOD_1|RD_3, 0, I37, 0, 0 },
+{"and", "md,ml,mx", 0x4401, 0xfc0f, MOD_1|RD_2, 0, I37, 0, 0 },
+{"and", "mf,mt,mg", 0x4480, 0xffc0, MOD_1|RD_3, 0, I1, 0, I37 },
+{"and", "mf,mg,mx", 0x4480, 0xffc0, MOD_1|RD_2, 0, I1, 0, I37 },
{"and", "d,v,t", 0x00000250, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1, 0, 0 },
{"andi", "md,mc,mC", 0x2c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 },
@@ -367,212 +424,251 @@ const struct mips_opcode micromips_opcodes[] =
{"aset", "\\,A(b)", 0, (int) M_ASET_AB, INSN_MACRO, 0, 0, MC, 0 },
/* b is at the top of the table. */
/* bal is at the top of the table. */
-{"bc1f", "p", 0x43800000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, 0 },
-{"bc1f", "N,p", 0x43800000, 0xffe30000, RD_CC|CBD|FP_S, 0, I1, 0, 0 },
-{"bc1fl", "p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
-{"bc1fl", "N,p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
-{"bc2f", "p", 0x42800000, 0xffff0000, RD_CC|CBD, 0, I1, 0, 0 },
-{"bc2f", "N,p", 0x42800000, 0xffe30000, RD_CC|CBD, 0, I1, 0, 0 },
-{"bc2fl", "p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1, 0, 0 },
-{"bc2fl", "N,p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1, 0, 0 },
-{"bc1t", "p", 0x43a00000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, 0 },
-{"bc1t", "N,p", 0x43a00000, 0xffe30000, RD_CC|CBD|FP_S, 0, I1, 0, 0 },
-{"bc1tl", "p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
-{"bc1tl", "N,p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
-{"bc2t", "p", 0x42a00000, 0xffff0000, RD_CC|CBD, 0, I1, 0, 0 },
-{"bc2t", "N,p", 0x42a00000, 0xffe30000, RD_CC|CBD, 0, I1, 0, 0 },
-{"bc2tl", "p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, 0 },
-{"bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, 0 },
-{"beqz", "md,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 },
-{"beqz", "s,p", 0x94000000, 0xffe00000, RD_1|CBD, AL, I1, 0, 0 },
-{"beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 },
-{"beq", "md,mz,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* beqz */
-{"beq", "mz,md,mE", 0x8c00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* beqz */
-{"beq", "s,t,p", 0x94000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 },
+{"bc1f", "p", 0x43800000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, I37 },
+{"bc1f", "N,p", 0x43800000, 0xffe30000, RD_CC|CBD|FP_S, 0, I1, 0, I37 },
+{"bc1fl", "p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1, 0, I37 },
+{"bc1fl", "N,p", 0, (int) M_BC1FL, INSN_MACRO, INSN2_M_FP_S, I1, 0, I37 },
+{"bc2f", "p", 0x42800000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I37 },
+{"bc2f", "N,p", 0x42800000, 0xffe30000, RD_CC|CBD, 0, I1, 0, I37 },
+{"bc2fl", "p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1, 0, I37 },
+{"bc2fl", "N,p", 0, (int) M_BC2FL, INSN_MACRO, 0, I1, 0, I37 },
+{"bc1t", "p", 0x43a00000, 0xffff0000, RD_CC|CBD|FP_S, 0, I1, 0, I37 },
+{"bc1t", "N,p", 0x43a00000, 0xffe30000, RD_CC|CBD|FP_S, 0, I1, 0, I37 },
+{"bc1tl", "p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1, 0, I37 },
+{"bc1tl", "N,p", 0, (int) M_BC1TL, INSN_MACRO, INSN2_M_FP_S, I1, 0, I37 },
+{"bc2t", "p", 0x42a00000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I37 },
+{"bc2t", "N,p", 0x42a00000, 0xffe30000, RD_CC|CBD, 0, I1, 0, I37 },
+{"bc2tl", "p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, I37 },
+{"bc2tl", "N,p", 0, (int) M_BC2TL, INSN_MACRO, 0, I1, 0, I37 },
+{"beqz", "md,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, I37 },
+{"beqz", "md,mE", 0x8c00, 0xfc00, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* beqzc */
+{"beqz", "s,p", 0x94000000, 0xffe00000, RD_1|CBD, 0, I1, 0, I37 },
+{"beqz", "-t,+\"", 0x80000000, 0xfc000000, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* beqzc */
+{"beqzl", "s,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, I37 },
+{"beq", "md,mz,mE", 0x8c00, 0xfc00, RD_1|CBD, 0, I1, 0, I37 }, /* beqz */
+{"beq", "mz,md,mE", 0x8c00, 0xfc00, RD_2|CBD, 0, I1, 0, I37 }, /* beqz */
+{"beq", "md,mz,mE", 0x8c00, 0xfc00, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* beqzc16 */
+{"beq", "mz,md,mE", 0x8c00, 0xfc00, RD_2, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* beqzc16 */
+{"beq", "-t,z,+\"", 0x80000000, 0xfc000000, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* beqzc */
+{"beq", "z,-t,+\"", 0x80000000, 0xfc000000, RD_2, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* beqzc */
+{"beq", "-s,-u,p", 0x74000000, 0xfc000000, RD_1|RD_2, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* beqc */
+{"beq", "t,-y,p", 0x74000000, 0xfc000000, RD_1|RD_2, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* beqc */
+{"beq", "s,t,p", 0x94000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, I37 },
{"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1, 0, 0 },
/* BEQZC is next to BEQ so that we easily find it when converting a normal
branch to a compact one. */
-{"beqzc", "s,p", 0x40e00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 },
-{"beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, 0 },
-{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1, 0, 0 },
+{"beqzc", "md,mE", 0x8c00, 0xfc00, RD_1, CBR, I37, 0, 0 },
+{"beqzc", "-t,+\"", 0x80000000, 0xfc000000, RD_1, CBR, I37, 0, 0 },
+{"beqzc", "s,p", 0x40e00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, I37 },
+{"bovc", "s,-w,p", 0x74000000, 0xfc000000, RD_1|RD_2, CBR, I37, 0, 0 },
+{"bovc", "t,-x,p", 0x74000000, 0xfc000000, RD_1|RD_2, INSN2_ALIAS|CBR, I37, 0, 0 },
+{"beqzalc", "-t,p", 0x74000000, 0xfc1f0000, RD_1|WR_31, CBR, I37, 0, 0 },
+{"beqc", "-s,-u,p", 0x74000000, 0xfc000000, RD_1|RD_2, CBR, I37, 0, 0 },
+{"beqc", "t,-y,p", 0x74000000, 0xfc000000, RD_1|RD_2, INSN2_ALIAS|CBR, I37, 0, 0 },
+{"beql", "s,t,p", 0, (int) M_BEQL, INSN_MACRO, 0, I1, 0, I37 },
+{"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I1, 0, I37 },
{"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1, 0, 0 },
{"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I1, 0, 0 },
-{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I1, 0, 0 },
+{"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I1, 0, I37 },
+{"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I1, 0, I37 },
{"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1, 0, 0 },
{"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I1, 0, 0 },
-{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bgez", "s,p", 0x40400000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 },
-{"bgezl", "s,p", 0, (int) M_BGEZL, INSN_MACRO, 0, I1, 0, 0 },
-{"bgezal", "s,p", 0x40600000, 0xffe00000, RD_1|WR_31|CBD, BD32, I1, 0, 0 },
-{"bgezals", "s,p", 0x42600000, 0xffe00000, RD_1|WR_31|CBD, BD16, I1, 0, 0 },
-{"bgezall", "s,p", 0, (int) M_BGEZALL, INSN_MACRO, 0, I1, 0, 0 },
+{"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I1, 0, I37 },
+{"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I1, 0, I37 },
+{"bgez", "s,p", 0x40400000, 0xffe00000, RD_1|CBD, 0, I1, 0, I37 },
+{"bgez", "+;,p", 0xf4000000, 0xfc000000, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bgezc */
+{"bgezl", "s,p", 0, (int) M_BGEZL, INSN_MACRO, 0, I1, 0, I37 },
+{"bgezal", "s,p", 0x40600000, 0xffe00000, RD_1|WR_31|CBD, BD32, I1, 0, I37 },
+{"bgezal", "+;,p", 0xc0000000, 0xfc000000, RD_1|WR_31, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bgezalc */
+{"bgezals", "s,p", 0x42600000, 0xffe00000, RD_1|WR_31|CBD, BD16, I1, 0, I37 },
+{"bgezall", "s,p", 0, (int) M_BGEZALL, INSN_MACRO, 0, I1, 0, I37 },
{"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1, 0, 0 },
{"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I1, 0, 0 },
-{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I1, 0, 0 },
+{"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I1, 0, I37 },
+{"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I1, 0, I37 },
{"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1, 0, 0 },
{"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I1, 0, 0 },
-{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bgtz", "s,p", 0x40c00000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 },
-{"bgtzl", "s,p", 0, (int) M_BGTZL, INSN_MACRO, 0, I1, 0, 0 },
+{"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I1, 0, I37 },
+{"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I1, 0, I37 },
+{"bgtz", "s,p", 0x40c00000, 0xffe00000, RD_1|CBD, 0, I1, 0, I37 },
+{"bgtz", "-t,p", 0xd4000000, 0xfc1f0000, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bgtzc */
+{"bgtzl", "s,p", 0, (int) M_BGTZL, INSN_MACRO, 0, I1, 0, I37 },
{"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1, 0, 0 },
{"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1, 0, 0 },
-{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I1, 0, 0 },
-{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I1, 0, 0 },
+{"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I1, 0, I37 },
+{"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I1, 0, I37 },
{"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1, 0, 0 },
{"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I1, 0, 0 },
-{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I1, 0, 0 },
-{"blez", "s,p", 0x40800000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 },
-{"blezl", "s,p", 0, (int) M_BLEZL, INSN_MACRO, 0, I1, 0, 0 },
+{"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I1, 0, I37 },
+{"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I1, 0, I37 },
+{"blez", "s,p", 0x40800000, 0xffe00000, RD_1|CBD, 0, I1, 0, I37 },
+{"blez", "-t,p", 0xf4000000, 0xfc1f0000, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* blezc */
+{"blezl", "s,p", 0, (int) M_BLEZL, INSN_MACRO, 0, I1, 0, I37 },
{"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1, 0, 0 },
{"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I1, 0, 0 },
-{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I1, 0, 0 },
+{"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I1, 0, I37 },
+{"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I1, 0, I37 },
{"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1, 0, 0 },
{"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I1, 0, 0 },
-{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I1, 0, 0 },
-{"bltz", "s,p", 0x40000000, 0xffe00000, RD_1|CBD, 0, I1, 0, 0 },
-{"bltzl", "s,p", 0, (int) M_BLTZL, INSN_MACRO, 0, I1, 0, 0 },
-{"bltzal", "s,p", 0x40200000, 0xffe00000, RD_1|WR_31|CBD, BD32, I1, 0, 0 },
-{"bltzals", "s,p", 0x42200000, 0xffe00000, RD_1|WR_31|CBD, BD16, I1, 0, 0 },
-{"bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1, 0, 0 },
-{"bnez", "md,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 },
-{"bnez", "s,p", 0xb4000000, 0xffe00000, RD_1|CBD, AL, I1, 0, 0 },
-{"bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 },
-{"bne", "md,mz,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, 0 }, /* bnez */
-{"bne", "mz,md,mE", 0xac00, 0xfc00, RD_2|CBD, 0, I1, 0, 0 }, /* bnez */
-{"bne", "s,t,p", 0xb4000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, 0 },
+{"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I1, 0, I37 },
+{"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I1, 0, I37 },
+{"bltz", "s,p", 0x40000000, 0xffe00000, RD_1|CBD, 0, I1, 0, I37 },
+{"bltz", "+;,p", 0xd4000000, 0xfc000000, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bltzc */
+{"bltzl", "s,p", 0, (int) M_BLTZL, INSN_MACRO, 0, I1, 0, I37 },
+{"bltzal", "s,p", 0x40200000, 0xffe00000, RD_1|WR_31|CBD, BD32, I1, 0, I37 },
+{"bltzal", "+;,p", 0xe0000000, 0xfc000000, RD_1|WR_31, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bltzalc */
+{"bltzals", "s,p", 0x42200000, 0xffe00000, RD_1|WR_31|CBD, BD16, I1, 0, I37 },
+{"bltzall", "s,p", 0, (int) M_BLTZALL, INSN_MACRO, 0, I1, 0, I37 },
+{"bnez", "md,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, I37 },
+{"bnez", "md,mE", 0xac00, 0xfc00, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bnezc */
+{"bnez", "s,p", 0xb4000000, 0xffe00000, RD_1|CBD, 0, I1, 0, I37 },
+{"bnez", "-t,+\"", 0xa0000000, 0xfc000000, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bnezc */
+{"bnezl", "s,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, I37 },
+{"bne", "md,mz,mE", 0xac00, 0xfc00, RD_1|CBD, 0, I1, 0, I37 }, /* bnez */
+{"bne", "mz,md,mE", 0xac00, 0xfc00, RD_2|CBD, 0, I1, 0, I37 }, /* bnez */
+{"bne", "md,mz,mE", 0xac00, 0xfc00, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bnezc16 */
+{"bne", "mz,md,mE", 0xac00, 0xfc00, RD_2, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bnezc16 */
+{"bne", "s,t,p", 0xb4000000, 0xfc000000, RD_1|RD_2|CBD, 0, I1, 0, I37 },
{"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1, 0, 0 },
+{"bne", "-t,z,+\"", 0xa0000000, 0xfc000000, RD_1, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bnezc */
+{"bne", "z,-t,+\"", 0xa0000000, 0xfc000000, RD_2, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bnezc */
+{"bne", "-s,-u,p", 0x7c000000, 0xfc000000, RD_1|RD_2, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bnec */
+{"bne", "t,-y,p", 0x7c000000, 0xfc000000, RD_1|RD_2, INSN2_ALIAS|CBR|CTC, I37, 0, 0 }, /* bnec */
/* BNEZC is next to BNE so that we easily find it when converting a normal
branch to a compact one. */
-{"bnezc", "s,p", 0x40a00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, 0 },
-{"bnel", "s,t,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, 0 },
-{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I1, 0, 0 },
-{"break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, 0 },
+{"bnezc", "md,mE", 0xac00, 0xfc00, RD_1, CBR, I37, 0, 0 },
+{"bnezc", "-t,+\"", 0xa0000000, 0xfc000000, RD_1, CBR, I37, 0, 0 },
+{"bnezc", "s,p", 0x40a00000, 0xffe00000, RD_1|NODS, CBR, I1, 0, I37 },
+{"bnvc", "s,-w,p", 0x7c000000, 0xfc000000, RD_1|RD_2, CBR, I37, 0, 0 },
+{"bnvc", "t,-x,p", 0x7c000000, 0xfc000000, RD_1|RD_2, INSN2_ALIAS|CBR, I37, 0, 0 },
+{"bnezalc", "-t,p", 0x7c000000, 0xfc1f0000, RD_1|WR_31, CBR, I37, 0, 0 },
+{"bnec", "-s,-u,p", 0x7c000000, 0xfc000000, RD_1|RD_2, CBR, I37, 0, 0 },
+{"bnec", "t,-y,p", 0x7c000000, 0xfc000000, RD_1|RD_2, INSN2_ALIAS|CBR, I37, 0, 0 },
+{"bnel", "s,t,p", 0, (int) M_BNEL, INSN_MACRO, 0, I1, 0, I37 },
+{"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I1, 0, I37 },
+{"break", "", 0x441b, 0xffff, TRAP, 0, I37, 0, 0 },
+{"break", "", 0x4680, 0xffff, TRAP, 0, I1, 0, I37 },
{"break", "", 0x00000007, 0xffffffff, TRAP, 0, I1, 0, 0 },
-{"break", "mF", 0x4680, 0xfff0, TRAP, 0, I1, 0, 0 },
+{"break", "+K", 0x441b, 0xfc3f, TRAP, 0, I37, 0, 0 },
+{"break", "mF", 0x4680, 0xfff0, TRAP, 0, I1, 0, I37 },
{"break", "c", 0x00000007, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
{"break", "c,q", 0x00000007, 0xfc00003f, TRAP, 0, I1, 0, 0 },
-{"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.un.s", "M,S,T", 0x5400007c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.un.ps", "S,T", 0x5400087c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.un.ps", "M,S,T", 0x5400087c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.eq.d", "S,T", 0x540004bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.eq.d", "M,S,T", 0x540004bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.eq.s", "S,T", 0x540000bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.eq.s", "M,S,T", 0x540000bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.eq.ps", "S,T", 0x540008bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.eq.ps", "M,S,T", 0x540008bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ueq.d", "S,T", 0x540004fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ueq.d", "M,S,T", 0x540004fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ueq.s", "S,T", 0x540000fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ueq.s", "M,S,T", 0x540000fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ueq.ps", "S,T", 0x540008fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ueq.ps", "M,S,T", 0x540008fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.olt.d", "S,T", 0x5400053c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.olt.d", "M,S,T", 0x5400053c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.olt.s", "S,T", 0x5400013c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.olt.s", "M,S,T", 0x5400013c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.olt.ps", "S,T", 0x5400093c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.olt.ps", "M,S,T", 0x5400093c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ult.d", "S,T", 0x5400057c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ult.d", "M,S,T", 0x5400057c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ult.s", "S,T", 0x5400017c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ult.s", "M,S,T", 0x5400017c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ult.ps", "S,T", 0x5400097c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ult.ps", "M,S,T", 0x5400097c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ole.d", "S,T", 0x540005bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ole.d", "M,S,T", 0x540005bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ole.s", "S,T", 0x540001bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ole.s", "M,S,T", 0x540001bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ole.ps", "S,T", 0x540009bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ole.ps", "M,S,T", 0x540009bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ule.d", "S,T", 0x540005fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ule.d", "M,S,T", 0x540005fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ule.s", "S,T", 0x540001fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ule.s", "M,S,T", 0x540001fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ule.ps", "S,T", 0x540009fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ule.ps", "M,S,T", 0x540009fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.sf.d", "S,T", 0x5400063c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.sf.d", "M,S,T", 0x5400063c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.sf.s", "S,T", 0x5400023c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.sf.s", "M,S,T", 0x5400023c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.sf.ps", "S,T", 0x54000a3c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.sf.ps", "M,S,T", 0x54000a3c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngle.d", "S,T", 0x5400067c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngle.d", "M,S,T", 0x5400067c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngle.s", "S,T", 0x5400027c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ngle.s", "M,S,T", 0x5400027c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ngle.ps", "S,T", 0x54000a7c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngle.ps", "M,S,T", 0x54000a7c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.seq.d", "S,T", 0x540006bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.seq.d", "M,S,T", 0x540006bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.seq.s", "S,T", 0x540002bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.seq.s", "M,S,T", 0x540002bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.seq.ps", "S,T", 0x54000abc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.seq.ps", "M,S,T", 0x54000abc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngl.d", "S,T", 0x540006fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngl.d", "M,S,T", 0x540006fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngl.s", "S,T", 0x540002fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ngl.s", "M,S,T", 0x540002fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ngl.ps", "S,T", 0x54000afc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngl.ps", "M,S,T", 0x54000afc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.lt.d", "S,T", 0x5400073c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.lt.d", "M,S,T", 0x5400073c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.lt.s", "S,T", 0x5400033c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.lt.s", "M,S,T", 0x5400033c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.lt.ps", "S,T", 0x54000b3c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.lt.ps", "M,S,T", 0x54000b3c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.nge.d", "S,T", 0x5400077c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.nge.d", "M,S,T", 0x5400077c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.nge.s", "S,T", 0x5400037c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.nge.s", "M,S,T", 0x5400037c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.nge.ps", "S,T", 0x54000b7c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.nge.ps", "M,S,T", 0x54000b7c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.le.d", "S,T", 0x540007bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.le.d", "M,S,T", 0x540007bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.le.s", "S,T", 0x540003bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.le.s", "M,S,T", 0x540003bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.le.ps", "S,T", 0x54000bbc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.le.ps", "M,S,T", 0x54000bbc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngt.d", "S,T", 0x540007fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngt.d", "M,S,T", 0x540007fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngt.s", "S,T", 0x540003fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ngt.s", "M,S,T", 0x540003fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, 0 },
-{"c.ngt.ps", "S,T", 0x54000bfc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, 0 },
-{"c.ngt.ps", "M,S,T", 0x54000bfc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, 0 },
-{"cache", "k,~(b)", 0x20006000, 0xfc00f000, RD_3, 0, I1, 0, 0 },
+{"c.f.d", "S,T", 0x5400043c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.f.d", "M,S,T", 0x5400043c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.f.s", "S,T", 0x5400003c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.f.s", "M,S,T", 0x5400003c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.f.ps", "S,T", 0x5400083c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.f.ps", "M,S,T", 0x5400083c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.un.d", "S,T", 0x5400047c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.un.d", "M,S,T", 0x5400047c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.un.s", "S,T", 0x5400007c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.un.s", "M,S,T", 0x5400007c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.un.ps", "S,T", 0x5400087c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.un.ps", "M,S,T", 0x5400087c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.eq.d", "S,T", 0x540004bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.eq.d", "M,S,T", 0x540004bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.eq.s", "S,T", 0x540000bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.eq.s", "M,S,T", 0x540000bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.eq.ps", "S,T", 0x540008bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.eq.ps", "M,S,T", 0x540008bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ueq.d", "S,T", 0x540004fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ueq.d", "M,S,T", 0x540004fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ueq.s", "S,T", 0x540000fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ueq.s", "M,S,T", 0x540000fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ueq.ps", "S,T", 0x540008fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ueq.ps", "M,S,T", 0x540008fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.olt.d", "S,T", 0x5400053c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.olt.d", "M,S,T", 0x5400053c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.olt.s", "S,T", 0x5400013c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.olt.s", "M,S,T", 0x5400013c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.olt.ps", "S,T", 0x5400093c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.olt.ps", "M,S,T", 0x5400093c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ult.d", "S,T", 0x5400057c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ult.d", "M,S,T", 0x5400057c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ult.s", "S,T", 0x5400017c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ult.s", "M,S,T", 0x5400017c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ult.ps", "S,T", 0x5400097c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ult.ps", "M,S,T", 0x5400097c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ole.d", "S,T", 0x540005bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ole.d", "M,S,T", 0x540005bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ole.s", "S,T", 0x540001bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ole.s", "M,S,T", 0x540001bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ole.ps", "S,T", 0x540009bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ole.ps", "M,S,T", 0x540009bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ule.d", "S,T", 0x540005fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ule.d", "M,S,T", 0x540005fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ule.s", "S,T", 0x540001fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ule.s", "M,S,T", 0x540001fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ule.ps", "S,T", 0x540009fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ule.ps", "M,S,T", 0x540009fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.sf.d", "S,T", 0x5400063c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.sf.d", "M,S,T", 0x5400063c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.sf.s", "S,T", 0x5400023c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.sf.s", "M,S,T", 0x5400023c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.sf.ps", "S,T", 0x54000a3c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.sf.ps", "M,S,T", 0x54000a3c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngle.d", "S,T", 0x5400067c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngle.d", "M,S,T", 0x5400067c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngle.s", "S,T", 0x5400027c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ngle.s", "M,S,T", 0x5400027c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ngle.ps", "S,T", 0x54000a7c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngle.ps", "M,S,T", 0x54000a7c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.seq.d", "S,T", 0x540006bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.seq.d", "M,S,T", 0x540006bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.seq.s", "S,T", 0x540002bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.seq.s", "M,S,T", 0x540002bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.seq.ps", "S,T", 0x54000abc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.seq.ps", "M,S,T", 0x54000abc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngl.d", "S,T", 0x540006fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngl.d", "M,S,T", 0x540006fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngl.s", "S,T", 0x540002fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ngl.s", "M,S,T", 0x540002fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ngl.ps", "S,T", 0x54000afc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngl.ps", "M,S,T", 0x54000afc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.lt.d", "S,T", 0x5400073c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.lt.d", "M,S,T", 0x5400073c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.lt.s", "S,T", 0x5400033c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.lt.s", "M,S,T", 0x5400033c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.lt.ps", "S,T", 0x54000b3c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.lt.ps", "M,S,T", 0x54000b3c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.nge.d", "S,T", 0x5400077c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.nge.d", "M,S,T", 0x5400077c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.nge.s", "S,T", 0x5400037c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.nge.s", "M,S,T", 0x5400037c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.nge.ps", "S,T", 0x54000b7c, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.nge.ps", "M,S,T", 0x54000b7c, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.le.d", "S,T", 0x540007bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.le.d", "M,S,T", 0x540007bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.le.s", "S,T", 0x540003bc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.le.s", "M,S,T", 0x540003bc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.le.ps", "S,T", 0x54000bbc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.le.ps", "M,S,T", 0x54000bbc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngt.d", "S,T", 0x540007fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngt.d", "M,S,T", 0x540007fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngt.s", "S,T", 0x540003fc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ngt.s", "M,S,T", 0x540003fc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_S, 0, I1, 0, I37 },
+{"c.ngt.ps", "S,T", 0x54000bfc, 0xfc00ffff, RD_1|RD_2|WR_CC|FP_D, 0, I1, 0, I37 },
+{"c.ngt.ps", "M,S,T", 0x54000bfc, 0xfc001fff, RD_2|RD_3|WR_CC|FP_D, 0, I1, 0, I37 },
+{"cache", "k,~(b)", 0x20006000, 0xfc00f000, RD_3, 0, I1, 0, I37 },
+{"cache", "k,+j(b)", 0x20006000, 0xfc00fe00, RD_3, 0, I37, 0, 0 },
{"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I1, 0, 0 },
{"ceil.l.d", "T,S", 0x5400533b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"ceil.w.d", "T,S", 0x54005b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"ceil.w.s", "T,S", 0x54001b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
-{"cfc1", "t,g", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 },
+{"cfc1", "t,G", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 },
{"cfc1", "t,S", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 },
-{"cfc2", "t,g", 0x0000cd3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
-{"cftc1", "s,y", 0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
+{"cfc2", "t,G", 0x0000cd3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
+{"cftc1", "s,x", 0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
{"cftc1", "s,T", 0x0000043e, 0xfc00ffff, WR_1|RD_C1|TRAP|LC, AL, 0, MT32, 0 },
-{"cftc2", "s,y", 0x0000045e, 0xfc00ffff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, 0 },
+{"cftc2", "s,x", 0x0000045e, 0xfc00ffff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, 0 },
{"clo", "t,s", 0x00004b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 },
{"clz", "t,s", 0x00005b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 },
{"cop2", "C", 0x00000002, 0xfc000007, CP, 0, I1, 0, 0 },
-{"ctc1", "t,g", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 },
+{"ctc1", "t,G", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 },
{"ctc1", "t,S", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 },
-{"ctc2", "t,g", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
-{"cttc1", "t,g", 0x00000436, 0xfc00ffff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
+{"ctc2", "t,G", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
+{"cttc1", "t,G", 0x00000436, 0xfc00ffff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
{"cttc1", "t,S", 0x00000436, 0xfc00ffff, RD_1|WR_CC|TRAP|CM, AL, 0, MT32, 0 },
{"cttc2", "t,G", 0x00000456, 0xfc00ffff, WR_1|RD_C2|TRAP|LC, AL, 0, MT32, 0 },
{"cvt.d.l", "T,S", 0x5400537b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
@@ -587,12 +683,12 @@ const struct mips_opcode micromips_opcodes[] =
{"cvt.s.pu", "T,S", 0x5400293b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"cvt.w.d", "T,S", 0x5400493b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"cvt.w.s", "T,S", 0x5400093b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
-{"cvt.ps.s", "D,V,T", 0x54000180, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S|FP_D, 0, I1, 0, 0 },
+{"cvt.ps.s", "D,V,T", 0x54000180, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S|FP_D, 0, I1, 0, I37 },
{"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3, 0, 0 },
{"dadd", "d,v,t", 0x58000110, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
-{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 },
-{"daddi", "t,r,.", 0x5800001c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 },
-{"daddi", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, 0 },
+{"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, I69 },
+{"daddi", "t,r,.", 0x5800001c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, I69 },
+{"daddi", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3, 0, I69 },
{"daddiu", "t,r,j", 0x5c000000, 0xfc000000, WR_1|RD_2, 0, I3, 0, 0 },
{"daddu", "d,v,t", 0x58000150, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
@@ -605,15 +701,17 @@ const struct mips_opcode micromips_opcodes[] =
{"dextm", "t,r,+A,+G", 0x58000024, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 },
{"dextu", "t,r,+E,+H", 0x58000014, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 },
/* For ddiv, see the comments about div. */
-{"ddiv", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 },
-{"ddiv", "z,t", 0x5800ab3c, 0xfc1fffff, RD_2|WR_HILO, 0, I3, 0, 0 },
-{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, 0 },
-{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, 0 },
+{"ddiv", "d,+t,+s", 0x58000118, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
+{"ddiv", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, I69 },
+{"ddiv", "z,t", 0x5800ab3c, 0xfc1fffff, RD_2|WR_HILO, 0, I3, 0, I69 },
+{"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3, 0, I69 },
+{"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3, 0, I69 },
/* For ddivu, see the comments about div. */
-{"ddivu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 },
-{"ddivu", "z,t", 0x5800bb3c, 0xfc1fffff, RD_2|WR_HILO, 0, I3, 0, 0 },
-{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, 0 },
-{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, 0 },
+{"ddivu", "d,+t,+s", 0x58000198, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
+{"ddivu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, I69 },
+{"ddivu", "z,t", 0x5800bb3c, 0xfc1fffff, RD_2|WR_HILO, 0, I3, 0, I69 },
+{"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3, 0, I69 },
+{"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3, 0, I69 },
{"di", "", 0x0000477c, 0xffffffff, RD_C0, 0, I1, 0, 0 },
{"di", "s", 0x0000477c, 0xffe0ffff, WR_1|RD_C0, 0, I1, 0, 0 },
{"dins", "t,r,+A,+B", 0x5800000c, 0xfc00003f, WR_1|RD_2, 0, I3, 0, 0 },
@@ -625,17 +723,19 @@ const struct mips_opcode micromips_opcodes[] =
though the first operand appeared twice (the first operand is both
a source and a destination). To get the div machine instruction,
you must use an explicit destination of $0. */
-{"div", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 },
-{"div", "z,t", 0x0000ab3c, 0xfc1fffff, RD_2|WR_HILO, 0, I1, 0, 0 },
-{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, 0 },
-{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, 0 },
+{"div", "d,v,t", 0x00000118, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 },
+{"div", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 },
+{"div", "z,t", 0x0000ab3c, 0xfc1fffff, RD_2|WR_HILO, 0, I1, 0, I37 },
+{"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1, 0, I37 },
+{"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1, 0, I37 },
{"div.d", "D,V,T", 0x540001f0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
{"div.s", "D,V,T", 0x540000f0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 },
/* For divu, see the comments about div. */
-{"divu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 },
-{"divu", "z,t", 0x0000bb3c, 0xfc1fffff, RD_2|WR_HILO, 0, I1, 0, 0 },
-{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, 0 },
-{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, 0 },
+{"divu", "d,v,t", 0x00000198, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0},
+{"divu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 },
+{"divu", "z,t", 0x0000bb3c, 0xfc1fffff, RD_2|WR_HILO, 0, I1, 0, I37 },
+{"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1, 0, I37 },
+{"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1, 0, I37 },
{"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3, 0, 0 },
{"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3, 0, 0 },
{"dli", "t,j", 0x30000000, 0xfc1f0000, WR_1, 0, I3, 0, 0 }, /* addiu */
@@ -659,22 +759,28 @@ const struct mips_opcode micromips_opcodes[] =
/*{"dmtc2", "t,G,H", 0x58000683, 0xfc001fff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 },*/
{"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 },
{"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 },
-{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, 0 },
-{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, 0 },
-{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, 0 },
-{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, 0 },
-{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, 0 },
-{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, 0 },
-{"dmult", "s,t", 0x58008b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, 0 },
-{"dmultu", "s,t", 0x58009b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, 0 },
+{"dmod", "d,s,t", 0x58000158, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
+{"dmodu", "d,s,t", 0x580001d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
+{"dmuh", "d,s,t", 0x58000058, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
+{"dmuhu", "d,s,t", 0x580000d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
+{"dmul", "d,s,t", 0x58000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
+{"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3, 0, I69 },
+{"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3, 0, I69 },
+{"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3, 0, I69 },
+{"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3, 0, I69 },
+{"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3, 0, I69 },
+{"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3, 0, I69 },
+{"dmult", "s,t", 0x58008b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, I69 },
+{"dmultu", "s,t", 0x58009b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I3, 0, I69 },
+{"dmulu", "d,s,t", 0x58000098, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
{"dneg", "d,w", 0x58000190, 0xfc1f07ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsub 0 */
{"dnegu", "d,w", 0x580001d0, 0xfc1f07ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsubu 0 */
-{"drem", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 },
-{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, 0 },
-{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, 0 },
-{"dremu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, 0 },
-{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, 0 },
-{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, 0 },
+{"drem", "z,s,t", 0x5800ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, I69 },
+{"drem", "d,v,t", 0, (int) M_DREM_3, INSN_MACRO, 0, I3, 0, I69 },
+{"drem", "d,v,I", 0, (int) M_DREM_3I, INSN_MACRO, 0, I3, 0, I69 },
+{"dremu", "z,s,t", 0x5800bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I3, 0, I69 },
+{"dremu", "d,v,t", 0, (int) M_DREMU_3, INSN_MACRO, 0, I3, 0, I69 },
+{"dremu", "d,v,I", 0, (int) M_DREMU_3I, INSN_MACRO, 0, I3, 0, I69 },
{"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3, 0, 0 },
{"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3, 0, 0 },
{"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3, 0, 0 },
@@ -706,9 +812,10 @@ const struct mips_opcode micromips_opcodes[] =
{"dsrl", "t,r,>", 0x58000048, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 }, /* dsrl32 */
{"dsrl", "t,r,<", 0x58000040, 0xfc0007ff, WR_1|RD_2, 0, I3, 0, 0 },
{"dsub", "d,v,t", 0x58000190, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
-{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, 0 },
+{"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3, 0, I69 },
{"dsubu", "d,v,t", 0x580001d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3, 0, 0 },
+{"dvp", "s", 0x41600024, 0xffe0ffff, WR_1|NODS, 0, I37, 0, 0 },
{"dvpe", "", 0x0000157c, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"dvpe", "t", 0x0000157c, 0xfc1fffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"ei", "", 0x0000577c, 0xffffffff, WR_C0, 0, I1, 0, 0 },
@@ -720,6 +827,7 @@ const struct mips_opcode micromips_opcodes[] =
{"evpe", "", 0x0000357c, 0xffffffff, TRAP, 0, 0, MT32, 0 },
{"evpe", "t", 0x0000357c, 0xfc1fffff, WR_1|TRAP, 0, 0, MT32, 0 },
{"ext", "t,r,+A,+C", 0x0000002c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 },
+{"evp", "s", 0x41600004, 0xffe0ffff, WR_1|NODS, 0, I37, 0, 0 },
{"floor.l.d", "T,V", 0x5400433b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"floor.l.s", "T,V", 0x5400033b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"floor.w.d", "T,V", 0x54004b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
@@ -729,42 +837,74 @@ const struct mips_opcode micromips_opcodes[] =
{"hypcall", "+J", 0x0000c37c, 0xfc00ffff, TRAP, 0, 0, IVIRT, 0 },
{"ins", "t,r,+A,+B", 0x0000000c, 0xfc00003f, WR_1|RD_2, 0, I1, 0, 0 },
{"iret", "", 0x0000d37c, 0xffffffff, NODS, 0, 0, MC, 0 },
-{"jr", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 },
-{"jr", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr */
-{"jrs", "s", 0x00004f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs */
-{"jraddiusp", "mP", 0x4700, 0xffe0, NODS, WR_sp|RD_31|RD_sp|UBR, I1, 0, 0 },
+{"jr", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, I37 },
+{"jr", "mp", 0x4403, 0xfc1f, RD_1, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jrc16 */
+{"jr", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, I37 }, /* jalr */
+{"jr", "s", 0x80000000, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jic */
+{"jrs", "s", 0x00004f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, I37 }, /* jalrs */
+{"jrcaddiusp", "+P", 0x4413, 0xfc1f, 0, WR_sp|RD_31|RD_sp|UBR, I37, 0, 0 },
+{"jrcaddiusp", "mP", 0, (int) M_JRADDIUSP, INSN_MACRO, 0, I37, 0, 0 },
+{"jraddiusp", "mP", 0x4700, 0xffe0, NODS, WR_sp|RD_31|RD_sp|UBR, I1, 0, I37 },
+{"jraddiusp", "+P", 0x4413, 0xfc1f, 0, INSN2_ALIAS|WR_sp|RD_31|RD_sp|UBR, I37, 0, 0 },
/* This macro is after the real instruction so that it only matches with
-minsn32. */
{"jraddiusp", "mP", 0, (int) M_JRADDIUSP, INSN_MACRO, 0, I1, 0, 0 },
-{"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jalr.hb */
-{"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, 0 }, /* jalrs.hb */
-{"j", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, 0 }, /* jr */
-{"j", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, 0 }, /* jr */
+{"jrc.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1, UBR, I37, 0, 0 }, /* jalrc.hb */
+{"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, I37 }, /* jalr.hb */
+{"jr.hb", "s", 0x00001f3c, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jalrc.hb */
+{"jrs.hb", "s", 0x00005f3c, 0xffe0ffff, RD_1|UBD, BD16, I1, 0, I37 }, /* jalrs.hb */
+{"j", "mj", 0x4580, 0xffe0, RD_1|UBD, 0, I1, 0, I37 }, /* jr */
+{"j", "mp", 0x4403, 0xfc1f, RD_1, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jrc16 */
+{"j", "+'", 0x94000000, 0xfc000000, 0, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* bc */
+{"j", "s", 0x00000f3c, 0xffe0ffff, RD_1|UBD, BD32, I1, 0, I37 }, /* jr */
+{"j", "s", 0x80000000, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jic */
/* SVR4 PIC code requires special handling for j, so it must be a
macro. */
-{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1, 0, 0 },
+{"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1, 0, I37 },
/* This form of j is used by the disassembler and internally by the
assembler, but will never match user input (because the line above
will match first). */
-{"j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1, 0, 0 },
+{"j", "a", 0xd4000000, 0xfc000000, UBD, 0, I1, 0, I37 },
/* JRC is close to JR and J so that we easily find it when converting
a normal jump to a compact one. */
-{"jrc", "mj", 0x45a0, 0xffe0, RD_1|NODS, UBR, I1, 0, 0 },
+{"jrc", "mj", 0x45a0, 0xffe0, RD_1|NODS, UBR, I1, 0, I37 },
+{"jrc", "mp", 0x4403, 0xfc1f, RD_1, UBR, I37, 0, 0 },
+{"jrc", "s", 0x80000000, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR, I37, 0, 0 }, /* jic */
+{"jrc", "s", 0x00000f3c, 0xffe0ffff, RD_1, INSN2_ALIAS|UBR, I37, 0, 0 }, /* jalrc */
/* This macro is after the real instruction so that it only matches with
-minsn32. */
-{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1, 0, 0 },
-{"jalr", "mj", 0x45c0, 0xffe0, RD_1|WR_31|UBD, BD32, I1, 0, 0 },
-{"jalr", "my,mj", 0x45c0, 0xffe0, RD_2|WR_31|UBD, BD32, I1, 0, 0 },
-{"jalr", "s", 0x03e00f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, 0 },
-{"jalr", "t,s", 0x00000f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD32, I1, 0, 0 },
-{"jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, 0 },
-{"jalr.hb", "t,s", 0x00001f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD32, I1, 0, 0 },
-{"jalrs", "mj", 0x45e0, 0xffe0, RD_1|WR_31|UBD, BD16, I1, 0, 0 },
-{"jalrs", "my,mj", 0x45e0, 0xffe0, RD_2|WR_31|UBD, BD16, I1, 0, 0 },
-{"jalrs", "s", 0x03e04f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD16, I1, 0, 0 },
-{"jalrs", "t,s", 0x00004f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD16, I1, 0, 0 },
-{"jalrs.hb", "s", 0x03e05f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD16, I1, 0, 0 },
-{"jalrs.hb", "t,s", 0x00005f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD16, I1, 0, 0 },
+{"jrc", "s", 0, (int) M_JRC, INSN_MACRO, 0, I1, 0, I37 },
+
+{"jalr", "mj", 0x45c0, 0xffe0, RD_1|WR_31|UBD, BD32, I1, 0, I37 },
+{"jalr", "my,mj", 0x45c0, 0xffe0, RD_2|WR_31|UBD, BD32, I1, 0, I37 },
+{"jalr", "mp", 0x440b, 0xfc1f, RD_1|WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 },
+{"jalr", "my,mp", 0x440b, 0xfc1f, RD_2|WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 },
+{"jalr", "s", 0x03e00f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, I37 },
+{"jalr", "t,s", 0x00000f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD32, I1, 0, I37 },
+{"jalr", "s", 0x03e00f3c, 0xffe0ffff, RD_1|WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 },
+{"jalr", "t,s", 0x00000f3c, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS|UBR|CTC, I37, 0, 0 },
+{"jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, RD_1|WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 },
+{"jalr.hb", "t,s", 0x00001f3c, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS|UBR|CTC, I37, 0, 0 },
+{"jalr.hb", "s", 0x03e01f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD32, I1, 0, I37 },
+{"jalr.hb", "t,s", 0x00001f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD32, I1, 0, I37 },
+{"jalrc", "mp", 0x440b, 0xfc1f, RD_1|WR_31, UBR, I37, 0, 0 },
+{"jalrc", "my,mp", 0x440b, 0xfc1f, RD_2|WR_31, UBR, I37, 0, 0 },
+{"jalrc", "s", 0x03e00f3c, 0xffe0ffff, RD_1|WR_31, UBR, I37, 0, 0 },
+{"jalrc", "t,s", 0x00000f3c, 0xfc00ffff, WR_1|RD_2, UBR, I37, 0, 0 },
+{"jalrc.hb", "s", 0x03e01f3c, 0xffe0ffff, RD_1|WR_31, UBR, I37, 0, 0 },
+{"jalrc.hb", "t,s", 0x00001f3c, 0xfc00ffff, WR_1|RD_2, UBR, I37, 0, 0 },
+{"jalrs", "mp", 0x440b, 0xfc1f, RD_1|WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jalrc */
+{"jalrs", "my,mp", 0x440b, 0xfc1f, RD_2|WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jalrc */
+{"jalrs", "s", 0x03e00f3c, 0xffe0ffff, RD_1|WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jalrc */
+{"jalrs", "t,s", 0x00000f3c, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jalrc */
+{"jalrs", "mj", 0x45e0, 0xffe0, RD_1|WR_31|UBD, BD16, I1, 0, I37 },
+{"jalrs", "my,mj", 0x45e0, 0xffe0, RD_2|WR_31|UBD, BD16, I1, 0, I37 },
+{"jalrs", "s", 0x03e04f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD16, I1, 0, I37 },
+{"jalrs", "t,s", 0x00004f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD16, I1, 0, I37 },
+{"jalrs.hb", "s", 0x03e01f3c, 0xffe0ffff, RD_1|WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jalrc.hb */
+{"jalrs.hb", "t,s", 0x00001f3c, 0xfc00ffff, WR_1|RD_2, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* jalrc.hb */
+{"jalrs.hb", "s", 0x03e05f3c, 0xffe0ffff, RD_1|WR_31|UBD, BD16, I1, 0, I37 },
+{"jalrs.hb", "t,s", 0x00005f3c, 0xfc00ffff, WR_1|RD_2|UBD, BD16, I1, 0, I37 },
/* SVR4 PIC code requires special handling for jal, so it must be a
macro. */
{"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1, 0, 0 },
@@ -773,12 +913,14 @@ const struct mips_opcode micromips_opcodes[] =
/* This form of jal is used by the disassembler and internally by the
assembler, but will never match user input (because the line above
will match first). */
-{"jal", "a", 0xf4000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, 0 },
-{"jals", "d,s", 0, (int) M_JALS_2, INSN_MACRO, 0, I1, 0, 0 },
-{"jals", "s", 0, (int) M_JALS_1, INSN_MACRO, 0, I1, 0, 0 },
-{"jals", "a", 0, (int) M_JALS_A, INSN_MACRO, 0, I1, 0, 0 },
-{"jals", "a", 0x74000000, 0xfc000000, WR_31|UBD, BD16, I1, 0, 0 },
-{"jalx", "+i", 0xf0000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, 0 },
+{"jal", "+'", 0xb4000000, 0xfc000000, WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* balc */
+{"jal", "a", 0xf4000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, I37 },
+{"jals", "d,s", 0, (int) M_JALS_2, INSN_MACRO, 0, I1, 0, I37 },
+{"jals", "s", 0, (int) M_JALS_1, INSN_MACRO, 0, I1, 0, I37 },
+{"jals", "a", 0, (int) M_JALS_A, INSN_MACRO, 0, I1, 0, I37 },
+{"jals", "a", 0x74000000, 0xfc000000, WR_31|UBD, BD16, I1, 0, I37 },
+{"jals", "+'", 0xb4000000, 0xfc000000, WR_31, INSN2_ALIAS|UBR|CTC, I37, 0, 0 }, /* balc */
+{"jalx", "+i", 0xf0000000, 0xfc000000, WR_31|UBD, BD32, I1, 0, I37 },
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lb", "t,o(b)", 0x1c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1, 0, 0 },
@@ -787,25 +929,28 @@ const struct mips_opcode micromips_opcodes[] =
{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1, 0, 0 },
/* The macro has to be first to handle o32 correctly. */
+{"ldpc", "t,-B", 0x78180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
+{"ld", "t,-b(mr)", 0x78180000, 0xfc1c0000, WR_1, RD_pc, I69, 0, 0 },
{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1, 0, 0 },
{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_1|RD_3|LM, 0, I3, 0, 0 },
{"ldc1", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 },
{"ldc1", "E,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 },
{"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
-{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, 0 },
+{"ldc2", "E,~(b)", 0x20002000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, I37 },
+{"ldc2", "E,+:(b)", 0x20002000, 0xfc00f800, RD_3|WR_CC|LM, 0, I37, 0, 0 },
{"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I1, 0, 0 },
{"l.d", "T,o(b)", 0xbc000000, 0xfc000000, WR_1|RD_3|FP_D|LM, 0, I1, 0, 0 }, /* ldc1 */
{"l.d", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
-{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 },
-{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, 0 },
+{"ldl", "t,~(b)", 0x60004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, I69 },
+{"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3, 0, I69 },
{"ldm", "n,~(b)", 0x20007000, 0xfc00f000, RD_3|LM, 0, I3, 0, 0 },
{"ldm", "n,A(b)", 0, (int) M_LDM_AB, INSN_MACRO, 0, I3, 0, 0 },
{"ldp", "t,~(b)", 0x20004000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 },
{"ldp", "t,A(b)", 0, (int) M_LDP_AB, INSN_MACRO, 0, I3, 0, 0 },
-{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 },
-{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, 0 },
-{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, 0 },
+{"ldr", "t,~(b)", 0x60005000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, I69 },
+{"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3, 0, I69 },
+{"ldxc1", "D,t(b)", 0x540000c8, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, I37 },
{"lh", "t,o(b)", 0x3c000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lhu", "md,mH(ml)", 0x2800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 },
@@ -816,48 +961,62 @@ const struct mips_opcode micromips_opcodes[] =
{"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
-{"ll", "t,~(b)", 0x60003000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 },
+{"ll", "t,~(b)", 0x60003000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, I37 },
+{"ll", "t,+j(b)", 0x60003000, 0xfc00fe00, WR_1|RD_3|LM, 0, I37, 0, 0 },
{"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"lld", "t,~(b)", 0x60007000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 },
+{"llwp", "t,-p,s", 0x60001000, 0xfc00fe0f, WR_1|WR_2|RD_3|LM, 0, I37, 0, 0 },
+{"llwp", "t,-p,A(b)", 0, (int) M_LLWP_AB, INSN_MACRO, 0, I37, 0, 0 },
+{"lld", "t,~(b)", 0x60007000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, I69 },
+{"lld", "t,+j(b)", 0x60007000, 0xfc00fe00, WR_1|RD_3|LM, 0, I69, 0, 0 },
{"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3, 0, 0 },
-{"lui", "s,u", 0x41a00000, 0xffe00000, WR_1, 0, I1, 0, 0 },
-{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, 0 },
+{"lldp", "t,-p,s", 0x60005000, 0xfc00fe0f, WR_1|WR_2|RD_3|LM, 0, I69, 0, 0 },
+{"lldp", "t,-p,A(b)", 0, (int) M_LLDP_AB, INSN_MACRO, 0, I69, 0, 0 },
+{"lui", "t,u", 0x10000000, 0xfc1f0000, WR_1, 0, I37, 0, 0 },
+{"lui", "s,u", 0x41a00000, 0xffe00000, WR_1, 0, I1, 0, I37 },
+{"luxc1", "D,t(b)", 0x54000148, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D|LM, 0, I1, 0, I37 },
+{"lwpc", "t,-A", 0x78080000, 0xfc180000, WR_1|LM, RD_pc, I37, 0, 0 },
{"lw", "md,mJ(ml)", 0x6800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lw", "mp,mU(ms)", 0x4800, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* lwsp */
{"lw", "md,mA(ma)", 0x6400, 0xfc00, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* lwgp */
+{"lw", "t,-a(mr)", 0x78080000, 0xfc180000, WR_1|LM, RD_pc, I37, 0, 0 },
{"lw", "t,o(b)", 0xfc000000, 0xfc000000, WR_1|RD_3|LM, 0, I1, 0, 0 },
{"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lwc1", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 },
{"lwc1", "E,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 },
{"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
-{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, 0 },
+{"lwc2", "E,~(b)", 0x20000000, 0xfc00f000, RD_3|WR_CC|LM, 0, I1, 0, I37 },
+{"lwc2", "E,+:(b)", 0x20000000, 0xfc00f800, RD_3|WR_CC|LM, 0, I37, 0, 0 },
{"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1, 0, 0 },
{"l.s", "T,o(b)", 0x9c000000, 0xfc000000, WR_1|RD_3|FP_S|LM, 0, I1, 0, 0 }, /* lwc1 */
{"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
-{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 },
-{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 }, /* same */
-{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, RD_3|NODS|LM, 0, I1, 0, 0 },
+{"lwl", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, I37 },
+{"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"lcache", "t,~(b)", 0x60000000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, I37 }, /* same */
+{"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"lwm", "+N,+L(ms)", 0x4402, 0xfc0f, RD_3|LM, 0, I37, 0, 0 },
+{"lwm", "mN,mJ(ms)", 0x4500, 0xffc0, RD_3|NODS|LM, 0, I1, 0, I37 },
{"lwm", "n,~(b)", 0x20005000, 0xfc00f000, RD_3|NODS|LM, 0, I1, 0, 0 },
{"lwm", "n,A(b)", 0, (int) M_LWM_AB, INSN_MACRO, 0, I1, 0, 0 },
{"lwp", "t,~(b)", 0x20001000, 0xfc00f000, WR_1|RD_3|NODS|LM, 0, I1, 0, 0 },
{"lwp", "t,A(b)", 0, (int) M_LWP_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, 0 },
-{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 },
+{"lwr", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3|LM, 0, I1, 0, I37 },
+{"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"lwupc", "t,-A", 0x78100000, 0xfc180000, WR_1|LM, RD_pc, I69, 0, 0 },
{"lwu", "t,~(b)", 0x6000e000, 0xfc00f000, WR_1|RD_3|LM, 0, I3, 0, 0 },
+{"lwu" , "t,-a(mr)", 0x78100000, 0xfc180000, WR_1|RD_pc, 0, I69, 0, 0 },
{"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3, 0, 0 },
-{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S|LM, 0, I1, 0, 0 },
-{"flush", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, 0 }, /* same */
-{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, I1, 0, 0 },
-{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 },
+{"lwxc1", "D,t(b)", 0x54000048, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S|LM, 0, I1, 0, I37 },
+{"flush", "t,~(b)", 0x60001000, 0xfc00f000, WR_1|RD_3, 0, I1, 0, I37 }, /* same */
+{"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"lwxs", "d,t(b)", 0x00000100, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, I37, 0, 0 },
+{"lwxs", "d,t(b)", 0x00000118, 0xfc0007ff, WR_1|RD_2|RD_3|LM, 0, I1, 0, I37 },
+{"madd", "s,t", 0x0000cb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, I37 },
{"madd", "7,s,t", 0x00000abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 },
-{"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
-{"madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 },
-{"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
-{"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 },
+{"madd.d", "D,R,S,T", 0x54000009, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, I37 },
+{"madd.s", "D,R,S,T", 0x54000001, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, I37 },
+{"madd.ps", "D,R,S,T", 0x54000011, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, I37 },
+{"maddu", "s,t", 0x0000db3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, I37 },
{"maddu", "7,s,t", 0x00001abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 },
{"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_1|RD_C0, 0, I1, 0, 0 },
{"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I1, 0, 0 },
@@ -873,11 +1032,11 @@ const struct mips_opcode micromips_opcodes[] =
{"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 },
{"mfhgc0", "t,G", 0x000004f4, 0xfc00ffff, WR_1|RD_C0, 0, 0, XPAVZ, 0 },
{"mfhgc0", "t,G,H", 0x000004f4, 0xfc00c7ff, WR_1|RD_C0, 0, 0, XPAVZ, 0 },
-{"mfhi", "mj", 0x4600, 0xffe0, WR_1|RD_HI, 0, I1, 0, 0 },
-{"mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_1|RD_HI, 0, I1, 0, 0 },
+{"mfhi", "mj", 0x4600, 0xffe0, WR_1|RD_HI, 0, I1, 0, I37 },
+{"mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_1|RD_HI, 0, I1, 0, I37 },
{"mfhi", "s,7", 0x0000007c, 0xffe03fff, WR_1|RD_HI, 0, 0, D32, 0 },
-{"mflo", "mj", 0x4640, 0xffe0, WR_1|RD_LO, 0, I1, 0, 0 },
-{"mflo", "s", 0x00001d7c, 0xffe0ffff, WR_1|RD_LO, 0, I1, 0, 0 },
+{"mflo", "mj", 0x4640, 0xffe0, WR_1|RD_LO, 0, I1, 0, I37 },
+{"mflo", "s", 0x00001d7c, 0xffe0ffff, WR_1|RD_LO, 0, I1, 0, I37 },
{"mflo", "s,7", 0x0000107c, 0xffe03fff, WR_1|RD_LO, 0, 0, D32, 0 },
{"mftacx", "s", 0x0040041e, 0xffe0ffff, WR_1|RD_a|TRAP, AL, 0, MT32, 0 },
{"mftacx", "s,*", 0x0040041e, 0xfe60ffff, WR_1|RD_a|TRAP, AL, 0, MT32, 0 },
@@ -896,35 +1055,38 @@ const struct mips_opcode micromips_opcodes[] =
{"mftlo", "s", 0x0000041e, 0xffe0ffff, WR_1|RD_a|TRAP, AL, 0, MT32, 0 },
{"mftlo", "s,*", 0x0000041e, 0xfe60ffff, WR_1|RD_a|TRAP, AL, 0, MT32, 0 },
{"mftr", "s,E,!,J,$", 0x0000000e, 0xfc00f98f, WR_1|TRAP, 0, 0, MT32, 0 },
+{"mod", "d,v,t", 0x00000158, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0},
+{"modu", "d,v,t", 0x000001d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0},
{"mov.d", "T,S", 0x5400207b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"mov.s", "T,S", 0x5400007b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
-{"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
-{"movep", "mh,mm,mn", 0x8400, 0xfc01, WR_1|RD_2|RD_3|NODS, 0, I1, 0, 0 },
+{"mov.ps", "T,S", 0x5400407b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, I37 },
+{"movep", "mh,-m,mn", 0x4404, 0xfc04, WR_1|RD_2|RD_3|NODS, 0, I37, 0, 0 },
+{"movep", "mh,mm,mn", 0x8400, 0xfc01, WR_1|RD_2|RD_3|NODS, 0, I1, 0, I37 },
/* This macro is after the real instruction so that it only matches with
-minsn32. */
{"movep", "mh,mm,mn", 0, (int) M_MOVEP, INSN_MACRO, 0, I1, 0, 0 },
-{"movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I1, 0, 0 },
-{"movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 },
-{"movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S, 0, I1, 0, 0 },
-{"movf.ps", "T,S,M", 0x54000420, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 },
-{"movn", "d,v,t", 0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
-{"movn.d", "D,S,t", 0x54000138, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
-{"movn.s", "D,S,t", 0x54000038, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 },
-{"movn.ps", "D,S,t", 0x54000238, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
-{"movt", "t,s,M", 0x5400097b, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I1, 0, 0 },
-{"movt.d", "T,S,M", 0x54000260, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 },
-{"movt.s", "T,S,M", 0x54000060, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S, 0, I1, 0, 0 },
-{"movt.ps", "T,S,M", 0x54000460, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, 0 },
-{"movz", "d,v,t", 0x00000058, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
-{"movz.d", "D,S,t", 0x54000178, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
-{"movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 },
-{"movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
-{"msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 },
+{"movf", "t,s,M", 0x5400017b, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I1, 0, I37 },
+{"movf.d", "T,S,M", 0x54000220, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, I37 },
+{"movf.s", "T,S,M", 0x54000020, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S, 0, I1, 0, I37 },
+{"movf.ps", "T,S,M", 0x54000420, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, I37 },
+{"movn", "d,v,t", 0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, I37 },
+{"movn.d", "D,S,t", 0x54000138, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
+{"movn.s", "D,S,t", 0x54000038, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, I37 },
+{"movn.ps", "D,S,t", 0x54000238, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
+{"movt", "t,s,M", 0x5400097b, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S|FP_D, 0, I1, 0, I37 },
+{"movt.d", "T,S,M", 0x54000260, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, I37 },
+{"movt.s", "T,S,M", 0x54000060, 0xfc001fff, WR_1|RD_2|RD_CC|FP_S, 0, I1, 0, I37 },
+{"movt.ps", "T,S,M", 0x54000460, 0xfc001fff, WR_1|RD_2|RD_CC|FP_D, 0, I1, 0, I37 },
+{"movz", "d,v,t", 0x00000058, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, I37 },
+{"movz.d", "D,S,t", 0x54000178, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
+{"movz.s", "D,S,t", 0x54000078, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, I37 },
+{"movz.ps", "D,S,t", 0x54000278, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
+{"msub", "s,t", 0x0000eb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, I37 },
{"msub", "7,s,t", 0x00002abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 },
-{"msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
-{"msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 },
-{"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
-{"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, 0 },
+{"msub.d", "D,R,S,T", 0x54000029, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, I37 },
+{"msub.s", "D,R,S,T", 0x54000021, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, I37 },
+{"msub.ps", "D,R,S,T", 0x54000031, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, I37 },
+{"msubu", "s,t", 0x0000fb3c, 0xfc00ffff, RD_1|RD_2|MOD_HILO, 0, I1, 0, I37 },
{"msubu", "7,s,t", 0x00003abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 },
{"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 },
{"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 },
@@ -940,9 +1102,9 @@ const struct mips_opcode micromips_opcodes[] =
{"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 },
{"mthgc0", "t,G", 0x000006f4, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 },
{"mthgc0", "t,G,H", 0x000006f4, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, XPAVZ, 0 },
-{"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_1|WR_HI, 0, I1, 0, 0 },
+{"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_1|WR_HI, 0, I1, 0, I37 },
{"mthi", "s,7", 0x0000207c, 0xffe03fff, RD_1|WR_HI, 0, 0, D32, 0 },
-{"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_1|WR_LO, 0, I1, 0, 0 },
+{"mtlo", "s", 0x00003d7c, 0xffe0ffff, RD_1|WR_LO, 0, I1, 0, I37 },
{"mtlo", "s,7", 0x0000307c, 0xffe03fff, RD_1|WR_LO, 0, 0, D32, 0 },
{"mttacx", "t", 0x00020416, 0xfc1fffff, RD_1|WR_a|TRAP, AL, 0, MT32, 0 },
{"mttacx", "t,&", 0x00020416, 0xfc13ffff, RD_1|WR_a|TRAP, AL, 0, MT32, 0 },
@@ -961,59 +1123,70 @@ const struct mips_opcode micromips_opcodes[] =
{"mttlo", "t", 0x00000416, 0xfc1fffff, RD_1|WR_a|TRAP, AL, 0, MT32, 0 },
{"mttlo", "t,&", 0x00000416, 0xfc13ffff, RD_1|WR_a|TRAP, AL, 0, MT32, 0 },
{"mttr", "t,G,!,J,$", 0x00000006, 0xfc00f98f, RD_1|TRAP, 0, 0, MT32, 0 },
-{"mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, I1, 0, 0 },
-{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1, 0, 0 },
+{"muh", "d,v,t", 0x00000058, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 },
+{"muhu", "d,v,t", 0x000000d8, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0},
+{"mul", "d,v,t", 0x00000018, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 },
+{"mul", "d,v,t", 0x00000210, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO, 0, I1, 0, I37 },
+{"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1, 0, I37 },
{"mul.d", "D,V,T", 0x540001b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
{"mul.s", "D,V,T", 0x540000b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 },
-{"mul.ps", "D,V,T", 0x540002b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
-{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1, 0, 0 },
-{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1, 0, 0 },
-{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1, 0, 0 },
-{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1, 0, 0 },
-{"mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I1, 0, 0 },
+{"mul.ps", "D,V,T", 0x540002b0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
+{"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1, 0, I37 },
+{"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1, 0, I37 },
+{"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1, 0, I37 },
+{"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1, 0, I37 },
+{"mult", "s,t", 0x00008b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I1, 0, I37 },
{"mult", "7,s,t", 0x00000cbc, 0xfc003fff, RD_2|RD_3|WR_a, 0, 0, D32, 0 },
-{"multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I1, 0, 0 },
+{"multu", "s,t", 0x00009b3c, 0xfc00ffff, RD_1|RD_2|WR_HILO, 0, I1, 0, I37 },
{"multu", "7,s,t", 0x00001cbc, 0xfc003fff, RD_2|RD_3|WR_a, 0, 0, D32, 0 },
+{"mulu", "d,v,t", 0x00000098, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0},
{"neg", "d,w", 0x00000190, 0xfc1f07ff, WR_1|RD_2, 0, I1, 0, 0 }, /* sub 0 */
{"negu", "d,w", 0x000001d0, 0xfc1f07ff, WR_1|RD_2, 0, I1, 0, 0 }, /* subu 0 */
{"neg.d", "T,V", 0x54002b7b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"neg.s", "T,V", 0x54000b7b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
-{"neg.ps", "T,V", 0x54004b7b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
-{"nmadd.d", "D,R,S,T", 0x5400000a, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
-{"nmadd.s", "D,R,S,T", 0x54000002, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 },
-{"nmadd.ps", "D,R,S,T", 0x54000012, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
-{"nmsub.d", "D,R,S,T", 0x5400002a, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
-{"nmsub.s", "D,R,S,T", 0x54000022, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, 0 },
-{"nmsub.ps", "D,R,S,T", 0x54000032, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, 0 },
+{"neg.ps", "T,V", 0x54004b7b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, I37 },
+{"nmadd.d", "D,R,S,T", 0x5400000a, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, I37 },
+{"nmadd.s", "D,R,S,T", 0x54000002, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, I37 },
+{"nmadd.ps", "D,R,S,T", 0x54000012, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, I37 },
+{"nmsub.d", "D,R,S,T", 0x5400002a, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, I37 },
+{"nmsub.s", "D,R,S,T", 0x54000022, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_S, 0, I1, 0, I37 },
+{"nmsub.ps", "D,R,S,T", 0x54000032, 0xfc00003f, WR_1|RD_2|RD_3|RD_4|FP_D, 0, I1, 0, I37 },
/* nop is at the start of the table. */
-{"not", "mf,mg", 0x4400, 0xffc0, WR_1|RD_2, 0, I1, 0, 0 }, /* put not before nor */
+{"not", "md,ml", 0x4400, 0xfc0f, WR_1|RD_2, 0, I37, 0, 0 }, /* put not before nor */
+{"not", "mf,mg", 0x4400, 0xffc0, WR_1|RD_2, 0, I1, 0, I37 }, /* put not before nor */
{"not", "d,v", 0x000002d0, 0xffe007ff, WR_1|RD_2, 0, I1, 0, 0 }, /* nor d,s,0 */
-{"nor", "mf,mz,mg", 0x4400, 0xffc0, WR_1|RD_3, 0, I1, 0, 0 }, /* not */
-{"nor", "mf,mg,mz", 0x4400, 0xffc0, WR_1|RD_2, 0, I1, 0, 0 }, /* not */
+{"nor", "md,mz,ml", 0x4400, 0xfc0f, WR_1|RD_3, 0, I37, 0, 0 }, /* not */
+{"nor", "md,ml,mz", 0x4400, 0xfc0f, WR_1|RD_2, 0, I37, 0, 0 }, /* not */
+{"nor", "mf,mz,mg", 0x4400, 0xffc0, WR_1|RD_3, 0, I1, 0, I37 }, /* not */
+{"nor", "mf,mg,mz", 0x4400, 0xffc0, WR_1|RD_2, 0, I1, 0, I37 }, /* not */
{"nor", "d,v,t", 0x000002d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1, 0, 0 },
{"or", "mp,mj,mz", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */
{"or", "mp,mz,mj", 0x0c00, 0xfc00, WR_1|RD_3, 0, I1, 0, 0 }, /* move */
-{"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 },
-{"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 },
+{"or", "md,mt,ml", 0x4409, 0xfc0f, MOD_1|RD_3, 0, I37, 0, 0 },
+{"or", "md,ml,mx", 0x4409, 0xfc0f, MOD_1|RD_2, 0, I37, 0, 0 },
+{"or", "mf,mt,mg", 0x44c0, 0xffc0, MOD_1|RD_3, 0, I1, 0, I37 },
+{"or", "mf,mg,mx", 0x44c0, 0xffc0, MOD_1|RD_2, 0, I1, 0, I37 },
{"or", "d,v,t", 0x00000290, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1, 0, 0 },
{"ori", "mp,mj,mZ", 0x0c00, 0xfc00, WR_1|RD_2, 0, I1, 0, 0 }, /* move */
{"ori", "t,r,i", 0x50000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
-{"pll.ps", "D,V,T", 0x54000080, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
-{"plu.ps", "D,V,T", 0x540000c0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
-{"pul.ps", "D,V,T", 0x54000100, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
-{"puu.ps", "D,V,T", 0x54000140, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
+{"pll.ps", "D,V,T", 0x54000080, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
+{"plu.ps", "D,V,T", 0x540000c0, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
+{"pul.ps", "D,V,T", 0x54000100, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
+{"puu.ps", "D,V,T", 0x54000140, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
/* pref is at the start of the table. */
{"recip.d", "T,S", 0x5400523b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"recip.s", "T,S", 0x5400123b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
-{"rem", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 },
-{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, 0 },
-{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1, 0, 0 },
-{"remu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, 0 },
-{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, 0 },
-{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, 0 },
-{"rdhwr", "t,K", 0x00006b3c, 0xfc00ffff, WR_1, 0, I1, 0, 0 },
+{"rem", "z,s,t", 0x0000ab3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 },
+{"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1, 0, I37 },
+{"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1, 0, I37 },
+{"remu", "z,s,t", 0x0000bb3c, 0xfc00ffff, RD_2|RD_3|WR_HILO, 0, I1, 0, I37 },
+{"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1, 0, I37 },
+{"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1, 0, I37 },
+{"rdhwr", "t,K", 0x00006b3c, 0xfc00ffff, WR_1, 0, I1, 0, I37 },
+{"rdhwr", "t,K", 0x000001c0, 0xfc00ffff, WR_1, 0, I37, 0, 0 },
+{"rdhwr", "t,K,H", 0x000001c0, 0xfc00c7ff, WR_1, 0, I37, 0, 0 },
{"rdpgpr", "t,r", 0x0000e17c, 0xfc00ffff, WR_1, 0, I1, 0, 0 },
{"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1, 0, 0 },
{"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1, 0, 0 },
@@ -1035,34 +1208,43 @@ const struct mips_opcode micromips_opcodes[] =
{"sb", "mq,mL(ml)", 0x8800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 },
{"sb", "t,o(b)", 0x18000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
{"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, 0 },
+{"scwp", "t,-p,s", 0x60009000, 0xfc00fe0f, MOD_1|RD_2|RD_3|SM, 0, I37, 0, 0 },
+{"scwp", "t,-p,A(b)", 0, (int) M_SCWP_AB, INSN_MACRO, 0, I37, 0, 0 },
+{"sc", "t,~(b)", 0x6000b000, 0xfc00f000, MOD_1|RD_3|SM, 0, I1, 0, I37 },
+{"sc", "t,+j(b)", 0x6000b000, 0xfc00fe00, MOD_1|RD_3|SM, 0, I37, 0, 0 },
{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"scd", "t,~(b)", 0x6000f000, 0xfc00f000, MOD_1|RD_3|SM, 0, I3, 0, 0 },
+{"scdp", "t,-p,s", 0x6000d000, 0xfc00fe0f, MOD_1|RD_2|RD_3|SM, 0, I69, 0, 0 },
+{"scdp", "t,-p,A(b)", 0, (int) M_SCDP_AB, INSN_MACRO, 0, I69, 0, 0 },
+{"scd", "t,~(b)", 0x6000f000, 0xfc00f000, MOD_1|RD_3|SM, 0, I3, 0, I69 },
+{"scd", "t,+j(b)", 0x6000f000, 0xfc00fe00, MOD_1|RD_3|SM, 0, I69, 0, 0 },
{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3, 0, 0 },
/* The macro has to be first to handle o32 correctly. */
{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1, 0, 0 },
{"sd", "t,o(b)", 0xd8000000, 0xfc000000, RD_1|RD_3|SM, 0, I3, 0, 0 },
-{"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1, 0, 0 },
+{"sdbbp", "", 0x443b, 0xffff, TRAP, 0, I37, 0, 0 },
+{"sdbbp", "", 0x46c0, 0xffff, TRAP, 0, I1, 0, I37 },
{"sdbbp", "", 0x0000db7c, 0xffffffff, TRAP, 0, I1, 0, 0 },
-{"sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1, 0, 0 },
+{"sdbbp", "+K", 0x443b, 0xfc3f, TRAP, 0, I37, 0, 0 },
+{"sdbbp", "mO", 0x46c0, 0xfff0, TRAP, 0, I1, 0, I37 },
{"sdbbp", "+J", 0x0000db7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
{"sdc1", "T,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 },
{"sdc1", "E,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 },
{"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
{"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
-{"sdc2", "E,~(b)", 0x2000a000, 0xfc00f000, RD_3|RD_C2|SM, 0, I1, 0, 0 },
+{"sdc2", "E,~(b)", 0x2000a000, 0xfc00f000, RD_3|RD_C2|SM, 0, I1, 0, I37 },
+{"sdc2", "E,+:(b)", 0x2000a000, 0xfc00f800, RD_3|RD_C2|SM, 0, I37, 0, 0 },
{"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I1, 0, 0 },
{"s.d", "T,o(b)", 0xb8000000, 0xfc000000, RD_1|RD_3|SM|FP_D, 0, I1, 0, 0 }, /* sdc1 */
{"s.d", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, INSN2_M_FP_D, I1, 0, 0 },
-{"sdl", "t,~(b)", 0x6000c000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, 0 },
-{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3, 0, 0 },
+{"sdl", "t,~(b)", 0x6000c000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, I69 },
+{"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3, 0, I69 },
{"sdm", "n,~(b)", 0x2000f000, 0xfc00f000, RD_3|SM, 0, I3, 0, 0 },
{"sdm", "n,A(b)", 0, (int) M_SDM_AB, INSN_MACRO, 0, I3, 0, 0 },
{"sdp", "t,~(b)", 0x2000c000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, 0 },
{"sdp", "t,A(b)", 0, (int) M_SDP_AB, INSN_MACRO, 0, I3, 0, 0 },
-{"sdr", "t,~(b)", 0x6000d000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, 0 },
-{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, 0 },
-{"sdxc1", "D,t(b)", 0x54000108, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I1, 0, 0 },
+{"sdr", "t,~(b)", 0x6000d000, 0xfc00f000, RD_1|RD_3|SM, 0, I3, 0, I69 },
+{"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3, 0, I69 },
+{"sdxc1", "D,t(b)", 0x54000108, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I1, 0, I37 },
{"seb", "t,r", 0x00002b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 },
{"seh", "t,r", 0x00003b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 },
{"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1, 0, 0 },
@@ -1078,6 +1260,7 @@ const struct mips_opcode micromips_opcodes[] =
{"sh", "mq,mH(ml)", 0xa800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 },
{"sh", "t,o(b)", 0x38000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
{"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1, 0, 0 },
+{"sigrie", "+M", 0x0000003f, 0xffc0003f, TRAP, 0, I37, 0, 0 },
{"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1, 0, 0 },
{"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1, 0, 0 },
{"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1, 0, 0 },
@@ -1105,14 +1288,15 @@ const struct mips_opcode micromips_opcodes[] =
{"srl", "t,r,<", 0x00000040, 0xfc0007ff, WR_1|RD_2, 0, I1, 0, 0 },
/* ssnop is at the start of the table. */
{"sub", "d,v,t", 0x00000190, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
-{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, 0 },
+{"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1, 0, I37 },
{"sub.d", "D,V,T", 0x54000170, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
{"sub.s", "D,V,T", 0x54000070, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I1, 0, 0 },
-{"sub.ps", "D,V,T", 0x54000270, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, 0 },
-{"subu", "md,me,ml", 0x0401, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
+{"sub.ps", "D,V,T", 0x54000270, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I1, 0, I37 },
+{"subu", "-d,-e,ml", 0x0401, 0xfc01, WR_1|RD_2|RD_3, 0, I37, 0, 0 },
+{"subu", "md,me,ml", 0x0401, 0xfc01, WR_1|RD_2|RD_3, 0, I1, 0, I37 },
{"subu", "d,v,t", 0x000001d0, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1, 0, 0 },
-{"suxc1", "D,t(b)", 0x54000188, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I1, 0, 0 },
+{"suxc1", "D,t(b)", 0x54000188, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0, I1, 0, I37 },
{"sw", "mq,mJ(ml)", 0xe800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 },
{"sw", "mp,mU(ms)", 0xc800, 0xfc00, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* swsp */
{"sw", "t,o(b)", 0xf8000000, 0xfc000000, RD_1|RD_3|SM, 0, I1, 0, 0 },
@@ -1121,51 +1305,54 @@ const struct mips_opcode micromips_opcodes[] =
{"swc1", "E,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 },
{"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
{"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
-{"swc2", "E,~(b)", 0x20008000, 0xfc00f000, RD_3|RD_C2|SM, 0, I1, 0, 0 },
+{"swc2", "E,~(b)", 0x20008000, 0xfc00f000, RD_3|RD_C2|SM, 0, I1, 0, I37 },
+{"swc2", "E,+:(b)", 0x20008000, 0xfc00f800, RD_3|RD_C2|SM, 0, I37, 0, 0 },
{"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1, 0, 0 },
{"s.s", "T,o(b)", 0x98000000, 0xfc000000, RD_1|RD_3|SM|FP_S, 0, I1, 0, 0 }, /* swc1 */
{"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, INSN2_M_FP_S, I1, 0, 0 },
-{"swl", "t,~(b)", 0x60008000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 },
-{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"scache", "t,~(b)", 0x60008000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* same */
-{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"swm", "mN,mJ(ms)", 0x4540, 0xffc0, RD_3|NODS, 0, I1, 0, 0 },
+{"swl", "t,~(b)", 0x60008000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, I37 },
+{"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"scache", "t,~(b)", 0x60008000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, I37 }, /* same */
+{"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"swm", "+N,+L(ms)", 0x440a, 0xfc0f, RD_3, 0, I37, 0, 0 },
+{"swm", "mN,mJ(ms)", 0x4540, 0xffc0, RD_3|NODS, 0, I1, 0, I37 },
{"swm", "n,~(b)", 0x2000d000, 0xfc00f000, RD_3|SM|NODS, 0, I1, 0, 0 },
{"swm", "n,A(b)", 0, (int) M_SWM_AB, INSN_MACRO, 0, I1, 0, 0 },
{"swp", "t,~(b)", 0x20009000, 0xfc00f000, RD_1|RD_3|SM|NODS, 0, I1, 0, 0 },
{"swp", "t,A(b)", 0, (int) M_SWP_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"swr", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 },
-{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"invalidate", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, 0 }, /* same */
-{"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I1, 0, 0 },
-{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, AL, I1, 0, 0 },
-{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, AL, I1, 0, 0 },
-{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, AL, I1, 0, 0 },
-{"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, AL, I1, 0, 0 },
-{"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, AL, I1, 0, 0 },
+{"swr", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, I37 },
+{"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"invalidate", "t,~(b)", 0x60009000, 0xfc00f000, RD_1|RD_3|SM, 0, I1, 0, I37 }, /* same */
+{"invalidate", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"swxc1", "D,t(b)", 0x54000088, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0, I1, 0, I37 },
+{"sync_acquire", "", 0x00116b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 },
+{"sync_mb", "", 0x00106b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 },
+{"sync_release", "", 0x00126b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 },
+{"sync_rmb", "", 0x00136b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 },
+{"sync_wmb", "", 0x00046b7c, 0xffffffff, NODS, INSN2_ALIAS, I1, 0, 0 },
{"sync", "", 0x00006b7c, 0xffffffff, NODS, 0, I1, 0, 0 },
{"sync", "1", 0x00006b7c, 0xffe0ffff, NODS, 0, I1, 0, 0 },
-{"synci", "o(b)", 0x42000000, 0xffe00000, RD_2|SM, 0, I1, 0, 0 },
+{"synci", "o(b)", 0x41800000, 0xffe00000, RD_2|SM, 0, I37, 0, 0 },
+{"synci", "o(b)", 0x42000000, 0xffe00000, RD_2|SM, 0, I1, 0, I37 },
{"syscall", "", 0x00008b7c, 0xffffffff, TRAP, 0, I1, 0, 0 },
{"syscall", "+J", 0x00008b7c, 0xfc00ffff, TRAP, 0, I1, 0, 0 },
-{"teqi", "s,j", 0x41c00000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 },
+{"teqi", "s,j", 0x41c00000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 },
{"teq", "s,t", 0x0000003c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
{"teq", "s,t,|", 0x0000003c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
-{"teq", "s,j", 0x41c00000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* teqi */
+{"teq", "s,j", 0x41c00000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 }, /* teqi */
{"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I1, 0, 0 },
-{"tgei", "s,j", 0x41200000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 },
+{"tgei", "s,j", 0x41200000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 },
{"tge", "s,t", 0x0000023c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
{"tge", "s,t,|", 0x0000023c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
-{"tge", "s,j", 0x41200000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tgei */
+{"tge", "s,j", 0x41200000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 }, /* tgei */
{"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I1, 0, 0 },
-{"tgeiu", "s,j", 0x41600000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 },
+{"tgeiu", "s,j", 0x41600000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 },
{"tgeu", "s,t", 0x0000043c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
{"tgeu", "s,t,|", 0x0000043c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
-{"tgeu", "s,j", 0x41600000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tgeiu */
+{"tgeu", "s,j", 0x41600000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 }, /* tgeiu */
{"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I1, 0, 0 },
-{"tlbinv", "", 0x0000437c, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 },
-{"tlbinvf", "", 0x0000537c, 0xffffffff, INSN_TLB, 0, 0, TLBINV, 0 },
+{"tlbinv", "", 0x0000437c, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 },
+{"tlbinvf", "", 0x0000537c, 0xffffffff, INSN_TLB, 0, I37, TLBINV, 0 },
{"tlbginv", "", 0x0000417c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 },
{"tlbginvf", "", 0x0000517c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 },
{"tlbgp", "", 0x0000017c, 0xffffffff, INSN_TLB, 0, 0, IVIRT, 0 },
@@ -1176,43 +1363,150 @@ const struct mips_opcode micromips_opcodes[] =
{"tlbr", "", 0x0000137c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 },
{"tlbwi", "", 0x0000237c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 },
{"tlbwr", "", 0x0000337c, 0xffffffff, INSN_TLB, 0, I1, 0, 0 },
-{"tlti", "s,j", 0x41000000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 },
+{"tlti", "s,j", 0x41000000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 },
{"tlt", "s,t", 0x0000083c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
{"tlt", "s,t,|", 0x0000083c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
-{"tlt", "s,j", 0x41000000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tlti */
+{"tlt", "s,j", 0x41000000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 }, /* tlti */
{"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I1, 0, 0 },
-{"tltiu", "s,j", 0x41400000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 },
+{"tltiu", "s,j", 0x41400000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 },
{"tltu", "s,t", 0x00000a3c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
{"tltu", "s,t,|", 0x00000a3c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
-{"tltu", "s,j", 0x41400000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tltiu */
+{"tltu", "s,j", 0x41400000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 }, /* tltiu */
{"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I1, 0, 0 },
-{"tnei", "s,j", 0x41800000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 },
+{"tnei", "s,j", 0x41800000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 },
{"tne", "s,t", 0x00000c3c, 0xfc00ffff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
{"tne", "s,t,|", 0x00000c3c, 0xfc000fff, RD_1|RD_2|TRAP, 0, I1, 0, 0 },
-{"tne", "s,j", 0x41800000, 0xffe00000, RD_1|TRAP, 0, I1, 0, 0 }, /* tnei */
+{"tne", "s,j", 0x41800000, 0xffe00000, RD_1|TRAP, 0, I1, 0, I37 }, /* tnei */
{"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I1, 0, 0 },
{"trunc.l.d", "T,S", 0x5400633b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 },
{"trunc.l.s", "T,S", 0x5400233b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"trunc.w.d", "T,S", 0x54006b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 },
{"trunc.w.s", "T,S", 0x54002b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 },
-{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3, 0, 0 },
-{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, 0 },
-{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, 0 },
+{"uld", "t,A(b)", 0, (int) M_ULD_AB, INSN_MACRO, 0, I3, 0, I69 },
+{"ulh", "t,A(b)", 0, (int) M_ULH_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"ulhu", "t,A(b)", 0, (int) M_ULHU_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"ulw", "t,A(b)", 0, (int) M_ULW_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"usd", "t,A(b)", 0, (int) M_USD_AB, INSN_MACRO, 0, I3, 0, I69 },
+{"ush", "t,A(b)", 0, (int) M_USH_AB, INSN_MACRO, 0, I1, 0, I37 },
+{"usw", "t,A(b)", 0, (int) M_USW_AB, INSN_MACRO, 0, I1, 0, I37 },
{"wait", "", 0x0000937c, 0xffffffff, NODS, 0, I1, 0, 0 },
{"wait", "+J", 0x0000937c, 0xfc00ffff, NODS, 0, I1, 0, 0 },
{"wrpgpr", "t,r", 0x0000f17c, 0xfc00ffff, RD_2, 0, I1, 0, 0 },
{"wsbh", "t,r", 0x00007b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 },
-{"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, 0 },
-{"xor", "mf,mg,mx", 0x4440, 0xffc0, MOD_1|RD_2, 0, I1, 0, 0 },
+{"xor", "md,mt,ml", 0x4408, 0xfc0f, MOD_1|RD_3, 0, I37, 0, 0 },
+{"xor", "md,ml,mx", 0x4408, 0xfc0f, MOD_1|RD_2, 0, I37, 0, 0 },
+{"xor", "mf,mt,mg", 0x4440, 0xffc0, MOD_1|RD_3, 0, I1, 0, I37 },
+{"xor", "mf,mg,mx", 0x4440, 0xffc0, MOD_1|RD_2, 0, I1, 0, I37 },
{"xor", "d,v,t", 0x00000310, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I1, 0, 0 },
{"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1, 0, 0 },
{"xori", "t,r,i", 0x70000000, 0xfc000000, WR_1|RD_2, 0, I1, 0, 0 },
{"yield", "t", 0x000009bc, 0xfc1fffff, RD_1|NODS, 0, 0, MT32, 0 },
{"yield", "s,t", 0x000009bc, 0xfc00ffff, WR_1|RD_2|NODS, 0, 0, MT32, 0 },
+/* microMIPS R6 */
+{"aui", "t,s,u", 0x10000000, 0xfc000000, WR_1|RD_2, 0, I37, 0, 0 },
+{"aluipc", "t,u", 0x781f0000, 0xfc1f0000, WR_1, RD_pc, I37, 0, 0 },
+{"auipc", "t,u", 0x781e0000, 0xfc1f0000, WR_1, RD_pc, I37, 0, 0 },
+{"daui", "t,-s,u", 0xf0000000, 0xfc000000, WR_1|RD_2, 0, I69, 0, 0 },
+
+{"align", "d,s,t,+I", 0x0000001f, 0xfc0001ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 },
+{"dalign", "d,s,t,+O", 0x5800001c, 0xfc0000ff, WR_1|RD_2|RD_3, 0, I69, 0, 0 },
+{"bitswap", "v,w", 0x00000b3c, 0xfc00ffff, WR_1|RD_2, 0, I37, 0, 0 },
+{"dbitswap", "v,w", 0x58000b3c, 0xfc00ffff, WR_1|RD_2, 0, I69, 0, 0 },
+
+{"blezc", "-t,p", 0xf4000000, 0xfc1f0000, RD_1, CBR, I37, 0, 0 },
+{"bgezc", "+;,p", 0xf4000000, 0xfc000000, RD_1, CBR, I37, 0, 0 },
+{"bgec", "-s,-v,p", 0xf4000000, 0xfc000000, RD_1|RD_2, CBR, I37, 0, 0 },
+{"bgtzc", "-t,p", 0xd4000000, 0xfc1f0000, RD_1, CBR, I37, 0, 0 },
+{"bltzc", "+;,p", 0xd4000000, 0xfc000000, RD_1, CBR, I37, 0, 0 },
+{"bltc", "-s,-v,p", 0xd4000000, 0xfc000000, RD_1|RD_2, CBR, I37, 0, 0 },
+{"blezalc", "-t,p", 0xc0000000, 0xfc1f0000, RD_1|WR_31, CBR, I37, 0, 0 },
+{"bgezalc", "+;,p", 0xc0000000, 0xfc000000, RD_1|WR_31, CBR, I37, 0, 0 },
+{"bgeuc", "-s,-v,p", 0xc0000000, 0xfc000000, RD_1|RD_2, CBR, I37, 0, 0 },
+{"bgtzalc", "-t,p", 0xe0000000, 0xfc1f0000, RD_1|WR_31, CBR, I37, 0, 0 },
+{"bltzalc", "+;,p", 0xe0000000, 0xfc000000, RD_1|WR_31, CBR, I37, 0, 0 },
+{"bltuc", "-s,-v,p", 0xe0000000, 0xfc000000, RD_1|RD_2, CBR, I37, 0, 0 },
+
+{"jic", "s,j", 0x80000000, 0xffe00000, RD_1, UBR, I37, 0, 0 },
+{"jialc", "s,j", 0xa0000000, 0xffe00000, RD_1, UBR, I37, 0, 0 },
+
+{"cmp.af.s", "D,S,T", 0x54000005, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.af.d", "D,S,T", 0x54000015, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.eq.s", "D,S,T", 0x54000085, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.eq.d", "D,S,T", 0x54000095, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.le.s", "D,S,T", 0x54000185, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.le.d", "D,S,T", 0x54000195, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.lt.s", "D,S,T", 0x54000105, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.lt.d", "D,S,T", 0x54000115, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.ne.s", "D,S,T", 0x540004c5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.ne.d", "D,S,T", 0x540004d5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.or.s", "D,S,T", 0x54000445, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.or.d", "D,S,T", 0x54000455, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.ueq.s", "D,S,T", 0x540000c5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.ueq.d", "D,S,T", 0x540000d5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.ule.s", "D,S,T", 0x540001c5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.ule.d", "D,S,T", 0x540001d5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.ult.s", "D,S,T", 0x54000145, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.ult.d", "D,S,T", 0x54000155, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.un.s", "D,S,T", 0x54000045, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.un.d", "D,S,T", 0x54000055, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.une.s", "D,S,T", 0x54000485, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.une.d", "D,S,T", 0x54000495, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.saf.s", "D,S,T", 0x54000205, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.saf.d", "D,S,T", 0x54000215, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.seq.s", "D,S,T", 0x54000285, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.seq.d", "D,S,T", 0x54000295, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.sle.s", "D,S,T", 0x54000385, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.sle.d", "D,S,T", 0x54000395, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.slt.s", "D,S,T", 0x54000305, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.slt.d", "D,S,T", 0x54000315, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.sne.s", "D,S,T", 0x540006c5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.sne.d", "D,S,T", 0x540006d5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.sor.s", "D,S,T", 0x54000645, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.sor.d", "D,S,T", 0x54000655, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.sueq.s", "D,S,T", 0x540002c5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.sueq.d", "D,S,T", 0x540002d5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.sule.s", "D,S,T", 0x540003c5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.sule.d", "D,S,T", 0x540003d5, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.sult.s", "D,S,T", 0x54000345, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.sult.d", "D,S,T", 0x54000355, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"cmp.sun.s", "D,S,T", 0x54000245, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.sun.d", "D,S,T", 0x54000255, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.sune.s", "D,S,T", 0x54000685, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"cmp.sune.d", "D,S,T", 0x54000695, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+
+{"maddf.s", "D,S,T", 0x540001b8, 0xfc0007ff, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"maddf.d", "D,S,T", 0x540003b8, 0xfc0007ff, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"msubf.s", "D,S,T", 0x540001f8, 0xfc0007ff, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"msubf.d", "D,S,T", 0x540003f8, 0xfc0007ff, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"sel.s", "D,S,T", 0x540000b8, 0xfc0007ff, MOD_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"sel.d", "D,S,T", 0x540002b8, 0xfc0007ff, MOD_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"seleqz", "d,s,t", 0x00000140, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 },
+{"seleqz.s", "D,S,T", 0x54000038, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"seleqz.d", "D,S,T", 0x54000238, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"selnez", "d,s,t", 0x00000180, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I37, 0, 0 },
+{"selnez.s", "D,S,T", 0x54000078, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"selnez.d", "D,S,T", 0x54000278, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+
+{"class.s", "+D,+S", 0x54000060, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I37, 0, 0 },
+{"class.d", "+D,+S", 0x54000260, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I37, 0, 0 },
+{"min.s", "D,S,T", 0x54000003, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"min.d", "D,S,T", 0x54000203, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"max.s", "D,S,T", 0x5400000b, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"max.d", "D,S,T", 0x5400020b, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"mina.s", "D,S,T", 0x54000023, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"mina.d", "D,S,T", 0x54000223, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"maxa.s", "D,S,T", 0x5400002b, 0xfc0007ff, WR_1|RD_2|RD_3|FP_S, 0, I37, 0, 0 },
+{"maxa.d", "D,S,T", 0x5400022b, 0xfc0007ff, WR_1|RD_2|RD_3|FP_D, 0, I37, 0, 0 },
+{"rint.s", "+D,+S", 0x54000020, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I37, 0, 0 },
+{"rint.d", "+D,+S", 0x54000220, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I37, 0, 0 },
+
+{"bc1eqzc", "+D,p", 0x41000000, 0xffe00000, RD_1|FP_S, CBR, I37, 0, 0 },
+{"bc1nezc", "+D,p", 0x41200000, 0xffe00000, RD_1|FP_S, CBR, I37, 0, 0 },
+{"bc2eqzc", "G,p", 0x41400000, 0xffe00000, RD_C2, CBR, I37, 0, 0 },
+{"bc2nezc", "G,p", 0x41600000, 0xffe00000, RD_C2, CBR, I37, 0, 0 },
+{"dahi", "s,mx,u", 0x42200000, 0xffe00000, MOD_1, 0, I69, 0, 0 },
+{"dati", "s,mx,u", 0x42000000, 0xffe00000, MOD_1, 0, I69, 0, 0 },
+
/* microMIPS Enhanced VA Scheme */
{"lbue", "t,+j(b)", 0x60006000, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lbue", "t,A(b)", 0, (int) M_LBUE_AB, INSN_MACRO, 0, 0, EVA, 0 },
@@ -1224,24 +1518,28 @@ const struct mips_opcode micromips_opcodes[] =
{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lle", "t,+j(b)", 0x60006c00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 },
+{"llwpe", "t,-p,s", 0x60006400, 0xfc00fe0f, WR_1|WR_2|RD_3|LM, 0, 0, EVAR6, 0 },
+{"llwpe", "t,-p,A(b)", 0, (int) M_LLWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 },
{"lwe", "t,+j(b)", 0x60006e00, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 },
-{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
-{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, 0 },
-{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, 0 },
-{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, 0 },
+{"lwle", "t,+j(b)", 0x60006400, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, I37 },
+{"lwle", "t,A(b)", 0, (int) M_LWLE_AB, INSN_MACRO, 0, 0, EVA, I37 },
+{"lwre", "t,+j(b)", 0x60006600, 0xfc00fe00, WR_1|RD_3|LM, 0, 0, EVA, I37 },
+{"lwre", "t,A(b)", 0, (int) M_LWRE_AB, INSN_MACRO, 0, 0, EVA, I37 },
{"sbe", "t,+j(b)", 0x6000a800, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 },
{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 },
+{"scwpe", "t,-p,s", 0x6000a000, 0xfc00fe0f, MOD_1|RD_2|RD_3|SM, 0, 0, EVAR6, 0 },
+{"scwpe", "t,-p,A(b)", 0, (int) M_SCWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 },
{"sce", "t,+j(b)", 0x6000ac00, 0xfc00fe00, MOD_1|RD_3|SM, 0, 0, EVA, 0 },
{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"she", "t,+j(b)", 0x6000aa00, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 },
{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"swe", "t,+j(b)", 0x6000ae00, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 },
{"swe", "t,A(b)", 0, (int) M_SWE_AB, INSN_MACRO, 0, 0, EVA, 0 },
-{"swle", "t,+j(b)", 0x6000a000, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 },
-{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA, 0 },
-{"swre", "t,+j(b)", 0x6000a200, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, 0 },
-{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, 0 },
+{"swle", "t,+j(b)", 0x6000a000, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, I37 },
+{"swle", "t,A(b)", 0, (int) M_SWLE_AB, INSN_MACRO, 0, 0, EVA, I37 },
+{"swre", "t,+j(b)", 0x6000a200, 0xfc00fe00, WR_1|RD_3|SM, 0, 0, EVA, I37 },
+{"swre", "t,A(b)", 0, (int) M_SWRE_AB, INSN_MACRO, 0, 0, EVA, I37 },
{"cachee", "k,+j(b)", 0x6000a600, 0xfc00fe00, RD_3, 0, 0, EVA, 0 },
{"cachee", "k,A(b)", 0, (int) M_CACHEE_AB,INSN_MACRO, 0, 0, EVA, 0 },
{"prefe", "k,+j(b)", 0x6000a400, 0xfc00fe00, RD_3|LM, 0, 0, EVA, 0 },
@@ -1257,7 +1555,9 @@ const struct mips_opcode micromips_opcodes[] =
{"addu_s.qb", "d,s,t", 0x000004cd, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 },
{"addwc", "d,s,t", 0x000003c5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 },
{"bitrev", "t,s", 0x0000313c, 0xfc00ffff, WR_1|RD_2, 0, 0, D32, 0 },
-{"bposge32", "p", 0x43600000, 0xffff0000, CBD, 0, 0, D32, 0 },
+{"bposge32c", "p", 0x43200000, 0xffff0000, 0, CBR, 0, D34, 0 },
+{"bposge32", "p", 0x43200000, 0xffff0000, 0, INSN2_ALIAS|CBR|CTC, 0, D34, 0 },
+{"bposge32", "p", 0x43600000, 0xffff0000, CBD, 0, 0, D32, I37 },
{"cmp.eq.ph", "s,t", 0x00000005, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 },
{"cmpgu.eq.qb", "d,s,t", 0x000000c5, 0xfc0007ff, WR_1|RD_2|RD_3, 0, 0, D32, 0 },
{"cmp.le.ph", "s,t", 0x00000085, 0xfc00ffff, RD_1|RD_2, 0, 0, D32, 0 },
@@ -1931,8 +2231,10 @@ const struct mips_opcode micromips_opcodes[] =
{"ctcmsa", "+l,d", 0x583e0016, 0xffff003f, RD_2, 0, 0, MSA, 0 },
{"cfcmsa", "+k,+n", 0x587e0016, 0xffff003f, WR_1, 0, 0, MSA, 0 },
{"move.v", "+d,+e", 0x58be0016, 0xffff003f, WR_1|RD_2, 0, 0, MSA, 0 },
-{"lsa", "d,v,t,+~", 0x00000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA, 0 },
-{"dlsa", "d,v,t,+~", 0x58000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA64, 0 },
+{"lsa", "d,v,t,+~", 0x00000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA, I37 },
+{"lsa", "d,v,t,+.", 0x0000000f, 0xfc0001ff, WR_1|RD_2|RD_3, 0, I37, MSA, 0 },
+{"dlsa", "d,v,t,+~", 0x58000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA64, I69 },
+{"dlsa", "d,v,t,+.", 0x58000108, 0xfc0001ff, WR_1|RD_2|RD_3, 0, I69, MSA64, 0 },
};
const int bfd_micromips_num_opcodes =
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 4861150d0dd..612f694f442 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -2574,6 +2574,10 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
&& ((length == 2 && (op->mask & 0xffff0000) == 0)
|| (length == 4 && (op->mask & 0xffff0000) != 0)))
{
+ if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor)
+ || (op->pinfo2 & INSN2_CONVERTED_TO_COMPACT))
+ continue;
+
if (!validate_insn_args (op, decode_micromips_operand, insn))
continue;
diff --git a/opcodes/mips-formats.h b/opcodes/mips-formats.h
index c4dec6352bf..7f786f3c2a8 100644
--- a/opcodes/mips-formats.h
+++ b/opcodes/mips-formats.h
@@ -21,7 +21,7 @@
#define INT_BIAS(SIZE, LSB, MAX_VAL, BIAS, SHIFT, PRINT_HEX) \
{ \
static const struct mips_int_operand op = { \
- { OP_INT, SIZE, LSB }, MAX_VAL, BIAS, SHIFT, PRINT_HEX \
+ { OP_INT, SIZE, LSB, 0, 0 }, MAX_VAL, BIAS, SHIFT, PRINT_HEX \
}; \
return &op.root; \
}
@@ -41,7 +41,7 @@
#define BIT(SIZE, LSB, BIAS) \
{ \
static const struct mips_int_operand op = { \
- { OP_INT, SIZE, LSB }, (1 << (SIZE)) - 1, BIAS, 0, true \
+ { OP_INT, SIZE, LSB, 0, 0 }, (1 << (SIZE)) - 1, BIAS, 0, true \
}; \
return &op.root; \
}
@@ -51,7 +51,7 @@
typedef char ATTRIBUTE_UNUSED \
static_assert_3[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \
static const struct mips_mapped_int_operand op = { \
- { OP_MAPPED_INT, SIZE, LSB }, MAP, PRINT_HEX \
+ { OP_MAPPED_INT, SIZE, LSB, 0, 0 }, MAP, PRINT_HEX \
}; \
return &op.root; \
}
@@ -59,7 +59,7 @@
#define MSB(SIZE, LSB, BIAS, ADD_LSB, OPSIZE) \
{ \
static const struct mips_msb_operand op = { \
- { OP_MSB, SIZE, LSB }, BIAS, ADD_LSB, OPSIZE \
+ { OP_MSB, SIZE, LSB, 0, 0 }, BIAS, ADD_LSB, OPSIZE \
}; \
return &op.root; \
}
@@ -67,7 +67,7 @@
#define REG(SIZE, LSB, BANK) \
{ \
static const struct mips_reg_operand op = { \
- { OP_REG, SIZE, LSB }, OP_REG_##BANK, 0 \
+ { OP_REG, SIZE, LSB, 0, 0 }, OP_REG_##BANK, 0 \
}; \
return &op.root; \
}
@@ -75,7 +75,7 @@
#define OPTIONAL_REG(SIZE, LSB, BANK) \
{ \
static const struct mips_reg_operand op = { \
- { OP_OPTIONAL_REG, SIZE, LSB }, OP_REG_##BANK, 0 \
+ { OP_OPTIONAL_REG, SIZE, LSB, 0, 0 }, OP_REG_##BANK, 0 \
}; \
return &op.root; \
}
@@ -85,7 +85,17 @@
typedef char ATTRIBUTE_UNUSED \
static_assert_4[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \
static const struct mips_reg_operand op = { \
- { OP_REG, SIZE, LSB }, OP_REG_##BANK, MAP \
+ { OP_REG, SIZE, LSB, 0, 0 }, OP_REG_##BANK, MAP \
+ }; \
+ return &op.root; \
+ }
+
+#define SPLIT_MAPPED_REG(SIZE, LSB, SIZE_T, LSB_T, BANK, MAP) \
+ { \
+ typedef char ATTRIBUTE_UNUSED \
+ static_assert[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \
+ static const struct mips_reg_operand op = { \
+ { OP_REG, SIZE, LSB, SIZE_T, LSB_T }, OP_REG_##BANK, MAP \
}; \
return &op.root; \
}
@@ -95,7 +105,7 @@
typedef char ATTRIBUTE_UNUSED \
static_assert_5[(1 << (SIZE)) == ARRAY_SIZE (MAP)]; \
static const struct mips_reg_operand op = { \
- { OP_OPTIONAL_REG, SIZE, LSB }, OP_REG_##BANK, MAP \
+ { OP_OPTIONAL_REG, SIZE, LSB, 0, 0 }, OP_REG_##BANK, MAP \
}; \
return &op.root; \
}
@@ -107,7 +117,7 @@
typedef char ATTRIBUTE_UNUSED \
static_assert2[(1 << (SIZE)) == ARRAY_SIZE (MAP##2)]; \
static const struct mips_reg_pair_operand op = { \
- { OP_REG_PAIR, SIZE, LSB }, OP_REG_##BANK, MAP##1, MAP##2 \
+ { OP_REG_PAIR, SIZE, LSB, 0, 0 }, OP_REG_##BANK, MAP##1, MAP##2 \
}; \
return &op.root; \
}
@@ -116,7 +126,7 @@
FLIP_ISA_BIT) \
{ \
static const struct mips_pcrel_operand op = { \
- { { OP_PCREL, SIZE, LSB }, \
+ { { OP_PCREL, SIZE, LSB, 0, 0 }, \
(1 << ((SIZE) - (IS_SIGNED))) - 1, 0, SHIFT, true }, \
ALIGN_LOG2, INCLUDE_ISA_BIT, FLIP_ISA_BIT \
}; \
@@ -134,14 +144,14 @@
#define SPECIAL(SIZE, LSB, TYPE) \
{ \
- static const struct mips_operand op = { OP_##TYPE, SIZE, LSB }; \
+ static const struct mips_operand op = { OP_##TYPE, SIZE, LSB, 0, 0 }; \
return &op; \
}
#define PREV_CHECK(SIZE, LSB, GT_OK, LT_OK, EQ_OK, ZERO_OK) \
{ \
static const struct mips_check_prev_operand op = { \
- { OP_CHECK_PREV, SIZE, LSB }, GT_OK, LT_OK, EQ_OK, ZERO_OK \
+ { OP_CHECK_PREV, SIZE, LSB, 0, 0 }, GT_OK, LT_OK, EQ_OK, ZERO_OK \
}; \
return &op.root; \
}
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 7b1aa5f71a0..97441a4e01e 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -29,7 +29,7 @@
#include "mips-formats.h"
/* The 4-bit XYZW mask used in some VU0 instructions. */
-const struct mips_operand mips_vu0_channel_mask = { OP_VU0_SUFFIX, 4, 21 };
+const struct mips_operand mips_vu0_channel_mask = { OP_VU0_SUFFIX, 4, 21, 0, 0 };
static unsigned char reg_0_map[] = { 0 };
--
2.34.1
^ permalink raw reply [flat|nested] 26+ messages in thread* [PATCH 17/21] Extend trap macros to handle immediate zero
2024-12-13 15:53 [PATCH 0/21] Integrate MIPS-Specific Support into Official binutils-gdb Milica Matic
` (16 preceding siblings ...)
2024-12-13 15:53 ` [PATCH 16/21] Fix addr2line mapping - garbage collected modules Milica Matic
@ 2024-12-13 15:53 ` Milica Matic
2024-12-13 15:53 ` [PATCH 18/21] Fix failing test cases for linux and 64-bit target Milica Matic
` (5 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Milica Matic @ 2024-12-13 15:53 UTC (permalink / raw)
To: gdb-patches
Cc: milica.matic, simark, cfu, aburgess, kevinb, macro,
djordje.todorovic, Faraz Shahbazker
From: Faraz Shahbazker <fshahbazker@wavecomp.com>
Immediate zero can be replaced by the zero register for ISAs
which don't have a trap-on-compare-immediate instruction. Extend
the macro expansion of trap-on-compare instructions to handle 0
without needing intermediate $AT.
Cherry-picked 3ad13bb
from https://github.com/MIPS/binutils-gdb
Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Milica Matic <milica.matic@htecgroup.com>
gas/
* config/tc-mips.c (macro): Extend trap macros to short
circuit immediate zero with register $0.
* testsuite/gas/mips/micromipsr6@micromips-insn32.d: Update
reference output.
* testsuite/gas/mips/micromipsr6@micromips.d: Likewise.
---
gas/config/tc-mips.c | 11 +-
.../gas/mips/micromipsr6@micromips-insn32.d | 68 +-
.../gas/mips/micromipsr6@micromips.d | 8902 ++++++++---------
3 files changed, 4487 insertions(+), 4494 deletions(-)
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 87fad61c7a4..00999e58f9d 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -14160,9 +14160,14 @@ macro (struct mips_cl_insn *ip, char *str)
case M_TNE_I:
s = "tne";
trap:
- used_at = 1;
- load_register (AT, &imm_expr, GPR_SIZE == 64);
- macro_build (NULL, s, "s,t", op[0], AT);
+ if (imm_expr.X_add_number == 0)
+ macro_build (NULL, s, "s,t", op[0], 0);
+ else
+ {
+ used_at = 1;
+ load_register (AT, &imm_expr, GPR_SIZE == 64);
+ macro_build (NULL, s, "s,t", op[0], AT);
+ }
break;
case M_TRUNCWS:
diff --git a/gas/testsuite/gas/mips/micromipsr6@micromips-insn32.d b/gas/testsuite/gas/mips/micromipsr6@micromips-insn32.d
index 66147ebfd6e..69141430684 100644
--- a/gas/testsuite/gas/mips/micromipsr6@micromips-insn32.d
+++ b/gas/testsuite/gas/mips/micromipsr6@micromips-insn32.d
@@ -2241,8 +2241,7 @@ Disassembly of section .text:
[ 0-9a-f]+: 0062 003c teq v0,v1
[ 0-9a-f]+: 0062 103c teq v0,v1,0x1
[ 0-9a-f]+: 0062 f03c teq v0,v1,0xf
-[ 0-9a-f]+: 3020 0000 li at,0
-[ 0-9a-f]+: 0022 003c teq v0,at
+[ 0-9a-f]+: 0002 003c teq v0,zero
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 0022 003c teq v0,at
[ 0-9a-f]+: 3020 7fff li at,32767
@@ -2254,8 +2253,7 @@ Disassembly of section .text:
[ 0-9a-f]+: 0062 023c tge v0,v1
[ 0-9a-f]+: 0062 123c tge v0,v1,0x1
[ 0-9a-f]+: 0062 f23c tge v0,v1,0xf
-[ 0-9a-f]+: 3020 0000 li at,0
-[ 0-9a-f]+: 0022 023c tge v0,at
+[ 0-9a-f]+: 0002 023c tge v0,zero
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 0022 023c tge v0,at
[ 0-9a-f]+: 3020 7fff li at,32767
@@ -2267,8 +2265,7 @@ Disassembly of section .text:
[ 0-9a-f]+: 0062 043c tgeu v0,v1
[ 0-9a-f]+: 0062 143c tgeu v0,v1,0x1
[ 0-9a-f]+: 0062 f43c tgeu v0,v1,0xf
-[ 0-9a-f]+: 3020 0000 li at,0
-[ 0-9a-f]+: 0022 043c tgeu v0,at
+[ 0-9a-f]+: 0002 043c tgeu v0,zero
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 0022 043c tgeu v0,at
[ 0-9a-f]+: 3020 7fff li at,32767
@@ -2284,8 +2281,7 @@ Disassembly of section .text:
[ 0-9a-f]+: 0062 083c tlt v0,v1
[ 0-9a-f]+: 0062 183c tlt v0,v1,0x1
[ 0-9a-f]+: 0062 f83c tlt v0,v1,0xf
-[ 0-9a-f]+: 3020 0000 li at,0
-[ 0-9a-f]+: 0022 083c tlt v0,at
+[ 0-9a-f]+: 0002 083c tlt v0,zero
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 0022 083c tlt v0,at
[ 0-9a-f]+: 3020 7fff li at,32767
@@ -2297,8 +2293,7 @@ Disassembly of section .text:
[ 0-9a-f]+: 0062 0a3c tltu v0,v1
[ 0-9a-f]+: 0062 1a3c tltu v0,v1,0x1
[ 0-9a-f]+: 0062 fa3c tltu v0,v1,0xf
-[ 0-9a-f]+: 3020 0000 li at,0
-[ 0-9a-f]+: 0022 0a3c tltu v0,at
+[ 0-9a-f]+: 0002 0a3c tltu v0,zero
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 0022 0a3c tltu v0,at
[ 0-9a-f]+: 3020 7fff li at,32767
@@ -2314,8 +2309,7 @@ Disassembly of section .text:
[ 0-9a-f]+: 0062 0c3c tne v0,v1
[ 0-9a-f]+: 0062 1c3c tne v0,v1,0x1
[ 0-9a-f]+: 0062 fc3c tne v0,v1,0xf
-[ 0-9a-f]+: 3020 0000 li at,0
-[ 0-9a-f]+: 0022 0c3c tne v0,at
+[ 0-9a-f]+: 0002 0c3c tne v0,zero
[ 0-9a-f]+: 3020 8000 li at,-32768
[ 0-9a-f]+: 0022 0c3c tne v0,at
[ 0-9a-f]+: 3020 7fff li at,32767
@@ -3696,17 +3690,17 @@ Disassembly of section .text:
[0-9a-f]+ <test_mips64>:
[ 0-9a-f]+: 0003 1290 move v0,v1
-[ 0-9a-f]+: f463 fffe bgezc v1,3804 <.*>
+[ 0-9a-f]+: f463 fffe bgezc v1,37ec <.*>
[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_4
[ 0-9a-f]+: 5860 1190 dneg v0,v1
[0-9a-f]+ <\.L\^\_4>:
-[ 0-9a-f]+: f442 fffe bgezc v0,380c <\.L\^\_4>
+[ 0-9a-f]+: f442 fffe bgezc v0,37f4 <\.L\^\_4>
[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_5
[ 0-9a-f]+: 5840 1190 dneg v0,v0
[0-9a-f]+ <\.L\^\_5>:
-[ 0-9a-f]+: f442 fffe bgezc v0,3814 <\.L\^\_5>
+[ 0-9a-f]+: f442 fffe bgezc v0,37fc <\.L\^\_5>
[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_6
[ 0-9a-f]+: 5840 1190 dneg v0,v0
@@ -4343,9 +4337,9 @@ Disassembly of section .text:
[0-9a-f]+ <test_delay_slot>:
[ 0-9a-f]+: b3fe 0000 sltiu ra,s8,0
[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
-[ 0-9a-f]+: c063 fffe bgezalc v1,41bc <.*>
+[ 0-9a-f]+: c063 fffe bgezalc v1,41a4 <.*>
[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
-[ 0-9a-f]+: e063 fffe bltzalc v1,41c0 <.*>
+[ 0-9a-f]+: e063 fffe bltzalc v1,41a8 <.*>
[ ]*[ 0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
[ 0-9a-f]+: b3fe 0000 sltiu ra,s8,0
[ ]*[ 0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
@@ -4378,26 +4372,26 @@ Disassembly of section .text:
[ 0-9a-f]+: fe3c fffe lw s1,-2\(gp\)
[ 0-9a-f]+: fe3c fffd lw s1,-3\(gp\)
[ 0-9a-f]+: fe3b 0000 lw s1,0\(k1\)
-[ 0-9a-f]+: 7840 0000 lapc v0,4234 <.*>
-[ 0-9a-f]+: 7860 0000 lapc v1,4238 <.*>
-[ 0-9a-f]+: 7880 0000 lapc a0,423c <.*>
-[ 0-9a-f]+: 78a0 0000 lapc a1,4240 <.*>
-[ 0-9a-f]+: 78c0 0000 lapc a2,4244 <.*>
-[ 0-9a-f]+: 78e0 0000 lapc a3,4248 <.*>
-[ 0-9a-f]+: 7a00 0000 lapc s0,424c <.*>
-[ 0-9a-f]+: 7a20 0000 lapc s1,4250 <.*>
-[ 0-9a-f]+: 7a23 ffff lapc s1,104250 <.*>
-[ 0-9a-f]+: 7a24 0000 lapc s1,fff04258 <.*>
-[ 0-9a-f]+: 7840 0000 lapc v0,425c <.*>
-[ 0-9a-f]+: 7860 0000 lapc v1,4260 <.*>
-[ 0-9a-f]+: 7880 0000 lapc a0,4264 <.*>
-[ 0-9a-f]+: 78a0 0000 lapc a1,4268 <.*>
-[ 0-9a-f]+: 78c0 0000 lapc a2,426c <.*>
-[ 0-9a-f]+: 78e0 0000 lapc a3,4270 <.*>
-[ 0-9a-f]+: 7a00 0000 lapc s0,4274 <.*>
-[ 0-9a-f]+: 7a20 0000 lapc s1,4278 <.*>
-[ 0-9a-f]+: 7a23 ffff lapc s1,104278 <.*>
-[ 0-9a-f]+: 7a24 0000 lapc s1,fff04280 <.*>
+[ 0-9a-f]+: 7840 0000 lapc v0,421c <.*>
+[ 0-9a-f]+: 7860 0000 lapc v1,4220 <.*>
+[ 0-9a-f]+: 7880 0000 lapc a0,4224 <.*>
+[ 0-9a-f]+: 78a0 0000 lapc a1,4228 <.*>
+[ 0-9a-f]+: 78c0 0000 lapc a2,422c <.*>
+[ 0-9a-f]+: 78e0 0000 lapc a3,4230 <.*>
+[ 0-9a-f]+: 7a00 0000 lapc s0,4234 <.*>
+[ 0-9a-f]+: 7a20 0000 lapc s1,4238 <.*>
+[ 0-9a-f]+: 7a23 ffff lapc s1,104238 <.*>
+[ 0-9a-f]+: 7a24 0000 lapc s1,fff04240 <.*>
+[ 0-9a-f]+: 7840 0000 lapc v0,4244 <.*>
+[ 0-9a-f]+: 7860 0000 lapc v1,4248 <.*>
+[ 0-9a-f]+: 7880 0000 lapc a0,424c <.*>
+[ 0-9a-f]+: 78a0 0000 lapc a1,4250 <.*>
+[ 0-9a-f]+: 78c0 0000 lapc a2,4254 <.*>
+[ 0-9a-f]+: 78e0 0000 lapc a3,4258 <.*>
+[ 0-9a-f]+: 7a00 0000 lapc s0,425c <.*>
+[ 0-9a-f]+: 7a20 0000 lapc s1,4260 <.*>
+[ 0-9a-f]+: 7a23 ffff lapc s1,104260 <.*>
+[ 0-9a-f]+: 7a24 0000 lapc s1,fff04268 <.*>
[0-9a-f]+ <test_spec107>:
[ 0-9a-f]+: 0000 2a90 move a1,zero
diff --git a/gas/testsuite/gas/mips/micromipsr6@micromips.d b/gas/testsuite/gas/mips/micromipsr6@micromips.d
index 140d72af665..f0d5f89da75 100644
--- a/gas/testsuite/gas/mips/micromipsr6@micromips.d
+++ b/gas/testsuite/gas/mips/micromipsr6@micromips.d
@@ -8,4488 +8,4482 @@
Disassembly of section .text:
[ 0-9a-f]+ <test>:
- [0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
- [0-9a-f]+: 6000 20ff pref 0x0,255\(zero\)
- [0-9a-f]+: 6000 2100 pref 0x0,-256\(zero\)
- [0-9a-f]+: 3020 0100 li at,256
- [0-9a-f]+: 6001 2000 pref 0x0,0\(at\)
- [0-9a-f]+: 3020 feff li at,-257
- [0-9a-f]+: 6001 2000 pref 0x0,0\(at\)
- [0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
- [0-9a-f]+: 6000 2000 pref 0x0,0\(zero\)
- [0-9a-f]+: 6020 2000 pref 0x1,0\(zero\)
- [0-9a-f]+: 6040 2000 pref 0x2,0\(zero\)
- [0-9a-f]+: 6060 2000 pref 0x3,0\(zero\)
- [0-9a-f]+: 6080 2000 pref 0x4,0\(zero\)
- [0-9a-f]+: 60a0 2000 pref 0x5,0\(zero\)
- [0-9a-f]+: 60c0 2000 pref 0x6,0\(zero\)
- [0-9a-f]+: 60e0 2000 pref 0x7,0\(zero\)
- [0-9a-f]+: 60e0 207f pref 0x7,127\(zero\)
- [0-9a-f]+: 60e0 2180 pref 0x7,-128\(zero\)
- [0-9a-f]+: 63e0 20ff pref 0x1f,255\(zero\)
- [0-9a-f]+: 63e0 2100 pref 0x1f,-256\(zero\)
- [0-9a-f]+: 3020 0100 li at,256
- [0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
- [0-9a-f]+: 3020 feff li at,-257
- [0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
- [0-9a-f]+: 3020 7fff li at,32767
- [0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
- [0-9a-f]+: 3020 8000 li at,-32768
- [0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
- [0-9a-f]+: 63e2 20ff pref 0x1f,255\(v0\)
- [0-9a-f]+: 63e2 2100 pref 0x1f,-256\(v0\)
- [0-9a-f]+: 3022 0100 addiu at,v0,256
- [0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
- [0-9a-f]+: 3022 feff addiu at,v0,-257
- [0-9a-f]+: 63e1 2000 pref 0x1f,0\(at\)
- [0-9a-f]+: 3022 7fff addiu at,v0,32767
- [0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
- [0-9a-f]+: 3022 8000 addiu at,v0,-32768
- [0-9a-f]+: 6061 2000 pref 0x3,0\(at\)
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 0000 0000 nop
- [0-9a-f]+: 0000 0800 ssnop
- [0-9a-f]+: 0000 1800 ehb
- [0-9a-f]+: 0000 2800 pause
- [0-9a-f]+: ed7f li v0,-1
- [0-9a-f]+: edff li v1,-1
- [0-9a-f]+: ee7f li a0,-1
- [0-9a-f]+: eeff li a1,-1
- [0-9a-f]+: ef7f li a2,-1
- [0-9a-f]+: efff li a3,-1
- [0-9a-f]+: ec7f li s0,-1
- [0-9a-f]+: ecff li s1,-1
- [0-9a-f]+: ec80 li s1,0
- [0-9a-f]+: ecfd li s1,125
- [0-9a-f]+: ecfe li s1,126
- [0-9a-f]+: 3220 007f li s1,127
- [0-9a-f]+: 3040 0000 li v0,0
- [0-9a-f]+: 3040 0001 li v0,1
- [0-9a-f]+: 3040 7fff li v0,32767
- [0-9a-f]+: 3040 8000 li v0,-32768
- [0-9a-f]+: 5040 ffff li v0,0xffff
- [0-9a-f]+: 1040 0001 lui v0,0x1
- [0-9a-f]+: 3040 8000 li v0,-32768
- [0-9a-f]+: 3040 8001 li v0,-32767
- [0-9a-f]+: 3040 ffff li v0,-1
- [0-9a-f]+: 1040 1234 lui v0,0x1234
- [0-9a-f]+: 5042 5678 ori v0,v0,0x5678
- [0-9a-f]+: 0c16 move zero,s6
- [0-9a-f]+: 0c56 move v0,s6
- [0-9a-f]+: 0c76 move v1,s6
- [0-9a-f]+: 0c96 move a0,s6
- [0-9a-f]+: 0cb6 move a1,s6
- [0-9a-f]+: 0cd6 move a2,s6
- [0-9a-f]+: 0cf6 move a3,s6
- [0-9a-f]+: 0d16 move t0,s6
- [0-9a-f]+: 0d36 move t1,s6
- [0-9a-f]+: 0d56 move t2,s6
- [0-9a-f]+: 0fd6 move s8,s6
- [0-9a-f]+: 0ff6 move ra,s6
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 0c02 move zero,v0
- [0-9a-f]+: 0c03 move zero,v1
- [0-9a-f]+: 0c04 move zero,a0
- [0-9a-f]+: 0c05 move zero,a1
- [0-9a-f]+: 0c06 move zero,a2
- [0-9a-f]+: 0c07 move zero,a3
- [0-9a-f]+: 0c08 move zero,t0
- [0-9a-f]+: 0c09 move zero,t1
- [0-9a-f]+: 0c0a move zero,t2
- [0-9a-f]+: 0c1e move zero,s8
- [0-9a-f]+: 0c1f move zero,ra
- [0-9a-f]+: 0ec2 move s6,v0
- [0-9a-f]+: 0c56 move v0,s6
- [0-9a-f]+: 0ec2 move s6,v0
- [0-9a-f]+: 0016 1290 move v0,s6
- [0-9a-f]+: 0002 b290 move s6,v0
- [0-9a-f]+: cfff bc 130 <.*>
- [0-9a-f]+: R_MICROMIPS_PC10_S1 test
- [0-9a-f]+: cfff bc 132 <.*>
- [0-9a-f]+: R_MICROMIPS_PC10_S1 test
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 93fe 0000 slti ra,s8,0
- [0-9a-f]+: R_MICROMIPS_PC26_S1 test
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: cfff bc 13c <.*>
- [0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
- [0-9a-f]+: cfff bc 13e <.*>
- [0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 93fe 0000 slti ra,s8,0
- [0-9a-f]+: R_MICROMIPS_PC26_S1 \.L1\^B1
+[ ]*[0-9a-f]+: [ ]*6000 2000 pref 0x0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6000 20ff pref 0x0,255\(zero\)
+[ ]*[0-9a-f]+: [ ]*6000 2100 pref 0x0,-256\(zero\)
+[ ]*[0-9a-f]+: [ ]*3020 0100 li at,256
+[ ]*[0-9a-f]+: [ ]*6001 2000 pref 0x0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 feff li at,-257
+[ ]*[0-9a-f]+: [ ]*6001 2000 pref 0x0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*6000 2000 pref 0x0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6000 2000 pref 0x0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6020 2000 pref 0x1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 2000 pref 0x2,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6060 2000 pref 0x3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6080 2000 pref 0x4,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*60a0 2000 pref 0x5,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*60c0 2000 pref 0x6,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*60e0 2000 pref 0x7,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*60e0 207f pref 0x7,127\(zero\)
+[ ]*[0-9a-f]+: [ ]*60e0 2180 pref 0x7,-128\(zero\)
+[ ]*[0-9a-f]+: [ ]*63e0 20ff pref 0x1f,255\(zero\)
+[ ]*[0-9a-f]+: [ ]*63e0 2100 pref 0x1f,-256\(zero\)
+[ ]*[0-9a-f]+: [ ]*3020 0100 li at,256
+[ ]*[0-9a-f]+: [ ]*63e1 2000 pref 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 feff li at,-257
+[ ]*[0-9a-f]+: [ ]*63e1 2000 pref 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*6061 2000 pref 0x3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*6061 2000 pref 0x3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*63e2 20ff pref 0x1f,255\(v0\)
+[ ]*[0-9a-f]+: [ ]*63e2 2100 pref 0x1f,-256\(v0\)
+[ ]*[0-9a-f]+: [ ]*3022 0100 addiu at,v0,256
+[ ]*[0-9a-f]+: [ ]*63e1 2000 pref 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3022 feff addiu at,v0,-257
+[ ]*[0-9a-f]+: [ ]*63e1 2000 pref 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3022 7fff addiu at,v0,32767
+[ ]*[0-9a-f]+: [ ]*6061 2000 pref 0x3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3022 8000 addiu at,v0,-32768
+[ ]*[0-9a-f]+: [ ]*6061 2000 pref 0x3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*0000 0000 nop
+[ ]*[0-9a-f]+: [ ]*0000 0800 ssnop
+[ ]*[0-9a-f]+: [ ]*0000 1800 ehb
+[ ]*[0-9a-f]+: [ ]*0000 2800 pause
+[ ]*[0-9a-f]+: [ ]*ed7f li v0,-1
+[ ]*[0-9a-f]+: [ ]*edff li v1,-1
+[ ]*[0-9a-f]+: [ ]*ee7f li a0,-1
+[ ]*[0-9a-f]+: [ ]*eeff li a1,-1
+[ ]*[0-9a-f]+: [ ]*ef7f li a2,-1
+[ ]*[0-9a-f]+: [ ]*efff li a3,-1
+[ ]*[0-9a-f]+: [ ]*ec7f li s0,-1
+[ ]*[0-9a-f]+: [ ]*ecff li s1,-1
+[ ]*[0-9a-f]+: [ ]*ec80 li s1,0
+[ ]*[0-9a-f]+: [ ]*ecfd li s1,125
+[ ]*[0-9a-f]+: [ ]*ecfe li s1,126
+[ ]*[0-9a-f]+: [ ]*3220 007f li s1,127
+[ ]*[0-9a-f]+: [ ]*3040 0000 li v0,0
+[ ]*[0-9a-f]+: [ ]*3040 0001 li v0,1
+[ ]*[0-9a-f]+: [ ]*3040 7fff li v0,32767
+[ ]*[0-9a-f]+: [ ]*3040 8000 li v0,-32768
+[ ]*[0-9a-f]+: [ ]*5040 ffff li v0,0xffff
+[ ]*[0-9a-f]+: [ ]*1040 0001 lui v0,0x1
+[ ]*[0-9a-f]+: [ ]*3040 8000 li v0,-32768
+[ ]*[0-9a-f]+: [ ]*3040 8001 li v0,-32767
+[ ]*[0-9a-f]+: [ ]*3040 ffff li v0,-1
+[ ]*[0-9a-f]+: [ ]*1040 1234 lui v0,0x1234
+[ ]*[0-9a-f]+: [ ]*5042 5678 ori v0,v0,0x5678
+[ ]*[0-9a-f]+: [ ]*0c16 move zero,s6
+[ ]*[0-9a-f]+: [ ]*0c56 move v0,s6
+[ ]*[0-9a-f]+: [ ]*0c76 move v1,s6
+[ ]*[0-9a-f]+: [ ]*0c96 move a0,s6
+[ ]*[0-9a-f]+: [ ]*0cb6 move a1,s6
+[ ]*[0-9a-f]+: [ ]*0cd6 move a2,s6
+[ ]*[0-9a-f]+: [ ]*0cf6 move a3,s6
+[ ]*[0-9a-f]+: [ ]*0d16 move t0,s6
+[ ]*[0-9a-f]+: [ ]*0d36 move t1,s6
+[ ]*[0-9a-f]+: [ ]*0d56 move t2,s6
+[ ]*[0-9a-f]+: [ ]*0fd6 move s8,s6
+[ ]*[0-9a-f]+: [ ]*0ff6 move ra,s6
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*0c02 move zero,v0
+[ ]*[0-9a-f]+: [ ]*0c03 move zero,v1
+[ ]*[0-9a-f]+: [ ]*0c04 move zero,a0
+[ ]*[0-9a-f]+: [ ]*0c05 move zero,a1
+[ ]*[0-9a-f]+: [ ]*0c06 move zero,a2
+[ ]*[0-9a-f]+: [ ]*0c07 move zero,a3
+[ ]*[0-9a-f]+: [ ]*0c08 move zero,t0
+[ ]*[0-9a-f]+: [ ]*0c09 move zero,t1
+[ ]*[0-9a-f]+: [ ]*0c0a move zero,t2
+[ ]*[0-9a-f]+: [ ]*0c1e move zero,s8
+[ ]*[0-9a-f]+: [ ]*0c1f move zero,ra
+[ ]*[0-9a-f]+: [ ]*0ec2 move s6,v0
+[ ]*[0-9a-f]+: [ ]*0c56 move v0,s6
+[ ]*[0-9a-f]+: [ ]*0ec2 move s6,v0
+[ ]*[0-9a-f]+: [ ]*0016 1290 move v0,s6
+[ ]*[0-9a-f]+: [ ]*0002 b290 move s6,v0
+[ ]*[0-9a-f]+: [ ]*cfff bc 130 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 test
+[ ]*[0-9a-f]+: [ ]*cfff bc 132 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 test
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*93fe 0000 slti ra,s8,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 test
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*cfff bc 13c <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
+[ ]*[0-9a-f]+: [ ]*cfff bc 13e <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*93fe 0000 slti ra,s8,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 \.L1\^B1
[ 0-9a-f]+ <\.L1\^B1>:
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: cfff bc 148 <.*>
- [0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
- [0-9a-f]+: cfff bc 14a <.*>
- [0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 93fe 0000 slti ra,s8,0
- [0-9a-f]+: R_MICROMIPS_PC26_S1 \.L1\^B1
- [0-9a-f]+: 0c43 move v0,v1
- [0-9a-f]+: f463 fffe bgezc v1,154 <.*>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_0
- [0-9a-f]+: 0060 1190 neg v0,v1
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*cfff bc 148 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
+[ ]*[0-9a-f]+: [ ]*cfff bc 14a <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 \.L1\^B1
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*93fe 0000 slti ra,s8,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 \.L1\^B1
+[ ]*[0-9a-f]+: [ ]*0c43 move v0,v1
+[ ]*[0-9a-f]+: [ ]*f463 fffe bgezc v1,154 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_0
+[ ]*[0-9a-f]+: [ ]*0060 1190 neg v0,v1
[ 0-9a-f]+ <\.L\^\_0>:
- [0-9a-f]+: 0c44 move v0,a0
- [0-9a-f]+: f484 fffe bgezc a0,15e <.*>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_1
- [0-9a-f]+: 0080 1190 neg v0,a0
+[ ]*[0-9a-f]+: [ ]*0c44 move v0,a0
+[ ]*[0-9a-f]+: [ ]*f484 fffe bgezc a0,15e <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_1
+[ ]*[0-9a-f]+: [ ]*0080 1190 neg v0,a0
[ 0-9a-f]+ <\.L\^\_1>:
- [0-9a-f]+: f442 fffe bgezc v0,166 <\.L\^\_1>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_2
- [0-9a-f]+: 0040 1190 neg v0,v0
+[ ]*[0-9a-f]+: [ ]*f442 fffe bgezc v0,166 <\.L\^\_1>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_2
+[ ]*[0-9a-f]+: [ ]*0040 1190 neg v0,v0
[ 0-9a-f]+ <\.L\^\_2>:
- [0-9a-f]+: f442 fffe bgezc v0,16e <\.L\^\_2>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_3
- [0-9a-f]+: 0040 1190 neg v0,v0
+[ ]*[0-9a-f]+: [ ]*f442 fffe bgezc v0,16e <\.L\^\_2>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_3
+[ ]*[0-9a-f]+: [ ]*0040 1190 neg v0,v0
[ 0-9a-f]+ <\.L\^\_3>:
- [0-9a-f]+: 0083 1110 add v0,v1,a0
- [0-9a-f]+: 03fe e910 add sp,s8,ra
- [0-9a-f]+: 0082 1110 add v0,v0,a0
- [0-9a-f]+: 0082 1110 add v0,v0,a0
- [0-9a-f]+: 4c10 addiu zero,zero,-8
- [0-9a-f]+: 4c50 addiu v0,v0,-8
- [0-9a-f]+: 4c70 addiu v1,v1,-8
- [0-9a-f]+: 4c90 addiu a0,a0,-8
- [0-9a-f]+: 4cb0 addiu a1,a1,-8
- [0-9a-f]+: 4cd0 addiu a2,a2,-8
- [0-9a-f]+: 4cf0 addiu a3,a3,-8
- [0-9a-f]+: 4d10 addiu t0,t0,-8
- [0-9a-f]+: 4d30 addiu t1,t1,-8
- [0-9a-f]+: 4d50 addiu t2,t2,-8
- [0-9a-f]+: 4fd0 addiu s8,s8,-8
- [0-9a-f]+: 4ff0 addiu ra,ra,-8
- [0-9a-f]+: 4ff2 addiu ra,ra,-7
- [0-9a-f]+: 4fe0 addiu ra,ra,0
- [0-9a-f]+: 4fe2 addiu ra,ra,1
- [0-9a-f]+: 4fec addiu ra,ra,6
- [0-9a-f]+: 4fee addiu ra,ra,7
- [0-9a-f]+: 33ff 0008 addiu ra,ra,8
- [0-9a-f]+: 4ffd addiu sp,sp,-1032
- [0-9a-f]+: 4fff addiu sp,sp,-1028
- [0-9a-f]+: 4e01 addiu sp,sp,-1024
- [0-9a-f]+: 4dff addiu sp,sp,1020
- [0-9a-f]+: 4c01 addiu sp,sp,1024
- [0-9a-f]+: 4c03 addiu sp,sp,1028
- [0-9a-f]+: 4c03 addiu sp,sp,1028
- [0-9a-f]+: 33bd 0408 addiu sp,sp,1032
- [0-9a-f]+: 6d2e addiu v0,v0,-1
- [0-9a-f]+: 6d3e addiu v0,v1,-1
- [0-9a-f]+: 6d4e addiu v0,a0,-1
- [0-9a-f]+: 6d5e addiu v0,a1,-1
- [0-9a-f]+: 6d6e addiu v0,a2,-1
- [0-9a-f]+: 6d7e addiu v0,a3,-1
- [0-9a-f]+: 6d0e addiu v0,s0,-1
- [0-9a-f]+: 6d1e addiu v0,s1,-1
- [0-9a-f]+: 6d10 addiu v0,s1,1
- [0-9a-f]+: 6d12 addiu v0,s1,4
- [0-9a-f]+: 6d14 addiu v0,s1,8
- [0-9a-f]+: 6d16 addiu v0,s1,12
- [0-9a-f]+: 6d18 addiu v0,s1,16
- [0-9a-f]+: 6d1a addiu v0,s1,20
- [0-9a-f]+: 6d1c addiu v0,s1,24
- [0-9a-f]+: 6d9c addiu v1,s1,24
- [0-9a-f]+: 6e1c addiu a0,s1,24
- [0-9a-f]+: 6e9c addiu a1,s1,24
- [0-9a-f]+: 6f1c addiu a2,s1,24
- [0-9a-f]+: 6f9c addiu a3,s1,24
- [0-9a-f]+: 6c1c addiu s0,s1,24
- [0-9a-f]+: 6c9c addiu s1,s1,24
- [0-9a-f]+: 0c5d move v0,sp
- [0-9a-f]+: 6d03 addiu v0,sp,4
- [0-9a-f]+: 6d7d addiu v0,sp,248
- [0-9a-f]+: 6d7f addiu v0,sp,252
- [0-9a-f]+: 305d 0100 addiu v0,sp,256
- [0-9a-f]+: 6d7f addiu v0,sp,252
- [0-9a-f]+: 6dff addiu v1,sp,252
- [0-9a-f]+: 6e7f addiu a0,sp,252
- [0-9a-f]+: 6eff addiu a1,sp,252
- [0-9a-f]+: 6f7f addiu a2,sp,252
- [0-9a-f]+: 6fff addiu a3,sp,252
- [0-9a-f]+: 6c7f addiu s0,sp,252
- [0-9a-f]+: 6cff addiu s1,sp,252
- [0-9a-f]+: 3064 8000 addiu v1,a0,-32768
- [0-9a-f]+: 0c64 move v1,a0
- [0-9a-f]+: 3064 7fff addiu v1,a0,32767
- [0-9a-f]+: 3064 ffff addiu v1,a0,-1
- [0-9a-f]+: 3063 ffff addiu v1,v1,-1
- [0-9a-f]+: 3063 ffff addiu v1,v1,-1
- [0-9a-f]+: 0c56 move v0,s6
- [0-9a-f]+: 0ec2 move s6,v0
- [0-9a-f]+: 0c56 move v0,s6
- [0-9a-f]+: 0ec2 move s6,v0
- [0-9a-f]+: 05a4 addu v0,v1,v0
- [0-9a-f]+: 05b4 addu v0,v1,v1
- [0-9a-f]+: 05c4 addu v0,v1,a0
- [0-9a-f]+: 05d4 addu v0,v1,a1
- [0-9a-f]+: 05e4 addu v0,v1,a2
- [0-9a-f]+: 05f4 addu v0,v1,a3
- [0-9a-f]+: 0584 addu v0,v1,s0
- [0-9a-f]+: 0594 addu v0,v1,s1
- [0-9a-f]+: 0514 addu v0,v0,s1
- [0-9a-f]+: 0594 addu v0,v1,s1
- [0-9a-f]+: 0614 addu v0,a0,s1
- [0-9a-f]+: 0694 addu v0,a1,s1
- [0-9a-f]+: 0714 addu v0,a2,s1
- [0-9a-f]+: 0794 addu v0,a3,s1
- [0-9a-f]+: 0414 addu v0,s0,s1
- [0-9a-f]+: 0494 addu v0,s1,s1
- [0-9a-f]+: 0514 addu v0,v0,s1
- [0-9a-f]+: 0516 addu v1,v0,s1
- [0-9a-f]+: 0518 addu a0,v0,s1
- [0-9a-f]+: 051a addu a1,v0,s1
- [0-9a-f]+: 051c addu a2,v0,s1
- [0-9a-f]+: 051e addu a3,v0,s1
- [0-9a-f]+: 0510 addu s0,v0,s1
- [0-9a-f]+: 0512 addu s1,v0,s1
- [0-9a-f]+: 07ae addu a3,a3,v0
- [0-9a-f]+: 07ae addu a3,a3,v0
- [0-9a-f]+: 057e addu a3,v0,a3
- [0-9a-f]+: 03fe e950 addu sp,s8,ra
- [0-9a-f]+: 3042 0000 addiu v0,v0,0
- [0-9a-f]+: 3042 0001 addiu v0,v0,1
- [0-9a-f]+: 3042 7fff addiu v0,v0,32767
- [0-9a-f]+: 3042 8000 addiu v0,v0,-32768
- [0-9a-f]+: 5020 ffff li at,0xffff
- [0-9a-f]+: 0022 1150 addu v0,v0,at
- [0-9a-f]+: 4521 and v0,v0,v0
- [0-9a-f]+: 4531 and v0,v0,v1
- [0-9a-f]+: 4541 and v0,v0,a0
- [0-9a-f]+: 4551 and v0,v0,a1
- [0-9a-f]+: 4561 and v0,v0,a2
- [0-9a-f]+: 4571 and v0,v0,a3
- [0-9a-f]+: 4501 and v0,v0,s0
- [0-9a-f]+: 4511 and v0,v0,s1
- [0-9a-f]+: 45a1 and v1,v1,v0
- [0-9a-f]+: 4621 and a0,a0,v0
- [0-9a-f]+: 46a1 and a1,a1,v0
- [0-9a-f]+: 4721 and a2,a2,v0
- [0-9a-f]+: 47a1 and a3,a3,v0
- [0-9a-f]+: 4421 and s0,s0,v0
- [0-9a-f]+: 44a1 and s1,s1,v0
- [0-9a-f]+: 4531 and v0,v0,v1
- [0-9a-f]+: 4531 and v0,v0,v1
- [0-9a-f]+: 4531 and v0,v0,v1
- [0-9a-f]+: 4531 and v0,v0,v1
- [0-9a-f]+: 0062 1250 and v0,v0,v1
- [0-9a-f]+: 2d21 andi v0,v0,0x1
- [0-9a-f]+: 2d22 andi v0,v0,0x2
- [0-9a-f]+: 2d23 andi v0,v0,0x3
- [0-9a-f]+: 2d24 andi v0,v0,0x4
- [0-9a-f]+: 2d25 andi v0,v0,0x7
- [0-9a-f]+: 2d26 andi v0,v0,0x8
- [0-9a-f]+: 2d27 andi v0,v0,0xf
- [0-9a-f]+: 2d28 andi v0,v0,0x10
- [0-9a-f]+: 2d29 andi v0,v0,0x1f
- [0-9a-f]+: 2d2a andi v0,v0,0x20
- [0-9a-f]+: 2d2b andi v0,v0,0x3f
- [0-9a-f]+: 2d2c andi v0,v0,0x40
- [0-9a-f]+: 2d20 andi v0,v0,0x80
- [0-9a-f]+: 2d2d andi v0,v0,0xff
- [0-9a-f]+: 2d2e andi v0,v0,0x8000
- [0-9a-f]+: 2d2f andi v0,v0,0xffff
- [0-9a-f]+: 2d3f andi v0,v1,0xffff
- [0-9a-f]+: 2d4f andi v0,a0,0xffff
- [0-9a-f]+: 2d5f andi v0,a1,0xffff
- [0-9a-f]+: 2d6f andi v0,a2,0xffff
- [0-9a-f]+: 2d7f andi v0,a3,0xffff
- [0-9a-f]+: 2d0f andi v0,s0,0xffff
- [0-9a-f]+: 2d1f andi v0,s1,0xffff
- [0-9a-f]+: 2d9f andi v1,s1,0xffff
- [0-9a-f]+: 2e1f andi a0,s1,0xffff
- [0-9a-f]+: 2e9f andi a1,s1,0xffff
- [0-9a-f]+: 2f1f andi a2,s1,0xffff
- [0-9a-f]+: 2f9f andi a3,s1,0xffff
- [0-9a-f]+: 2c1f andi s0,s1,0xffff
- [0-9a-f]+: 2c9f andi s1,s1,0xffff
- [0-9a-f]+: 2fff andi a3,a3,0xffff
- [0-9a-f]+: 2fff andi a3,a3,0xffff
- [0-9a-f]+: 2fff andi a3,a3,0xffff
- [0-9a-f]+: d0e7 ffff andi a3,a3,0xffff
- [0-9a-f]+: 0083 1250 and v0,v1,a0
- [0-9a-f]+: 0082 1250 and v0,v0,a0
- [0-9a-f]+: 0082 1250 and v0,v0,a0
- [0-9a-f]+: d043 0000 andi v0,v1,0x0
- [0-9a-f]+: d043 ffff andi v0,v1,0xffff
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 0023 1250 and v0,v1,at
- [0-9a-f]+: 1020 ffff lui at,0xffff
- [0-9a-f]+: 5021 0001 ori at,at,0x1
- [0-9a-f]+: 0023 1250 and v0,v1,at
+[ ]*[0-9a-f]+: [ ]*0083 1110 add v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*03fe e910 add sp,s8,ra
+[ ]*[0-9a-f]+: [ ]*0082 1110 add v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0082 1110 add v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*4c10 addiu zero,zero,-8
+[ ]*[0-9a-f]+: [ ]*4c50 addiu v0,v0,-8
+[ ]*[0-9a-f]+: [ ]*4c70 addiu v1,v1,-8
+[ ]*[0-9a-f]+: [ ]*4c90 addiu a0,a0,-8
+[ ]*[0-9a-f]+: [ ]*4cb0 addiu a1,a1,-8
+[ ]*[0-9a-f]+: [ ]*4cd0 addiu a2,a2,-8
+[ ]*[0-9a-f]+: [ ]*4cf0 addiu a3,a3,-8
+[ ]*[0-9a-f]+: [ ]*4d10 addiu t0,t0,-8
+[ ]*[0-9a-f]+: [ ]*4d30 addiu t1,t1,-8
+[ ]*[0-9a-f]+: [ ]*4d50 addiu t2,t2,-8
+[ ]*[0-9a-f]+: [ ]*4fd0 addiu s8,s8,-8
+[ ]*[0-9a-f]+: [ ]*4ff0 addiu ra,ra,-8
+[ ]*[0-9a-f]+: [ ]*4ff2 addiu ra,ra,-7
+[ ]*[0-9a-f]+: [ ]*4fe0 addiu ra,ra,0
+[ ]*[0-9a-f]+: [ ]*4fe2 addiu ra,ra,1
+[ ]*[0-9a-f]+: [ ]*4fec addiu ra,ra,6
+[ ]*[0-9a-f]+: [ ]*4fee addiu ra,ra,7
+[ ]*[0-9a-f]+: [ ]*33ff 0008 addiu ra,ra,8
+[ ]*[0-9a-f]+: [ ]*4ffd addiu sp,sp,-1032
+[ ]*[0-9a-f]+: [ ]*4fff addiu sp,sp,-1028
+[ ]*[0-9a-f]+: [ ]*4e01 addiu sp,sp,-1024
+[ ]*[0-9a-f]+: [ ]*4dff addiu sp,sp,1020
+[ ]*[0-9a-f]+: [ ]*4c01 addiu sp,sp,1024
+[ ]*[0-9a-f]+: [ ]*4c03 addiu sp,sp,1028
+[ ]*[0-9a-f]+: [ ]*4c03 addiu sp,sp,1028
+[ ]*[0-9a-f]+: [ ]*33bd 0408 addiu sp,sp,1032
+[ ]*[0-9a-f]+: [ ]*6d2e addiu v0,v0,-1
+[ ]*[0-9a-f]+: [ ]*6d3e addiu v0,v1,-1
+[ ]*[0-9a-f]+: [ ]*6d4e addiu v0,a0,-1
+[ ]*[0-9a-f]+: [ ]*6d5e addiu v0,a1,-1
+[ ]*[0-9a-f]+: [ ]*6d6e addiu v0,a2,-1
+[ ]*[0-9a-f]+: [ ]*6d7e addiu v0,a3,-1
+[ ]*[0-9a-f]+: [ ]*6d0e addiu v0,s0,-1
+[ ]*[0-9a-f]+: [ ]*6d1e addiu v0,s1,-1
+[ ]*[0-9a-f]+: [ ]*6d10 addiu v0,s1,1
+[ ]*[0-9a-f]+: [ ]*6d12 addiu v0,s1,4
+[ ]*[0-9a-f]+: [ ]*6d14 addiu v0,s1,8
+[ ]*[0-9a-f]+: [ ]*6d16 addiu v0,s1,12
+[ ]*[0-9a-f]+: [ ]*6d18 addiu v0,s1,16
+[ ]*[0-9a-f]+: [ ]*6d1a addiu v0,s1,20
+[ ]*[0-9a-f]+: [ ]*6d1c addiu v0,s1,24
+[ ]*[0-9a-f]+: [ ]*6d9c addiu v1,s1,24
+[ ]*[0-9a-f]+: [ ]*6e1c addiu a0,s1,24
+[ ]*[0-9a-f]+: [ ]*6e9c addiu a1,s1,24
+[ ]*[0-9a-f]+: [ ]*6f1c addiu a2,s1,24
+[ ]*[0-9a-f]+: [ ]*6f9c addiu a3,s1,24
+[ ]*[0-9a-f]+: [ ]*6c1c addiu s0,s1,24
+[ ]*[0-9a-f]+: [ ]*6c9c addiu s1,s1,24
+[ ]*[0-9a-f]+: [ ]*0c5d move v0,sp
+[ ]*[0-9a-f]+: [ ]*6d03 addiu v0,sp,4
+[ ]*[0-9a-f]+: [ ]*6d7d addiu v0,sp,248
+[ ]*[0-9a-f]+: [ ]*6d7f addiu v0,sp,252
+[ ]*[0-9a-f]+: [ ]*305d 0100 addiu v0,sp,256
+[ ]*[0-9a-f]+: [ ]*6d7f addiu v0,sp,252
+[ ]*[0-9a-f]+: [ ]*6dff addiu v1,sp,252
+[ ]*[0-9a-f]+: [ ]*6e7f addiu a0,sp,252
+[ ]*[0-9a-f]+: [ ]*6eff addiu a1,sp,252
+[ ]*[0-9a-f]+: [ ]*6f7f addiu a2,sp,252
+[ ]*[0-9a-f]+: [ ]*6fff addiu a3,sp,252
+[ ]*[0-9a-f]+: [ ]*6c7f addiu s0,sp,252
+[ ]*[0-9a-f]+: [ ]*6cff addiu s1,sp,252
+[ ]*[0-9a-f]+: [ ]*3064 8000 addiu v1,a0,-32768
+[ ]*[0-9a-f]+: [ ]*0c64 move v1,a0
+[ ]*[0-9a-f]+: [ ]*3064 7fff addiu v1,a0,32767
+[ ]*[0-9a-f]+: [ ]*3064 ffff addiu v1,a0,-1
+[ ]*[0-9a-f]+: [ ]*3063 ffff addiu v1,v1,-1
+[ ]*[0-9a-f]+: [ ]*3063 ffff addiu v1,v1,-1
+[ ]*[0-9a-f]+: [ ]*0c56 move v0,s6
+[ ]*[0-9a-f]+: [ ]*0ec2 move s6,v0
+[ ]*[0-9a-f]+: [ ]*0c56 move v0,s6
+[ ]*[0-9a-f]+: [ ]*0ec2 move s6,v0
+[ ]*[0-9a-f]+: [ ]*05a4 addu v0,v1,v0
+[ ]*[0-9a-f]+: [ ]*05b4 addu v0,v1,v1
+[ ]*[0-9a-f]+: [ ]*05c4 addu v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*05d4 addu v0,v1,a1
+[ ]*[0-9a-f]+: [ ]*05e4 addu v0,v1,a2
+[ ]*[0-9a-f]+: [ ]*05f4 addu v0,v1,a3
+[ ]*[0-9a-f]+: [ ]*0584 addu v0,v1,s0
+[ ]*[0-9a-f]+: [ ]*0594 addu v0,v1,s1
+[ ]*[0-9a-f]+: [ ]*0514 addu v0,v0,s1
+[ ]*[0-9a-f]+: [ ]*0594 addu v0,v1,s1
+[ ]*[0-9a-f]+: [ ]*0614 addu v0,a0,s1
+[ ]*[0-9a-f]+: [ ]*0694 addu v0,a1,s1
+[ ]*[0-9a-f]+: [ ]*0714 addu v0,a2,s1
+[ ]*[0-9a-f]+: [ ]*0794 addu v0,a3,s1
+[ ]*[0-9a-f]+: [ ]*0414 addu v0,s0,s1
+[ ]*[0-9a-f]+: [ ]*0494 addu v0,s1,s1
+[ ]*[0-9a-f]+: [ ]*0514 addu v0,v0,s1
+[ ]*[0-9a-f]+: [ ]*0516 addu v1,v0,s1
+[ ]*[0-9a-f]+: [ ]*0518 addu a0,v0,s1
+[ ]*[0-9a-f]+: [ ]*051a addu a1,v0,s1
+[ ]*[0-9a-f]+: [ ]*051c addu a2,v0,s1
+[ ]*[0-9a-f]+: [ ]*051e addu a3,v0,s1
+[ ]*[0-9a-f]+: [ ]*0510 addu s0,v0,s1
+[ ]*[0-9a-f]+: [ ]*0512 addu s1,v0,s1
+[ ]*[0-9a-f]+: [ ]*07ae addu a3,a3,v0
+[ ]*[0-9a-f]+: [ ]*07ae addu a3,a3,v0
+[ ]*[0-9a-f]+: [ ]*057e addu a3,v0,a3
+[ ]*[0-9a-f]+: [ ]*03fe e950 addu sp,s8,ra
+[ ]*[0-9a-f]+: [ ]*3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: [ ]*3042 0001 addiu v0,v0,1
+[ ]*[0-9a-f]+: [ ]*3042 7fff addiu v0,v0,32767
+[ ]*[0-9a-f]+: [ ]*3042 8000 addiu v0,v0,-32768
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*0022 1150 addu v0,v0,at
+[ ]*[0-9a-f]+: [ ]*4521 and v0,v0,v0
+[ ]*[0-9a-f]+: [ ]*4531 and v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*4541 and v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*4551 and v0,v0,a1
+[ ]*[0-9a-f]+: [ ]*4561 and v0,v0,a2
+[ ]*[0-9a-f]+: [ ]*4571 and v0,v0,a3
+[ ]*[0-9a-f]+: [ ]*4501 and v0,v0,s0
+[ ]*[0-9a-f]+: [ ]*4511 and v0,v0,s1
+[ ]*[0-9a-f]+: [ ]*45a1 and v1,v1,v0
+[ ]*[0-9a-f]+: [ ]*4621 and a0,a0,v0
+[ ]*[0-9a-f]+: [ ]*46a1 and a1,a1,v0
+[ ]*[0-9a-f]+: [ ]*4721 and a2,a2,v0
+[ ]*[0-9a-f]+: [ ]*47a1 and a3,a3,v0
+[ ]*[0-9a-f]+: [ ]*4421 and s0,s0,v0
+[ ]*[0-9a-f]+: [ ]*44a1 and s1,s1,v0
+[ ]*[0-9a-f]+: [ ]*4531 and v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*4531 and v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*4531 and v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*4531 and v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*0062 1250 and v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*2d21 andi v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*2d22 andi v0,v0,0x2
+[ ]*[0-9a-f]+: [ ]*2d23 andi v0,v0,0x3
+[ ]*[0-9a-f]+: [ ]*2d24 andi v0,v0,0x4
+[ ]*[0-9a-f]+: [ ]*2d25 andi v0,v0,0x7
+[ ]*[0-9a-f]+: [ ]*2d26 andi v0,v0,0x8
+[ ]*[0-9a-f]+: [ ]*2d27 andi v0,v0,0xf
+[ ]*[0-9a-f]+: [ ]*2d28 andi v0,v0,0x10
+[ ]*[0-9a-f]+: [ ]*2d29 andi v0,v0,0x1f
+[ ]*[0-9a-f]+: [ ]*2d2a andi v0,v0,0x20
+[ ]*[0-9a-f]+: [ ]*2d2b andi v0,v0,0x3f
+[ ]*[0-9a-f]+: [ ]*2d2c andi v0,v0,0x40
+[ ]*[0-9a-f]+: [ ]*2d20 andi v0,v0,0x80
+[ ]*[0-9a-f]+: [ ]*2d2d andi v0,v0,0xff
+[ ]*[0-9a-f]+: [ ]*2d2e andi v0,v0,0x8000
+[ ]*[0-9a-f]+: [ ]*2d2f andi v0,v0,0xffff
+[ ]*[0-9a-f]+: [ ]*2d3f andi v0,v1,0xffff
+[ ]*[0-9a-f]+: [ ]*2d4f andi v0,a0,0xffff
+[ ]*[0-9a-f]+: [ ]*2d5f andi v0,a1,0xffff
+[ ]*[0-9a-f]+: [ ]*2d6f andi v0,a2,0xffff
+[ ]*[0-9a-f]+: [ ]*2d7f andi v0,a3,0xffff
+[ ]*[0-9a-f]+: [ ]*2d0f andi v0,s0,0xffff
+[ ]*[0-9a-f]+: [ ]*2d1f andi v0,s1,0xffff
+[ ]*[0-9a-f]+: [ ]*2d9f andi v1,s1,0xffff
+[ ]*[0-9a-f]+: [ ]*2e1f andi a0,s1,0xffff
+[ ]*[0-9a-f]+: [ ]*2e9f andi a1,s1,0xffff
+[ ]*[0-9a-f]+: [ ]*2f1f andi a2,s1,0xffff
+[ ]*[0-9a-f]+: [ ]*2f9f andi a3,s1,0xffff
+[ ]*[0-9a-f]+: [ ]*2c1f andi s0,s1,0xffff
+[ ]*[0-9a-f]+: [ ]*2c9f andi s1,s1,0xffff
+[ ]*[0-9a-f]+: [ ]*2fff andi a3,a3,0xffff
+[ ]*[0-9a-f]+: [ ]*2fff andi a3,a3,0xffff
+[ ]*[0-9a-f]+: [ ]*2fff andi a3,a3,0xffff
+[ ]*[0-9a-f]+: [ ]*d0e7 ffff andi a3,a3,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1250 and v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0082 1250 and v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0082 1250 and v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*d043 0000 andi v0,v1,0x0
+[ ]*[0-9a-f]+: [ ]*d043 ffff andi v0,v1,0xffff
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0023 1250 and v0,v1,at
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*5021 0001 ori at,at,0x1
+[ ]*[0-9a-f]+: [ ]*0023 1250 and v0,v1,at
[ 0-9a-f]+ <test2>:
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8d7f beqzc v0,310 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8dff beqzc v1,314 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8e7f beqzc a0,318 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8eff beqzc a1,31c <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8f7f beqzc a2,320 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8fff beqzc a3,324 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8c7f beqzc s0,328 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8cff beqzc s1,32c <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8d7f beqzc v0,330 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8dff beqzc v1,334 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8e7f beqzc a0,338 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8eff beqzc a1,33c <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8f7f beqzc a2,340 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8fff beqzc a3,344 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8c7f beqzc s0,348 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8cff beqzc s1,34c <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8d7f beqzc v0,350 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8dff beqzc v1,354 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8e7f beqzc a0,358 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8eff beqzc a1,35c <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8f7f beqzc a2,360 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8fff beqzc a3,364 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8c7f beqzc s0,368 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8cff beqzc s1,36c <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 8c7f beqzc s0,36e <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 81fe 0000 beqzc t7,fffc0376 <.*>
- [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 8cff beqzc s1,378 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 821e 0000 beqzc s0,fffc0380 <.*>
- [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
- [0-9a-f]+: 8cff beqzc s1,380 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 81fe 0000 beqzc t7,fffc0388 <.*>
- [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
- [0-9a-f]+: 3020 000a li at,10
- [0-9a-f]+: 7601 fffe beqc at,s0,38c <.*>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 test2
- [0-9a-f]+: 3020 7fff li at,32767
- [0-9a-f]+: 7601 fffe beqc at,s0,394 <.*>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 test2
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 7601 fffe beqc at,s0,39c <.*>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: ad7f bnezc v0,3a4 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: adff bnezc v1,3a8 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: ae7f bnezc a0,3ac <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: aeff bnezc a1,3b0 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: af7f bnezc a2,3b4 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: afff bnezc a3,3b8 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: ac7f bnezc s0,3bc <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: acff bnezc s1,3c0 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: ad7f bnezc v0,3c4 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: adff bnezc v1,3c8 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: ae7f bnezc a0,3cc <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: aeff bnezc a1,3d0 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: af7f bnezc a2,3d4 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: afff bnezc a3,3d8 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: ac7f bnezc s0,3dc <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: acff bnezc s1,3e0 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: ad7f bnezc v0,3e4 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: adff bnezc v1,3e8 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: ae7f bnezc a0,3ec <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: aeff bnezc a1,3f0 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: af7f bnezc a2,3f4 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: afff bnezc a3,3f8 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: ac7f bnezc s0,3fc <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: acff bnezc s1,400 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: ac7f bnezc s0,402 <.*>
- [0-9a-f]+: R_MICROMIPS_PC7_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: a1fe 0000 bnezc t7,fffc040a <.*>
- [0-9a-f]+: R_MICROMIPS_PC21_S1 test3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: a21e 0000 bnezc s0,fffc0410 <.*>
- [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: a21e 0000 bnezc s0,fffc0416 <.*>
- [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8d7f beqzc v0,310 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8dff beqzc v1,314 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8e7f beqzc a0,318 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8eff beqzc a1,31c <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8f7f beqzc a2,320 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8fff beqzc a3,324 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8c7f beqzc s0,328 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8cff beqzc s1,32c <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8d7f beqzc v0,330 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8dff beqzc v1,334 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8e7f beqzc a0,338 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8eff beqzc a1,33c <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8f7f beqzc a2,340 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8fff beqzc a3,344 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8c7f beqzc s0,348 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8cff beqzc s1,34c <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8d7f beqzc v0,350 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8dff beqzc v1,354 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8e7f beqzc a0,358 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8eff beqzc a1,35c <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8f7f beqzc a2,360 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8fff beqzc a3,364 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8c7f beqzc s0,368 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8cff beqzc s1,36c <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*8c7f beqzc s0,36e <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*81fe 0000 beqzc t7,fffc0376 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*8cff beqzc s1,378 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*821e 0000 beqzc s0,fffc0380 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ ]*[0-9a-f]+: [ ]*8cff beqzc s1,380 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*81fe 0000 beqzc t7,fffc0388 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ ]*[0-9a-f]+: [ ]*3020 000a li at,10
+[ ]*[0-9a-f]+: [ ]*7601 fffe beqc at,s0,38c <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*7601 fffe beqc at,s0,394 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*7601 fffe beqc at,s0,39c <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*ad7f bnezc v0,3a4 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*adff bnezc v1,3a8 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*ae7f bnezc a0,3ac <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*aeff bnezc a1,3b0 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*af7f bnezc a2,3b4 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*afff bnezc a3,3b8 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*ac7f bnezc s0,3bc <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*acff bnezc s1,3c0 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*ad7f bnezc v0,3c4 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*adff bnezc v1,3c8 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*ae7f bnezc a0,3cc <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*aeff bnezc a1,3d0 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*af7f bnezc a2,3d4 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*afff bnezc a3,3d8 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*ac7f bnezc s0,3dc <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*acff bnezc s1,3e0 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*ad7f bnezc v0,3e4 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*adff bnezc v1,3e8 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*ae7f bnezc a0,3ec <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*aeff bnezc a1,3f0 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*af7f bnezc a2,3f4 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*afff bnezc a3,3f8 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*ac7f bnezc s0,3fc <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*acff bnezc s1,400 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*ac7f bnezc s0,402 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC7_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*a1fe 0000 bnezc t7,fffc040a <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 test3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*a21e 0000 bnezc s0,fffc0410 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*a21e 0000 bnezc s0,fffc0416 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 test2
[ 0-9a-f]+ <test3>:
- [0-9a-f]+: a21e 0000 bnezc s0,fffc041a <.*>
- [0-9a-f]+: R_MICROMIPS_PC21_S1 test2
- [0-9a-f]+: 441b break
- [0-9a-f]+: 441b break
- [0-9a-f]+: 445b break 0x1
- [0-9a-f]+: 449b break 0x2
- [0-9a-f]+: 44db break 0x3
- [0-9a-f]+: 451b break 0x4
- [0-9a-f]+: 455b break 0x5
- [0-9a-f]+: 459b break 0x6
- [0-9a-f]+: 45db break 0x7
- [0-9a-f]+: 461b break 0x8
- [0-9a-f]+: 465b break 0x9
- [0-9a-f]+: 469b break 0xa
- [0-9a-f]+: 46db break 0xb
- [0-9a-f]+: 471b break 0xc
- [0-9a-f]+: 475b break 0xd
- [0-9a-f]+: 479b break 0xe
- [0-9a-f]+: 47db break 0xf
- [0-9a-f]+: 003f 0007 break 0x3f
- [0-9a-f]+: 0040 0007 break 0x40
- [0-9a-f]+: 03ff 0007 break 0x3ff
- [0-9a-f]+: 03ff ffc7 break 0x3ff,0x3ff
- [0-9a-f]+: 0000 0007 break
- [0-9a-f]+: 0000 0007 break
- [0-9a-f]+: 0001 0007 break 0x1
- [0-9a-f]+: 0002 0007 break 0x2
- [0-9a-f]+: 000f 0007 break 0xf
- [0-9a-f]+: 003f 0007 break 0x3f
- [0-9a-f]+: 0040 0007 break 0x40
- [0-9a-f]+: 03ff 0007 break 0x3ff
- [0-9a-f]+: 03ff ffc7 break 0x3ff,0x3ff
- [0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
- [0-9a-f]+: 2000 6100 cache 0x0,-256\(zero\)
- [0-9a-f]+: 2000 60ff cache 0x0,255\(zero\)
- [0-9a-f]+: 3020 feff li at,-257
- [0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
- [0-9a-f]+: 3020 0100 li at,256
- [0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
- [0-9a-f]+: 2002 6000 cache 0x0,0\(v0\)
- [0-9a-f]+: 2002 6100 cache 0x0,-256\(v0\)
- [0-9a-f]+: 2002 60ff cache 0x0,255\(v0\)
- [0-9a-f]+: 3022 feff addiu at,v0,-257
- [0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
- [0-9a-f]+: 3022 0100 addiu at,v0,256
- [0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
- [0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
- [0-9a-f]+: 2000 6000 cache 0x0,0\(zero\)
- [0-9a-f]+: 2020 6000 cache 0x1,0\(zero\)
- [0-9a-f]+: 2040 6000 cache 0x2,0\(zero\)
- [0-9a-f]+: 2060 6000 cache 0x3,0\(zero\)
- [0-9a-f]+: 2080 6000 cache 0x4,0\(zero\)
- [0-9a-f]+: 20a0 6000 cache 0x5,0\(zero\)
- [0-9a-f]+: 20c0 6000 cache 0x6,0\(zero\)
- [0-9a-f]+: 23e0 6000 cache 0x1f,0\(zero\)
- [0-9a-f]+: 23e0 60ff cache 0x1f,255\(zero\)
- [0-9a-f]+: 23e0 6100 cache 0x1f,-256\(zero\)
- [0-9a-f]+: 2000 60ff cache 0x0,255\(zero\)
- [0-9a-f]+: 2000 6100 cache 0x0,-256\(zero\)
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 0061 0950 addu at,at,v1
- [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
- [0-9a-f]+: 3023 0100 addiu at,v1,256
- [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
- [0-9a-f]+: 3023 feff addiu at,v1,-257
- [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 0061 0950 addu at,at,v1
- [0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
- [0-9a-f]+: 23e3 61ff cache 0x1f,-1\(v1\)
- [0-9a-f]+: 1020 ffff lui at,0xffff
- [0-9a-f]+: 0061 0950 addu at,at,v1
- [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
- [0-9a-f]+: 1020 ffff lui at,0xffff
- [0-9a-f]+: 0061 0950 addu at,at,v1
- [0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 0061 0950 addu at,at,v1
- [0-9a-f]+: 23e1 61ff cache 0x1f,-1\(at\)
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
- [0-9a-f]+: 3020 0100 li at,256
- [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
- [0-9a-f]+: 3020 feff li at,-257
- [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
- [0-9a-f]+: 23e0 61ff cache 0x1f,-1\(zero\)
- [0-9a-f]+: 1020 ffff lui at,0xffff
- [0-9a-f]+: 23e1 6000 cache 0x1f,0\(at\)
- [0-9a-f]+: 1020 ffff lui at,0xffff
- [0-9a-f]+: 23e1 6001 cache 0x1f,1\(at\)
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 23e1 61ff cache 0x1f,-1\(at\)
- [0-9a-f]+: 0043 4b3c clo v0,v1
- [0-9a-f]+: 0062 4b3c clo v1,v0
- [0-9a-f]+: 0043 5b3c clz v0,v1
- [0-9a-f]+: 0062 5b3c clz v1,v0
- [0-9a-f]+: 0000 e37c deret
- [0-9a-f]+: 0000 477c di
- [0-9a-f]+: 0000 477c di
- [0-9a-f]+: 0002 477c di v0
- [0-9a-f]+: 0003 477c di v1
- [0-9a-f]+: 001e 477c di s8
- [0-9a-f]+: 001f 477c di ra
- [0-9a-f]+: 0062 0118 div zero,v0,v1
- [0-9a-f]+: 03fe 0118 div zero,s8,ra
- [0-9a-f]+: 0060 0118 div zero,zero,v1
- [0-9a-f]+: 03e0 0118 div zero,zero,ra
- [0-9a-f]+: 0003 1118 div v0,v1,zero
- [0-9a-f]+: 0083 1118 div v0,v1,a0
- [0-9a-f]+: 0062 0198 divu zero,v0,v1
- [0-9a-f]+: 03fe 0198 divu zero,s8,ra
- [0-9a-f]+: 0060 0198 divu zero,zero,v1
- [0-9a-f]+: 03e0 0198 divu zero,zero,ra
- [0-9a-f]+: 0003 1198 divu v0,v1,zero
- [0-9a-f]+: 0083 1198 divu v0,v1,a0
- [0-9a-f]+: 0000 577c ei
- [0-9a-f]+: 0000 577c ei
- [0-9a-f]+: 0002 577c ei v0
- [0-9a-f]+: 0003 577c ei v1
- [0-9a-f]+: 001e 577c ei s8
- [0-9a-f]+: 001f 577c ei ra
- [0-9a-f]+: 0000 f37c eret
- [0-9a-f]+: 0043 716c ext v0,v1,0x5,0xf
- [0-9a-f]+: 0043 f82c ext v0,v1,0x0,0x20
- [0-9a-f]+: 0043 07ec ext v0,v1,0x1f,0x1
- [0-9a-f]+: 03fe 07ec ext ra,s8,0x1f,0x1
- [0-9a-f]+: 0043 994c ins v0,v1,0x5,0xf
- [0-9a-f]+: 0043 f80c ins v0,v1,0x0,0x20
- [0-9a-f]+: 0043 ffcc ins v0,v1,0x1f,0x1
- [0-9a-f]+: 03fe ffcc ins ra,s8,0x1f,0x1
- [0-9a-f]+: 4403 jrc zero
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 4443 jrc v0
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 4463 jrc v1
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 4483 jrc a0
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 44a3 jrc a1
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 44c3 jrc a2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 44e3 jrc a3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 4503 jrc t0
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 47c3 jrc s8
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 47e3 jrc ra
- [0-9a-f]+: 8000 0000 jrc zero
- [0-9a-f]+: 8002 0000 jrc v0
- [0-9a-f]+: 8003 0000 jrc v1
- [0-9a-f]+: 8004 0000 jrc a0
- [0-9a-f]+: 8005 0000 jrc a1
- [0-9a-f]+: 8006 0000 jrc a2
- [0-9a-f]+: 8007 0000 jrc a3
- [0-9a-f]+: 8008 0000 jrc t0
- [0-9a-f]+: 801e 0000 jrc s8
- [0-9a-f]+: 801f 0000 jrc ra
- [0-9a-f]+: 4403 jrc zero
- [0-9a-f]+: 4443 jrc v0
- [0-9a-f]+: 4463 jrc v1
- [0-9a-f]+: 4483 jrc a0
- [0-9a-f]+: 44a3 jrc a1
- [0-9a-f]+: 44c3 jrc a2
- [0-9a-f]+: 44e3 jrc a3
- [0-9a-f]+: 4503 jrc t0
- [0-9a-f]+: 47c3 jrc s8
- [0-9a-f]+: 47e3 jrc ra
- [0-9a-f]+: 0000 1f3c jrc.hb zero
- [0-9a-f]+: 0002 1f3c jrc.hb v0
- [0-9a-f]+: 0003 1f3c jrc.hb v1
- [0-9a-f]+: 0004 1f3c jrc.hb a0
- [0-9a-f]+: 0005 1f3c jrc.hb a1
- [0-9a-f]+: 0006 1f3c jrc.hb a2
- [0-9a-f]+: 0007 1f3c jrc.hb a3
- [0-9a-f]+: 0008 1f3c jrc.hb t0
- [0-9a-f]+: 001e 1f3c jrc.hb s8
- [0-9a-f]+: 001f 1f3c jrc.hb ra
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 4403 jrc zero
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 4443 jrc v0
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 4463 jrc v1
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 4483 jrc a0
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 44a3 jrc a1
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 44c3 jrc a2
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 44e3 jrc a3
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 4503 jrc t0
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 47c3 jrc s8
- [0-9a-f]+: 0c00 nop
- [0-9a-f]+: 47e3 jrc ra
- [0-9a-f]+: 440b jalrc zero
- [0-9a-f]+: 444b jalrc v0
- [0-9a-f]+: 446b jalrc v1
- [0-9a-f]+: 448b jalrc a0
- [0-9a-f]+: 44ab jalrc a1
- [0-9a-f]+: 44cb jalrc a2
- [0-9a-f]+: 44eb jalrc a3
- [0-9a-f]+: 450b jalrc t0
- [0-9a-f]+: 47cb jalrc s8
- [0-9a-f]+: 03e0 0f3c jalrc zero
- [0-9a-f]+: 03e2 0f3c jalrc v0
- [0-9a-f]+: 03e3 0f3c jalrc v1
- [0-9a-f]+: 03e4 0f3c jalrc a0
- [0-9a-f]+: 03e5 0f3c jalrc a1
- [0-9a-f]+: 03e6 0f3c jalrc a2
- [0-9a-f]+: 03e7 0f3c jalrc a3
- [0-9a-f]+: 03e8 0f3c jalrc t0
- [0-9a-f]+: 03fe 0f3c jalrc s8
- [0-9a-f]+: 440b jalrc zero
- [0-9a-f]+: 444b jalrc v0
- [0-9a-f]+: 446b jalrc v1
- [0-9a-f]+: 448b jalrc a0
- [0-9a-f]+: 44ab jalrc a1
- [0-9a-f]+: 44cb jalrc a2
- [0-9a-f]+: 44eb jalrc a3
- [0-9a-f]+: 450b jalrc t0
- [0-9a-f]+: 47cb jalrc s8
- [0-9a-f]+: 03df 0f3c jalrc s8,ra
- [0-9a-f]+: 0040 0f3c jalrc v0,zero
- [0-9a-f]+: 0062 0f3c jalrc v1,v0
- [0-9a-f]+: 0043 0f3c jalrc v0,v1
- [0-9a-f]+: 0044 0f3c jalrc v0,a0
- [0-9a-f]+: 0045 0f3c jalrc v0,a1
- [0-9a-f]+: 0046 0f3c jalrc v0,a2
- [0-9a-f]+: 0047 0f3c jalrc v0,a3
- [0-9a-f]+: 0048 0f3c jalrc v0,t0
- [0-9a-f]+: 005e 0f3c jalrc v0,s8
- [0-9a-f]+: 005f 0f3c jalrc v0,ra
- [0-9a-f]+: 03e0 1f3c jalrc.hb zero
- [0-9a-f]+: 03e2 1f3c jalrc.hb v0
- [0-9a-f]+: 03e3 1f3c jalrc.hb v1
- [0-9a-f]+: 03e4 1f3c jalrc.hb a0
- [0-9a-f]+: 03e5 1f3c jalrc.hb a1
- [0-9a-f]+: 03e6 1f3c jalrc.hb a2
- [0-9a-f]+: 03e7 1f3c jalrc.hb a3
- [0-9a-f]+: 03e8 1f3c jalrc.hb t0
- [0-9a-f]+: 03fe 1f3c jalrc.hb s8
- [0-9a-f]+: 03e0 1f3c jalrc.hb zero
- [0-9a-f]+: 03e2 1f3c jalrc.hb v0
- [0-9a-f]+: 03e3 1f3c jalrc.hb v1
- [0-9a-f]+: 03e4 1f3c jalrc.hb a0
- [0-9a-f]+: 03e5 1f3c jalrc.hb a1
- [0-9a-f]+: 03e6 1f3c jalrc.hb a2
- [0-9a-f]+: 03e7 1f3c jalrc.hb a3
- [0-9a-f]+: 03e8 1f3c jalrc.hb t0
- [0-9a-f]+: 03fe 1f3c jalrc.hb s8
- [0-9a-f]+: 03df 1f3c jalrc.hb s8,ra
- [0-9a-f]+: 0040 1f3c jalrc.hb v0,zero
- [0-9a-f]+: 0062 1f3c jalrc.hb v1,v0
- [0-9a-f]+: 0043 1f3c jalrc.hb v0,v1
- [0-9a-f]+: 0044 1f3c jalrc.hb v0,a0
- [0-9a-f]+: 0045 1f3c jalrc.hb v0,a1
- [0-9a-f]+: 0046 1f3c jalrc.hb v0,a2
- [0-9a-f]+: 0047 1f3c jalrc.hb v0,a3
- [0-9a-f]+: 0048 1f3c jalrc.hb v0,t0
- [0-9a-f]+: 005e 1f3c jalrc.hb v0,s8
- [0-9a-f]+: 005f 1f3c jalrc.hb v0,ra
- [0-9a-f]+: 0043 0f3c jalrc v0,v1
- [0-9a-f]+: 03df 0f3c jalrc s8,ra
- [0-9a-f]+: 446b jalrc v1
- [0-9a-f]+: 47eb jalrc ra
- [0-9a-f]+: b3fe 0000 sltiu ra,s8,0
- [0-9a-f]+: R_MICROMIPS_PC26_S1 test
- [0-9a-f]+: b3fe 0000 sltiu ra,s8,0
- [0-9a-f]+: R_MICROMIPS_PC26_S1 test2
- [0-9a-f]+: 1040 0000 lui v0,0x0
- [0-9a-f]+: R_MICROMIPS_HI16 test
- [0-9a-f]+: 3042 0000 addiu v0,v0,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
- [0-9a-f]+: 1040 0000 lui v0,0x0
- [0-9a-f]+: R_MICROMIPS_HI16 test
- [0-9a-f]+: 3042 0000 addiu v0,v0,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
- [0-9a-f]+: 1c60 0000 lb v1,0\(zero\)
- [0-9a-f]+: 1c60 0004 lb v1,4\(zero\)
- [0-9a-f]+: 1c60 0000 lb v1,0\(zero\)
- [0-9a-f]+: 1c60 0004 lb v1,4\(zero\)
- [0-9a-f]+: 1c60 7fff lb v1,32767\(zero\)
- [0-9a-f]+: 1c60 8000 lb v1,-32768\(zero\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 1c63 ffff lb v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
- [0-9a-f]+: 1c60 8000 lb v1,-32768\(zero\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 1c63 0001 lb v1,1\(v1\)
- [0-9a-f]+: 1c60 8001 lb v1,-32767\(zero\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
- [0-9a-f]+: 1c60 ffff lb v1,-1\(zero\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 1c63 5678 lb v1,22136\(v1\)
- [0-9a-f]+: 1c64 0000 lb v1,0\(a0\)
- [0-9a-f]+: 1c64 0000 lb v1,0\(a0\)
- [0-9a-f]+: 1c64 0004 lb v1,4\(a0\)
- [0-9a-f]+: 1c64 7fff lb v1,32767\(a0\)
- [0-9a-f]+: 1c64 8000 lb v1,-32768\(a0\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 1c63 ffff lb v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
- [0-9a-f]+: 1c64 8000 lb v1,-32768\(a0\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 1c63 0001 lb v1,1\(v1\)
- [0-9a-f]+: 1c64 8001 lb v1,-32767\(a0\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 1c63 0000 lb v1,0\(v1\)
- [0-9a-f]+: 1c64 ffff lb v1,-1\(a0\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 1c63 5678 lb v1,22136\(v1\)
- [0-9a-f]+: 093f lbu v0,-1\(v1\)
- [0-9a-f]+: 0930 lbu v0,0\(v1\)
- [0-9a-f]+: 0930 lbu v0,0\(v1\)
- [0-9a-f]+: 0931 lbu v0,1\(v1\)
- [0-9a-f]+: 0932 lbu v0,2\(v1\)
- [0-9a-f]+: 0933 lbu v0,3\(v1\)
- [0-9a-f]+: 0934 lbu v0,4\(v1\)
- [0-9a-f]+: 0935 lbu v0,5\(v1\)
- [0-9a-f]+: 0936 lbu v0,6\(v1\)
- [0-9a-f]+: 0937 lbu v0,7\(v1\)
- [0-9a-f]+: 0938 lbu v0,8\(v1\)
- [0-9a-f]+: 0939 lbu v0,9\(v1\)
- [0-9a-f]+: 093a lbu v0,10\(v1\)
- [0-9a-f]+: 093b lbu v0,11\(v1\)
- [0-9a-f]+: 093c lbu v0,12\(v1\)
- [0-9a-f]+: 093d lbu v0,13\(v1\)
- [0-9a-f]+: 093e lbu v0,14\(v1\)
- [0-9a-f]+: 092e lbu v0,14\(v0\)
- [0-9a-f]+: 094e lbu v0,14\(a0\)
- [0-9a-f]+: 095e lbu v0,14\(a1\)
- [0-9a-f]+: 096e lbu v0,14\(a2\)
- [0-9a-f]+: 097e lbu v0,14\(a3\)
- [0-9a-f]+: 090e lbu v0,14\(s0\)
- [0-9a-f]+: 091e lbu v0,14\(s1\)
- [0-9a-f]+: 099e lbu v1,14\(s1\)
- [0-9a-f]+: 0a1e lbu a0,14\(s1\)
- [0-9a-f]+: 0a9e lbu a1,14\(s1\)
- [0-9a-f]+: 0b1e lbu a2,14\(s1\)
- [0-9a-f]+: 0b9e lbu a3,14\(s1\)
- [0-9a-f]+: 081e lbu s0,14\(s1\)
- [0-9a-f]+: 089e lbu s1,14\(s1\)
- [0-9a-f]+: 1460 0000 lbu v1,0\(zero\)
- [0-9a-f]+: 1460 0004 lbu v1,4\(zero\)
- [0-9a-f]+: 1460 0000 lbu v1,0\(zero\)
- [0-9a-f]+: 1460 0004 lbu v1,4\(zero\)
- [0-9a-f]+: 1460 7fff lbu v1,32767\(zero\)
- [0-9a-f]+: 1460 8000 lbu v1,-32768\(zero\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 1463 ffff lbu v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
- [0-9a-f]+: 1460 8000 lbu v1,-32768\(zero\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 1463 0001 lbu v1,1\(v1\)
- [0-9a-f]+: 1460 8001 lbu v1,-32767\(zero\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
- [0-9a-f]+: 1460 ffff lbu v1,-1\(zero\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 1463 5678 lbu v1,22136\(v1\)
- [0-9a-f]+: 09c0 lbu v1,0\(a0\)
- [0-9a-f]+: 09c0 lbu v1,0\(a0\)
- [0-9a-f]+: 09c4 lbu v1,4\(a0\)
- [0-9a-f]+: 1464 7fff lbu v1,32767\(a0\)
- [0-9a-f]+: 1464 8000 lbu v1,-32768\(a0\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 1463 ffff lbu v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
- [0-9a-f]+: 1464 8000 lbu v1,-32768\(a0\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 1463 0001 lbu v1,1\(v1\)
- [0-9a-f]+: 1464 8001 lbu v1,-32767\(a0\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 1463 0000 lbu v1,0\(v1\)
- [0-9a-f]+: 1464 ffff lbu v1,-1\(a0\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 1463 5678 lbu v1,22136\(v1\)
- [0-9a-f]+: 3c60 0000 lh v1,0\(zero\)
- [0-9a-f]+: 3c60 0004 lh v1,4\(zero\)
- [0-9a-f]+: 3c60 0000 lh v1,0\(zero\)
- [0-9a-f]+: 3c60 0004 lh v1,4\(zero\)
- [0-9a-f]+: 3c60 7fff lh v1,32767\(zero\)
- [0-9a-f]+: 3c60 8000 lh v1,-32768\(zero\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 3c63 ffff lh v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
- [0-9a-f]+: 3c60 8000 lh v1,-32768\(zero\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 3c63 0001 lh v1,1\(v1\)
- [0-9a-f]+: 3c60 8001 lh v1,-32767\(zero\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
- [0-9a-f]+: 3c60 ffff lh v1,-1\(zero\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 3c63 5678 lh v1,22136\(v1\)
- [0-9a-f]+: 3c64 0000 lh v1,0\(a0\)
- [0-9a-f]+: 3c64 0000 lh v1,0\(a0\)
- [0-9a-f]+: 3c64 0004 lh v1,4\(a0\)
- [0-9a-f]+: 3c64 7fff lh v1,32767\(a0\)
- [0-9a-f]+: 3c64 8000 lh v1,-32768\(a0\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 3c63 ffff lh v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
- [0-9a-f]+: 3c64 8000 lh v1,-32768\(a0\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 3c63 0001 lh v1,1\(v1\)
- [0-9a-f]+: 3c64 8001 lh v1,-32767\(a0\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 3c63 0000 lh v1,0\(v1\)
- [0-9a-f]+: 3c64 ffff lh v1,-1\(a0\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 3c63 5678 lh v1,22136\(v1\)
- [0-9a-f]+: 2930 lhu v0,0\(v1\)
- [0-9a-f]+: 2930 lhu v0,0\(v1\)
- [0-9a-f]+: 2931 lhu v0,2\(v1\)
- [0-9a-f]+: 2932 lhu v0,4\(v1\)
- [0-9a-f]+: 2933 lhu v0,6\(v1\)
- [0-9a-f]+: 2934 lhu v0,8\(v1\)
- [0-9a-f]+: 2935 lhu v0,10\(v1\)
- [0-9a-f]+: 2936 lhu v0,12\(v1\)
- [0-9a-f]+: 2937 lhu v0,14\(v1\)
- [0-9a-f]+: 2938 lhu v0,16\(v1\)
- [0-9a-f]+: 2939 lhu v0,18\(v1\)
- [0-9a-f]+: 293a lhu v0,20\(v1\)
- [0-9a-f]+: 293b lhu v0,22\(v1\)
- [0-9a-f]+: 293c lhu v0,24\(v1\)
- [0-9a-f]+: 293d lhu v0,26\(v1\)
- [0-9a-f]+: 293e lhu v0,28\(v1\)
- [0-9a-f]+: 293f lhu v0,30\(v1\)
- [0-9a-f]+: 294f lhu v0,30\(a0\)
- [0-9a-f]+: 295f lhu v0,30\(a1\)
- [0-9a-f]+: 296f lhu v0,30\(a2\)
- [0-9a-f]+: 297f lhu v0,30\(a3\)
- [0-9a-f]+: 292f lhu v0,30\(v0\)
- [0-9a-f]+: 290f lhu v0,30\(s0\)
- [0-9a-f]+: 291f lhu v0,30\(s1\)
- [0-9a-f]+: 299f lhu v1,30\(s1\)
- [0-9a-f]+: 2a1f lhu a0,30\(s1\)
- [0-9a-f]+: 2a9f lhu a1,30\(s1\)
- [0-9a-f]+: 2b1f lhu a2,30\(s1\)
- [0-9a-f]+: 2b9f lhu a3,30\(s1\)
- [0-9a-f]+: 281f lhu s0,30\(s1\)
- [0-9a-f]+: 289f lhu s1,30\(s1\)
- [0-9a-f]+: 3460 0000 lhu v1,0\(zero\)
- [0-9a-f]+: 3460 0004 lhu v1,4\(zero\)
- [0-9a-f]+: 3460 0000 lhu v1,0\(zero\)
- [0-9a-f]+: 3460 0004 lhu v1,4\(zero\)
- [0-9a-f]+: 3460 7fff lhu v1,32767\(zero\)
- [0-9a-f]+: 3460 8000 lhu v1,-32768\(zero\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 3463 ffff lhu v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
- [0-9a-f]+: 3460 8000 lhu v1,-32768\(zero\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 3463 0001 lhu v1,1\(v1\)
- [0-9a-f]+: 3460 8001 lhu v1,-32767\(zero\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
- [0-9a-f]+: 3460 ffff lhu v1,-1\(zero\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 3463 5678 lhu v1,22136\(v1\)
- [0-9a-f]+: 29c0 lhu v1,0\(a0\)
- [0-9a-f]+: 29c0 lhu v1,0\(a0\)
- [0-9a-f]+: 29c2 lhu v1,4\(a0\)
- [0-9a-f]+: 3464 7fff lhu v1,32767\(a0\)
- [0-9a-f]+: 3464 8000 lhu v1,-32768\(a0\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 3463 ffff lhu v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
- [0-9a-f]+: 3464 8000 lhu v1,-32768\(a0\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 3463 0001 lhu v1,1\(v1\)
- [0-9a-f]+: 3464 8001 lhu v1,-32767\(a0\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 3463 0000 lhu v1,0\(v1\)
- [0-9a-f]+: 3464 ffff lhu v1,-1\(a0\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 3463 5678 lhu v1,22136\(v1\)
- [0-9a-f]+: 6060 3000 ll v1,0\(zero\)
- [0-9a-f]+: 6060 3000 ll v1,0\(zero\)
- [0-9a-f]+: 6060 3004 ll v1,4\(zero\)
- [0-9a-f]+: 6060 3004 ll v1,4\(zero\)
- [0-9a-f]+: 3060 7fff li v1,32767
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 3060 8000 li v1,-32768
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 6063 31ff ll v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 3060 8000 li v1,-32768
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 6063 3001 ll v1,1\(v1\)
- [0-9a-f]+: 3060 8001 li v1,-32767
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 6060 31ff ll v1,-1\(zero\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 5063 5600 ori v1,v1,0x5600
- [0-9a-f]+: 6063 3078 ll v1,120\(v1\)
- [0-9a-f]+: 6064 3000 ll v1,0\(a0\)
- [0-9a-f]+: 6064 3000 ll v1,0\(a0\)
- [0-9a-f]+: 6064 3004 ll v1,4\(a0\)
- [0-9a-f]+: 3064 7fff addiu v1,a0,32767
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 3064 8000 addiu v1,a0,-32768
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 6063 31ff ll v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 3064 8000 addiu v1,a0,-32768
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 6063 3001 ll v1,1\(v1\)
- [0-9a-f]+: 3064 8001 addiu v1,a0,-32767
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 6063 3000 ll v1,0\(v1\)
- [0-9a-f]+: 6064 31ff ll v1,-1\(a0\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 5063 5600 ori v1,v1,0x5600
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: 6063 3078 ll v1,120\(v1\)
- [0-9a-f]+: 1060 0000 lui v1,0x0
- [0-9a-f]+: 1060 7fff lui v1,0x7fff
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 6940 lw v0,0\(a0\)
- [0-9a-f]+: 6940 lw v0,0\(a0\)
- [0-9a-f]+: 6941 lw v0,4\(a0\)
- [0-9a-f]+: 6942 lw v0,8\(a0\)
- [0-9a-f]+: 6943 lw v0,12\(a0\)
- [0-9a-f]+: 6944 lw v0,16\(a0\)
- [0-9a-f]+: 6945 lw v0,20\(a0\)
- [0-9a-f]+: 6946 lw v0,24\(a0\)
- [0-9a-f]+: 6947 lw v0,28\(a0\)
- [0-9a-f]+: 6948 lw v0,32\(a0\)
- [0-9a-f]+: 6949 lw v0,36\(a0\)
- [0-9a-f]+: 694a lw v0,40\(a0\)
- [0-9a-f]+: 694b lw v0,44\(a0\)
- [0-9a-f]+: 694c lw v0,48\(a0\)
- [0-9a-f]+: 694d lw v0,52\(a0\)
- [0-9a-f]+: 694e lw v0,56\(a0\)
- [0-9a-f]+: 694f lw v0,60\(a0\)
- [0-9a-f]+: 695f lw v0,60\(a1\)
- [0-9a-f]+: 696f lw v0,60\(a2\)
- [0-9a-f]+: 697f lw v0,60\(a3\)
- [0-9a-f]+: 692f lw v0,60\(v0\)
- [0-9a-f]+: 693f lw v0,60\(v1\)
- [0-9a-f]+: 690f lw v0,60\(s0\)
- [0-9a-f]+: 691f lw v0,60\(s1\)
- [0-9a-f]+: 699f lw v1,60\(s1\)
- [0-9a-f]+: 6a1f lw a0,60\(s1\)
- [0-9a-f]+: 6a9f lw a1,60\(s1\)
- [0-9a-f]+: 6b1f lw a2,60\(s1\)
- [0-9a-f]+: 6b9f lw a3,60\(s1\)
- [0-9a-f]+: 681f lw s0,60\(s1\)
- [0-9a-f]+: 689f lw s1,60\(s1\)
- [0-9a-f]+: 4880 lw a0,0\(sp\)
- [0-9a-f]+: 4880 lw a0,0\(sp\)
- [0-9a-f]+: 4881 lw a0,4\(sp\)
- [0-9a-f]+: 4882 lw a0,8\(sp\)
- [0-9a-f]+: 4883 lw a0,12\(sp\)
- [0-9a-f]+: 4884 lw a0,16\(sp\)
- [0-9a-f]+: 4885 lw a0,20\(sp\)
- [0-9a-f]+: 489f lw a0,124\(sp\)
- [0-9a-f]+: 485f lw v0,124\(sp\)
- [0-9a-f]+: 485f lw v0,124\(sp\)
- [0-9a-f]+: 487f lw v1,124\(sp\)
- [0-9a-f]+: 489f lw a0,124\(sp\)
- [0-9a-f]+: 48bf lw a1,124\(sp\)
- [0-9a-f]+: 48df lw a2,124\(sp\)
- [0-9a-f]+: 48ff lw a3,124\(sp\)
- [0-9a-f]+: 491f lw t0,124\(sp\)
- [0-9a-f]+: 493f lw t1,124\(sp\)
- [0-9a-f]+: 495f lw t2,124\(sp\)
- [0-9a-f]+: 4bdf lw s8,124\(sp\)
- [0-9a-f]+: 4bff lw ra,124\(sp\)
- [0-9a-f]+: fc9d 01f8 lw a0,504\(sp\)
- [0-9a-f]+: fc9d 01fc lw a0,508\(sp\)
- [0-9a-f]+: fe1d 01fc lw s0,508\(sp\)
- [0-9a-f]+: fe3d 01fc lw s1,508\(sp\)
- [0-9a-f]+: fe5d 01fc lw s2,508\(sp\)
- [0-9a-f]+: fe7d 01fc lw s3,508\(sp\)
- [0-9a-f]+: fe9d 01fc lw s4,508\(sp\)
- [0-9a-f]+: febd 01fc lw s5,508\(sp\)
- [0-9a-f]+: fffd 01fc lw ra,508\(sp\)
- [0-9a-f]+: fc60 0000 lw v1,0\(zero\)
- [0-9a-f]+: fc60 0004 lw v1,4\(zero\)
- [0-9a-f]+: fc60 0000 lw v1,0\(zero\)
- [0-9a-f]+: fc60 0000 lw v1,0\(zero\)
- [0-9a-f]+: fc60 0000 lw v1,0\(zero\)
- [0-9a-f]+: fc60 0004 lw v1,4\(zero\)
- [0-9a-f]+: fc60 7fff lw v1,32767\(zero\)
- [0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: fc63 ffff lw v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: fc63 0000 lw v1,0\(v1\)
- [0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: fc63 0001 lw v1,1\(v1\)
- [0-9a-f]+: fc60 8001 lw v1,-32767\(zero\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: fc63 0000 lw v1,0\(v1\)
- [0-9a-f]+: fc60 ffff lw v1,-1\(zero\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: fc63 5678 lw v1,22136\(v1\)
- [0-9a-f]+: 69c0 lw v1,0\(a0\)
- [0-9a-f]+: 69c0 lw v1,0\(a0\)
- [0-9a-f]+: 69c1 lw v1,4\(a0\)
- [0-9a-f]+: fc64 7fff lw v1,32767\(a0\)
- [0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: fc63 ffff lw v1,-1\(v1\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: fc63 0000 lw v1,0\(v1\)
- [0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
- [0-9a-f]+: 1060 ffff lui v1,0xffff
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: fc63 0001 lw v1,1\(v1\)
- [0-9a-f]+: fc64 8001 lw v1,-32767\(a0\)
- [0-9a-f]+: 1060 f000 lui v1,0xf000
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: fc63 0000 lw v1,0\(v1\)
- [0-9a-f]+: fc64 ffff lw v1,-1\(a0\)
- [0-9a-f]+: 1060 1234 lui v1,0x1234
- [0-9a-f]+: 0083 1950 addu v1,v1,a0
- [0-9a-f]+: fc63 5678 lw v1,22136\(v1\)
- [0-9a-f]+: 44c2 lwm s0,ra,48\(sp\)
- [0-9a-f]+: 45c2 lwm s0-s1,ra,48\(sp\)
- [0-9a-f]+: 45c2 lwm s0-s1,ra,48\(sp\)
- [0-9a-f]+: 46c2 lwm s0-s2,ra,48\(sp\)
- [0-9a-f]+: 46c2 lwm s0-s2,ra,48\(sp\)
- [0-9a-f]+: 47c2 lwm s0-s3,ra,48\(sp\)
- [0-9a-f]+: 47c2 lwm s0-s3,ra,48\(sp\)
- [0-9a-f]+: 4402 lwm s0,ra,0\(sp\)
- [0-9a-f]+: 4402 lwm s0,ra,0\(sp\)
- [0-9a-f]+: 4412 lwm s0,ra,4\(sp\)
- [0-9a-f]+: 4422 lwm s0,ra,8\(sp\)
- [0-9a-f]+: 4432 lwm s0,ra,12\(sp\)
- [0-9a-f]+: 4442 lwm s0,ra,16\(sp\)
- [0-9a-f]+: 4452 lwm s0,ra,20\(sp\)
- [0-9a-f]+: 4462 lwm s0,ra,24\(sp\)
- [0-9a-f]+: 4472 lwm s0,ra,28\(sp\)
- [0-9a-f]+: 4482 lwm s0,ra,32\(sp\)
- [0-9a-f]+: 4492 lwm s0,ra,36\(sp\)
- [0-9a-f]+: 44a2 lwm s0,ra,40\(sp\)
- [0-9a-f]+: 44b2 lwm s0,ra,44\(sp\)
- [0-9a-f]+: 44c2 lwm s0,ra,48\(sp\)
- [0-9a-f]+: 44d2 lwm s0,ra,52\(sp\)
- [0-9a-f]+: 44e2 lwm s0,ra,56\(sp\)
- [0-9a-f]+: 44f2 lwm s0,ra,60\(sp\)
- [0-9a-f]+: 2020 5000 lwm s0,0\(zero\)
- [0-9a-f]+: 2020 5004 lwm s0,4\(zero\)
- [0-9a-f]+: 2025 5000 lwm s0,0\(a1\)
- [0-9a-f]+: 2025 57ff lwm s0,2047\(a1\)
- [0-9a-f]+: 2045 57ff lwm s0-s1,2047\(a1\)
- [0-9a-f]+: 2065 57ff lwm s0-s2,2047\(a1\)
- [0-9a-f]+: 2085 57ff lwm s0-s3,2047\(a1\)
- [0-9a-f]+: 20a5 57ff lwm s0-s4,2047\(a1\)
- [0-9a-f]+: 20c5 57ff lwm s0-s5,2047\(a1\)
- [0-9a-f]+: 20e5 57ff lwm s0-s6,2047\(a1\)
- [0-9a-f]+: 2105 57ff lwm s0-s7,2047\(a1\)
- [0-9a-f]+: 2125 57ff lwm s0-s7,s8,2047\(a1\)
- [0-9a-f]+: 2205 57ff lwm ra,2047\(a1\)
- [0-9a-f]+: 2225 5000 lwm s0,ra,0\(a1\)
- [0-9a-f]+: 2245 5000 lwm s0-s1,ra,0\(a1\)
- [0-9a-f]+: 2265 5000 lwm s0-s2,ra,0\(a1\)
- [0-9a-f]+: 2285 5000 lwm s0-s3,ra,0\(a1\)
- [0-9a-f]+: 22a5 5000 lwm s0-s4,ra,0\(a1\)
- [0-9a-f]+: 22c5 5000 lwm s0-s5,ra,0\(a1\)
- [0-9a-f]+: 22e5 5000 lwm s0-s6,ra,0\(a1\)
- [0-9a-f]+: 2305 5000 lwm s0-s7,ra,0\(a1\)
- [0-9a-f]+: 2325 5000 lwm s0-s7,s8,ra,0\(a1\)
- [0-9a-f]+: 3020 8000 li at,-32768
- [0-9a-f]+: 2021 5000 lwm s0,0\(at\)
- [0-9a-f]+: 3020 7fff li at,32767
- [0-9a-f]+: 2021 5000 lwm s0,0\(at\)
- [0-9a-f]+: 2020 5000 lwm s0,0\(zero\)
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
- [0-9a-f]+: 303d 8000 addiu at,sp,-32768
- [0-9a-f]+: 2021 5000 lwm s0,0\(at\)
- [0-9a-f]+: 303d 7fff addiu at,sp,32767
- [0-9a-f]+: 2021 5000 lwm s0,0\(at\)
- [0-9a-f]+: 203d 5000 lwm s0,0\(sp\)
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 03a1 0950 addu at,at,sp
- [0-9a-f]+: 2021 5fff lwm s0,-1\(at\)
- [0-9a-f]+: 2040 1000 lwp v0,0\(zero\)
- [0-9a-f]+: 2040 1004 lwp v0,4\(zero\)
- [0-9a-f]+: 205d 1000 lwp v0,0\(sp\)
- [0-9a-f]+: 205d 1000 lwp v0,0\(sp\)
- [0-9a-f]+: 2043 1800 lwp v0,-2048\(v1\)
- [0-9a-f]+: 2043 17ff lwp v0,2047\(v1\)
- [0-9a-f]+: 3023 8000 addiu at,v1,-32768
- [0-9a-f]+: 2041 1000 lwp v0,0\(at\)
- [0-9a-f]+: 3023 7fff addiu at,v1,32767
- [0-9a-f]+: 2041 1000 lwp v0,0\(at\)
- [0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
- [0-9a-f]+: 1020 0001 lui at,0x1
- [0-9a-f]+: 0061 0950 addu at,at,v1
- [0-9a-f]+: 2041 1fff lwp v0,-1\(at\)
- [0-9a-f]+: 3060 8000 li v1,-32768
- [0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
- [0-9a-f]+: 3060 7fff li v1,32767
- [0-9a-f]+: 2043 1000 lwp v0,0\(v1\)
- [0-9a-f]+: 1060 0001 lui v1,0x1
- [0-9a-f]+: 2043 1fff lwp v0,-1\(v1\)
- [0-9a-f]+: 0085 1900 lwxs v1,a0\(a1\)
- [0-9a-f]+: 0040 00fc mfc0 v0,c0_index
- [0-9a-f]+: 0041 00fc mfc0 v0,c0_random
- [0-9a-f]+: 0042 00fc mfc0 v0,c0_entrylo0
- [0-9a-f]+: 0043 00fc mfc0 v0,c0_entrylo1
- [0-9a-f]+: 0044 00fc mfc0 v0,c0_context
- [0-9a-f]+: 0045 00fc mfc0 v0,c0_pagemask
- [0-9a-f]+: 0046 00fc mfc0 v0,c0_wired
- [0-9a-f]+: 0047 00fc mfc0 v0,c0_hwrena
- [0-9a-f]+: 0048 00fc mfc0 v0,c0_badvaddr
- [0-9a-f]+: 0049 00fc mfc0 v0,c0_count
- [0-9a-f]+: 004a 00fc mfc0 v0,c0_entryhi
- [0-9a-f]+: 004b 00fc mfc0 v0,c0_compare
- [0-9a-f]+: 004c 00fc mfc0 v0,c0_status
- [0-9a-f]+: 004d 00fc mfc0 v0,c0_cause
- [0-9a-f]+: 004e 00fc mfc0 v0,c0_epc
- [0-9a-f]+: 004f 00fc mfc0 v0,c0_prid
- [0-9a-f]+: 0050 00fc mfc0 v0,c0_config
- [0-9a-f]+: 0051 00fc mfc0 v0,c0_lladdr
- [0-9a-f]+: 0052 00fc mfc0 v0,c0_watchlo
- [0-9a-f]+: 0053 00fc mfc0 v0,c0_watchhi
- [0-9a-f]+: 0054 00fc mfc0 v0,c0_xcontext
- [0-9a-f]+: 0055 00fc mfc0 v0,\$21
- [0-9a-f]+: 0056 00fc mfc0 v0,\$22
- [0-9a-f]+: 0057 00fc mfc0 v0,c0_debug
- [0-9a-f]+: 0058 00fc mfc0 v0,c0_depc
- [0-9a-f]+: 0059 00fc mfc0 v0,c0_perfcnt
- [0-9a-f]+: 005a 00fc mfc0 v0,c0_errctl
- [0-9a-f]+: 005b 00fc mfc0 v0,c0_cacheerr
- [0-9a-f]+: 005c 00fc mfc0 v0,c0_taglo
- [0-9a-f]+: 005d 00fc mfc0 v0,c0_taghi
- [0-9a-f]+: 005e 00fc mfc0 v0,c0_errorepc
- [0-9a-f]+: 005f 00fc mfc0 v0,c0_desave
- [0-9a-f]+: 0040 00fc mfc0 v0,c0_index
- [0-9a-f]+: 0040 08fc mfc0 v0,c0_mvpcontrol
- [0-9a-f]+: 0040 10fc mfc0 v0,c0_mvpconf0
- [0-9a-f]+: 0040 18fc mfc0 v0,c0_mvpconf1
- [0-9a-f]+: 0040 20fc mfc0 v0,\$0,4
- [0-9a-f]+: 0040 28fc mfc0 v0,\$0,5
- [0-9a-f]+: 0040 30fc mfc0 v0,\$0,6
- [0-9a-f]+: 0040 38fc mfc0 v0,\$0,7
- [0-9a-f]+: 0041 00fc mfc0 v0,c0_random
- [0-9a-f]+: 0041 08fc mfc0 v0,c0_vpecontrol
- [0-9a-f]+: 0041 10fc mfc0 v0,c0_vpeconf0
- [0-9a-f]+: 0041 18fc mfc0 v0,c0_vpeconf1
- [0-9a-f]+: 0041 20fc mfc0 v0,c0_yqmask
- [0-9a-f]+: 0041 28fc mfc0 v0,c0_vpeschedule
- [0-9a-f]+: 0041 30fc mfc0 v0,c0_vpeschefback
- [0-9a-f]+: 0041 38fc mfc0 v0,\$1,7
- [0-9a-f]+: 0042 00fc mfc0 v0,c0_entrylo0
- [0-9a-f]+: 0042 08fc mfc0 v0,c0_tcstatus
- [0-9a-f]+: 0042 10fc mfc0 v0,c0_tcbind
- [0-9a-f]+: 0042 18fc mfc0 v0,c0_tcrestart
- [0-9a-f]+: 0042 20fc mfc0 v0,c0_tchalt
- [0-9a-f]+: 0042 28fc mfc0 v0,c0_tccontext
- [0-9a-f]+: 0042 30fc mfc0 v0,c0_tcschedule
- [0-9a-f]+: 0042 38fc mfc0 v0,c0_tcschefback
- [0-9a-f]+: 0040 02fc mtc0 v0,c0_index
- [0-9a-f]+: 0041 02fc mtc0 v0,c0_random
- [0-9a-f]+: 0042 02fc mtc0 v0,c0_entrylo0
- [0-9a-f]+: 0043 02fc mtc0 v0,c0_entrylo1
- [0-9a-f]+: 0044 02fc mtc0 v0,c0_context
- [0-9a-f]+: 0045 02fc mtc0 v0,c0_pagemask
- [0-9a-f]+: 0046 02fc mtc0 v0,c0_wired
- [0-9a-f]+: 0047 02fc mtc0 v0,c0_hwrena
- [0-9a-f]+: 0048 02fc mtc0 v0,c0_badvaddr
- [0-9a-f]+: 0049 02fc mtc0 v0,c0_count
- [0-9a-f]+: 004a 02fc mtc0 v0,c0_entryhi
- [0-9a-f]+: 004b 02fc mtc0 v0,c0_compare
- [0-9a-f]+: 004c 02fc mtc0 v0,c0_status
- [0-9a-f]+: 004d 02fc mtc0 v0,c0_cause
- [0-9a-f]+: 004e 02fc mtc0 v0,c0_epc
- [0-9a-f]+: 004f 02fc mtc0 v0,c0_prid
- [0-9a-f]+: 0050 02fc mtc0 v0,c0_config
- [0-9a-f]+: 0051 02fc mtc0 v0,c0_lladdr
- [0-9a-f]+: 0052 02fc mtc0 v0,c0_watchlo
- [0-9a-f]+: 0053 02fc mtc0 v0,c0_watchhi
- [0-9a-f]+: 0054 02fc mtc0 v0,c0_xcontext
- [0-9a-f]+: 0055 02fc mtc0 v0,\$21
- [0-9a-f]+: 0056 02fc mtc0 v0,\$22
- [0-9a-f]+: 0057 02fc mtc0 v0,c0_debug
- [0-9a-f]+: 0058 02fc mtc0 v0,c0_depc
- [0-9a-f]+: 0059 02fc mtc0 v0,c0_perfcnt
- [0-9a-f]+: 005a 02fc mtc0 v0,c0_errctl
- [0-9a-f]+: 005b 02fc mtc0 v0,c0_cacheerr
- [0-9a-f]+: 005c 02fc mtc0 v0,c0_taglo
- [0-9a-f]+: 005d 02fc mtc0 v0,c0_taghi
- [0-9a-f]+: 005e 02fc mtc0 v0,c0_errorepc
- [0-9a-f]+: 005f 02fc mtc0 v0,c0_desave
- [0-9a-f]+: 0040 02fc mtc0 v0,c0_index
- [0-9a-f]+: 0040 0afc mtc0 v0,c0_mvpcontrol
- [0-9a-f]+: 0040 12fc mtc0 v0,c0_mvpconf0
- [0-9a-f]+: 0040 1afc mtc0 v0,c0_mvpconf1
- [0-9a-f]+: 0040 22fc mtc0 v0,\$0,4
- [0-9a-f]+: 0040 2afc mtc0 v0,\$0,5
- [0-9a-f]+: 0040 32fc mtc0 v0,\$0,6
- [0-9a-f]+: 0040 3afc mtc0 v0,\$0,7
- [0-9a-f]+: 0041 02fc mtc0 v0,c0_random
- [0-9a-f]+: 0041 0afc mtc0 v0,c0_vpecontrol
- [0-9a-f]+: 0041 12fc mtc0 v0,c0_vpeconf0
- [0-9a-f]+: 0041 1afc mtc0 v0,c0_vpeconf1
- [0-9a-f]+: 0041 22fc mtc0 v0,c0_yqmask
- [0-9a-f]+: 0041 2afc mtc0 v0,c0_vpeschedule
- [0-9a-f]+: 0041 32fc mtc0 v0,c0_vpeschefback
- [0-9a-f]+: 0041 3afc mtc0 v0,\$1,7
- [0-9a-f]+: 0042 02fc mtc0 v0,c0_entrylo0
- [0-9a-f]+: 0042 0afc mtc0 v0,c0_tcstatus
- [0-9a-f]+: 0042 12fc mtc0 v0,c0_tcbind
- [0-9a-f]+: 0042 1afc mtc0 v0,c0_tcrestart
- [0-9a-f]+: 0042 22fc mtc0 v0,c0_tchalt
- [0-9a-f]+: 0042 2afc mtc0 v0,c0_tccontext
- [0-9a-f]+: 0042 32fc mtc0 v0,c0_tcschedule
- [0-9a-f]+: 0042 3afc mtc0 v0,c0_tcschefback
- [0-9a-f]+: 0083 1018 mul v0,v1,a0
- [0-9a-f]+: 03fe e818 mul sp,s8,ra
- [0-9a-f]+: 0082 1018 mul v0,v0,a0
- [0-9a-f]+: 0082 1018 mul v0,v0,a0
- [0-9a-f]+: 0060 1190 neg v0,v1
- [0-9a-f]+: 0040 1190 neg v0,v0
- [0-9a-f]+: 0040 1190 neg v0,v0
- [0-9a-f]+: 0060 11d0 negu v0,v1
- [0-9a-f]+: 0040 11d0 negu v0,v0
- [0-9a-f]+: 0040 11d0 negu v0,v0
- [0-9a-f]+: 0060 11d0 negu v0,v1
- [0-9a-f]+: 0040 11d0 negu v0,v0
- [0-9a-f]+: 0040 11d0 negu v0,v0
- [0-9a-f]+: 4520 not v0,v0
- [0-9a-f]+: 4520 not v0,v0
- [0-9a-f]+: 4530 not v0,v1
- [0-9a-f]+: 4540 not v0,a0
- [0-9a-f]+: 4550 not v0,a1
- [0-9a-f]+: 4560 not v0,a2
- [0-9a-f]+: 4570 not v0,a3
- [0-9a-f]+: 4500 not v0,s0
- [0-9a-f]+: 4510 not v0,s1
- [0-9a-f]+: 4590 not v1,s1
- [0-9a-f]+: 4610 not a0,s1
-[ ]*[0-9a-f]+: 4690 not a1,s1
-[ ]*[0-9a-f]+: 4710 not a2,s1
-[ ]*[0-9a-f]+: 4790 not a3,s1
-[ ]*[0-9a-f]+: 4410 not s0,s1
-[ ]*[0-9a-f]+: 4490 not s1,s1
-[ ]*[0-9a-f]+: 4570 not v0,a3
-[ ]*[0-9a-f]+: 4570 not v0,a3
-[ ]*[0-9a-f]+: 0083 12d0 nor v0,v1,a0
-[ ]*[0-9a-f]+: 03fe ead0 nor sp,s8,ra
-[ ]*[0-9a-f]+: 0082 12d0 nor v0,v0,a0
-[ ]*[0-9a-f]+: 0082 12d0 nor v0,v0,a0
-[ ]*[0-9a-f]+: 5043 8000 ori v0,v1,0x8000
-[ ]*[0-9a-f]+: 0002 12d0 not v0,v0
-[ ]*[0-9a-f]+: 5043 ffff ori v0,v1,0xffff
-[ ]*[0-9a-f]+: 0002 12d0 not v0,v0
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0023 12d0 nor v0,v1,at
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0023 12d0 nor v0,v1,at
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0023 12d0 nor v0,v1,at
-[ ]*[0-9a-f]+: 0c56 move v0,s6
-[ ]*[0-9a-f]+: 0ec2 move s6,v0
-[ ]*[0-9a-f]+: 0c56 move v0,s6
-[ ]*[0-9a-f]+: 0ec2 move s6,v0
-[ ]*[0-9a-f]+: 4529 or v0,v0,v0
-[ ]*[0-9a-f]+: 4539 or v0,v0,v1
-[ ]*[0-9a-f]+: 4549 or v0,v0,a0
-[ ]*[0-9a-f]+: 4559 or v0,v0,a1
-[ ]*[0-9a-f]+: 4569 or v0,v0,a2
-[ ]*[0-9a-f]+: 4579 or v0,v0,a3
-[ ]*[0-9a-f]+: 4509 or v0,v0,s0
-[ ]*[0-9a-f]+: 4519 or v0,v0,s1
-[ ]*[0-9a-f]+: 45a9 or v1,v1,v0
-[ ]*[0-9a-f]+: 4629 or a0,a0,v0
-[ ]*[0-9a-f]+: 46a9 or a1,a1,v0
-[ ]*[0-9a-f]+: 4729 or a2,a2,v0
-[ ]*[0-9a-f]+: 47a9 or a3,a3,v0
-[ ]*[0-9a-f]+: 4429 or s0,s0,v0
-[ ]*[0-9a-f]+: 44a9 or s1,s1,v0
-[ ]*[0-9a-f]+: 4529 or v0,v0,v0
-[ ]*[0-9a-f]+: 4539 or v0,v0,v1
-[ ]*[0-9a-f]+: 4539 or v0,v0,v1
-[ ]*[0-9a-f]+: 0083 1290 or v0,v1,a0
-[ ]*[0-9a-f]+: 03fe ea90 or sp,s8,ra
-[ ]*[0-9a-f]+: 0082 1290 or v0,v0,a0
-[ ]*[0-9a-f]+: 0082 1290 or v0,v0,a0
-[ ]*[0-9a-f]+: 5043 8000 ori v0,v1,0x8000
-[ ]*[0-9a-f]+: 5043 ffff ori v0,v1,0xffff
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0023 1290 or v0,v1,at
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0023 1290 or v0,v1,at
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0023 1290 or v0,v1,at
-[ ]*[0-9a-f]+: 0c64 move v1,a0
-[ ]*[0-9a-f]+: 5064 7fff ori v1,a0,0x7fff
-[ ]*[0-9a-f]+: 5064 ffff ori v1,a0,0xffff
-[ ]*[0-9a-f]+: 5063 ffff ori v1,v1,0xffff
-[ ]*[0-9a-f]+: 5063 ffff ori v1,v1,0xffff
-[ ]*[0-9a-f]+: 0040 01c0 rdhwr v0,hwr_cpunum
-[ ]*[0-9a-f]+: 0041 01c0 rdhwr v0,hwr_synci_step
-[ ]*[0-9a-f]+: 0042 01c0 rdhwr v0,hwr_cc
-[ ]*[0-9a-f]+: 0043 01c0 rdhwr v0,hwr_ccres
-[ ]*[0-9a-f]+: 0044 01c0 rdhwr v0,\$4
-[ ]*[0-9a-f]+: 0045 01c0 rdhwr v0,\$5
-[ ]*[0-9a-f]+: 0046 01c0 rdhwr v0,\$6
-[ ]*[0-9a-f]+: 0047 01c0 rdhwr v0,\$7
-[ ]*[0-9a-f]+: 0048 01c0 rdhwr v0,\$8
-[ ]*[0-9a-f]+: 0049 01c0 rdhwr v0,\$9
-[ ]*[0-9a-f]+: 004a 01c0 rdhwr v0,\$10
-[ ]*[0-9a-f]+: 0043 e17c rdpgpr v0,v1
-[ ]*[0-9a-f]+: 0042 e17c rdpgpr v0,v0
-[ ]*[0-9a-f]+: 0042 e17c rdpgpr v0,v0
-[ ]*[0-9a-f]+: 0080 11d0 negu v0,a0
-[ ]*[0-9a-f]+: 0062 10d0 rorv v0,v1,v0
-[ ]*[0-9a-f]+: 0080 09d0 negu at,a0
-[ ]*[0-9a-f]+: 0041 10d0 rorv v0,v0,at
-[ ]*[0-9a-f]+: 0060 11d0 negu v0,v1
-[ ]*[0-9a-f]+: 0062 10d0 rorv v0,v1,v0
-[ ]*[0-9a-f]+: 0040 11d0 negu v0,v0
-[ ]*[0-9a-f]+: 0062 10d0 rorv v0,v1,v0
-[ ]*[0-9a-f]+: 0043 00c0 ror v0,v1,0x0
-[ ]*[0-9a-f]+: 0043 f8c0 ror v0,v1,0x1f
-[ ]*[0-9a-f]+: 0043 08c0 ror v0,v1,0x1
-[ ]*[0-9a-f]+: 0042 08c0 ror v0,v0,0x1
-[ ]*[0-9a-f]+: 0042 08c0 ror v0,v0,0x1
-[ ]*[0-9a-f]+: 0043 00c0 ror v0,v1,0x0
-[ ]*[0-9a-f]+: 0043 08c0 ror v0,v1,0x1
-[ ]*[0-9a-f]+: 0043 f8c0 ror v0,v1,0x1f
-[ ]*[0-9a-f]+: 0042 f8c0 ror v0,v0,0x1f
-[ ]*[0-9a-f]+: 0042 f8c0 ror v0,v0,0x1f
-[ ]*[0-9a-f]+: 0064 10d0 rorv v0,v1,a0
-[ ]*[0-9a-f]+: 0044 10d0 rorv v0,v0,a0
-[ ]*[0-9a-f]+: 0064 10d0 rorv v0,v1,a0
-[ ]*[0-9a-f]+: 0044 10d0 rorv v0,v0,a0
-[ ]*[0-9a-f]+: 0064 10d0 rorv v0,v1,a0
-[ ]*[0-9a-f]+: 0044 10d0 rorv v0,v0,a0
-[ ]*[0-9a-f]+: 0064 10d0 rorv v0,v1,a0
-[ ]*[0-9a-f]+: 0044 10d0 rorv v0,v0,a0
-[ ]*[0-9a-f]+: 8830 sb zero,0\(v1\)
-[ ]*[0-9a-f]+: 8830 sb zero,0\(v1\)
-[ ]*[0-9a-f]+: 8831 sb zero,1\(v1\)
-[ ]*[0-9a-f]+: 8832 sb zero,2\(v1\)
-[ ]*[0-9a-f]+: 8833 sb zero,3\(v1\)
-[ ]*[0-9a-f]+: 8834 sb zero,4\(v1\)
-[ ]*[0-9a-f]+: 8835 sb zero,5\(v1\)
-[ ]*[0-9a-f]+: 8836 sb zero,6\(v1\)
-[ ]*[0-9a-f]+: 8837 sb zero,7\(v1\)
-[ ]*[0-9a-f]+: 8838 sb zero,8\(v1\)
-[ ]*[0-9a-f]+: 8839 sb zero,9\(v1\)
-[ ]*[0-9a-f]+: 883a sb zero,10\(v1\)
-[ ]*[0-9a-f]+: 883b sb zero,11\(v1\)
-[ ]*[0-9a-f]+: 883c sb zero,12\(v1\)
-[ ]*[0-9a-f]+: 883d sb zero,13\(v1\)
-[ ]*[0-9a-f]+: 883e sb zero,14\(v1\)
-[ ]*[0-9a-f]+: 883f sb zero,15\(v1\)
-[ ]*[0-9a-f]+: 893f sb v0,15\(v1\)
-[ ]*[0-9a-f]+: 89bf sb v1,15\(v1\)
-[ ]*[0-9a-f]+: 8a3f sb a0,15\(v1\)
-[ ]*[0-9a-f]+: 8abf sb a1,15\(v1\)
-[ ]*[0-9a-f]+: 8b3f sb a2,15\(v1\)
-[ ]*[0-9a-f]+: 8bbf sb a3,15\(v1\)
-[ ]*[0-9a-f]+: 88bf sb s1,15\(v1\)
-[ ]*[0-9a-f]+: 88cf sb s1,15\(a0\)
-[ ]*[0-9a-f]+: 88df sb s1,15\(a1\)
-[ ]*[0-9a-f]+: 88ef sb s1,15\(a2\)
-[ ]*[0-9a-f]+: 88ff sb s1,15\(a3\)
-[ ]*[0-9a-f]+: 88af sb s1,15\(v0\)
-[ ]*[0-9a-f]+: 888f sb s1,15\(s0\)
-[ ]*[0-9a-f]+: 889f sb s1,15\(s1\)
-[ ]*[0-9a-f]+: 1860 0004 sb v1,4\(zero\)
-[ ]*[0-9a-f]+: 1860 0004 sb v1,4\(zero\)
-[ ]*[0-9a-f]+: 1860 7fff sb v1,32767\(zero\)
-[ ]*[0-9a-f]+: 1860 8000 sb v1,-32768\(zero\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 1861 ffff sb v1,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 1861 0000 sb v1,0\(at\)
-[ ]*[0-9a-f]+: 1860 8000 sb v1,-32768\(zero\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 1861 0001 sb v1,1\(at\)
-[ ]*[0-9a-f]+: 1860 8001 sb v1,-32767\(zero\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 1861 0000 sb v1,0\(at\)
-[ ]*[0-9a-f]+: 1860 ffff sb v1,-1\(zero\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 1861 5678 sb v1,22136\(at\)
-[ ]*[0-9a-f]+: 1864 0000 sb v1,0\(a0\)
-[ ]*[0-9a-f]+: 1864 0000 sb v1,0\(a0\)
-[ ]*[0-9a-f]+: 1864 7fff sb v1,32767\(a0\)
-[ ]*[0-9a-f]+: 1864 8000 sb v1,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 1861 ffff sb v1,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 1861 0000 sb v1,0\(at\)
-[ ]*[0-9a-f]+: 1864 8000 sb v1,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 1861 0001 sb v1,1\(at\)
-[ ]*[0-9a-f]+: 1864 8001 sb v1,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 1861 0000 sb v1,0\(at\)
-[ ]*[0-9a-f]+: 1864 ffff sb v1,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 1861 5678 sb v1,22136\(at\)
-[ ]*[0-9a-f]+: 6060 b004 sc v1,4\(zero\)
-[ ]*[0-9a-f]+: 6060 b004 sc v1,4\(zero\)
-[ ]*[0-9a-f]+: 6060 b0ff sc v1,255\(zero\)
-[ ]*[0-9a-f]+: 6060 b100 sc v1,-256\(zero\)
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 6061 b1ff sc v1,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 6061 b001 sc v1,1\(at\)
-[ ]*[0-9a-f]+: 3020 8001 li at,-32767
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 6060 b1ff sc v1,-1\(zero\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5600 ori at,at,0x5600
-[ ]*[0-9a-f]+: 6061 b078 sc v1,120\(at\)
-[ ]*[0-9a-f]+: 6064 b000 sc v1,0\(a0\)
-[ ]*[0-9a-f]+: 6064 b000 sc v1,0\(a0\)
-[ ]*[0-9a-f]+: 6064 b0ff sc v1,255\(a0\)
-[ ]*[0-9a-f]+: 6064 b100 sc v1,-256\(a0\)
-[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 6061 b1ff sc v1,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 6061 b001 sc v1,1\(at\)
-[ ]*[0-9a-f]+: 3024 8001 addiu at,a0,-32767
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 6061 b000 sc v1,0\(at\)
-[ ]*[0-9a-f]+: 6064 b1ff sc v1,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5600 ori at,at,0x5600
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 6061 b078 sc v1,120\(at\)
-[ ]*[0-9a-f]+: 443b sdbbp
-[ ]*[0-9a-f]+: 443b sdbbp
-[ ]*[0-9a-f]+: 447b sdbbp 0x1
-[ ]*[0-9a-f]+: 44bb sdbbp 0x2
-[ ]*[0-9a-f]+: 44fb sdbbp 0x3
-[ ]*[0-9a-f]+: 453b sdbbp 0x4
-[ ]*[0-9a-f]+: 457b sdbbp 0x5
-[ ]*[0-9a-f]+: 45bb sdbbp 0x6
-[ ]*[0-9a-f]+: 45fb sdbbp 0x7
-[ ]*[0-9a-f]+: 463b sdbbp 0x8
-[ ]*[0-9a-f]+: 467b sdbbp 0x9
-[ ]*[0-9a-f]+: 46bb sdbbp 0xa
-[ ]*[0-9a-f]+: 46fb sdbbp 0xb
-[ ]*[0-9a-f]+: 473b sdbbp 0xc
-[ ]*[0-9a-f]+: 477b sdbbp 0xd
-[ ]*[0-9a-f]+: 47bb sdbbp 0xe
-[ ]*[0-9a-f]+: 47fb sdbbp 0xf
-[ ]*[0-9a-f]+: 0000 db7c sdbbp
-[ ]*[0-9a-f]+: 0000 db7c sdbbp
-[ ]*[0-9a-f]+: 0001 db7c sdbbp 0x1
-[ ]*[0-9a-f]+: 0002 db7c sdbbp 0x2
-[ ]*[0-9a-f]+: 00ff db7c sdbbp 0xff
-[ ]*[0-9a-f]+: 0043 2b3c seb v0,v1
-[ ]*[0-9a-f]+: 0042 2b3c seb v0,v0
-[ ]*[0-9a-f]+: 0042 2b3c seb v0,v0
-[ ]*[0-9a-f]+: 0043 3b3c seh v0,v1
-[ ]*[0-9a-f]+: 0042 3b3c seh v0,v0
-[ ]*[0-9a-f]+: 0042 3b3c seh v0,v0
-[ ]*[0-9a-f]+: 0083 1310 xor v0,v1,a0
-[ ]*[0-9a-f]+: b042 0001 sltiu v0,v0,1
-[ ]*[0-9a-f]+: b043 0001 sltiu v0,v1,1
-[ ]*[0-9a-f]+: b044 0001 sltiu v0,a0,1
-[ ]*[0-9a-f]+: b043 0001 sltiu v0,v1,1
-[ ]*[0-9a-f]+: 7043 0001 xori v0,v1,0x1
-[ ]*[0-9a-f]+: b042 0001 sltiu v0,v0,1
-[ ]*[0-9a-f]+: 3043 0001 addiu v0,v1,1
-[ ]*[0-9a-f]+: b042 0001 sltiu v0,v0,1
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0023 1310 xor v0,v1,at
-[ ]*[0-9a-f]+: b042 0001 sltiu v0,v0,1
-[ ]*[0-9a-f]+: 0083 1350 slt v0,v1,a0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0082 1350 slt v0,v0,a0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0082 1350 slt v0,v0,a0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 9043 0000 slti v0,v1,0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 9043 8000 slti v0,v1,-32768
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 9043 0000 slti v0,v1,0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 9043 7fff slti v0,v1,32767
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0083 1390 sltu v0,v1,a0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0082 1390 sltu v0,v0,a0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0082 1390 sltu v0,v0,a0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: b043 0000 sltiu v0,v1,0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: b043 8000 sltiu v0,v1,-32768
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: b043 0000 sltiu v0,v1,0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: b043 7fff sltiu v0,v1,32767
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0064 1350 slt v0,a0,v1
-[ ]*[0-9a-f]+: 0044 1350 slt v0,a0,v0
-[ ]*[0-9a-f]+: 0044 1350 slt v0,a0,v0
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 0064 1390 sltu v0,a0,v1
-[ ]*[0-9a-f]+: 0044 1390 sltu v0,a0,v0
-[ ]*[0-9a-f]+: 0044 1390 sltu v0,a0,v0
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: a930 sh v0,0\(v1\)
-[ ]*[0-9a-f]+: a930 sh v0,0\(v1\)
-[ ]*[0-9a-f]+: a931 sh v0,2\(v1\)
-[ ]*[0-9a-f]+: a932 sh v0,4\(v1\)
-[ ]*[0-9a-f]+: a933 sh v0,6\(v1\)
-[ ]*[0-9a-f]+: a934 sh v0,8\(v1\)
-[ ]*[0-9a-f]+: a935 sh v0,10\(v1\)
-[ ]*[0-9a-f]+: a936 sh v0,12\(v1\)
-[ ]*[0-9a-f]+: a937 sh v0,14\(v1\)
-[ ]*[0-9a-f]+: a938 sh v0,16\(v1\)
-[ ]*[0-9a-f]+: a939 sh v0,18\(v1\)
-[ ]*[0-9a-f]+: a93a sh v0,20\(v1\)
-[ ]*[0-9a-f]+: a93b sh v0,22\(v1\)
-[ ]*[0-9a-f]+: a93c sh v0,24\(v1\)
-[ ]*[0-9a-f]+: a93d sh v0,26\(v1\)
-[ ]*[0-9a-f]+: a93e sh v0,28\(v1\)
-[ ]*[0-9a-f]+: a93f sh v0,30\(v1\)
-[ ]*[0-9a-f]+: a94f sh v0,30\(a0\)
-[ ]*[0-9a-f]+: a95f sh v0,30\(a1\)
-[ ]*[0-9a-f]+: a96f sh v0,30\(a2\)
-[ ]*[0-9a-f]+: a97f sh v0,30\(a3\)
-[ ]*[0-9a-f]+: a92f sh v0,30\(v0\)
-[ ]*[0-9a-f]+: a90f sh v0,30\(s0\)
-[ ]*[0-9a-f]+: a91f sh v0,30\(s1\)
-[ ]*[0-9a-f]+: a99f sh v1,30\(s1\)
-[ ]*[0-9a-f]+: aa1f sh a0,30\(s1\)
-[ ]*[0-9a-f]+: aa9f sh a1,30\(s1\)
-[ ]*[0-9a-f]+: ab1f sh a2,30\(s1\)
-[ ]*[0-9a-f]+: ab9f sh a3,30\(s1\)
-[ ]*[0-9a-f]+: a89f sh s1,30\(s1\)
-[ ]*[0-9a-f]+: a81f sh zero,30\(s1\)
-[ ]*[0-9a-f]+: 3860 0004 sh v1,4\(zero\)
-[ ]*[0-9a-f]+: 3860 0004 sh v1,4\(zero\)
-[ ]*[0-9a-f]+: 3860 7fff sh v1,32767\(zero\)
-[ ]*[0-9a-f]+: 3860 8000 sh v1,-32768\(zero\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 3861 ffff sh v1,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 3861 0000 sh v1,0\(at\)
-[ ]*[0-9a-f]+: 3860 8000 sh v1,-32768\(zero\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 3861 0001 sh v1,1\(at\)
-[ ]*[0-9a-f]+: 3860 8001 sh v1,-32767\(zero\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 3861 0000 sh v1,0\(at\)
-[ ]*[0-9a-f]+: 3860 ffff sh v1,-1\(zero\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 3861 5678 sh v1,22136\(at\)
-[ ]*[0-9a-f]+: 3864 0000 sh v1,0\(a0\)
-[ ]*[0-9a-f]+: 3864 0000 sh v1,0\(a0\)
-[ ]*[0-9a-f]+: 3864 7fff sh v1,32767\(a0\)
-[ ]*[0-9a-f]+: 3864 8000 sh v1,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 3861 ffff sh v1,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 3861 0000 sh v1,0\(at\)
-[ ]*[0-9a-f]+: 3864 8000 sh v1,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 3861 0001 sh v1,1\(at\)
-[ ]*[0-9a-f]+: 3864 8001 sh v1,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 3861 0000 sh v1,0\(at\)
-[ ]*[0-9a-f]+: 3864 ffff sh v1,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 3861 5678 sh v1,22136\(at\)
-[ ]*[0-9a-f]+: 0064 1350 slt v0,a0,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0044 1350 slt v0,a0,v0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0044 1350 slt v0,a0,v0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0061 1350 slt v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0064 1390 sltu v0,a0,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0044 1390 sltu v0,a0,v0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 0044 1390 sltu v0,a0,v0
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0061 1390 sltu v0,at,v1
-[ ]*[0-9a-f]+: 7042 0001 xori v0,v0,0x1
-[ ]*[0-9a-f]+: 2522 sll v0,v0,1
-[ ]*[0-9a-f]+: 2524 sll v0,v0,2
-[ ]*[0-9a-f]+: 2526 sll v0,v0,3
-[ ]*[0-9a-f]+: 2528 sll v0,v0,4
-[ ]*[0-9a-f]+: 252a sll v0,v0,5
-[ ]*[0-9a-f]+: 252c sll v0,v0,6
-[ ]*[0-9a-f]+: 252e sll v0,v0,7
-[ ]*[0-9a-f]+: 2520 sll v0,v0,8
-[ ]*[0-9a-f]+: 2530 sll v0,v1,8
-[ ]*[0-9a-f]+: 2540 sll v0,a0,8
-[ ]*[0-9a-f]+: 2550 sll v0,a1,8
-[ ]*[0-9a-f]+: 2560 sll v0,a2,8
-[ ]*[0-9a-f]+: 2570 sll v0,a3,8
-[ ]*[0-9a-f]+: 2500 sll v0,s0,8
-[ ]*[0-9a-f]+: 2510 sll v0,s1,8
-[ ]*[0-9a-f]+: 25a0 sll v1,v0,8
-[ ]*[0-9a-f]+: 2620 sll a0,v0,8
-[ ]*[0-9a-f]+: 26a0 sll a1,v0,8
-[ ]*[0-9a-f]+: 2720 sll a2,v0,8
-[ ]*[0-9a-f]+: 27a0 sll a3,v0,8
-[ ]*[0-9a-f]+: 2420 sll s0,v0,8
-[ ]*[0-9a-f]+: 24a0 sll s1,v0,8
-[ ]*[0-9a-f]+: 2522 sll v0,v0,1
-[ ]*[0-9a-f]+: 25b2 sll v1,v1,1
-[ ]*[0-9a-f]+: 0064 1010 sllv v0,v1,a0
-[ ]*[0-9a-f]+: 0044 1010 sllv v0,v0,a0
-[ ]*[0-9a-f]+: 0044 1010 sllv v0,v0,a0
-[ ]*[0-9a-f]+: 0044 1010 sllv v0,v0,a0
-[ ]*[0-9a-f]+: 0044 0000 sll v0,a0,0x0
-[ ]*[0-9a-f]+: 0044 0800 sll v0,a0,0x1
-[ ]*[0-9a-f]+: 0044 f800 sll v0,a0,0x1f
-[ ]*[0-9a-f]+: 0042 f800 sll v0,v0,0x1f
-[ ]*[0-9a-f]+: 0042 f800 sll v0,v0,0x1f
-[ ]*[0-9a-f]+: 0083 1350 slt v0,v1,a0
-[ ]*[0-9a-f]+: 0082 1350 slt v0,v0,a0
-[ ]*[0-9a-f]+: 0082 1350 slt v0,v0,a0
-[ ]*[0-9a-f]+: 9043 0000 slti v0,v1,0
-[ ]*[0-9a-f]+: 9043 8000 slti v0,v1,-32768
-[ ]*[0-9a-f]+: 9043 0000 slti v0,v1,0
-[ ]*[0-9a-f]+: 9043 7fff slti v0,v1,32767
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0023 1350 slt v0,v1,at
-[ ]*[0-9a-f]+: 9064 8000 slti v1,a0,-32768
-[ ]*[0-9a-f]+: 9064 0000 slti v1,a0,0
-[ ]*[0-9a-f]+: 9064 7fff slti v1,a0,32767
-[ ]*[0-9a-f]+: 9064 ffff slti v1,a0,-1
-[ ]*[0-9a-f]+: 9063 ffff slti v1,v1,-1
-[ ]*[0-9a-f]+: 9063 ffff slti v1,v1,-1
-[ ]*[0-9a-f]+: b064 8000 sltiu v1,a0,-32768
-[ ]*[0-9a-f]+: b064 0000 sltiu v1,a0,0
-[ ]*[0-9a-f]+: b064 7fff sltiu v1,a0,32767
-[ ]*[0-9a-f]+: b064 ffff sltiu v1,a0,-1
-[ ]*[0-9a-f]+: b063 ffff sltiu v1,v1,-1
-[ ]*[0-9a-f]+: b063 ffff sltiu v1,v1,-1
-[ ]*[0-9a-f]+: 0083 1390 sltu v0,v1,a0
-[ ]*[0-9a-f]+: 0082 1390 sltu v0,v0,a0
-[ ]*[0-9a-f]+: 0082 1390 sltu v0,v0,a0
-[ ]*[0-9a-f]+: b043 0000 sltiu v0,v1,0
-[ ]*[0-9a-f]+: b043 8000 sltiu v0,v1,-32768
-[ ]*[0-9a-f]+: b043 0000 sltiu v0,v1,0
-[ ]*[0-9a-f]+: b043 7fff sltiu v0,v1,32767
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0023 1390 sltu v0,v1,at
-[ ]*[0-9a-f]+: 0083 1310 xor v0,v1,a0
-[ ]*[0-9a-f]+: 0040 1390 sltu v0,zero,v0
-[ ]*[0-9a-f]+: 0080 1390 sltu v0,zero,a0
-[ ]*[0-9a-f]+: 0060 1390 sltu v0,zero,v1
-[ ]*[0-9a-f]+: 0060 1390 sltu v0,zero,v1
-[ ]*[0-9a-f]+: 7043 0001 xori v0,v1,0x1
-[ ]*[0-9a-f]+: 0040 1390 sltu v0,zero,v0
-[ ]*[0-9a-f]+: 3043 0001 addiu v0,v1,1
-[ ]*[0-9a-f]+: 0040 1390 sltu v0,zero,v0
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0023 1310 xor v0,v1,at
-[ ]*[0-9a-f]+: 0040 1390 sltu v0,zero,v0
-[ ]*[0-9a-f]+: 0064 1090 srav v0,v1,a0
-[ ]*[0-9a-f]+: 0044 1090 srav v0,v0,a0
-[ ]*[0-9a-f]+: 0044 1090 srav v0,v0,a0
-[ ]*[0-9a-f]+: 0044 1090 srav v0,v0,a0
-[ ]*[0-9a-f]+: 0044 0080 sra v0,a0,0x0
-[ ]*[0-9a-f]+: 0044 0880 sra v0,a0,0x1
-[ ]*[0-9a-f]+: 0044 f880 sra v0,a0,0x1f
-[ ]*[0-9a-f]+: 0042 f880 sra v0,v0,0x1f
-[ ]*[0-9a-f]+: 0042 f880 sra v0,v0,0x1f
-[ ]*[0-9a-f]+: 0064 1050 srlv v0,v1,a0
-[ ]*[0-9a-f]+: 0044 1050 srlv v0,v0,a0
-[ ]*[0-9a-f]+: 0044 1050 srlv v0,v0,a0
-[ ]*[0-9a-f]+: 0044 1050 srlv v0,v0,a0
-[ ]*[0-9a-f]+: 0044 0040 srl v0,a0,0x0
-[ ]*[0-9a-f]+: 2543 srl v0,a0,1
-[ ]*[0-9a-f]+: 0044 f840 srl v0,a0,0x1f
-[ ]*[0-9a-f]+: 0042 f840 srl v0,v0,0x1f
-[ ]*[0-9a-f]+: 0042 f840 srl v0,v0,0x1f
-[ ]*[0-9a-f]+: 2523 srl v0,v0,1
-[ ]*[0-9a-f]+: 2525 srl v0,v0,2
-[ ]*[0-9a-f]+: 2527 srl v0,v0,3
-[ ]*[0-9a-f]+: 2529 srl v0,v0,4
-[ ]*[0-9a-f]+: 252b srl v0,v0,5
-[ ]*[0-9a-f]+: 252d srl v0,v0,6
-[ ]*[0-9a-f]+: 252f srl v0,v0,7
-[ ]*[0-9a-f]+: 2521 srl v0,v0,8
-[ ]*[0-9a-f]+: 2531 srl v0,v1,8
-[ ]*[0-9a-f]+: 2541 srl v0,a0,8
-[ ]*[0-9a-f]+: 2551 srl v0,a1,8
-[ ]*[0-9a-f]+: 2561 srl v0,a2,8
-[ ]*[0-9a-f]+: 2571 srl v0,a3,8
-[ ]*[0-9a-f]+: 2501 srl v0,s0,8
-[ ]*[0-9a-f]+: 2511 srl v0,s1,8
-[ ]*[0-9a-f]+: 2521 srl v0,v0,8
-[ ]*[0-9a-f]+: 25a1 srl v1,v0,8
-[ ]*[0-9a-f]+: 2621 srl a0,v0,8
-[ ]*[0-9a-f]+: 26a1 srl a1,v0,8
-[ ]*[0-9a-f]+: 2721 srl a2,v0,8
-[ ]*[0-9a-f]+: 27a1 srl a3,v0,8
-[ ]*[0-9a-f]+: 2421 srl s0,v0,8
-[ ]*[0-9a-f]+: 24a1 srl s1,v0,8
-[ ]*[0-9a-f]+: 25b3 srl v1,v1,1
-[ ]*[0-9a-f]+: 25b3 srl v1,v1,1
-[ ]*[0-9a-f]+: 0083 1190 sub v0,v1,a0
-[ ]*[0-9a-f]+: 03fe e990 sub sp,s8,ra
-[ ]*[0-9a-f]+: 0082 1190 sub v0,v0,a0
-[ ]*[0-9a-f]+: 0082 1190 sub v0,v0,a0
-[ ]*[0-9a-f]+: 05a5 subu v0,v1,v0
-[ ]*[0-9a-f]+: 05b5 subu v0,v1,v1
-[ ]*[0-9a-f]+: 05c5 subu v0,v1,a0
-[ ]*[0-9a-f]+: 05d5 subu v0,v1,a1
-[ ]*[0-9a-f]+: 05e5 subu v0,v1,a2
-[ ]*[0-9a-f]+: 05f5 subu v0,v1,a3
-[ ]*[0-9a-f]+: 0585 subu v0,v1,s0
-[ ]*[0-9a-f]+: 0595 subu v0,v1,s1
-[ ]*[0-9a-f]+: 0515 subu v0,v0,s1
-[ ]*[0-9a-f]+: 0615 subu v0,a0,s1
-[ ]*[0-9a-f]+: 0695 subu v0,a1,s1
-[ ]*[0-9a-f]+: 0715 subu v0,a2,s1
-[ ]*[0-9a-f]+: 0795 subu v0,a3,s1
-[ ]*[0-9a-f]+: 0415 subu v0,s0,s1
-[ ]*[0-9a-f]+: 0495 subu v0,s1,s1
-[ ]*[0-9a-f]+: 0515 subu v0,v0,s1
-[ ]*[0-9a-f]+: 0517 subu v1,v0,s1
-[ ]*[0-9a-f]+: 0519 subu a0,v0,s1
-[ ]*[0-9a-f]+: 051b subu a1,v0,s1
-[ ]*[0-9a-f]+: 051d subu a2,v0,s1
-[ ]*[0-9a-f]+: 051f subu a3,v0,s1
-[ ]*[0-9a-f]+: 0511 subu s0,v0,s1
-[ ]*[0-9a-f]+: 0513 subu s1,v0,s1
-[ ]*[0-9a-f]+: 07af subu a3,a3,v0
-[ ]*[0-9a-f]+: 07af subu a3,a3,v0
-[ ]*[0-9a-f]+: 0083 11d0 subu v0,v1,a0
-[ ]*[0-9a-f]+: 03fe e9d0 subu sp,s8,ra
-[ ]*[0-9a-f]+: 0082 11d0 subu v0,v0,a0
-[ ]*[0-9a-f]+: 0082 11d0 subu v0,v0,a0
-[ ]*[0-9a-f]+: 3042 0000 addiu v0,v0,0
-[ ]*[0-9a-f]+: 3042 ffff addiu v0,v0,-1
-[ ]*[0-9a-f]+: 3042 8001 addiu v0,v0,-32767
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0022 11d0 subu v0,v0,at
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0022 11d0 subu v0,v0,at
-[ ]*[0-9a-f]+: e940 sw v0,0\(a0\)
-[ ]*[0-9a-f]+: e940 sw v0,0\(a0\)
-[ ]*[0-9a-f]+: e941 sw v0,4\(a0\)
-[ ]*[0-9a-f]+: e942 sw v0,8\(a0\)
-[ ]*[0-9a-f]+: e943 sw v0,12\(a0\)
-[ ]*[0-9a-f]+: e944 sw v0,16\(a0\)
-[ ]*[0-9a-f]+: e945 sw v0,20\(a0\)
-[ ]*[0-9a-f]+: e946 sw v0,24\(a0\)
-[ ]*[0-9a-f]+: e947 sw v0,28\(a0\)
-[ ]*[0-9a-f]+: e948 sw v0,32\(a0\)
-[ ]*[0-9a-f]+: e949 sw v0,36\(a0\)
-[ ]*[0-9a-f]+: e94a sw v0,40\(a0\)
-[ ]*[0-9a-f]+: e94b sw v0,44\(a0\)
-[ ]*[0-9a-f]+: e94c sw v0,48\(a0\)
-[ ]*[0-9a-f]+: e94d sw v0,52\(a0\)
-[ ]*[0-9a-f]+: e94e sw v0,56\(a0\)
-[ ]*[0-9a-f]+: e94f sw v0,60\(a0\)
-[ ]*[0-9a-f]+: e95f sw v0,60\(a1\)
-[ ]*[0-9a-f]+: e96f sw v0,60\(a2\)
-[ ]*[0-9a-f]+: e97f sw v0,60\(a3\)
-[ ]*[0-9a-f]+: e90f sw v0,60\(s0\)
-[ ]*[0-9a-f]+: e91f sw v0,60\(s1\)
-[ ]*[0-9a-f]+: e92f sw v0,60\(v0\)
-[ ]*[0-9a-f]+: e93f sw v0,60\(v1\)
-[ ]*[0-9a-f]+: e9bf sw v1,60\(v1\)
-[ ]*[0-9a-f]+: ea3f sw a0,60\(v1\)
-[ ]*[0-9a-f]+: eabf sw a1,60\(v1\)
-[ ]*[0-9a-f]+: eb3f sw a2,60\(v1\)
-[ ]*[0-9a-f]+: ebbf sw a3,60\(v1\)
-[ ]*[0-9a-f]+: e8bf sw s1,60\(v1\)
-[ ]*[0-9a-f]+: e83f sw zero,60\(v1\)
-[ ]*[0-9a-f]+: c800 sw zero,0\(sp\)
-[ ]*[0-9a-f]+: c800 sw zero,0\(sp\)
-[ ]*[0-9a-f]+: c801 sw zero,4\(sp\)
-[ ]*[0-9a-f]+: c802 sw zero,8\(sp\)
-[ ]*[0-9a-f]+: c803 sw zero,12\(sp\)
-[ ]*[0-9a-f]+: c804 sw zero,16\(sp\)
-[ ]*[0-9a-f]+: c805 sw zero,20\(sp\)
-[ ]*[0-9a-f]+: c81e sw zero,120\(sp\)
-[ ]*[0-9a-f]+: c81f sw zero,124\(sp\)
-[ ]*[0-9a-f]+: c85f sw v0,124\(sp\)
-[ ]*[0-9a-f]+: ca3f sw s1,124\(sp\)
-[ ]*[0-9a-f]+: c87f sw v1,124\(sp\)
-[ ]*[0-9a-f]+: c89f sw a0,124\(sp\)
-[ ]*[0-9a-f]+: c8bf sw a1,124\(sp\)
-[ ]*[0-9a-f]+: c8df sw a2,124\(sp\)
-[ ]*[0-9a-f]+: c8ff sw a3,124\(sp\)
-[ ]*[0-9a-f]+: cbff sw ra,124\(sp\)
-[ ]*[0-9a-f]+: f860 0004 sw v1,4\(zero\)
-[ ]*[0-9a-f]+: f860 0004 sw v1,4\(zero\)
-[ ]*[0-9a-f]+: f860 7fff sw v1,32767\(zero\)
-[ ]*[0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: f861 ffff sw v1,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
-[ ]*[0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: f861 0001 sw v1,1\(at\)
-[ ]*[0-9a-f]+: f860 8001 sw v1,-32767\(zero\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
-[ ]*[0-9a-f]+: f860 ffff sw v1,-1\(zero\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: f861 5678 sw v1,22136\(at\)
-[ ]*[0-9a-f]+: f864 0000 sw v1,0\(a0\)
-[ ]*[0-9a-f]+: f864 0000 sw v1,0\(a0\)
-[ ]*[0-9a-f]+: f864 7fff sw v1,32767\(a0\)
-[ ]*[0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: f861 ffff sw v1,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
-[ ]*[0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: f861 0001 sw v1,1\(at\)
-[ ]*[0-9a-f]+: f864 8001 sw v1,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
-[ ]*[0-9a-f]+: f864 ffff sw v1,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: f861 5678 sw v1,22136\(at\)
-[ ]*[0-9a-f]+: 44ca swm s0,ra,48\(sp\)
-[ ]*[0-9a-f]+: 45ca swm s0-s1,ra,48\(sp\)
-[ ]*[0-9a-f]+: 45ca swm s0-s1,ra,48\(sp\)
-[ ]*[0-9a-f]+: 46ca swm s0-s2,ra,48\(sp\)
-[ ]*[0-9a-f]+: 46ca swm s0-s2,ra,48\(sp\)
-[ ]*[0-9a-f]+: 47ca swm s0-s3,ra,48\(sp\)
-[ ]*[0-9a-f]+: 47ca swm s0-s3,ra,48\(sp\)
-[ ]*[0-9a-f]+: 440a swm s0,ra,0\(sp\)
-[ ]*[0-9a-f]+: 440a swm s0,ra,0\(sp\)
-[ ]*[0-9a-f]+: 441a swm s0,ra,4\(sp\)
-[ ]*[0-9a-f]+: 442a swm s0,ra,8\(sp\)
-[ ]*[0-9a-f]+: 443a swm s0,ra,12\(sp\)
-[ ]*[0-9a-f]+: 444a swm s0,ra,16\(sp\)
-[ ]*[0-9a-f]+: 445a swm s0,ra,20\(sp\)
-[ ]*[0-9a-f]+: 446a swm s0,ra,24\(sp\)
-[ ]*[0-9a-f]+: 447a swm s0,ra,28\(sp\)
-[ ]*[0-9a-f]+: 448a swm s0,ra,32\(sp\)
-[ ]*[0-9a-f]+: 449a swm s0,ra,36\(sp\)
-[ ]*[0-9a-f]+: 44aa swm s0,ra,40\(sp\)
-[ ]*[0-9a-f]+: 44ba swm s0,ra,44\(sp\)
-[ ]*[0-9a-f]+: 44ca swm s0,ra,48\(sp\)
-[ ]*[0-9a-f]+: 44da swm s0,ra,52\(sp\)
-[ ]*[0-9a-f]+: 44ea swm s0,ra,56\(sp\)
-[ ]*[0-9a-f]+: 44fa swm s0,ra,60\(sp\)
-[ ]*[0-9a-f]+: 2020 d000 swm s0,0\(zero\)
-[ ]*[0-9a-f]+: 2020 d004 swm s0,4\(zero\)
-[ ]*[0-9a-f]+: 2020 d7ff swm s0,2047\(zero\)
-[ ]*[0-9a-f]+: 2020 d800 swm s0,-2048\(zero\)
-[ ]*[0-9a-f]+: 3020 0800 li at,2048
-[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
-[ ]*[0-9a-f]+: 3020 f7ff li at,-2049
-[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
-[ ]*[0-9a-f]+: 2025 d000 swm s0,0\(a1\)
-[ ]*[0-9a-f]+: 2025 d7ff swm s0,2047\(a1\)
-[ ]*[0-9a-f]+: 2025 d800 swm s0,-2048\(a1\)
-[ ]*[0-9a-f]+: 3025 0800 addiu at,a1,2048
-[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
-[ ]*[0-9a-f]+: 3025 f7ff addiu at,a1,-2049
-[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
-[ ]*[0-9a-f]+: 2045 d7ff swm s0-s1,2047\(a1\)
-[ ]*[0-9a-f]+: 2065 d7ff swm s0-s2,2047\(a1\)
-[ ]*[0-9a-f]+: 2085 d7ff swm s0-s3,2047\(a1\)
-[ ]*[0-9a-f]+: 20a5 d7ff swm s0-s4,2047\(a1\)
-[ ]*[0-9a-f]+: 20c5 d7ff swm s0-s5,2047\(a1\)
-[ ]*[0-9a-f]+: 20e5 d7ff swm s0-s6,2047\(a1\)
-[ ]*[0-9a-f]+: 2105 d7ff swm s0-s7,2047\(a1\)
-[ ]*[0-9a-f]+: 2125 d7ff swm s0-s7,s8,2047\(a1\)
-[ ]*[0-9a-f]+: 2205 d7ff swm ra,2047\(a1\)
-[ ]*[0-9a-f]+: 2225 d000 swm s0,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2245 d000 swm s0-s1,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2265 d000 swm s0-s2,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2285 d000 swm s0-s3,ra,0\(a1\)
-[ ]*[0-9a-f]+: 22a5 d000 swm s0-s4,ra,0\(a1\)
-[ ]*[0-9a-f]+: 22c5 d000 swm s0-s5,ra,0\(a1\)
-[ ]*[0-9a-f]+: 22e5 d000 swm s0-s6,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2305 d000 swm s0-s7,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2325 d000 swm s0-s7,s8,ra,0\(a1\)
-[ ]*[0-9a-f]+: 303d 8000 addiu at,sp,-32768
-[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
-[ ]*[0-9a-f]+: 303d 7fff addiu at,sp,32767
-[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
-[ ]*[0-9a-f]+: 203d d000 swm s0,0\(sp\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 03a1 0950 addu at,at,sp
-[ ]*[0-9a-f]+: 2021 dfff swm s0,-1\(at\)
-[ ]*[0-9a-f]+: 2040 9000 swp v0,0\(zero\)
-[ ]*[0-9a-f]+: 2040 9004 swp v0,4\(zero\)
-[ ]*[0-9a-f]+: 2040 97ff swp v0,2047\(zero\)
-[ ]*[0-9a-f]+: 2040 9800 swp v0,-2048\(zero\)
-[ ]*[0-9a-f]+: 3020 0800 li at,2048
-[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
-[ ]*[0-9a-f]+: 3020 f7ff li at,-2049
-[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
-[ ]*[0-9a-f]+: 205d 9000 swp v0,0\(sp\)
-[ ]*[0-9a-f]+: 205d 9000 swp v0,0\(sp\)
-[ ]*[0-9a-f]+: 2043 97ff swp v0,2047\(v1\)
-[ ]*[0-9a-f]+: 2043 9800 swp v0,-2048\(v1\)
-[ ]*[0-9a-f]+: 3023 0800 addiu at,v1,2048
-[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
-[ ]*[0-9a-f]+: 3023 f7ff addiu at,v1,-2049
-[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
-[ ]*[0-9a-f]+: 3023 7fff addiu at,v1,32767
-[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
-[ ]*[0-9a-f]+: 3023 8000 addiu at,v1,-32768
-[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
-[ ]*[0-9a-f]+: 2043 9000 swp v0,0\(v1\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0061 0950 addu at,at,v1
-[ ]*[0-9a-f]+: 2041 9fff swp v0,-1\(at\)
-[ ]*[0-9a-f]+: 0000 6b7c sync
-[ ]*[0-9a-f]+: 0000 6b7c sync
-[ ]*[0-9a-f]+: 0001 6b7c sync 0x1
-[ ]*[0-9a-f]+: 0002 6b7c sync 0x2
-[ ]*[0-9a-f]+: 0003 6b7c sync 0x3
-[ ]*[0-9a-f]+: 0004 6b7c sync_wmb
-[ ]*[0-9a-f]+: 001e 6b7c sync 0x1e
-[ ]*[0-9a-f]+: 001f 6b7c sync 0x1f
-[ ]*[0-9a-f]+: 4180 0000 synci 0\(zero\)
-[ ]*[0-9a-f]+: 4180 0000 synci 0\(zero\)
-[ ]*[0-9a-f]+: 4180 0000 synci 0\(zero\)
-[ ]*[0-9a-f]+: 4180 07ff synci 2047\(zero\)
-[ ]*[0-9a-f]+: 4180 f800 synci -2048\(zero\)
-[ ]*[0-9a-f]+: 4180 0800 synci 2048\(zero\)
-[ ]*[0-9a-f]+: 4180 f7ff synci -2049\(zero\)
-[ ]*[0-9a-f]+: 4180 7fff synci 32767\(zero\)
-[ ]*[0-9a-f]+: 4180 8000 synci -32768\(zero\)
-[ ]*[0-9a-f]+: 4182 0000 synci 0\(v0\)
-[ ]*[0-9a-f]+: 4183 0000 synci 0\(v1\)
-[ ]*[0-9a-f]+: 4183 07ff synci 2047\(v1\)
-[ ]*[0-9a-f]+: 4183 f800 synci -2048\(v1\)
-[ ]*[0-9a-f]+: 4183 0800 synci 2048\(v1\)
-[ ]*[0-9a-f]+: 4183 f7ff synci -2049\(v1\)
-[ ]*[0-9a-f]+: 4183 7fff synci 32767\(v1\)
-[ ]*[0-9a-f]+: 4183 8000 synci -32768\(v1\)
-[ ]*[0-9a-f]+: 0000 8b7c syscall
-[ ]*[0-9a-f]+: 0000 8b7c syscall
-[ ]*[0-9a-f]+: 0001 8b7c syscall 0x1
-[ ]*[0-9a-f]+: 0002 8b7c syscall 0x2
-[ ]*[0-9a-f]+: 00ff 8b7c syscall 0xff
-[ ]*[0-9a-f]+: 0062 003c teq v0,v1
-[ ]*[0-9a-f]+: 0043 003c teq v1,v0
-[ ]*[0-9a-f]+: 0062 003c teq v0,v1
-[ ]*[0-9a-f]+: 0062 103c teq v0,v1,0x1
-[ ]*[0-9a-f]+: 0062 f03c teq v0,v1,0xf
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0022 003c teq v0,at
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0022 003c teq v0,at
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 0022 003c teq v0,at
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0022 003c teq v0,at
-[ ]*[0-9a-f]+: 0062 023c tge v0,v1
-[ ]*[0-9a-f]+: 0043 023c tge v1,v0
-[ ]*[0-9a-f]+: 0062 023c tge v0,v1
-[ ]*[0-9a-f]+: 0062 123c tge v0,v1,0x1
-[ ]*[0-9a-f]+: 0062 f23c tge v0,v1,0xf
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0022 023c tge v0,at
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0022 023c tge v0,at
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 0022 023c tge v0,at
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0022 023c tge v0,at
-[ ]*[0-9a-f]+: 0062 043c tgeu v0,v1
-[ ]*[0-9a-f]+: 0043 043c tgeu v1,v0
-[ ]*[0-9a-f]+: 0062 043c tgeu v0,v1
-[ ]*[0-9a-f]+: 0062 143c tgeu v0,v1,0x1
-[ ]*[0-9a-f]+: 0062 f43c tgeu v0,v1,0xf
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0022 043c tgeu v0,at
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0022 043c tgeu v0,at
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 0022 043c tgeu v0,at
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0022 043c tgeu v0,at
-[ ]*[0-9a-f]+: 0000 037c tlbp
-[ ]*[0-9a-f]+: 0000 137c tlbr
-[ ]*[0-9a-f]+: 0000 237c tlbwi
-[ ]*[0-9a-f]+: 0000 337c tlbwr
-[ ]*[0-9a-f]+: 0062 083c tlt v0,v1
-[ ]*[0-9a-f]+: 0043 083c tlt v1,v0
-[ ]*[0-9a-f]+: 0062 083c tlt v0,v1
-[ ]*[0-9a-f]+: 0062 183c tlt v0,v1,0x1
-[ ]*[0-9a-f]+: 0062 f83c tlt v0,v1,0xf
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0022 083c tlt v0,at
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0022 083c tlt v0,at
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 0022 083c tlt v0,at
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0022 083c tlt v0,at
-[ ]*[0-9a-f]+: 0062 0a3c tltu v0,v1
-[ ]*[0-9a-f]+: 0043 0a3c tltu v1,v0
-[ ]*[0-9a-f]+: 0062 0a3c tltu v0,v1
-[ ]*[0-9a-f]+: 0062 1a3c tltu v0,v1,0x1
-[ ]*[0-9a-f]+: 0062 fa3c tltu v0,v1,0xf
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
-[ ]*[0-9a-f]+: 3020 ffff li at,-1
-[ ]*[0-9a-f]+: 0022 0a3c tltu v0,at
-[ ]*[0-9a-f]+: 0062 0c3c tne v0,v1
-[ ]*[0-9a-f]+: 0043 0c3c tne v1,v0
-[ ]*[0-9a-f]+: 0062 0c3c tne v0,v1
-[ ]*[0-9a-f]+: 0062 1c3c tne v0,v1,0x1
-[ ]*[0-9a-f]+: 0062 fc3c tne v0,v1,0xf
-[ ]*[0-9a-f]+: 3020 0000 li at,0
-[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
-[ ]*[0-9a-f]+: 3020 ffff li at,-1
-[ ]*[0-9a-f]+: 0022 0c3c tne v0,at
-[ ]*[0-9a-f]+: 0000 937c wait
-[ ]*[0-9a-f]+: 0000 937c wait
-[ ]*[0-9a-f]+: 0001 937c wait 0x1
-[ ]*[0-9a-f]+: 00ff 937c wait 0xff
-[ ]*[0-9a-f]+: 0043 f17c wrpgpr v0,v1
-[ ]*[0-9a-f]+: 0044 f17c wrpgpr v0,a0
-[ ]*[0-9a-f]+: 0042 f17c wrpgpr v0,v0
-[ ]*[0-9a-f]+: 0042 f17c wrpgpr v0,v0
-[ ]*[0-9a-f]+: 0043 7b3c wsbh v0,v1
-[ ]*[0-9a-f]+: 0044 7b3c wsbh v0,a0
-[ ]*[0-9a-f]+: 0042 7b3c wsbh v0,v0
-[ ]*[0-9a-f]+: 0042 7b3c wsbh v0,v0
-[ ]*[0-9a-f]+: 4528 xor v0,v0,v0
-[ ]*[0-9a-f]+: 4538 xor v0,v0,v1
-[ ]*[0-9a-f]+: 4548 xor v0,v0,a0
-[ ]*[0-9a-f]+: 4558 xor v0,v0,a1
-[ ]*[0-9a-f]+: 4568 xor v0,v0,a2
-[ ]*[0-9a-f]+: 4578 xor v0,v0,a3
-[ ]*[0-9a-f]+: 4508 xor v0,v0,s0
-[ ]*[0-9a-f]+: 4518 xor v0,v0,s1
-[ ]*[0-9a-f]+: 4598 xor v1,v1,s1
-[ ]*[0-9a-f]+: 4618 xor a0,a0,s1
-[ ]*[0-9a-f]+: 4698 xor a1,a1,s1
-[ ]*[0-9a-f]+: 4718 xor a2,a2,s1
-[ ]*[0-9a-f]+: 4798 xor a3,a3,s1
-[ ]*[0-9a-f]+: 4418 xor s0,s0,s1
-[ ]*[0-9a-f]+: 4498 xor s1,s1,s1
-[ ]*[0-9a-f]+: 4538 xor v0,v0,v1
-[ ]*[0-9a-f]+: 4538 xor v0,v0,v1
-[ ]*[0-9a-f]+: 4538 xor v0,v0,v1
-[ ]*[0-9a-f]+: 0083 1310 xor v0,v1,a0
-[ ]*[0-9a-f]+: 03fe eb10 xor sp,s8,ra
-[ ]*[0-9a-f]+: 0082 1310 xor v0,v0,a0
-[ ]*[0-9a-f]+: 0082 1310 xor v0,v0,a0
-[ ]*[0-9a-f]+: 7043 8000 xori v0,v1,0x8000
-[ ]*[0-9a-f]+: 7043 ffff xori v0,v1,0xffff
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0023 1310 xor v0,v1,at
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 0023 1310 xor v0,v1,at
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 5021 7fff ori at,at,0x7fff
-[ ]*[0-9a-f]+: 0023 1310 xor v0,v1,at
-[ ]*[0-9a-f]+: 7064 0000 xori v1,a0,0x0
-[ ]*[0-9a-f]+: 7064 7fff xori v1,a0,0x7fff
-[ ]*[0-9a-f]+: 7064 ffff xori v1,a0,0xffff
-[ ]*[0-9a-f]+: 7063 ffff xori v1,v1,0xffff
-[ ]*[0-9a-f]+: 7063 ffff xori v1,v1,0xffff
-[ ]*[0-9a-f]+: 6d01 addiu v0,sp,0
-[ ]*[0-9a-f]+: 6d03 addiu v0,sp,4
-[ ]*[0-9a-f]+: 6d05 addiu v0,sp,8
-[ ]*[0-9a-f]+: 6d07 addiu v0,sp,12
-[ ]*[0-9a-f]+: 6d09 addiu v0,sp,16
-[ ]*[0-9a-f]+: 6d7f addiu v0,sp,252
-[ ]*[0-9a-f]+: 6dff addiu v1,sp,252
-[ ]*[0-9a-f]+: 6e7f addiu a0,sp,252
-[ ]*[0-9a-f]+: 6eff addiu a1,sp,252
-[ ]*[0-9a-f]+: 6f7f addiu a2,sp,252
-[ ]*[0-9a-f]+: 6fff addiu a3,sp,252
-[ ]*[0-9a-f]+: 6c7f addiu s0,sp,252
-[ ]*[0-9a-f]+: 6cff addiu s1,sp,252
-[ ]*[0-9a-f]+: 6d2e addiu v0,v0,-1
-[ ]*[0-9a-f]+: 6d3e addiu v0,v1,-1
-[ ]*[0-9a-f]+: 6d4e addiu v0,a0,-1
-[ ]*[0-9a-f]+: 6d5e addiu v0,a1,-1
-[ ]*[0-9a-f]+: 6d6e addiu v0,a2,-1
-[ ]*[0-9a-f]+: 6d7e addiu v0,a3,-1
-[ ]*[0-9a-f]+: 6d0e addiu v0,s0,-1
-[ ]*[0-9a-f]+: 6d1e addiu v0,s1,-1
-[ ]*[0-9a-f]+: 6d9e addiu v1,s1,-1
-[ ]*[0-9a-f]+: 6e1e addiu a0,s1,-1
-[ ]*[0-9a-f]+: 6e9e addiu a1,s1,-1
-[ ]*[0-9a-f]+: 6f1e addiu a2,s1,-1
-[ ]*[0-9a-f]+: 6f9e addiu a3,s1,-1
-[ ]*[0-9a-f]+: 6c1e addiu s0,s1,-1
-[ ]*[0-9a-f]+: 6c9e addiu s1,s1,-1
-[ ]*[0-9a-f]+: 6c90 addiu s1,s1,1
-[ ]*[0-9a-f]+: 6c92 addiu s1,s1,4
-[ ]*[0-9a-f]+: 6c94 addiu s1,s1,8
-[ ]*[0-9a-f]+: 6c96 addiu s1,s1,12
-[ ]*[0-9a-f]+: 6c98 addiu s1,s1,16
-[ ]*[0-9a-f]+: 6c9a addiu s1,s1,20
-[ ]*[0-9a-f]+: 6c9c addiu s1,s1,24
-[ ]*[0-9a-f]+: 4c05 addiu sp,sp,8
-[ ]*[0-9a-f]+: 4c07 addiu sp,sp,12
-[ ]*[0-9a-f]+: 4dfd addiu sp,sp,1016
-[ ]*[0-9a-f]+: 4dff addiu sp,sp,1020
-[ ]*[0-9a-f]+: 4c01 addiu sp,sp,1024
-[ ]*[0-9a-f]+: 4c03 addiu sp,sp,1028
-[ ]*[0-9a-f]+: 4ffb addiu sp,sp,-12
-[ ]*[0-9a-f]+: 4ff9 addiu sp,sp,-16
-[ ]*[0-9a-f]+: 4e03 addiu sp,sp,-1020
-[ ]*[0-9a-f]+: 4e01 addiu sp,sp,-1024
-[ ]*[0-9a-f]+: 4fff addiu sp,sp,-1028
-[ ]*[0-9a-f]+: 4ffd addiu sp,sp,-1032
-[ ]*[0-9a-f]+: 4c00 addiu zero,zero,0
-[ ]*[0-9a-f]+: 4c40 addiu v0,v0,0
-[ ]*[0-9a-f]+: 4c60 addiu v1,v1,0
-[ ]*[0-9a-f]+: 4fc0 addiu s8,s8,0
-[ ]*[0-9a-f]+: 4fe0 addiu ra,ra,0
-[ ]*[0-9a-f]+: 4fe2 addiu ra,ra,1
-[ ]*[0-9a-f]+: 4fe4 addiu ra,ra,2
-[ ]*[0-9a-f]+: 4fe6 addiu ra,ra,3
-[ ]*[0-9a-f]+: 4fee addiu ra,ra,7
-[ ]*[0-9a-f]+: 4ff4 addiu ra,ra,-6
-[ ]*[0-9a-f]+: 4ff2 addiu ra,ra,-7
-[ ]*[0-9a-f]+: 4ff0 addiu ra,ra,-8
-[ ]*[0-9a-f]+: f860 0004 sw v1,4\(zero\)
-[ ]*[0-9a-f]+: f880 0008 sw a0,8\(zero\)
-[ ]*[0-9a-f]+: f860 0004 sw v1,4\(zero\)
-[ ]*[0-9a-f]+: f880 0008 sw a0,8\(zero\)
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
-[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
-[ ]*[0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
-[ ]*[0-9a-f]+: f880 8004 sw a0,-32764\(zero\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: f861 ffff sw v1,-1\(at\)
-[ ]*[0-9a-f]+: f881 0003 sw a0,3\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
-[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
-[ ]*[0-9a-f]+: f860 8000 sw v1,-32768\(zero\)
-[ ]*[0-9a-f]+: f880 8004 sw a0,-32764\(zero\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: f861 0001 sw v1,1\(at\)
-[ ]*[0-9a-f]+: f881 0005 sw a0,5\(at\)
-[ ]*[0-9a-f]+: f860 8001 sw v1,-32767\(zero\)
-[ ]*[0-9a-f]+: f880 8005 sw a0,-32763\(zero\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
-[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
-[ ]*[0-9a-f]+: f860 ffff sw v1,-1\(zero\)
-[ ]*[0-9a-f]+: f880 0003 sw a0,3\(zero\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: f861 5678 sw v1,22136\(at\)
-[ ]*[0-9a-f]+: f881 567c sw a0,22140\(at\)
-[ ]*[0-9a-f]+: f864 0000 sw v1,0\(a0\)
-[ ]*[0-9a-f]+: f884 0004 sw a0,4\(a0\)
-[ ]*[0-9a-f]+: f864 0000 sw v1,0\(a0\)
-[ ]*[0-9a-f]+: f884 0004 sw a0,4\(a0\)
-[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
-[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
-[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
-[ ]*[0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
-[ ]*[0-9a-f]+: f884 8004 sw a0,-32764\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
-[ ]*[0-9a-f]+: f861 ffff sw v1,-1\(at\)
-[ ]*[0-9a-f]+: f881 0003 sw a0,3\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
-[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
-[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
-[ ]*[0-9a-f]+: f864 8000 sw v1,-32768\(a0\)
-[ ]*[0-9a-f]+: f884 8004 sw a0,-32764\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
-[ ]*[0-9a-f]+: f861 0001 sw v1,1\(at\)
-[ ]*[0-9a-f]+: f881 0005 sw a0,5\(at\)
-[ ]*[0-9a-f]+: f864 8001 sw v1,-32767\(a0\)
-[ ]*[0-9a-f]+: f884 8005 sw a0,-32763\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
-[ ]*[0-9a-f]+: f861 0000 sw v1,0\(at\)
-[ ]*[0-9a-f]+: f881 0004 sw a0,4\(at\)
-[ ]*[0-9a-f]+: f864 ffff sw v1,-1\(a0\)
-[ ]*[0-9a-f]+: f884 0003 sw a0,3\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
-[ ]*[0-9a-f]+: f861 5678 sw v1,22136\(at\)
-[ ]*[0-9a-f]+: f881 567c sw a0,22140\(at\)
-[ ]*[0-9a-f]+: fc60 0004 lw v1,4\(zero\)
-[ ]*[0-9a-f]+: fc80 0008 lw a0,8\(zero\)
-[ ]*[0-9a-f]+: fc60 0004 lw v1,4\(zero\)
-[ ]*[0-9a-f]+: fc80 0008 lw a0,8\(zero\)
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
-[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
-[ ]*[0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
-[ ]*[0-9a-f]+: fc80 8004 lw a0,-32764\(zero\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: fc61 ffff lw v1,-1\(at\)
-[ ]*[0-9a-f]+: fc81 0003 lw a0,3\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
-[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
-[ ]*[0-9a-f]+: fc60 8000 lw v1,-32768\(zero\)
-[ ]*[0-9a-f]+: fc80 8004 lw a0,-32764\(zero\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: fc61 0001 lw v1,1\(at\)
-[ ]*[0-9a-f]+: fc81 0005 lw a0,5\(at\)
-[ ]*[0-9a-f]+: fc60 8001 lw v1,-32767\(zero\)
-[ ]*[0-9a-f]+: fc80 8005 lw a0,-32763\(zero\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
-[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
-[ ]*[0-9a-f]+: fc60 ffff lw v1,-1\(zero\)
-[ ]*[0-9a-f]+: fc80 0003 lw a0,3\(zero\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: fc61 5678 lw v1,22136\(at\)
-[ ]*[0-9a-f]+: fc81 567c lw a0,22140\(at\)
-[ ]*[0-9a-f]+: fc64 0000 lw v1,0\(a0\)
-[ ]*[0-9a-f]+: fc84 0004 lw a0,4\(a0\)
-[ ]*[0-9a-f]+: fc64 0000 lw v1,0\(a0\)
-[ ]*[0-9a-f]+: fc84 0004 lw a0,4\(a0\)
-[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
-[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
-[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
-[ ]*[0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
-[ ]*[0-9a-f]+: fc84 8004 lw a0,-32764\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
-[ ]*[0-9a-f]+: fc61 ffff lw v1,-1\(at\)
-[ ]*[0-9a-f]+: fc81 0003 lw a0,3\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
-[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
-[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
-[ ]*[0-9a-f]+: fc64 8000 lw v1,-32768\(a0\)
-[ ]*[0-9a-f]+: fc84 8004 lw a0,-32764\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
-[ ]*[0-9a-f]+: fc61 0001 lw v1,1\(at\)
-[ ]*[0-9a-f]+: fc81 0005 lw a0,5\(at\)
-[ ]*[0-9a-f]+: fc64 8001 lw v1,-32767\(a0\)
-[ ]*[0-9a-f]+: fc84 8005 lw a0,-32763\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
-[ ]*[0-9a-f]+: fc61 0000 lw v1,0\(at\)
-[ ]*[0-9a-f]+: fc81 0004 lw a0,4\(at\)
-[ ]*[0-9a-f]+: fc64 ffff lw v1,-1\(a0\)
-[ ]*[0-9a-f]+: fc84 0003 lw a0,3\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0024 0950 addu at,a0,at
-[ ]*[0-9a-f]+: fc61 5678 lw v1,22136\(at\)
-[ ]*[0-9a-f]+: fc81 567c lw a0,22140\(at\)
-[ ]*[0-9a-f]+: 4413 jrcaddiusp 0
-[ ]*[0-9a-f]+: 4433 jrcaddiusp 4
-[ ]*[0-9a-f]+: 4453 jrcaddiusp 8
-[ ]*[0-9a-f]+: 4473 jrcaddiusp 12
-[ ]*[0-9a-f]+: 4493 jrcaddiusp 16
-[ ]*[0-9a-f]+: 44b3 jrcaddiusp 20
-[ ]*[0-9a-f]+: 44d3 jrcaddiusp 24
-[ ]*[0-9a-f]+: 44f3 jrcaddiusp 28
-[ ]*[0-9a-f]+: 4513 jrcaddiusp 32
-[ ]*[0-9a-f]+: 4533 jrcaddiusp 36
-[ ]*[0-9a-f]+: 4553 jrcaddiusp 40
-[ ]*[0-9a-f]+: 47d3 jrcaddiusp 120
-[ ]*[0-9a-f]+: 47f3 jrcaddiusp 124
-[ ]*[0-9a-f]+: 2060 2000 ldc2 \$3,0\(zero\)
-[ ]*[0-9a-f]+: 2060 2000 ldc2 \$3,0\(zero\)
-[ ]*[0-9a-f]+: 2060 2004 ldc2 \$3,4\(zero\)
-[ ]*[0-9a-f]+: 2060 2004 ldc2 \$3,4\(zero\)
-[ ]*[0-9a-f]+: 2064 2000 ldc2 \$3,0\(a0\)
-[ ]*[0-9a-f]+: 2064 2000 ldc2 \$3,0\(a0\)
-[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
-[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
-[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 27ff ldc2 \$3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
-[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 2001 ldc2 \$3,1\(at\)
-[ ]*[0-9a-f]+: 3024 8001 addiu at,a0,-32767
-[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 2000 ldc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 2064 27ff ldc2 \$3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5800 ori at,at,0x5800
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 2678 ldc2 \$3,-392\(at\)
-[ ]*[0-9a-f]+: 2060 0000 lwc2 \$3,0\(zero\)
-[ ]*[0-9a-f]+: 2060 0000 lwc2 \$3,0\(zero\)
-[ ]*[0-9a-f]+: 2060 0004 lwc2 \$3,4\(zero\)
-[ ]*[0-9a-f]+: 2060 0004 lwc2 \$3,4\(zero\)
-[ ]*[0-9a-f]+: 2064 0000 lwc2 \$3,0\(a0\)
-[ ]*[0-9a-f]+: 2064 0000 lwc2 \$3,0\(a0\)
-[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
-[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
-[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 07ff lwc2 \$3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
-[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 0001 lwc2 \$3,1\(at\)
-[ ]*[0-9a-f]+: 3024 8001 addiu at,a0,-32767
-[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 0000 lwc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 2064 07ff lwc2 \$3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5800 ori at,at,0x5800
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 0678 lwc2 \$3,-392\(at\)
-[ ]*[0-9a-f]+: 00a0 4d3c mfc2 a1,\$0
-[ ]*[0-9a-f]+: 00a1 4d3c mfc2 a1,\$1
-[ ]*[0-9a-f]+: 00a2 4d3c mfc2 a1,\$2
-[ ]*[0-9a-f]+: 00a3 4d3c mfc2 a1,\$3
-[ ]*[0-9a-f]+: 00a4 4d3c mfc2 a1,\$4
-[ ]*[0-9a-f]+: 00a5 4d3c mfc2 a1,\$5
-[ ]*[0-9a-f]+: 00a6 4d3c mfc2 a1,\$6
-[ ]*[0-9a-f]+: 00a7 4d3c mfc2 a1,\$7
-[ ]*[0-9a-f]+: 00a8 4d3c mfc2 a1,\$8
-[ ]*[0-9a-f]+: 00a9 4d3c mfc2 a1,\$9
-[ ]*[0-9a-f]+: 00aa 4d3c mfc2 a1,\$10
-[ ]*[0-9a-f]+: 00ab 4d3c mfc2 a1,\$11
-[ ]*[0-9a-f]+: 00ac 4d3c mfc2 a1,\$12
-[ ]*[0-9a-f]+: 00ad 4d3c mfc2 a1,\$13
-[ ]*[0-9a-f]+: 00ae 4d3c mfc2 a1,\$14
-[ ]*[0-9a-f]+: 00af 4d3c mfc2 a1,\$15
-[ ]*[0-9a-f]+: 00b0 4d3c mfc2 a1,\$16
-[ ]*[0-9a-f]+: 00b1 4d3c mfc2 a1,\$17
-[ ]*[0-9a-f]+: 00b2 4d3c mfc2 a1,\$18
-[ ]*[0-9a-f]+: 00b3 4d3c mfc2 a1,\$19
-[ ]*[0-9a-f]+: 00b4 4d3c mfc2 a1,\$20
-[ ]*[0-9a-f]+: 00b5 4d3c mfc2 a1,\$21
-[ ]*[0-9a-f]+: 00b6 4d3c mfc2 a1,\$22
-[ ]*[0-9a-f]+: 00b7 4d3c mfc2 a1,\$23
-[ ]*[0-9a-f]+: 00b8 4d3c mfc2 a1,\$24
-[ ]*[0-9a-f]+: 00b9 4d3c mfc2 a1,\$25
-[ ]*[0-9a-f]+: 00ba 4d3c mfc2 a1,\$26
-[ ]*[0-9a-f]+: 00bb 4d3c mfc2 a1,\$27
-[ ]*[0-9a-f]+: 00bc 4d3c mfc2 a1,\$28
-[ ]*[0-9a-f]+: 00bd 4d3c mfc2 a1,\$29
-[ ]*[0-9a-f]+: 00be 4d3c mfc2 a1,\$30
-[ ]*[0-9a-f]+: 00bf 4d3c mfc2 a1,\$31
-[ ]*[0-9a-f]+: 00a0 8d3c mfhc2 a1,\$0
-[ ]*[0-9a-f]+: 00a1 8d3c mfhc2 a1,\$1
-[ ]*[0-9a-f]+: 00a2 8d3c mfhc2 a1,\$2
-[ ]*[0-9a-f]+: 00a3 8d3c mfhc2 a1,\$3
-[ ]*[0-9a-f]+: 00a4 8d3c mfhc2 a1,\$4
-[ ]*[0-9a-f]+: 00a5 8d3c mfhc2 a1,\$5
-[ ]*[0-9a-f]+: 00a6 8d3c mfhc2 a1,\$6
-[ ]*[0-9a-f]+: 00a7 8d3c mfhc2 a1,\$7
-[ ]*[0-9a-f]+: 00a8 8d3c mfhc2 a1,\$8
-[ ]*[0-9a-f]+: 00a9 8d3c mfhc2 a1,\$9
-[ ]*[0-9a-f]+: 00aa 8d3c mfhc2 a1,\$10
-[ ]*[0-9a-f]+: 00ab 8d3c mfhc2 a1,\$11
-[ ]*[0-9a-f]+: 00ac 8d3c mfhc2 a1,\$12
-[ ]*[0-9a-f]+: 00ad 8d3c mfhc2 a1,\$13
-[ ]*[0-9a-f]+: 00ae 8d3c mfhc2 a1,\$14
-[ ]*[0-9a-f]+: 00af 8d3c mfhc2 a1,\$15
-[ ]*[0-9a-f]+: 00b0 8d3c mfhc2 a1,\$16
-[ ]*[0-9a-f]+: 00b1 8d3c mfhc2 a1,\$17
-[ ]*[0-9a-f]+: 00b2 8d3c mfhc2 a1,\$18
-[ ]*[0-9a-f]+: 00b3 8d3c mfhc2 a1,\$19
-[ ]*[0-9a-f]+: 00b4 8d3c mfhc2 a1,\$20
-[ ]*[0-9a-f]+: 00b5 8d3c mfhc2 a1,\$21
-[ ]*[0-9a-f]+: 00b6 8d3c mfhc2 a1,\$22
-[ ]*[0-9a-f]+: 00b7 8d3c mfhc2 a1,\$23
-[ ]*[0-9a-f]+: 00b8 8d3c mfhc2 a1,\$24
-[ ]*[0-9a-f]+: 00b9 8d3c mfhc2 a1,\$25
-[ ]*[0-9a-f]+: 00ba 8d3c mfhc2 a1,\$26
-[ ]*[0-9a-f]+: 00bb 8d3c mfhc2 a1,\$27
-[ ]*[0-9a-f]+: 00bc 8d3c mfhc2 a1,\$28
-[ ]*[0-9a-f]+: 00bd 8d3c mfhc2 a1,\$29
-[ ]*[0-9a-f]+: 00be 8d3c mfhc2 a1,\$30
-[ ]*[0-9a-f]+: 00bf 8d3c mfhc2 a1,\$31
-[ ]*[0-9a-f]+: 00a0 5d3c mtc2 a1,\$0
-[ ]*[0-9a-f]+: 00a1 5d3c mtc2 a1,\$1
-[ ]*[0-9a-f]+: 00a2 5d3c mtc2 a1,\$2
-[ ]*[0-9a-f]+: 00a3 5d3c mtc2 a1,\$3
-[ ]*[0-9a-f]+: 00a4 5d3c mtc2 a1,\$4
-[ ]*[0-9a-f]+: 00a5 5d3c mtc2 a1,\$5
-[ ]*[0-9a-f]+: 00a6 5d3c mtc2 a1,\$6
-[ ]*[0-9a-f]+: 00a7 5d3c mtc2 a1,\$7
-[ ]*[0-9a-f]+: 00a8 5d3c mtc2 a1,\$8
-[ ]*[0-9a-f]+: 00a9 5d3c mtc2 a1,\$9
-[ ]*[0-9a-f]+: 00aa 5d3c mtc2 a1,\$10
-[ ]*[0-9a-f]+: 00ab 5d3c mtc2 a1,\$11
-[ ]*[0-9a-f]+: 00ac 5d3c mtc2 a1,\$12
-[ ]*[0-9a-f]+: 00ad 5d3c mtc2 a1,\$13
-[ ]*[0-9a-f]+: 00ae 5d3c mtc2 a1,\$14
-[ ]*[0-9a-f]+: 00af 5d3c mtc2 a1,\$15
-[ ]*[0-9a-f]+: 00b0 5d3c mtc2 a1,\$16
-[ ]*[0-9a-f]+: 00b1 5d3c mtc2 a1,\$17
-[ ]*[0-9a-f]+: 00b2 5d3c mtc2 a1,\$18
-[ ]*[0-9a-f]+: 00b3 5d3c mtc2 a1,\$19
-[ ]*[0-9a-f]+: 00b4 5d3c mtc2 a1,\$20
-[ ]*[0-9a-f]+: 00b5 5d3c mtc2 a1,\$21
-[ ]*[0-9a-f]+: 00b6 5d3c mtc2 a1,\$22
-[ ]*[0-9a-f]+: 00b7 5d3c mtc2 a1,\$23
-[ ]*[0-9a-f]+: 00b8 5d3c mtc2 a1,\$24
-[ ]*[0-9a-f]+: 00b9 5d3c mtc2 a1,\$25
-[ ]*[0-9a-f]+: 00ba 5d3c mtc2 a1,\$26
-[ ]*[0-9a-f]+: 00bb 5d3c mtc2 a1,\$27
-[ ]*[0-9a-f]+: 00bc 5d3c mtc2 a1,\$28
-[ ]*[0-9a-f]+: 00bd 5d3c mtc2 a1,\$29
-[ ]*[0-9a-f]+: 00be 5d3c mtc2 a1,\$30
-[ ]*[0-9a-f]+: 00bf 5d3c mtc2 a1,\$31
-[ ]*[0-9a-f]+: 00a0 9d3c mthc2 a1,\$0
-[ ]*[0-9a-f]+: 00a1 9d3c mthc2 a1,\$1
-[ ]*[0-9a-f]+: 00a2 9d3c mthc2 a1,\$2
-[ ]*[0-9a-f]+: 00a3 9d3c mthc2 a1,\$3
-[ ]*[0-9a-f]+: 00a4 9d3c mthc2 a1,\$4
-[ ]*[0-9a-f]+: 00a5 9d3c mthc2 a1,\$5
-[ ]*[0-9a-f]+: 00a6 9d3c mthc2 a1,\$6
-[ ]*[0-9a-f]+: 00a7 9d3c mthc2 a1,\$7
-[ ]*[0-9a-f]+: 00a8 9d3c mthc2 a1,\$8
-[ ]*[0-9a-f]+: 00a9 9d3c mthc2 a1,\$9
-[ ]*[0-9a-f]+: 00aa 9d3c mthc2 a1,\$10
-[ ]*[0-9a-f]+: 00ab 9d3c mthc2 a1,\$11
-[ ]*[0-9a-f]+: 00ac 9d3c mthc2 a1,\$12
-[ ]*[0-9a-f]+: 00ad 9d3c mthc2 a1,\$13
-[ ]*[0-9a-f]+: 00ae 9d3c mthc2 a1,\$14
-[ ]*[0-9a-f]+: 00af 9d3c mthc2 a1,\$15
-[ ]*[0-9a-f]+: 00b0 9d3c mthc2 a1,\$16
-[ ]*[0-9a-f]+: 00b1 9d3c mthc2 a1,\$17
-[ ]*[0-9a-f]+: 00b2 9d3c mthc2 a1,\$18
-[ ]*[0-9a-f]+: 00b3 9d3c mthc2 a1,\$19
-[ ]*[0-9a-f]+: 00b4 9d3c mthc2 a1,\$20
-[ ]*[0-9a-f]+: 00b5 9d3c mthc2 a1,\$21
-[ ]*[0-9a-f]+: 00b6 9d3c mthc2 a1,\$22
-[ ]*[0-9a-f]+: 00b7 9d3c mthc2 a1,\$23
-[ ]*[0-9a-f]+: 00b8 9d3c mthc2 a1,\$24
-[ ]*[0-9a-f]+: 00b9 9d3c mthc2 a1,\$25
-[ ]*[0-9a-f]+: 00ba 9d3c mthc2 a1,\$26
-[ ]*[0-9a-f]+: 00bb 9d3c mthc2 a1,\$27
-[ ]*[0-9a-f]+: 00bc 9d3c mthc2 a1,\$28
-[ ]*[0-9a-f]+: 00bd 9d3c mthc2 a1,\$29
-[ ]*[0-9a-f]+: 00be 9d3c mthc2 a1,\$30
-[ ]*[0-9a-f]+: 00bf 9d3c mthc2 a1,\$31
-[ ]*[0-9a-f]+: 2060 a000 sdc2 \$3,0\(zero\)
-[ ]*[0-9a-f]+: 2060 a000 sdc2 \$3,0\(zero\)
-[ ]*[0-9a-f]+: 2060 a004 sdc2 \$3,4\(zero\)
-[ ]*[0-9a-f]+: 2060 a004 sdc2 \$3,4\(zero\)
-[ ]*[0-9a-f]+: 2064 a000 sdc2 \$3,0\(a0\)
-[ ]*[0-9a-f]+: 2064 a000 sdc2 \$3,0\(a0\)
-[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
-[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
-[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 a7ff sdc2 \$3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
-[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 a001 sdc2 \$3,1\(at\)
-[ ]*[0-9a-f]+: 3024 8001 addiu at,a0,-32767
-[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 a000 sdc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 2064 a7ff sdc2 \$3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5800 ori at,at,0x5800
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 a678 sdc2 \$3,-392\(at\)
-[ ]*[0-9a-f]+: 2060 8000 swc2 \$3,0\(zero\)
-[ ]*[0-9a-f]+: 2060 8000 swc2 \$3,0\(zero\)
-[ ]*[0-9a-f]+: 2060 8004 swc2 \$3,4\(zero\)
-[ ]*[0-9a-f]+: 2060 8004 swc2 \$3,4\(zero\)
-[ ]*[0-9a-f]+: 2064 8000 swc2 \$3,0\(a0\)
-[ ]*[0-9a-f]+: 2064 8000 swc2 \$3,0\(a0\)
-[ ]*[0-9a-f]+: 3024 7fff addiu at,a0,32767
-[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
-[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 87ff swc2 \$3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 3024 8000 addiu at,a0,-32768
-[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 8001 swc2 \$3,1\(at\)
-[ ]*[0-9a-f]+: 3024 8001 addiu at,a0,-32767
-[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 8000 swc2 \$3,0\(at\)
-[ ]*[0-9a-f]+: 2064 87ff swc2 \$3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5800 ori at,at,0x5800
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 2061 8678 swc2 \$3,-392\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2001 6000 cache 0x0,0\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2041 1000 lwp v0,0\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2041 9000 swp v0,0\(at\)
-[ ]*[0-9a-f]+: 3043 0000 addiu v0,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 6042 3000 ll v0,0\(v0\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 6041 b000 sc v0,0\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2021 5000 lwm s0,0\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2021 d000 swm s0,0\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2201 0000 lwc2 \$16,0\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2201 8000 swc2 \$16,0\(at\)
-[ ]*[0-9a-f]+: 03ff db7c sdbbp 0x3ff
-[ ]*[0-9a-f]+: 03ff 937c wait 0x3ff
-[ ]*[0-9a-f]+: 03ff 8b7c syscall 0x3ff
-[ ]*[0-9a-f]+: 03ff fffa cop2 0x7fffff
+[ ]*[0-9a-f]+: [ ]*a21e 0000 bnezc s0,fffc041a <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC21_S1 test2
+[ ]*[0-9a-f]+: [ ]*441b break
+[ ]*[0-9a-f]+: [ ]*441b break
+[ ]*[0-9a-f]+: [ ]*445b break 0x1
+[ ]*[0-9a-f]+: [ ]*449b break 0x2
+[ ]*[0-9a-f]+: [ ]*44db break 0x3
+[ ]*[0-9a-f]+: [ ]*451b break 0x4
+[ ]*[0-9a-f]+: [ ]*455b break 0x5
+[ ]*[0-9a-f]+: [ ]*459b break 0x6
+[ ]*[0-9a-f]+: [ ]*45db break 0x7
+[ ]*[0-9a-f]+: [ ]*461b break 0x8
+[ ]*[0-9a-f]+: [ ]*465b break 0x9
+[ ]*[0-9a-f]+: [ ]*469b break 0xa
+[ ]*[0-9a-f]+: [ ]*46db break 0xb
+[ ]*[0-9a-f]+: [ ]*471b break 0xc
+[ ]*[0-9a-f]+: [ ]*475b break 0xd
+[ ]*[0-9a-f]+: [ ]*479b break 0xe
+[ ]*[0-9a-f]+: [ ]*47db break 0xf
+[ ]*[0-9a-f]+: [ ]*003f 0007 break 0x3f
+[ ]*[0-9a-f]+: [ ]*0040 0007 break 0x40
+[ ]*[0-9a-f]+: [ ]*03ff 0007 break 0x3ff
+[ ]*[0-9a-f]+: [ ]*03ff ffc7 break 0x3ff,0x3ff
+[ ]*[0-9a-f]+: [ ]*0000 0007 break
+[ ]*[0-9a-f]+: [ ]*0000 0007 break
+[ ]*[0-9a-f]+: [ ]*0001 0007 break 0x1
+[ ]*[0-9a-f]+: [ ]*0002 0007 break 0x2
+[ ]*[0-9a-f]+: [ ]*000f 0007 break 0xf
+[ ]*[0-9a-f]+: [ ]*003f 0007 break 0x3f
+[ ]*[0-9a-f]+: [ ]*0040 0007 break 0x40
+[ ]*[0-9a-f]+: [ ]*03ff 0007 break 0x3ff
+[ ]*[0-9a-f]+: [ ]*03ff ffc7 break 0x3ff,0x3ff
+[ ]*[0-9a-f]+: [ ]*2000 6000 cache 0x0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2000 6100 cache 0x0,-256\(zero\)
+[ ]*[0-9a-f]+: [ ]*2000 60ff cache 0x0,255\(zero\)
+[ ]*[0-9a-f]+: [ ]*3020 feff li at,-257
+[ ]*[0-9a-f]+: [ ]*2001 6000 cache 0x0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 0100 li at,256
+[ ]*[0-9a-f]+: [ ]*2001 6000 cache 0x0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2002 6000 cache 0x0,0\(v0\)
+[ ]*[0-9a-f]+: [ ]*2002 6100 cache 0x0,-256\(v0\)
+[ ]*[0-9a-f]+: [ ]*2002 60ff cache 0x0,255\(v0\)
+[ ]*[0-9a-f]+: [ ]*3022 feff addiu at,v0,-257
+[ ]*[0-9a-f]+: [ ]*2001 6000 cache 0x0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3022 0100 addiu at,v0,256
+[ ]*[0-9a-f]+: [ ]*2001 6000 cache 0x0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2000 6000 cache 0x0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2000 6000 cache 0x0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2020 6000 cache 0x1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2040 6000 cache 0x2,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 6000 cache 0x3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2080 6000 cache 0x4,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*20a0 6000 cache 0x5,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*20c0 6000 cache 0x6,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*23e0 6000 cache 0x1f,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*23e0 60ff cache 0x1f,255\(zero\)
+[ ]*[0-9a-f]+: [ ]*23e0 6100 cache 0x1f,-256\(zero\)
+[ ]*[0-9a-f]+: [ ]*2000 60ff cache 0x0,255\(zero\)
+[ ]*[0-9a-f]+: [ ]*2000 6100 cache 0x0,-256\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: [ ]*23e1 6000 cache 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0100 addiu at,v1,256
+[ ]*[0-9a-f]+: [ ]*23e1 6000 cache 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 feff addiu at,v1,-257
+[ ]*[0-9a-f]+: [ ]*23e1 6000 cache 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: [ ]*23e1 6001 cache 0x1f,1\(at\)
+[ ]*[0-9a-f]+: [ ]*23e3 61ff cache 0x1f,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: [ ]*23e1 6000 cache 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: [ ]*23e1 6001 cache 0x1f,1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: [ ]*23e1 61ff cache 0x1f,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*23e1 6000 cache 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 0100 li at,256
+[ ]*[0-9a-f]+: [ ]*23e1 6000 cache 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 feff li at,-257
+[ ]*[0-9a-f]+: [ ]*23e1 6000 cache 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*23e1 6001 cache 0x1f,1\(at\)
+[ ]*[0-9a-f]+: [ ]*23e0 61ff cache 0x1f,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*23e1 6000 cache 0x1f,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*23e1 6001 cache 0x1f,1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*23e1 61ff cache 0x1f,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*0043 4b3c clo v0,v1
+[ ]*[0-9a-f]+: [ ]*0062 4b3c clo v1,v0
+[ ]*[0-9a-f]+: [ ]*0043 5b3c clz v0,v1
+[ ]*[0-9a-f]+: [ ]*0062 5b3c clz v1,v0
+[ ]*[0-9a-f]+: [ ]*0000 e37c deret
+[ ]*[0-9a-f]+: [ ]*0000 477c di
+[ ]*[0-9a-f]+: [ ]*0000 477c di
+[ ]*[0-9a-f]+: [ ]*0002 477c di v0
+[ ]*[0-9a-f]+: [ ]*0003 477c di v1
+[ ]*[0-9a-f]+: [ ]*001e 477c di s8
+[ ]*[0-9a-f]+: [ ]*001f 477c di ra
+[ ]*[0-9a-f]+: [ ]*0062 0118 div zero,v0,v1
+[ ]*[0-9a-f]+: [ ]*03fe 0118 div zero,s8,ra
+[ ]*[0-9a-f]+: [ ]*0060 0118 div zero,zero,v1
+[ ]*[0-9a-f]+: [ ]*03e0 0118 div zero,zero,ra
+[ ]*[0-9a-f]+: [ ]*0003 1118 div v0,v1,zero
+[ ]*[0-9a-f]+: [ ]*0083 1118 div v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0062 0198 divu zero,v0,v1
+[ ]*[0-9a-f]+: [ ]*03fe 0198 divu zero,s8,ra
+[ ]*[0-9a-f]+: [ ]*0060 0198 divu zero,zero,v1
+[ ]*[0-9a-f]+: [ ]*03e0 0198 divu zero,zero,ra
+[ ]*[0-9a-f]+: [ ]*0003 1198 divu v0,v1,zero
+[ ]*[0-9a-f]+: [ ]*0083 1198 divu v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0000 577c ei
+[ ]*[0-9a-f]+: [ ]*0000 577c ei
+[ ]*[0-9a-f]+: [ ]*0002 577c ei v0
+[ ]*[0-9a-f]+: [ ]*0003 577c ei v1
+[ ]*[0-9a-f]+: [ ]*001e 577c ei s8
+[ ]*[0-9a-f]+: [ ]*001f 577c ei ra
+[ ]*[0-9a-f]+: [ ]*0000 f37c eret
+[ ]*[0-9a-f]+: [ ]*0043 716c ext v0,v1,0x5,0xf
+[ ]*[0-9a-f]+: [ ]*0043 f82c ext v0,v1,0x0,0x20
+[ ]*[0-9a-f]+: [ ]*0043 07ec ext v0,v1,0x1f,0x1
+[ ]*[0-9a-f]+: [ ]*03fe 07ec ext ra,s8,0x1f,0x1
+[ ]*[0-9a-f]+: [ ]*0043 994c ins v0,v1,0x5,0xf
+[ ]*[0-9a-f]+: [ ]*0043 f80c ins v0,v1,0x0,0x20
+[ ]*[0-9a-f]+: [ ]*0043 ffcc ins v0,v1,0x1f,0x1
+[ ]*[0-9a-f]+: [ ]*03fe ffcc ins ra,s8,0x1f,0x1
+[ ]*[0-9a-f]+: [ ]*4403 jrc zero
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*4443 jrc v0
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*4463 jrc v1
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*4483 jrc a0
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*44a3 jrc a1
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*44c3 jrc a2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*44e3 jrc a3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*4503 jrc t0
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*47c3 jrc s8
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*47e3 jrc ra
+[ ]*[0-9a-f]+: [ ]*8000 0000 jrc zero
+[ ]*[0-9a-f]+: [ ]*8002 0000 jrc v0
+[ ]*[0-9a-f]+: [ ]*8003 0000 jrc v1
+[ ]*[0-9a-f]+: [ ]*8004 0000 jrc a0
+[ ]*[0-9a-f]+: [ ]*8005 0000 jrc a1
+[ ]*[0-9a-f]+: [ ]*8006 0000 jrc a2
+[ ]*[0-9a-f]+: [ ]*8007 0000 jrc a3
+[ ]*[0-9a-f]+: [ ]*8008 0000 jrc t0
+[ ]*[0-9a-f]+: [ ]*801e 0000 jrc s8
+[ ]*[0-9a-f]+: [ ]*801f 0000 jrc ra
+[ ]*[0-9a-f]+: [ ]*4403 jrc zero
+[ ]*[0-9a-f]+: [ ]*4443 jrc v0
+[ ]*[0-9a-f]+: [ ]*4463 jrc v1
+[ ]*[0-9a-f]+: [ ]*4483 jrc a0
+[ ]*[0-9a-f]+: [ ]*44a3 jrc a1
+[ ]*[0-9a-f]+: [ ]*44c3 jrc a2
+[ ]*[0-9a-f]+: [ ]*44e3 jrc a3
+[ ]*[0-9a-f]+: [ ]*4503 jrc t0
+[ ]*[0-9a-f]+: [ ]*47c3 jrc s8
+[ ]*[0-9a-f]+: [ ]*47e3 jrc ra
+[ ]*[0-9a-f]+: [ ]*0000 1f3c jrc.hb zero
+[ ]*[0-9a-f]+: [ ]*0002 1f3c jrc.hb v0
+[ ]*[0-9a-f]+: [ ]*0003 1f3c jrc.hb v1
+[ ]*[0-9a-f]+: [ ]*0004 1f3c jrc.hb a0
+[ ]*[0-9a-f]+: [ ]*0005 1f3c jrc.hb a1
+[ ]*[0-9a-f]+: [ ]*0006 1f3c jrc.hb a2
+[ ]*[0-9a-f]+: [ ]*0007 1f3c jrc.hb a3
+[ ]*[0-9a-f]+: [ ]*0008 1f3c jrc.hb t0
+[ ]*[0-9a-f]+: [ ]*001e 1f3c jrc.hb s8
+[ ]*[0-9a-f]+: [ ]*001f 1f3c jrc.hb ra
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*4403 jrc zero
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*4443 jrc v0
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*4463 jrc v1
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*4483 jrc a0
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*44a3 jrc a1
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*44c3 jrc a2
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*44e3 jrc a3
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*4503 jrc t0
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*47c3 jrc s8
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*47e3 jrc ra
+[ ]*[0-9a-f]+: [ ]*440b jalrc zero
+[ ]*[0-9a-f]+: [ ]*444b jalrc v0
+[ ]*[0-9a-f]+: [ ]*446b jalrc v1
+[ ]*[0-9a-f]+: [ ]*448b jalrc a0
+[ ]*[0-9a-f]+: [ ]*44ab jalrc a1
+[ ]*[0-9a-f]+: [ ]*44cb jalrc a2
+[ ]*[0-9a-f]+: [ ]*44eb jalrc a3
+[ ]*[0-9a-f]+: [ ]*450b jalrc t0
+[ ]*[0-9a-f]+: [ ]*47cb jalrc s8
+[ ]*[0-9a-f]+: [ ]*03e0 0f3c jalrc zero
+[ ]*[0-9a-f]+: [ ]*03e2 0f3c jalrc v0
+[ ]*[0-9a-f]+: [ ]*03e3 0f3c jalrc v1
+[ ]*[0-9a-f]+: [ ]*03e4 0f3c jalrc a0
+[ ]*[0-9a-f]+: [ ]*03e5 0f3c jalrc a1
+[ ]*[0-9a-f]+: [ ]*03e6 0f3c jalrc a2
+[ ]*[0-9a-f]+: [ ]*03e7 0f3c jalrc a3
+[ ]*[0-9a-f]+: [ ]*03e8 0f3c jalrc t0
+[ ]*[0-9a-f]+: [ ]*03fe 0f3c jalrc s8
+[ ]*[0-9a-f]+: [ ]*440b jalrc zero
+[ ]*[0-9a-f]+: [ ]*444b jalrc v0
+[ ]*[0-9a-f]+: [ ]*446b jalrc v1
+[ ]*[0-9a-f]+: [ ]*448b jalrc a0
+[ ]*[0-9a-f]+: [ ]*44ab jalrc a1
+[ ]*[0-9a-f]+: [ ]*44cb jalrc a2
+[ ]*[0-9a-f]+: [ ]*44eb jalrc a3
+[ ]*[0-9a-f]+: [ ]*450b jalrc t0
+[ ]*[0-9a-f]+: [ ]*47cb jalrc s8
+[ ]*[0-9a-f]+: [ ]*03df 0f3c jalrc s8,ra
+[ ]*[0-9a-f]+: [ ]*0040 0f3c jalrc v0,zero
+[ ]*[0-9a-f]+: [ ]*0062 0f3c jalrc v1,v0
+[ ]*[0-9a-f]+: [ ]*0043 0f3c jalrc v0,v1
+[ ]*[0-9a-f]+: [ ]*0044 0f3c jalrc v0,a0
+[ ]*[0-9a-f]+: [ ]*0045 0f3c jalrc v0,a1
+[ ]*[0-9a-f]+: [ ]*0046 0f3c jalrc v0,a2
+[ ]*[0-9a-f]+: [ ]*0047 0f3c jalrc v0,a3
+[ ]*[0-9a-f]+: [ ]*0048 0f3c jalrc v0,t0
+[ ]*[0-9a-f]+: [ ]*005e 0f3c jalrc v0,s8
+[ ]*[0-9a-f]+: [ ]*005f 0f3c jalrc v0,ra
+[ ]*[0-9a-f]+: [ ]*03e0 1f3c jalrc.hb zero
+[ ]*[0-9a-f]+: [ ]*03e2 1f3c jalrc.hb v0
+[ ]*[0-9a-f]+: [ ]*03e3 1f3c jalrc.hb v1
+[ ]*[0-9a-f]+: [ ]*03e4 1f3c jalrc.hb a0
+[ ]*[0-9a-f]+: [ ]*03e5 1f3c jalrc.hb a1
+[ ]*[0-9a-f]+: [ ]*03e6 1f3c jalrc.hb a2
+[ ]*[0-9a-f]+: [ ]*03e7 1f3c jalrc.hb a3
+[ ]*[0-9a-f]+: [ ]*03e8 1f3c jalrc.hb t0
+[ ]*[0-9a-f]+: [ ]*03fe 1f3c jalrc.hb s8
+[ ]*[0-9a-f]+: [ ]*03e0 1f3c jalrc.hb zero
+[ ]*[0-9a-f]+: [ ]*03e2 1f3c jalrc.hb v0
+[ ]*[0-9a-f]+: [ ]*03e3 1f3c jalrc.hb v1
+[ ]*[0-9a-f]+: [ ]*03e4 1f3c jalrc.hb a0
+[ ]*[0-9a-f]+: [ ]*03e5 1f3c jalrc.hb a1
+[ ]*[0-9a-f]+: [ ]*03e6 1f3c jalrc.hb a2
+[ ]*[0-9a-f]+: [ ]*03e7 1f3c jalrc.hb a3
+[ ]*[0-9a-f]+: [ ]*03e8 1f3c jalrc.hb t0
+[ ]*[0-9a-f]+: [ ]*03fe 1f3c jalrc.hb s8
+[ ]*[0-9a-f]+: [ ]*03df 1f3c jalrc.hb s8,ra
+[ ]*[0-9a-f]+: [ ]*0040 1f3c jalrc.hb v0,zero
+[ ]*[0-9a-f]+: [ ]*0062 1f3c jalrc.hb v1,v0
+[ ]*[0-9a-f]+: [ ]*0043 1f3c jalrc.hb v0,v1
+[ ]*[0-9a-f]+: [ ]*0044 1f3c jalrc.hb v0,a0
+[ ]*[0-9a-f]+: [ ]*0045 1f3c jalrc.hb v0,a1
+[ ]*[0-9a-f]+: [ ]*0046 1f3c jalrc.hb v0,a2
+[ ]*[0-9a-f]+: [ ]*0047 1f3c jalrc.hb v0,a3
+[ ]*[0-9a-f]+: [ ]*0048 1f3c jalrc.hb v0,t0
+[ ]*[0-9a-f]+: [ ]*005e 1f3c jalrc.hb v0,s8
+[ ]*[0-9a-f]+: [ ]*005f 1f3c jalrc.hb v0,ra
+[ ]*[0-9a-f]+: [ ]*0043 0f3c jalrc v0,v1
+[ ]*[0-9a-f]+: [ ]*03df 0f3c jalrc s8,ra
+[ ]*[0-9a-f]+: [ ]*446b jalrc v1
+[ ]*[0-9a-f]+: [ ]*47eb jalrc ra
+[ ]*[0-9a-f]+: [ ]*b3fe 0000 sltiu ra,s8,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 test
+[ ]*[0-9a-f]+: [ ]*b3fe 0000 sltiu ra,s8,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 test2
+[ ]*[0-9a-f]+: [ ]*1040 0000 lui v0,0x0
+ [ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ ]*[0-9a-f]+: [ ]*3042 0000 addiu v0,v0,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*1040 0000 lui v0,0x0
+ [ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ ]*[0-9a-f]+: [ ]*3042 0000 addiu v0,v0,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*1c60 0000 lb v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*1c60 0004 lb v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*1c60 0000 lb v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*1c60 0004 lb v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*1c60 7fff lb v1,32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*1c60 8000 lb v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*1c63 ffff lb v1,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*1c63 0000 lb v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1c60 8000 lb v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*1c63 0001 lb v1,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1c60 8001 lb v1,-32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 f000 lui v1,0xf000
+[ ]*[0-9a-f]+: [ ]*1c63 0000 lb v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1c60 ffff lb v1,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*1c63 5678 lb v1,22136\(v1\)
+[ ]*[0-9a-f]+: [ ]*1c64 0000 lb v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*1c64 0000 lb v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*1c64 0004 lb v1,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*1c64 7fff lb v1,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1c64 8000 lb v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*1c63 ffff lb v1,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*1c63 0000 lb v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1c64 8000 lb v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*1c63 0001 lb v1,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1c64 8001 lb v1,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 f000 lui v1,0xf000
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*1c63 0000 lb v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1c64 ffff lb v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*1c63 5678 lb v1,22136\(v1\)
+[ ]*[0-9a-f]+: [ ]*093f lbu v0,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*0930 lbu v0,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*0930 lbu v0,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*0931 lbu v0,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*0932 lbu v0,2\(v1\)
+[ ]*[0-9a-f]+: [ ]*0933 lbu v0,3\(v1\)
+[ ]*[0-9a-f]+: [ ]*0934 lbu v0,4\(v1\)
+[ ]*[0-9a-f]+: [ ]*0935 lbu v0,5\(v1\)
+[ ]*[0-9a-f]+: [ ]*0936 lbu v0,6\(v1\)
+[ ]*[0-9a-f]+: [ ]*0937 lbu v0,7\(v1\)
+[ ]*[0-9a-f]+: [ ]*0938 lbu v0,8\(v1\)
+[ ]*[0-9a-f]+: [ ]*0939 lbu v0,9\(v1\)
+[ ]*[0-9a-f]+: [ ]*093a lbu v0,10\(v1\)
+[ ]*[0-9a-f]+: [ ]*093b lbu v0,11\(v1\)
+[ ]*[0-9a-f]+: [ ]*093c lbu v0,12\(v1\)
+[ ]*[0-9a-f]+: [ ]*093d lbu v0,13\(v1\)
+[ ]*[0-9a-f]+: [ ]*093e lbu v0,14\(v1\)
+[ ]*[0-9a-f]+: [ ]*092e lbu v0,14\(v0\)
+[ ]*[0-9a-f]+: [ ]*094e lbu v0,14\(a0\)
+[ ]*[0-9a-f]+: [ ]*095e lbu v0,14\(a1\)
+[ ]*[0-9a-f]+: [ ]*096e lbu v0,14\(a2\)
+[ ]*[0-9a-f]+: [ ]*097e lbu v0,14\(a3\)
+[ ]*[0-9a-f]+: [ ]*090e lbu v0,14\(s0\)
+[ ]*[0-9a-f]+: [ ]*091e lbu v0,14\(s1\)
+[ ]*[0-9a-f]+: [ ]*099e lbu v1,14\(s1\)
+[ ]*[0-9a-f]+: [ ]*0a1e lbu a0,14\(s1\)
+[ ]*[0-9a-f]+: [ ]*0a9e lbu a1,14\(s1\)
+[ ]*[0-9a-f]+: [ ]*0b1e lbu a2,14\(s1\)
+[ ]*[0-9a-f]+: [ ]*0b9e lbu a3,14\(s1\)
+[ ]*[0-9a-f]+: [ ]*081e lbu s0,14\(s1\)
+[ ]*[0-9a-f]+: [ ]*089e lbu s1,14\(s1\)
+[ ]*[0-9a-f]+: [ ]*1460 0000 lbu v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*1460 0004 lbu v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*1460 0000 lbu v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*1460 0004 lbu v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*1460 7fff lbu v1,32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*1460 8000 lbu v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*1463 ffff lbu v1,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*1463 0000 lbu v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1460 8000 lbu v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*1463 0001 lbu v1,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1460 8001 lbu v1,-32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 f000 lui v1,0xf000
+[ ]*[0-9a-f]+: [ ]*1463 0000 lbu v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1460 ffff lbu v1,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*1463 5678 lbu v1,22136\(v1\)
+[ ]*[0-9a-f]+: [ ]*09c0 lbu v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*09c0 lbu v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*09c4 lbu v1,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*1464 7fff lbu v1,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1464 8000 lbu v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*1463 ffff lbu v1,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*1463 0000 lbu v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1464 8000 lbu v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*1463 0001 lbu v1,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1464 8001 lbu v1,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 f000 lui v1,0xf000
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*1463 0000 lbu v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1464 ffff lbu v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*1463 5678 lbu v1,22136\(v1\)
+[ ]*[0-9a-f]+: [ ]*3c60 0000 lh v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*3c60 0004 lh v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*3c60 0000 lh v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*3c60 0004 lh v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*3c60 7fff lh v1,32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*3c60 8000 lh v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*3c63 ffff lh v1,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*3c63 0000 lh v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3c60 8000 lh v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*3c63 0001 lh v1,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*3c60 8001 lh v1,-32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 f000 lui v1,0xf000
+[ ]*[0-9a-f]+: [ ]*3c63 0000 lh v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3c60 ffff lh v1,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*3c63 5678 lh v1,22136\(v1\)
+[ ]*[0-9a-f]+: [ ]*3c64 0000 lh v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*3c64 0000 lh v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*3c64 0004 lh v1,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*3c64 7fff lh v1,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*3c64 8000 lh v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*3c63 ffff lh v1,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*3c63 0000 lh v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3c64 8000 lh v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*3c63 0001 lh v1,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*3c64 8001 lh v1,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 f000 lui v1,0xf000
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*3c63 0000 lh v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3c64 ffff lh v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*3c63 5678 lh v1,22136\(v1\)
+[ ]*[0-9a-f]+: [ ]*2930 lhu v0,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*2930 lhu v0,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*2931 lhu v0,2\(v1\)
+[ ]*[0-9a-f]+: [ ]*2932 lhu v0,4\(v1\)
+[ ]*[0-9a-f]+: [ ]*2933 lhu v0,6\(v1\)
+[ ]*[0-9a-f]+: [ ]*2934 lhu v0,8\(v1\)
+[ ]*[0-9a-f]+: [ ]*2935 lhu v0,10\(v1\)
+[ ]*[0-9a-f]+: [ ]*2936 lhu v0,12\(v1\)
+[ ]*[0-9a-f]+: [ ]*2937 lhu v0,14\(v1\)
+[ ]*[0-9a-f]+: [ ]*2938 lhu v0,16\(v1\)
+[ ]*[0-9a-f]+: [ ]*2939 lhu v0,18\(v1\)
+[ ]*[0-9a-f]+: [ ]*293a lhu v0,20\(v1\)
+[ ]*[0-9a-f]+: [ ]*293b lhu v0,22\(v1\)
+[ ]*[0-9a-f]+: [ ]*293c lhu v0,24\(v1\)
+[ ]*[0-9a-f]+: [ ]*293d lhu v0,26\(v1\)
+[ ]*[0-9a-f]+: [ ]*293e lhu v0,28\(v1\)
+[ ]*[0-9a-f]+: [ ]*293f lhu v0,30\(v1\)
+[ ]*[0-9a-f]+: [ ]*294f lhu v0,30\(a0\)
+[ ]*[0-9a-f]+: [ ]*295f lhu v0,30\(a1\)
+[ ]*[0-9a-f]+: [ ]*296f lhu v0,30\(a2\)
+[ ]*[0-9a-f]+: [ ]*297f lhu v0,30\(a3\)
+[ ]*[0-9a-f]+: [ ]*292f lhu v0,30\(v0\)
+[ ]*[0-9a-f]+: [ ]*290f lhu v0,30\(s0\)
+[ ]*[0-9a-f]+: [ ]*291f lhu v0,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*299f lhu v1,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*2a1f lhu a0,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*2a9f lhu a1,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*2b1f lhu a2,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*2b9f lhu a3,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*281f lhu s0,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*289f lhu s1,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*3460 0000 lhu v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*3460 0004 lhu v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*3460 0000 lhu v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*3460 0004 lhu v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*3460 7fff lhu v1,32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*3460 8000 lhu v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*3463 ffff lhu v1,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*3463 0000 lhu v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3460 8000 lhu v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*3463 0001 lhu v1,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*3460 8001 lhu v1,-32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 f000 lui v1,0xf000
+[ ]*[0-9a-f]+: [ ]*3463 0000 lhu v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3460 ffff lhu v1,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*3463 5678 lhu v1,22136\(v1\)
+[ ]*[0-9a-f]+: [ ]*29c0 lhu v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*29c0 lhu v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*29c2 lhu v1,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*3464 7fff lhu v1,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*3464 8000 lhu v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*3463 ffff lhu v1,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*3463 0000 lhu v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3464 8000 lhu v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*3463 0001 lhu v1,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*3464 8001 lhu v1,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 f000 lui v1,0xf000
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*3463 0000 lhu v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3464 ffff lhu v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*3463 5678 lhu v1,22136\(v1\)
+[ ]*[0-9a-f]+: [ ]*6060 3000 ll v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6060 3000 ll v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6060 3004 ll v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*6060 3004 ll v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*3060 7fff li v1,32767
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3060 8000 li v1,-32768
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*6063 31ff ll v1,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3060 8000 li v1,-32768
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*6063 3001 ll v1,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*3060 8001 li v1,-32767
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 f000 lui v1,0xf000
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*6060 31ff ll v1,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*5063 5600 ori v1,v1,0x5600
+[ ]*[0-9a-f]+: [ ]*6063 3078 ll v1,120\(v1\)
+[ ]*[0-9a-f]+: [ ]*6064 3000 ll v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*6064 3000 ll v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*6064 3004 ll v1,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*3064 7fff addiu v1,a0,32767
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3064 8000 addiu v1,a0,-32768
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*6063 31ff ll v1,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3064 8000 addiu v1,a0,-32768
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*6063 3001 ll v1,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*3064 8001 addiu v1,a0,-32767
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 f000 lui v1,0xf000
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*6063 3000 ll v1,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*6064 31ff ll v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*5063 5600 ori v1,v1,0x5600
+[ ]*[0-9a-f]+: [ ]*0083 1950 addu v1,v1,a0
+[ ]*[0-9a-f]+: [ ]*6063 3078 ll v1,120\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 0000 lui v1,0x0
+[ ]*[0-9a-f]+: [ ]*1060 7fff lui v1,0x7fff
+[ ]*[0-9a-f]+: [ ]*1060 ffff lui v1,0xffff
+[ ]*[0-9a-f]+: [ ]*6940 lw v0,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*6940 lw v0,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*6941 lw v0,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*6942 lw v0,8\(a0\)
+[ ]*[0-9a-f]+: [ ]*6943 lw v0,12\(a0\)
+[ ]*[0-9a-f]+: [ ]*6944 lw v0,16\(a0\)
+[ ]*[0-9a-f]+: [ ]*6945 lw v0,20\(a0\)
+[ ]*[0-9a-f]+: [ ]*6946 lw v0,24\(a0\)
+[ ]*[0-9a-f]+: [ ]*6947 lw v0,28\(a0\)
+[ ]*[0-9a-f]+: [ ]*6948 lw v0,32\(a0\)
+[ ]*[0-9a-f]+: [ ]*6949 lw v0,36\(a0\)
+[ ]*[0-9a-f]+: [ ]*694a lw v0,40\(a0\)
+[ ]*[0-9a-f]+: [ ]*694b lw v0,44\(a0\)
+[ ]*[0-9a-f]+: [ ]*694c lw v0,48\(a0\)
+[ ]*[0-9a-f]+: [ ]*694d lw v0,52\(a0\)
+[ ]*[0-9a-f]+: [ ]*694e lw v0,56\(a0\)
+[ ]*[0-9a-f]+: [ ]*694f lw v0,60\(a0\)
+[ ]*[0-9a-f]+: [ ]*695f lw v0,60\(a1\)
+[ ]*[0-9a-f]+: [ ]*696f lw v0,60\(a2\)
+[ ]*[0-9a-f]+: [ ]*697f lw v0,60\(a3\)
+[ ]*[0-9a-f]+: [ ]*692f lw v0,60\(v0\)
+[ ]*[0-9a-f]+: [ ]*693f lw v0,60\(v1\)
+[ ]*[0-9a-f]+: [ ]*690f lw v0,60\(s0\)
+[ ]*[0-9a-f]+: [ ]*691f lw v0,60\(s1\)
+[ ]*[0-9a-f]+: [ ]*699f lw v1,60\(s1\)
+[ ]*[0-9a-f]+: [ ]*6a1f lw a0,60\(s1\)
+[ ]*[0-9a-f]+: [ ]*6a9f lw a1,60\(s1\)
+[ ]*[0-9a-f]+: [ ]*6b1f lw a2,60\(s1\)
+[ ]*[0-9a-f]+: [ ]*6b9f lw a3,60\(s1\)
+[ ]*[0-9a-f]+: [ ]*681f lw s0,60\(s1\)
+[ ]*[0-9a-f]+: [ ]*689f lw s1,60\(s1\)
+[ ]*[0-9a-f]+: [ ]*4880 lw a0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*4880 lw a0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*4881 lw a0,4\(sp\)
+[ ]*[0-9a-f]+: [ ]*4882 lw a0,8\(sp\)
+[ ]*[0-9a-f]+: [ ]*4883 lw a0,12\(sp\)
+[ ]*[0-9a-f]+: [ ]*4884 lw a0,16\(sp\)
+[ ]*[0-9a-f]+: [ ]*4885 lw a0,20\(sp\)
+[ ]*[0-9a-f]+: [ ]*489f lw a0,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*485f lw v0,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*485f lw v0,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*487f lw v1,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*489f lw a0,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*48bf lw a1,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*48df lw a2,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*48ff lw a3,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*491f lw t0,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*493f lw t1,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*495f lw t2,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*4bdf lw s8,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*4bff lw ra,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*fc9d 01f8 lw a0,504\(sp\)
+[ ]*[0-9a-f]+: [ ]*fc9d 01fc lw a0,508\(sp\)
+[ ]*[0-9a-f]+: [ ]*fe1d 01fc lw s0,508\(sp\)
+[ ]*[0-9a-f]+: [ ]*fe3d 01fc lw s1,508\(sp\)
+[ ]*[0-9a-f]+: [ ]*fe5d 01fc lw s2,508\(sp\)
+[ ]*[0-9a-f]+: [ ]*fe7d 01fc lw s3,508\(sp\)
+[ ]*[0-9a-f]+: [ ]*fe9d 01fc lw s4,508\(sp\)
+[ ]*[0-9a-f]+: [ ]*febd 01fc lw s5,508\(sp\)
+[ ]*[0-9a-f]+: [ ]*fffd 01fc lw ra,508\(sp\)
+[ ]*[0-9a-f]+: [ ]*fc60 0000 lw v1,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*fc60 0004 lw v1,4\(zero\)
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+[ ]*[0-9a-f]+: [ ]*4540 not v0,a0
+[ ]*[0-9a-f]+: [ ]*4550 not v0,a1
+[ ]*[0-9a-f]+: [ ]*4560 not v0,a2
+[ ]*[0-9a-f]+: [ ]*4570 not v0,a3
+[ ]*[0-9a-f]+: [ ]*4500 not v0,s0
+[ ]*[0-9a-f]+: [ ]*4510 not v0,s1
+[ ]*[0-9a-f]+: [ ]*4590 not v1,s1
+[ ]*[0-9a-f]+: [ ]*4610 not a0,s1
+[ ]*[0-9a-f]+: [ ]*4690 not a1,s1
+[ ]*[0-9a-f]+: [ ]*4710 not a2,s1
+[ ]*[0-9a-f]+: [ ]*4790 not a3,s1
+[ ]*[0-9a-f]+: [ ]*4410 not s0,s1
+[ ]*[0-9a-f]+: [ ]*4490 not s1,s1
+[ ]*[0-9a-f]+: [ ]*4570 not v0,a3
+[ ]*[0-9a-f]+: [ ]*4570 not v0,a3
+[ ]*[0-9a-f]+: [ ]*0083 12d0 nor v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*03fe ead0 nor sp,s8,ra
+[ ]*[0-9a-f]+: [ ]*0082 12d0 nor v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0082 12d0 nor v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*5043 8000 ori v0,v1,0x8000
+[ ]*[0-9a-f]+: [ ]*0002 12d0 not v0,v0
+[ ]*[0-9a-f]+: [ ]*5043 ffff ori v0,v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0002 12d0 not v0,v0
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0023 12d0 nor v0,v1,at
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*0023 12d0 nor v0,v1,at
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: [ ]*0023 12d0 nor v0,v1,at
+[ ]*[0-9a-f]+: [ ]*0c56 move v0,s6
+[ ]*[0-9a-f]+: [ ]*0ec2 move s6,v0
+[ ]*[0-9a-f]+: [ ]*0c56 move v0,s6
+[ ]*[0-9a-f]+: [ ]*0ec2 move s6,v0
+[ ]*[0-9a-f]+: [ ]*4529 or v0,v0,v0
+[ ]*[0-9a-f]+: [ ]*4539 or v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*4549 or v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*4559 or v0,v0,a1
+[ ]*[0-9a-f]+: [ ]*4569 or v0,v0,a2
+[ ]*[0-9a-f]+: [ ]*4579 or v0,v0,a3
+[ ]*[0-9a-f]+: [ ]*4509 or v0,v0,s0
+[ ]*[0-9a-f]+: [ ]*4519 or v0,v0,s1
+[ ]*[0-9a-f]+: [ ]*45a9 or v1,v1,v0
+[ ]*[0-9a-f]+: [ ]*4629 or a0,a0,v0
+[ ]*[0-9a-f]+: [ ]*46a9 or a1,a1,v0
+[ ]*[0-9a-f]+: [ ]*4729 or a2,a2,v0
+[ ]*[0-9a-f]+: [ ]*47a9 or a3,a3,v0
+[ ]*[0-9a-f]+: [ ]*4429 or s0,s0,v0
+[ ]*[0-9a-f]+: [ ]*44a9 or s1,s1,v0
+[ ]*[0-9a-f]+: [ ]*4529 or v0,v0,v0
+[ ]*[0-9a-f]+: [ ]*4539 or v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*4539 or v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*0083 1290 or v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*03fe ea90 or sp,s8,ra
+[ ]*[0-9a-f]+: [ ]*0082 1290 or v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0082 1290 or v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*5043 8000 ori v0,v1,0x8000
+[ ]*[0-9a-f]+: [ ]*5043 ffff ori v0,v1,0xffff
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0023 1290 or v0,v1,at
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*0023 1290 or v0,v1,at
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: [ ]*0023 1290 or v0,v1,at
+[ ]*[0-9a-f]+: [ ]*0c64 move v1,a0
+[ ]*[0-9a-f]+: [ ]*5064 7fff ori v1,a0,0x7fff
+[ ]*[0-9a-f]+: [ ]*5064 ffff ori v1,a0,0xffff
+[ ]*[0-9a-f]+: [ ]*5063 ffff ori v1,v1,0xffff
+[ ]*[0-9a-f]+: [ ]*5063 ffff ori v1,v1,0xffff
+[ ]*[0-9a-f]+: [ ]*0040 01c0 rdhwr v0,hwr_cpunum
+[ ]*[0-9a-f]+: [ ]*0041 01c0 rdhwr v0,hwr_synci_step
+[ ]*[0-9a-f]+: [ ]*0042 01c0 rdhwr v0,hwr_cc
+[ ]*[0-9a-f]+: [ ]*0043 01c0 rdhwr v0,hwr_ccres
+[ ]*[0-9a-f]+: [ ]*0044 01c0 rdhwr v0,\$4
+[ ]*[0-9a-f]+: [ ]*0045 01c0 rdhwr v0,\$5
+[ ]*[0-9a-f]+: [ ]*0046 01c0 rdhwr v0,\$6
+[ ]*[0-9a-f]+: [ ]*0047 01c0 rdhwr v0,\$7
+[ ]*[0-9a-f]+: [ ]*0048 01c0 rdhwr v0,\$8
+[ ]*[0-9a-f]+: [ ]*0049 01c0 rdhwr v0,\$9
+[ ]*[0-9a-f]+: [ ]*004a 01c0 rdhwr v0,\$10
+[ ]*[0-9a-f]+: [ ]*0043 e17c rdpgpr v0,v1
+[ ]*[0-9a-f]+: [ ]*0042 e17c rdpgpr v0,v0
+[ ]*[0-9a-f]+: [ ]*0042 e17c rdpgpr v0,v0
+[ ]*[0-9a-f]+: [ ]*0080 11d0 negu v0,a0
+[ ]*[0-9a-f]+: [ ]*0062 10d0 rorv v0,v1,v0
+[ ]*[0-9a-f]+: [ ]*0080 09d0 negu at,a0
+[ ]*[0-9a-f]+: [ ]*0041 10d0 rorv v0,v0,at
+[ ]*[0-9a-f]+: [ ]*0060 11d0 negu v0,v1
+[ ]*[0-9a-f]+: [ ]*0062 10d0 rorv v0,v1,v0
+[ ]*[0-9a-f]+: [ ]*0040 11d0 negu v0,v0
+[ ]*[0-9a-f]+: [ ]*0062 10d0 rorv v0,v1,v0
+[ ]*[0-9a-f]+: [ ]*0043 00c0 ror v0,v1,0x0
+[ ]*[0-9a-f]+: [ ]*0043 f8c0 ror v0,v1,0x1f
+[ ]*[0-9a-f]+: [ ]*0043 08c0 ror v0,v1,0x1
+[ ]*[0-9a-f]+: [ ]*0042 08c0 ror v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*0042 08c0 ror v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*0043 00c0 ror v0,v1,0x0
+[ ]*[0-9a-f]+: [ ]*0043 08c0 ror v0,v1,0x1
+[ ]*[0-9a-f]+: [ ]*0043 f8c0 ror v0,v1,0x1f
+[ ]*[0-9a-f]+: [ ]*0042 f8c0 ror v0,v0,0x1f
+[ ]*[0-9a-f]+: [ ]*0042 f8c0 ror v0,v0,0x1f
+[ ]*[0-9a-f]+: [ ]*0064 10d0 rorv v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0044 10d0 rorv v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0064 10d0 rorv v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0044 10d0 rorv v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0064 10d0 rorv v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0044 10d0 rorv v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0064 10d0 rorv v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0044 10d0 rorv v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*8830 sb zero,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*8830 sb zero,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*8831 sb zero,1\(v1\)
+[ ]*[0-9a-f]+: [ ]*8832 sb zero,2\(v1\)
+[ ]*[0-9a-f]+: [ ]*8833 sb zero,3\(v1\)
+[ ]*[0-9a-f]+: [ ]*8834 sb zero,4\(v1\)
+[ ]*[0-9a-f]+: [ ]*8835 sb zero,5\(v1\)
+[ ]*[0-9a-f]+: [ ]*8836 sb zero,6\(v1\)
+[ ]*[0-9a-f]+: [ ]*8837 sb zero,7\(v1\)
+[ ]*[0-9a-f]+: [ ]*8838 sb zero,8\(v1\)
+[ ]*[0-9a-f]+: [ ]*8839 sb zero,9\(v1\)
+[ ]*[0-9a-f]+: [ ]*883a sb zero,10\(v1\)
+[ ]*[0-9a-f]+: [ ]*883b sb zero,11\(v1\)
+[ ]*[0-9a-f]+: [ ]*883c sb zero,12\(v1\)
+[ ]*[0-9a-f]+: [ ]*883d sb zero,13\(v1\)
+[ ]*[0-9a-f]+: [ ]*883e sb zero,14\(v1\)
+[ ]*[0-9a-f]+: [ ]*883f sb zero,15\(v1\)
+[ ]*[0-9a-f]+: [ ]*893f sb v0,15\(v1\)
+[ ]*[0-9a-f]+: [ ]*89bf sb v1,15\(v1\)
+[ ]*[0-9a-f]+: [ ]*8a3f sb a0,15\(v1\)
+[ ]*[0-9a-f]+: [ ]*8abf sb a1,15\(v1\)
+[ ]*[0-9a-f]+: [ ]*8b3f sb a2,15\(v1\)
+[ ]*[0-9a-f]+: [ ]*8bbf sb a3,15\(v1\)
+[ ]*[0-9a-f]+: [ ]*88bf sb s1,15\(v1\)
+[ ]*[0-9a-f]+: [ ]*88cf sb s1,15\(a0\)
+[ ]*[0-9a-f]+: [ ]*88df sb s1,15\(a1\)
+[ ]*[0-9a-f]+: [ ]*88ef sb s1,15\(a2\)
+[ ]*[0-9a-f]+: [ ]*88ff sb s1,15\(a3\)
+[ ]*[0-9a-f]+: [ ]*88af sb s1,15\(v0\)
+[ ]*[0-9a-f]+: [ ]*888f sb s1,15\(s0\)
+[ ]*[0-9a-f]+: [ ]*889f sb s1,15\(s1\)
+[ ]*[0-9a-f]+: [ ]*1860 0004 sb v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*1860 0004 sb v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*1860 7fff sb v1,32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*1860 8000 sb v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*1861 ffff sb v1,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*1861 0000 sb v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1860 8000 sb v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*1861 0001 sb v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*1860 8001 sb v1,-32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*1861 0000 sb v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1860 ffff sb v1,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*1861 5678 sb v1,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*1864 0000 sb v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*1864 0000 sb v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*1864 7fff sb v1,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1864 8000 sb v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*1861 ffff sb v1,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*1861 0000 sb v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1864 8000 sb v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*1861 0001 sb v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*1864 8001 sb v1,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*1861 0000 sb v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1864 ffff sb v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*1861 5678 sb v1,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*6060 b004 sc v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*6060 b004 sc v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*6060 b0ff sc v1,255\(zero\)
+[ ]*[0-9a-f]+: [ ]*6060 b100 sc v1,-256\(zero\)
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*6061 b1ff sc v1,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*6061 b001 sc v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 8001 li at,-32767
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*6060 b1ff sc v1,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5600 ori at,at,0x5600
+[ ]*[0-9a-f]+: [ ]*6061 b078 sc v1,120\(at\)
+[ ]*[0-9a-f]+: [ ]*6064 b000 sc v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*6064 b000 sc v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*6064 b0ff sc v1,255\(a0\)
+[ ]*[0-9a-f]+: [ ]*6064 b100 sc v1,-256\(a0\)
+[ ]*[0-9a-f]+: [ ]*3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*6061 b1ff sc v1,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*6061 b001 sc v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8001 addiu at,a0,-32767
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*6061 b000 sc v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*6064 b1ff sc v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5600 ori at,at,0x5600
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*6061 b078 sc v1,120\(at\)
+[ ]*[0-9a-f]+: [ ]*443b sdbbp
+[ ]*[0-9a-f]+: [ ]*443b sdbbp
+[ ]*[0-9a-f]+: [ ]*447b sdbbp 0x1
+[ ]*[0-9a-f]+: [ ]*44bb sdbbp 0x2
+[ ]*[0-9a-f]+: [ ]*44fb sdbbp 0x3
+[ ]*[0-9a-f]+: [ ]*453b sdbbp 0x4
+[ ]*[0-9a-f]+: [ ]*457b sdbbp 0x5
+[ ]*[0-9a-f]+: [ ]*45bb sdbbp 0x6
+[ ]*[0-9a-f]+: [ ]*45fb sdbbp 0x7
+[ ]*[0-9a-f]+: [ ]*463b sdbbp 0x8
+[ ]*[0-9a-f]+: [ ]*467b sdbbp 0x9
+[ ]*[0-9a-f]+: [ ]*46bb sdbbp 0xa
+[ ]*[0-9a-f]+: [ ]*46fb sdbbp 0xb
+[ ]*[0-9a-f]+: [ ]*473b sdbbp 0xc
+[ ]*[0-9a-f]+: [ ]*477b sdbbp 0xd
+[ ]*[0-9a-f]+: [ ]*47bb sdbbp 0xe
+[ ]*[0-9a-f]+: [ ]*47fb sdbbp 0xf
+[ ]*[0-9a-f]+: [ ]*0000 db7c sdbbp
+[ ]*[0-9a-f]+: [ ]*0000 db7c sdbbp
+[ ]*[0-9a-f]+: [ ]*0001 db7c sdbbp 0x1
+[ ]*[0-9a-f]+: [ ]*0002 db7c sdbbp 0x2
+[ ]*[0-9a-f]+: [ ]*00ff db7c sdbbp 0xff
+[ ]*[0-9a-f]+: [ ]*0043 2b3c seb v0,v1
+[ ]*[0-9a-f]+: [ ]*0042 2b3c seb v0,v0
+[ ]*[0-9a-f]+: [ ]*0042 2b3c seb v0,v0
+[ ]*[0-9a-f]+: [ ]*0043 3b3c seh v0,v1
+[ ]*[0-9a-f]+: [ ]*0042 3b3c seh v0,v0
+[ ]*[0-9a-f]+: [ ]*0042 3b3c seh v0,v0
+[ ]*[0-9a-f]+: [ ]*0083 1310 xor v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*b042 0001 sltiu v0,v0,1
+[ ]*[0-9a-f]+: [ ]*b043 0001 sltiu v0,v1,1
+[ ]*[0-9a-f]+: [ ]*b044 0001 sltiu v0,a0,1
+[ ]*[0-9a-f]+: [ ]*b043 0001 sltiu v0,v1,1
+[ ]*[0-9a-f]+: [ ]*7043 0001 xori v0,v1,0x1
+[ ]*[0-9a-f]+: [ ]*b042 0001 sltiu v0,v0,1
+[ ]*[0-9a-f]+: [ ]*3043 0001 addiu v0,v1,1
+[ ]*[0-9a-f]+: [ ]*b042 0001 sltiu v0,v0,1
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: [ ]*0023 1310 xor v0,v1,at
+[ ]*[0-9a-f]+: [ ]*b042 0001 sltiu v0,v0,1
+[ ]*[0-9a-f]+: [ ]*0083 1350 slt v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*0082 1350 slt v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
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+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*9043 0000 slti v0,v1,0
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+[ ]*[0-9a-f]+: [ ]*9043 8000 slti v0,v1,-32768
+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*9043 0000 slti v0,v1,0
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+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: [ ]*0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*0083 1390 sltu v0,v1,a0
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+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*b043 0000 sltiu v0,v1,0
+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*b043 8000 sltiu v0,v1,-32768
+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*b043 0000 sltiu v0,v1,0
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+[ ]*[0-9a-f]+: [ ]*b043 7fff sltiu v0,v1,32767
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+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
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+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
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+[ ]*[0-9a-f]+: [ ]*0023 1390 sltu v0,v1,at
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+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
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+[ ]*[0-9a-f]+: [ ]*a92f sh v0,30\(v0\)
+[ ]*[0-9a-f]+: [ ]*a90f sh v0,30\(s0\)
+[ ]*[0-9a-f]+: [ ]*a91f sh v0,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*a99f sh v1,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*aa1f sh a0,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*aa9f sh a1,30\(s1\)
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+[ ]*[0-9a-f]+: [ ]*a89f sh s1,30\(s1\)
+[ ]*[0-9a-f]+: [ ]*a81f sh zero,30\(s1\)
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+[ ]*[0-9a-f]+: [ ]*3860 0004 sh v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*3860 7fff sh v1,32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*3860 8000 sh v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*3861 ffff sh v1,-1\(at\)
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+[ ]*[0-9a-f]+: [ ]*3861 0000 sh v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3860 8000 sh v1,-32768\(zero\)
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+[ ]*[0-9a-f]+: [ ]*3860 8001 sh v1,-32767\(zero\)
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+[ ]*[0-9a-f]+: [ ]*3861 0000 sh v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3860 ffff sh v1,-1\(zero\)
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+[ ]*[0-9a-f]+: [ ]*3861 5678 sh v1,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*3864 0000 sh v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*3864 0000 sh v1,0\(a0\)
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+[ ]*[0-9a-f]+: [ ]*3864 8000 sh v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*3861 ffff sh v1,-1\(at\)
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+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*3861 0000 sh v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3864 8000 sh v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*3861 0001 sh v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*3864 8001 sh v1,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*3861 0000 sh v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3864 ffff sh v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
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+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
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+[ ]*[0-9a-f]+: [ ]*0061 1390 sltu v0,at,v1
+[ ]*[0-9a-f]+: [ ]*7042 0001 xori v0,v0,0x1
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+[ ]*[0-9a-f]+: [ ]*2570 sll v0,a3,8
+[ ]*[0-9a-f]+: [ ]*2500 sll v0,s0,8
+[ ]*[0-9a-f]+: [ ]*2510 sll v0,s1,8
+[ ]*[0-9a-f]+: [ ]*25a0 sll v1,v0,8
+[ ]*[0-9a-f]+: [ ]*2620 sll a0,v0,8
+[ ]*[0-9a-f]+: [ ]*26a0 sll a1,v0,8
+[ ]*[0-9a-f]+: [ ]*2720 sll a2,v0,8
+[ ]*[0-9a-f]+: [ ]*27a0 sll a3,v0,8
+[ ]*[0-9a-f]+: [ ]*2420 sll s0,v0,8
+[ ]*[0-9a-f]+: [ ]*24a0 sll s1,v0,8
+[ ]*[0-9a-f]+: [ ]*2522 sll v0,v0,1
+[ ]*[0-9a-f]+: [ ]*25b2 sll v1,v1,1
+[ ]*[0-9a-f]+: [ ]*0064 1010 sllv v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0044 1010 sllv v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0044 1010 sllv v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0044 1010 sllv v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0044 0000 sll v0,a0,0x0
+[ ]*[0-9a-f]+: [ ]*0044 0800 sll v0,a0,0x1
+[ ]*[0-9a-f]+: [ ]*0044 f800 sll v0,a0,0x1f
+[ ]*[0-9a-f]+: [ ]*0042 f800 sll v0,v0,0x1f
+[ ]*[0-9a-f]+: [ ]*0042 f800 sll v0,v0,0x1f
+[ ]*[0-9a-f]+: [ ]*0083 1350 slt v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0082 1350 slt v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0082 1350 slt v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*9043 0000 slti v0,v1,0
+[ ]*[0-9a-f]+: [ ]*9043 8000 slti v0,v1,-32768
+[ ]*[0-9a-f]+: [ ]*9043 0000 slti v0,v1,0
+[ ]*[0-9a-f]+: [ ]*9043 7fff slti v0,v1,32767
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: [ ]*0023 1350 slt v0,v1,at
+[ ]*[0-9a-f]+: [ ]*9064 8000 slti v1,a0,-32768
+[ ]*[0-9a-f]+: [ ]*9064 0000 slti v1,a0,0
+[ ]*[0-9a-f]+: [ ]*9064 7fff slti v1,a0,32767
+[ ]*[0-9a-f]+: [ ]*9064 ffff slti v1,a0,-1
+[ ]*[0-9a-f]+: [ ]*9063 ffff slti v1,v1,-1
+[ ]*[0-9a-f]+: [ ]*9063 ffff slti v1,v1,-1
+[ ]*[0-9a-f]+: [ ]*b064 8000 sltiu v1,a0,-32768
+[ ]*[0-9a-f]+: [ ]*b064 0000 sltiu v1,a0,0
+[ ]*[0-9a-f]+: [ ]*b064 7fff sltiu v1,a0,32767
+[ ]*[0-9a-f]+: [ ]*b064 ffff sltiu v1,a0,-1
+[ ]*[0-9a-f]+: [ ]*b063 ffff sltiu v1,v1,-1
+[ ]*[0-9a-f]+: [ ]*b063 ffff sltiu v1,v1,-1
+[ ]*[0-9a-f]+: [ ]*0083 1390 sltu v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0082 1390 sltu v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0082 1390 sltu v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*b043 0000 sltiu v0,v1,0
+[ ]*[0-9a-f]+: [ ]*b043 8000 sltiu v0,v1,-32768
+[ ]*[0-9a-f]+: [ ]*b043 0000 sltiu v0,v1,0
+[ ]*[0-9a-f]+: [ ]*b043 7fff sltiu v0,v1,32767
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*0023 1390 sltu v0,v1,at
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0023 1390 sltu v0,v1,at
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: [ ]*0023 1390 sltu v0,v1,at
+[ ]*[0-9a-f]+: [ ]*0083 1310 xor v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0040 1390 sltu v0,zero,v0
+[ ]*[0-9a-f]+: [ ]*0080 1390 sltu v0,zero,a0
+[ ]*[0-9a-f]+: [ ]*0060 1390 sltu v0,zero,v1
+[ ]*[0-9a-f]+: [ ]*0060 1390 sltu v0,zero,v1
+[ ]*[0-9a-f]+: [ ]*7043 0001 xori v0,v1,0x1
+[ ]*[0-9a-f]+: [ ]*0040 1390 sltu v0,zero,v0
+[ ]*[0-9a-f]+: [ ]*3043 0001 addiu v0,v1,1
+[ ]*[0-9a-f]+: [ ]*0040 1390 sltu v0,zero,v0
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: [ ]*0023 1310 xor v0,v1,at
+[ ]*[0-9a-f]+: [ ]*0040 1390 sltu v0,zero,v0
+[ ]*[0-9a-f]+: [ ]*0064 1090 srav v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0044 1090 srav v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0044 1090 srav v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0044 1090 srav v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0044 0080 sra v0,a0,0x0
+[ ]*[0-9a-f]+: [ ]*0044 0880 sra v0,a0,0x1
+[ ]*[0-9a-f]+: [ ]*0044 f880 sra v0,a0,0x1f
+[ ]*[0-9a-f]+: [ ]*0042 f880 sra v0,v0,0x1f
+[ ]*[0-9a-f]+: [ ]*0042 f880 sra v0,v0,0x1f
+[ ]*[0-9a-f]+: [ ]*0064 1050 srlv v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*0044 1050 srlv v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0044 1050 srlv v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0044 1050 srlv v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0044 0040 srl v0,a0,0x0
+[ ]*[0-9a-f]+: [ ]*2543 srl v0,a0,1
+[ ]*[0-9a-f]+: [ ]*0044 f840 srl v0,a0,0x1f
+[ ]*[0-9a-f]+: [ ]*0042 f840 srl v0,v0,0x1f
+[ ]*[0-9a-f]+: [ ]*0042 f840 srl v0,v0,0x1f
+[ ]*[0-9a-f]+: [ ]*2523 srl v0,v0,1
+[ ]*[0-9a-f]+: [ ]*2525 srl v0,v0,2
+[ ]*[0-9a-f]+: [ ]*2527 srl v0,v0,3
+[ ]*[0-9a-f]+: [ ]*2529 srl v0,v0,4
+[ ]*[0-9a-f]+: [ ]*252b srl v0,v0,5
+[ ]*[0-9a-f]+: [ ]*252d srl v0,v0,6
+[ ]*[0-9a-f]+: [ ]*252f srl v0,v0,7
+[ ]*[0-9a-f]+: [ ]*2521 srl v0,v0,8
+[ ]*[0-9a-f]+: [ ]*2531 srl v0,v1,8
+[ ]*[0-9a-f]+: [ ]*2541 srl v0,a0,8
+[ ]*[0-9a-f]+: [ ]*2551 srl v0,a1,8
+[ ]*[0-9a-f]+: [ ]*2561 srl v0,a2,8
+[ ]*[0-9a-f]+: [ ]*2571 srl v0,a3,8
+[ ]*[0-9a-f]+: [ ]*2501 srl v0,s0,8
+[ ]*[0-9a-f]+: [ ]*2511 srl v0,s1,8
+[ ]*[0-9a-f]+: [ ]*2521 srl v0,v0,8
+[ ]*[0-9a-f]+: [ ]*25a1 srl v1,v0,8
+[ ]*[0-9a-f]+: [ ]*2621 srl a0,v0,8
+[ ]*[0-9a-f]+: [ ]*26a1 srl a1,v0,8
+[ ]*[0-9a-f]+: [ ]*2721 srl a2,v0,8
+[ ]*[0-9a-f]+: [ ]*27a1 srl a3,v0,8
+[ ]*[0-9a-f]+: [ ]*2421 srl s0,v0,8
+[ ]*[0-9a-f]+: [ ]*24a1 srl s1,v0,8
+[ ]*[0-9a-f]+: [ ]*25b3 srl v1,v1,1
+[ ]*[0-9a-f]+: [ ]*25b3 srl v1,v1,1
+[ ]*[0-9a-f]+: [ ]*0083 1190 sub v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*03fe e990 sub sp,s8,ra
+[ ]*[0-9a-f]+: [ ]*0082 1190 sub v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0082 1190 sub v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*05a5 subu v0,v1,v0
+[ ]*[0-9a-f]+: [ ]*05b5 subu v0,v1,v1
+[ ]*[0-9a-f]+: [ ]*05c5 subu v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*05d5 subu v0,v1,a1
+[ ]*[0-9a-f]+: [ ]*05e5 subu v0,v1,a2
+[ ]*[0-9a-f]+: [ ]*05f5 subu v0,v1,a3
+[ ]*[0-9a-f]+: [ ]*0585 subu v0,v1,s0
+[ ]*[0-9a-f]+: [ ]*0595 subu v0,v1,s1
+[ ]*[0-9a-f]+: [ ]*0515 subu v0,v0,s1
+[ ]*[0-9a-f]+: [ ]*0615 subu v0,a0,s1
+[ ]*[0-9a-f]+: [ ]*0695 subu v0,a1,s1
+[ ]*[0-9a-f]+: [ ]*0715 subu v0,a2,s1
+[ ]*[0-9a-f]+: [ ]*0795 subu v0,a3,s1
+[ ]*[0-9a-f]+: [ ]*0415 subu v0,s0,s1
+[ ]*[0-9a-f]+: [ ]*0495 subu v0,s1,s1
+[ ]*[0-9a-f]+: [ ]*0515 subu v0,v0,s1
+[ ]*[0-9a-f]+: [ ]*0517 subu v1,v0,s1
+[ ]*[0-9a-f]+: [ ]*0519 subu a0,v0,s1
+[ ]*[0-9a-f]+: [ ]*051b subu a1,v0,s1
+[ ]*[0-9a-f]+: [ ]*051d subu a2,v0,s1
+[ ]*[0-9a-f]+: [ ]*051f subu a3,v0,s1
+[ ]*[0-9a-f]+: [ ]*0511 subu s0,v0,s1
+[ ]*[0-9a-f]+: [ ]*0513 subu s1,v0,s1
+[ ]*[0-9a-f]+: [ ]*07af subu a3,a3,v0
+[ ]*[0-9a-f]+: [ ]*07af subu a3,a3,v0
+[ ]*[0-9a-f]+: [ ]*0083 11d0 subu v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*03fe e9d0 subu sp,s8,ra
+[ ]*[0-9a-f]+: [ ]*0082 11d0 subu v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0082 11d0 subu v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*3042 0000 addiu v0,v0,0
+[ ]*[0-9a-f]+: [ ]*3042 ffff addiu v0,v0,-1
+[ ]*[0-9a-f]+: [ ]*3042 8001 addiu v0,v0,-32767
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*0022 11d0 subu v0,v0,at
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*0022 11d0 subu v0,v0,at
+[ ]*[0-9a-f]+: [ ]*e940 sw v0,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*e940 sw v0,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*e941 sw v0,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*e942 sw v0,8\(a0\)
+[ ]*[0-9a-f]+: [ ]*e943 sw v0,12\(a0\)
+[ ]*[0-9a-f]+: [ ]*e944 sw v0,16\(a0\)
+[ ]*[0-9a-f]+: [ ]*e945 sw v0,20\(a0\)
+[ ]*[0-9a-f]+: [ ]*e946 sw v0,24\(a0\)
+[ ]*[0-9a-f]+: [ ]*e947 sw v0,28\(a0\)
+[ ]*[0-9a-f]+: [ ]*e948 sw v0,32\(a0\)
+[ ]*[0-9a-f]+: [ ]*e949 sw v0,36\(a0\)
+[ ]*[0-9a-f]+: [ ]*e94a sw v0,40\(a0\)
+[ ]*[0-9a-f]+: [ ]*e94b sw v0,44\(a0\)
+[ ]*[0-9a-f]+: [ ]*e94c sw v0,48\(a0\)
+[ ]*[0-9a-f]+: [ ]*e94d sw v0,52\(a0\)
+[ ]*[0-9a-f]+: [ ]*e94e sw v0,56\(a0\)
+[ ]*[0-9a-f]+: [ ]*e94f sw v0,60\(a0\)
+[ ]*[0-9a-f]+: [ ]*e95f sw v0,60\(a1\)
+[ ]*[0-9a-f]+: [ ]*e96f sw v0,60\(a2\)
+[ ]*[0-9a-f]+: [ ]*e97f sw v0,60\(a3\)
+[ ]*[0-9a-f]+: [ ]*e90f sw v0,60\(s0\)
+[ ]*[0-9a-f]+: [ ]*e91f sw v0,60\(s1\)
+[ ]*[0-9a-f]+: [ ]*e92f sw v0,60\(v0\)
+[ ]*[0-9a-f]+: [ ]*e93f sw v0,60\(v1\)
+[ ]*[0-9a-f]+: [ ]*e9bf sw v1,60\(v1\)
+[ ]*[0-9a-f]+: [ ]*ea3f sw a0,60\(v1\)
+[ ]*[0-9a-f]+: [ ]*eabf sw a1,60\(v1\)
+[ ]*[0-9a-f]+: [ ]*eb3f sw a2,60\(v1\)
+[ ]*[0-9a-f]+: [ ]*ebbf sw a3,60\(v1\)
+[ ]*[0-9a-f]+: [ ]*e8bf sw s1,60\(v1\)
+[ ]*[0-9a-f]+: [ ]*e83f sw zero,60\(v1\)
+[ ]*[0-9a-f]+: [ ]*c800 sw zero,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*c800 sw zero,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*c801 sw zero,4\(sp\)
+[ ]*[0-9a-f]+: [ ]*c802 sw zero,8\(sp\)
+[ ]*[0-9a-f]+: [ ]*c803 sw zero,12\(sp\)
+[ ]*[0-9a-f]+: [ ]*c804 sw zero,16\(sp\)
+[ ]*[0-9a-f]+: [ ]*c805 sw zero,20\(sp\)
+[ ]*[0-9a-f]+: [ ]*c81e sw zero,120\(sp\)
+[ ]*[0-9a-f]+: [ ]*c81f sw zero,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*c85f sw v0,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*ca3f sw s1,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*c87f sw v1,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*c89f sw a0,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*c8bf sw a1,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*c8df sw a2,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*c8ff sw a3,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*cbff sw ra,124\(sp\)
+[ ]*[0-9a-f]+: [ ]*f860 0004 sw v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*f860 0004 sw v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*f860 7fff sw v1,32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*f860 8000 sw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*f861 ffff sw v1,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*f860 8000 sw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*f861 0001 sw v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*f860 8001 sw v1,-32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*f860 ffff sw v1,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*f861 5678 sw v1,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*f864 0000 sw v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*f864 0000 sw v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*f864 7fff sw v1,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*f864 8000 sw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*f861 ffff sw v1,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*f864 8000 sw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*f861 0001 sw v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*f864 8001 sw v1,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*f864 ffff sw v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*f861 5678 sw v1,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*44ca swm s0,ra,48\(sp\)
+[ ]*[0-9a-f]+: [ ]*45ca swm s0-s1,ra,48\(sp\)
+[ ]*[0-9a-f]+: [ ]*45ca swm s0-s1,ra,48\(sp\)
+[ ]*[0-9a-f]+: [ ]*46ca swm s0-s2,ra,48\(sp\)
+[ ]*[0-9a-f]+: [ ]*46ca swm s0-s2,ra,48\(sp\)
+[ ]*[0-9a-f]+: [ ]*47ca swm s0-s3,ra,48\(sp\)
+[ ]*[0-9a-f]+: [ ]*47ca swm s0-s3,ra,48\(sp\)
+[ ]*[0-9a-f]+: [ ]*440a swm s0,ra,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*440a swm s0,ra,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*441a swm s0,ra,4\(sp\)
+[ ]*[0-9a-f]+: [ ]*442a swm s0,ra,8\(sp\)
+[ ]*[0-9a-f]+: [ ]*443a swm s0,ra,12\(sp\)
+[ ]*[0-9a-f]+: [ ]*444a swm s0,ra,16\(sp\)
+[ ]*[0-9a-f]+: [ ]*445a swm s0,ra,20\(sp\)
+[ ]*[0-9a-f]+: [ ]*446a swm s0,ra,24\(sp\)
+[ ]*[0-9a-f]+: [ ]*447a swm s0,ra,28\(sp\)
+[ ]*[0-9a-f]+: [ ]*448a swm s0,ra,32\(sp\)
+[ ]*[0-9a-f]+: [ ]*449a swm s0,ra,36\(sp\)
+[ ]*[0-9a-f]+: [ ]*44aa swm s0,ra,40\(sp\)
+[ ]*[0-9a-f]+: [ ]*44ba swm s0,ra,44\(sp\)
+[ ]*[0-9a-f]+: [ ]*44ca swm s0,ra,48\(sp\)
+[ ]*[0-9a-f]+: [ ]*44da swm s0,ra,52\(sp\)
+[ ]*[0-9a-f]+: [ ]*44ea swm s0,ra,56\(sp\)
+[ ]*[0-9a-f]+: [ ]*44fa swm s0,ra,60\(sp\)
+[ ]*[0-9a-f]+: [ ]*2020 d000 swm s0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2020 d004 swm s0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2020 d7ff swm s0,2047\(zero\)
+[ ]*[0-9a-f]+: [ ]*2020 d800 swm s0,-2048\(zero\)
+[ ]*[0-9a-f]+: [ ]*3020 0800 li at,2048
+[ ]*[0-9a-f]+: [ ]*2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 f7ff li at,-2049
+[ ]*[0-9a-f]+: [ ]*2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2025 d000 swm s0,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2025 d7ff swm s0,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2025 d800 swm s0,-2048\(a1\)
+[ ]*[0-9a-f]+: [ ]*3025 0800 addiu at,a1,2048
+[ ]*[0-9a-f]+: [ ]*2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3025 f7ff addiu at,a1,-2049
+[ ]*[0-9a-f]+: [ ]*2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2045 d7ff swm s0-s1,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2065 d7ff swm s0-s2,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2085 d7ff swm s0-s3,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*20a5 d7ff swm s0-s4,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*20c5 d7ff swm s0-s5,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*20e5 d7ff swm s0-s6,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2105 d7ff swm s0-s7,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2125 d7ff swm s0-s7,s8,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2205 d7ff swm ra,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2225 d000 swm s0,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2245 d000 swm s0-s1,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2265 d000 swm s0-s2,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2285 d000 swm s0-s3,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*22a5 d000 swm s0-s4,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*22c5 d000 swm s0-s5,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*22e5 d000 swm s0-s6,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2305 d000 swm s0-s7,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2325 d000 swm s0-s7,s8,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*303d 8000 addiu at,sp,-32768
+[ ]*[0-9a-f]+: [ ]*2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*303d 7fff addiu at,sp,32767
+[ ]*[0-9a-f]+: [ ]*2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*203d d000 swm s0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*03a1 0950 addu at,at,sp
+[ ]*[0-9a-f]+: [ ]*2021 dfff swm s0,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*2040 9000 swp v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2040 9004 swp v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2040 97ff swp v0,2047\(zero\)
+[ ]*[0-9a-f]+: [ ]*2040 9800 swp v0,-2048\(zero\)
+[ ]*[0-9a-f]+: [ ]*3020 0800 li at,2048
+[ ]*[0-9a-f]+: [ ]*2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 f7ff li at,-2049
+[ ]*[0-9a-f]+: [ ]*2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*205d 9000 swp v0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*205d 9000 swp v0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*2043 97ff swp v0,2047\(v1\)
+[ ]*[0-9a-f]+: [ ]*2043 9800 swp v0,-2048\(v1\)
+[ ]*[0-9a-f]+: [ ]*3023 0800 addiu at,v1,2048
+[ ]*[0-9a-f]+: [ ]*2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 f7ff addiu at,v1,-2049
+[ ]*[0-9a-f]+: [ ]*2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 7fff addiu at,v1,32767
+[ ]*[0-9a-f]+: [ ]*2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 8000 addiu at,v1,-32768
+[ ]*[0-9a-f]+: [ ]*2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2043 9000 swp v0,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: [ ]*2041 9fff swp v0,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*0000 6b7c sync
+[ ]*[0-9a-f]+: [ ]*0000 6b7c sync
+[ ]*[0-9a-f]+: [ ]*0001 6b7c sync 0x1
+[ ]*[0-9a-f]+: [ ]*0002 6b7c sync 0x2
+[ ]*[0-9a-f]+: [ ]*0003 6b7c sync 0x3
+[ ]*[0-9a-f]+: [ ]*0004 6b7c sync_wmb
+[ ]*[0-9a-f]+: [ ]*001e 6b7c sync 0x1e
+[ ]*[0-9a-f]+: [ ]*001f 6b7c sync 0x1f
+[ ]*[0-9a-f]+: [ ]*4180 0000 synci 0\(zero\)
+[ ]*[0-9a-f]+: [ ]*4180 0000 synci 0\(zero\)
+[ ]*[0-9a-f]+: [ ]*4180 0000 synci 0\(zero\)
+[ ]*[0-9a-f]+: [ ]*4180 07ff synci 2047\(zero\)
+[ ]*[0-9a-f]+: [ ]*4180 f800 synci -2048\(zero\)
+[ ]*[0-9a-f]+: [ ]*4180 0800 synci 2048\(zero\)
+[ ]*[0-9a-f]+: [ ]*4180 f7ff synci -2049\(zero\)
+[ ]*[0-9a-f]+: [ ]*4180 7fff synci 32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*4180 8000 synci -32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*4182 0000 synci 0\(v0\)
+[ ]*[0-9a-f]+: [ ]*4183 0000 synci 0\(v1\)
+[ ]*[0-9a-f]+: [ ]*4183 07ff synci 2047\(v1\)
+[ ]*[0-9a-f]+: [ ]*4183 f800 synci -2048\(v1\)
+[ ]*[0-9a-f]+: [ ]*4183 0800 synci 2048\(v1\)
+[ ]*[0-9a-f]+: [ ]*4183 f7ff synci -2049\(v1\)
+[ ]*[0-9a-f]+: [ ]*4183 7fff synci 32767\(v1\)
+[ ]*[0-9a-f]+: [ ]*4183 8000 synci -32768\(v1\)
+[ ]*[0-9a-f]+: [ ]*0000 8b7c syscall
+[ ]*[0-9a-f]+: [ ]*0000 8b7c syscall
+[ ]*[0-9a-f]+: [ ]*0001 8b7c syscall 0x1
+[ ]*[0-9a-f]+: [ ]*0002 8b7c syscall 0x2
+[ ]*[0-9a-f]+: [ ]*00ff 8b7c syscall 0xff
+[ ]*[0-9a-f]+: [ ]*0062 003c teq v0,v1
+[ ]*[0-9a-f]+: [ ]*0043 003c teq v1,v0
+[ ]*[0-9a-f]+: [ ]*0062 003c teq v0,v1
+[ ]*[0-9a-f]+: [ ]*0062 103c teq v0,v1,0x1
+[ ]*[0-9a-f]+: [ ]*0062 f03c teq v0,v1,0xf
+[ ]*[0-9a-f]+: [ ]*0002 003c teq v0,zero
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*0022 003c teq v0,at
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*0022 003c teq v0,at
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*0022 003c teq v0,at
+[ ]*[0-9a-f]+: [ ]*0062 023c tge v0,v1
+[ ]*[0-9a-f]+: [ ]*0043 023c tge v1,v0
+[ ]*[0-9a-f]+: [ ]*0062 023c tge v0,v1
+[ ]*[0-9a-f]+: [ ]*0062 123c tge v0,v1,0x1
+[ ]*[0-9a-f]+: [ ]*0062 f23c tge v0,v1,0xf
+[ ]*[0-9a-f]+: [ ]*0002 023c tge v0,zero
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*0022 023c tge v0,at
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*0022 023c tge v0,at
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*0022 023c tge v0,at
+[ ]*[0-9a-f]+: [ ]*0062 043c tgeu v0,v1
+[ ]*[0-9a-f]+: [ ]*0043 043c tgeu v1,v0
+[ ]*[0-9a-f]+: [ ]*0062 043c tgeu v0,v1
+[ ]*[0-9a-f]+: [ ]*0062 143c tgeu v0,v1,0x1
+[ ]*[0-9a-f]+: [ ]*0062 f43c tgeu v0,v1,0xf
+[ ]*[0-9a-f]+: [ ]*0002 043c tgeu v0,zero
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*0022 043c tgeu v0,at
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*0022 043c tgeu v0,at
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*0022 043c tgeu v0,at
+[ ]*[0-9a-f]+: [ ]*0000 037c tlbp
+[ ]*[0-9a-f]+: [ ]*0000 137c tlbr
+[ ]*[0-9a-f]+: [ ]*0000 237c tlbwi
+[ ]*[0-9a-f]+: [ ]*0000 337c tlbwr
+[ ]*[0-9a-f]+: [ ]*0062 083c tlt v0,v1
+[ ]*[0-9a-f]+: [ ]*0043 083c tlt v1,v0
+[ ]*[0-9a-f]+: [ ]*0062 083c tlt v0,v1
+[ ]*[0-9a-f]+: [ ]*0062 183c tlt v0,v1,0x1
+[ ]*[0-9a-f]+: [ ]*0062 f83c tlt v0,v1,0xf
+[ ]*[0-9a-f]+: [ ]*0002 083c tlt v0,zero
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*0022 083c tlt v0,at
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*0022 083c tlt v0,at
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*0022 083c tlt v0,at
+[ ]*[0-9a-f]+: [ ]*0062 0a3c tltu v0,v1
+[ ]*[0-9a-f]+: [ ]*0043 0a3c tltu v1,v0
+[ ]*[0-9a-f]+: [ ]*0062 0a3c tltu v0,v1
+[ ]*[0-9a-f]+: [ ]*0062 1a3c tltu v0,v1,0x1
+[ ]*[0-9a-f]+: [ ]*0062 fa3c tltu v0,v1,0xf
+[ ]*[0-9a-f]+: [ ]*0002 0a3c tltu v0,zero
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: [ ]*3020 ffff li at,-1
+[ ]*[0-9a-f]+: [ ]*0022 0a3c tltu v0,at
+[ ]*[0-9a-f]+: [ ]*0062 0c3c tne v0,v1
+[ ]*[0-9a-f]+: [ ]*0043 0c3c tne v1,v0
+[ ]*[0-9a-f]+: [ ]*0062 0c3c tne v0,v1
+[ ]*[0-9a-f]+: [ ]*0062 1c3c tne v0,v1,0x1
+[ ]*[0-9a-f]+: [ ]*0062 fc3c tne v0,v1,0xf
+[ ]*[0-9a-f]+: [ ]*0002 0c3c tne v0,zero
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: [ ]*3020 ffff li at,-1
+[ ]*[0-9a-f]+: [ ]*0022 0c3c tne v0,at
+[ ]*[0-9a-f]+: [ ]*0000 937c wait
+[ ]*[0-9a-f]+: [ ]*0000 937c wait
+[ ]*[0-9a-f]+: [ ]*0001 937c wait 0x1
+[ ]*[0-9a-f]+: [ ]*00ff 937c wait 0xff
+[ ]*[0-9a-f]+: [ ]*0043 f17c wrpgpr v0,v1
+[ ]*[0-9a-f]+: [ ]*0044 f17c wrpgpr v0,a0
+[ ]*[0-9a-f]+: [ ]*0042 f17c wrpgpr v0,v0
+[ ]*[0-9a-f]+: [ ]*0042 f17c wrpgpr v0,v0
+[ ]*[0-9a-f]+: [ ]*0043 7b3c wsbh v0,v1
+[ ]*[0-9a-f]+: [ ]*0044 7b3c wsbh v0,a0
+[ ]*[0-9a-f]+: [ ]*0042 7b3c wsbh v0,v0
+[ ]*[0-9a-f]+: [ ]*0042 7b3c wsbh v0,v0
+[ ]*[0-9a-f]+: [ ]*4528 xor v0,v0,v0
+[ ]*[0-9a-f]+: [ ]*4538 xor v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*4548 xor v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*4558 xor v0,v0,a1
+[ ]*[0-9a-f]+: [ ]*4568 xor v0,v0,a2
+[ ]*[0-9a-f]+: [ ]*4578 xor v0,v0,a3
+[ ]*[0-9a-f]+: [ ]*4508 xor v0,v0,s0
+[ ]*[0-9a-f]+: [ ]*4518 xor v0,v0,s1
+[ ]*[0-9a-f]+: [ ]*4598 xor v1,v1,s1
+[ ]*[0-9a-f]+: [ ]*4618 xor a0,a0,s1
+[ ]*[0-9a-f]+: [ ]*4698 xor a1,a1,s1
+[ ]*[0-9a-f]+: [ ]*4718 xor a2,a2,s1
+[ ]*[0-9a-f]+: [ ]*4798 xor a3,a3,s1
+[ ]*[0-9a-f]+: [ ]*4418 xor s0,s0,s1
+[ ]*[0-9a-f]+: [ ]*4498 xor s1,s1,s1
+[ ]*[0-9a-f]+: [ ]*4538 xor v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*4538 xor v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*4538 xor v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*0083 1310 xor v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*03fe eb10 xor sp,s8,ra
+[ ]*[0-9a-f]+: [ ]*0082 1310 xor v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*0082 1310 xor v0,v0,a0
+[ ]*[0-9a-f]+: [ ]*7043 8000 xori v0,v1,0x8000
+[ ]*[0-9a-f]+: [ ]*7043 ffff xori v0,v1,0xffff
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0023 1310 xor v0,v1,at
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*0023 1310 xor v0,v1,at
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*5021 7fff ori at,at,0x7fff
+[ ]*[0-9a-f]+: [ ]*0023 1310 xor v0,v1,at
+[ ]*[0-9a-f]+: [ ]*7064 0000 xori v1,a0,0x0
+[ ]*[0-9a-f]+: [ ]*7064 7fff xori v1,a0,0x7fff
+[ ]*[0-9a-f]+: [ ]*7064 ffff xori v1,a0,0xffff
+[ ]*[0-9a-f]+: [ ]*7063 ffff xori v1,v1,0xffff
+[ ]*[0-9a-f]+: [ ]*7063 ffff xori v1,v1,0xffff
+[ ]*[0-9a-f]+: [ ]*6d01 addiu v0,sp,0
+[ ]*[0-9a-f]+: [ ]*6d03 addiu v0,sp,4
+[ ]*[0-9a-f]+: [ ]*6d05 addiu v0,sp,8
+[ ]*[0-9a-f]+: [ ]*6d07 addiu v0,sp,12
+[ ]*[0-9a-f]+: [ ]*6d09 addiu v0,sp,16
+[ ]*[0-9a-f]+: [ ]*6d7f addiu v0,sp,252
+[ ]*[0-9a-f]+: [ ]*6dff addiu v1,sp,252
+[ ]*[0-9a-f]+: [ ]*6e7f addiu a0,sp,252
+[ ]*[0-9a-f]+: [ ]*6eff addiu a1,sp,252
+[ ]*[0-9a-f]+: [ ]*6f7f addiu a2,sp,252
+[ ]*[0-9a-f]+: [ ]*6fff addiu a3,sp,252
+[ ]*[0-9a-f]+: [ ]*6c7f addiu s0,sp,252
+[ ]*[0-9a-f]+: [ ]*6cff addiu s1,sp,252
+[ ]*[0-9a-f]+: [ ]*6d2e addiu v0,v0,-1
+[ ]*[0-9a-f]+: [ ]*6d3e addiu v0,v1,-1
+[ ]*[0-9a-f]+: [ ]*6d4e addiu v0,a0,-1
+[ ]*[0-9a-f]+: [ ]*6d5e addiu v0,a1,-1
+[ ]*[0-9a-f]+: [ ]*6d6e addiu v0,a2,-1
+[ ]*[0-9a-f]+: [ ]*6d7e addiu v0,a3,-1
+[ ]*[0-9a-f]+: [ ]*6d0e addiu v0,s0,-1
+[ ]*[0-9a-f]+: [ ]*6d1e addiu v0,s1,-1
+[ ]*[0-9a-f]+: [ ]*6d9e addiu v1,s1,-1
+[ ]*[0-9a-f]+: [ ]*6e1e addiu a0,s1,-1
+[ ]*[0-9a-f]+: [ ]*6e9e addiu a1,s1,-1
+[ ]*[0-9a-f]+: [ ]*6f1e addiu a2,s1,-1
+[ ]*[0-9a-f]+: [ ]*6f9e addiu a3,s1,-1
+[ ]*[0-9a-f]+: [ ]*6c1e addiu s0,s1,-1
+[ ]*[0-9a-f]+: [ ]*6c9e addiu s1,s1,-1
+[ ]*[0-9a-f]+: [ ]*6c90 addiu s1,s1,1
+[ ]*[0-9a-f]+: [ ]*6c92 addiu s1,s1,4
+[ ]*[0-9a-f]+: [ ]*6c94 addiu s1,s1,8
+[ ]*[0-9a-f]+: [ ]*6c96 addiu s1,s1,12
+[ ]*[0-9a-f]+: [ ]*6c98 addiu s1,s1,16
+[ ]*[0-9a-f]+: [ ]*6c9a addiu s1,s1,20
+[ ]*[0-9a-f]+: [ ]*6c9c addiu s1,s1,24
+[ ]*[0-9a-f]+: [ ]*4c05 addiu sp,sp,8
+[ ]*[0-9a-f]+: [ ]*4c07 addiu sp,sp,12
+[ ]*[0-9a-f]+: [ ]*4dfd addiu sp,sp,1016
+[ ]*[0-9a-f]+: [ ]*4dff addiu sp,sp,1020
+[ ]*[0-9a-f]+: [ ]*4c01 addiu sp,sp,1024
+[ ]*[0-9a-f]+: [ ]*4c03 addiu sp,sp,1028
+[ ]*[0-9a-f]+: [ ]*4ffb addiu sp,sp,-12
+[ ]*[0-9a-f]+: [ ]*4ff9 addiu sp,sp,-16
+[ ]*[0-9a-f]+: [ ]*4e03 addiu sp,sp,-1020
+[ ]*[0-9a-f]+: [ ]*4e01 addiu sp,sp,-1024
+[ ]*[0-9a-f]+: [ ]*4fff addiu sp,sp,-1028
+[ ]*[0-9a-f]+: [ ]*4ffd addiu sp,sp,-1032
+[ ]*[0-9a-f]+: [ ]*4c00 addiu zero,zero,0
+[ ]*[0-9a-f]+: [ ]*4c40 addiu v0,v0,0
+[ ]*[0-9a-f]+: [ ]*4c60 addiu v1,v1,0
+[ ]*[0-9a-f]+: [ ]*4fc0 addiu s8,s8,0
+[ ]*[0-9a-f]+: [ ]*4fe0 addiu ra,ra,0
+[ ]*[0-9a-f]+: [ ]*4fe2 addiu ra,ra,1
+[ ]*[0-9a-f]+: [ ]*4fe4 addiu ra,ra,2
+[ ]*[0-9a-f]+: [ ]*4fe6 addiu ra,ra,3
+[ ]*[0-9a-f]+: [ ]*4fee addiu ra,ra,7
+[ ]*[0-9a-f]+: [ ]*4ff4 addiu ra,ra,-6
+[ ]*[0-9a-f]+: [ ]*4ff2 addiu ra,ra,-7
+[ ]*[0-9a-f]+: [ ]*4ff0 addiu ra,ra,-8
+[ ]*[0-9a-f]+: [ ]*f860 0004 sw v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*f880 0008 sw a0,8\(zero\)
+[ ]*[0-9a-f]+: [ ]*f860 0004 sw v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*f880 0008 sw a0,8\(zero\)
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*f860 8000 sw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*f880 8004 sw a0,-32764\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*f861 ffff sw v1,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 0003 sw a0,3\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*f860 8000 sw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*f880 8004 sw a0,-32764\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*f861 0001 sw v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 0005 sw a0,5\(at\)
+[ ]*[0-9a-f]+: [ ]*f860 8001 sw v1,-32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*f880 8005 sw a0,-32763\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*f860 ffff sw v1,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*f880 0003 sw a0,3\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*f861 5678 sw v1,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 567c sw a0,22140\(at\)
+[ ]*[0-9a-f]+: [ ]*f864 0000 sw v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*f884 0004 sw a0,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*f864 0000 sw v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*f884 0004 sw a0,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: [ ]*f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*f864 8000 sw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*f884 8004 sw a0,-32764\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: [ ]*f861 ffff sw v1,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 0003 sw a0,3\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: [ ]*f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*f864 8000 sw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*f884 8004 sw a0,-32764\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: [ ]*f861 0001 sw v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 0005 sw a0,5\(at\)
+[ ]*[0-9a-f]+: [ ]*f864 8001 sw v1,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*f884 8005 sw a0,-32763\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: [ ]*f861 0000 sw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 0004 sw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*f864 ffff sw v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*f884 0003 sw a0,3\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: [ ]*f861 5678 sw v1,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*f881 567c sw a0,22140\(at\)
+[ ]*[0-9a-f]+: [ ]*fc60 0004 lw v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*fc80 0008 lw a0,8\(zero\)
+[ ]*[0-9a-f]+: [ ]*fc60 0004 lw v1,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*fc80 0008 lw a0,8\(zero\)
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*fc60 8000 lw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*fc80 8004 lw a0,-32764\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*fc61 ffff lw v1,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 0003 lw a0,3\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*fc60 8000 lw v1,-32768\(zero\)
+[ ]*[0-9a-f]+: [ ]*fc80 8004 lw a0,-32764\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*fc61 0001 lw v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 0005 lw a0,5\(at\)
+[ ]*[0-9a-f]+: [ ]*fc60 8001 lw v1,-32767\(zero\)
+[ ]*[0-9a-f]+: [ ]*fc80 8005 lw a0,-32763\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*fc60 ffff lw v1,-1\(zero\)
+[ ]*[0-9a-f]+: [ ]*fc80 0003 lw a0,3\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*fc61 5678 lw v1,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 567c lw a0,22140\(at\)
+[ ]*[0-9a-f]+: [ ]*fc64 0000 lw v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*fc84 0004 lw a0,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*fc64 0000 lw v1,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*fc84 0004 lw a0,4\(a0\)
+[ ]*[0-9a-f]+: [ ]*3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: [ ]*fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*fc64 8000 lw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*fc84 8004 lw a0,-32764\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: [ ]*fc61 ffff lw v1,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 0003 lw a0,3\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: [ ]*fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*fc64 8000 lw v1,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*fc84 8004 lw a0,-32764\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: [ ]*fc61 0001 lw v1,1\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 0005 lw a0,5\(at\)
+[ ]*[0-9a-f]+: [ ]*fc64 8001 lw v1,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*fc84 8005 lw a0,-32763\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: [ ]*fc61 0000 lw v1,0\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 0004 lw a0,4\(at\)
+[ ]*[0-9a-f]+: [ ]*fc64 ffff lw v1,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*fc84 0003 lw a0,3\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0024 0950 addu at,a0,at
+[ ]*[0-9a-f]+: [ ]*fc61 5678 lw v1,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*fc81 567c lw a0,22140\(at\)
+[ ]*[0-9a-f]+: [ ]*4413 jrcaddiusp 0
+[ ]*[0-9a-f]+: [ ]*4433 jrcaddiusp 4
+[ ]*[0-9a-f]+: [ ]*4453 jrcaddiusp 8
+[ ]*[0-9a-f]+: [ ]*4473 jrcaddiusp 12
+[ ]*[0-9a-f]+: [ ]*4493 jrcaddiusp 16
+[ ]*[0-9a-f]+: [ ]*44b3 jrcaddiusp 20
+[ ]*[0-9a-f]+: [ ]*44d3 jrcaddiusp 24
+[ ]*[0-9a-f]+: [ ]*44f3 jrcaddiusp 28
+[ ]*[0-9a-f]+: [ ]*4513 jrcaddiusp 32
+[ ]*[0-9a-f]+: [ ]*4533 jrcaddiusp 36
+[ ]*[0-9a-f]+: [ ]*4553 jrcaddiusp 40
+[ ]*[0-9a-f]+: [ ]*47d3 jrcaddiusp 120
+[ ]*[0-9a-f]+: [ ]*47f3 jrcaddiusp 124
+[ ]*[0-9a-f]+: [ ]*2060 2000 ldc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 2000 ldc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 2004 ldc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 2004 ldc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2064 2000 ldc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*2064 2000 ldc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: [ ]*2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: [ ]*2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 27ff ldc2 \$3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: [ ]*2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 2001 ldc2 \$3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8001 addiu at,a0,-32767
+[ ]*[0-9a-f]+: [ ]*2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 2000 ldc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2064 27ff ldc2 \$3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5800 ori at,at,0x5800
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 2678 ldc2 \$3,-392\(at\)
+[ ]*[0-9a-f]+: [ ]*2060 0000 lwc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 0000 lwc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 0004 lwc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 0004 lwc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2064 0000 lwc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*2064 0000 lwc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: [ ]*2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: [ ]*2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 07ff lwc2 \$3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: [ ]*2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 0001 lwc2 \$3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8001 addiu at,a0,-32767
+[ ]*[0-9a-f]+: [ ]*2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 0000 lwc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2064 07ff lwc2 \$3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5800 ori at,at,0x5800
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 0678 lwc2 \$3,-392\(at\)
+[ ]*[0-9a-f]+: [ ]*00a0 4d3c mfc2 a1,\$0
+[ ]*[0-9a-f]+: [ ]*00a1 4d3c mfc2 a1,\$1
+[ ]*[0-9a-f]+: [ ]*00a2 4d3c mfc2 a1,\$2
+[ ]*[0-9a-f]+: [ ]*00a3 4d3c mfc2 a1,\$3
+[ ]*[0-9a-f]+: [ ]*00a4 4d3c mfc2 a1,\$4
+[ ]*[0-9a-f]+: [ ]*00a5 4d3c mfc2 a1,\$5
+[ ]*[0-9a-f]+: [ ]*00a6 4d3c mfc2 a1,\$6
+[ ]*[0-9a-f]+: [ ]*00a7 4d3c mfc2 a1,\$7
+[ ]*[0-9a-f]+: [ ]*00a8 4d3c mfc2 a1,\$8
+[ ]*[0-9a-f]+: [ ]*00a9 4d3c mfc2 a1,\$9
+[ ]*[0-9a-f]+: [ ]*00aa 4d3c mfc2 a1,\$10
+[ ]*[0-9a-f]+: [ ]*00ab 4d3c mfc2 a1,\$11
+[ ]*[0-9a-f]+: [ ]*00ac 4d3c mfc2 a1,\$12
+[ ]*[0-9a-f]+: [ ]*00ad 4d3c mfc2 a1,\$13
+[ ]*[0-9a-f]+: [ ]*00ae 4d3c mfc2 a1,\$14
+[ ]*[0-9a-f]+: [ ]*00af 4d3c mfc2 a1,\$15
+[ ]*[0-9a-f]+: [ ]*00b0 4d3c mfc2 a1,\$16
+[ ]*[0-9a-f]+: [ ]*00b1 4d3c mfc2 a1,\$17
+[ ]*[0-9a-f]+: [ ]*00b2 4d3c mfc2 a1,\$18
+[ ]*[0-9a-f]+: [ ]*00b3 4d3c mfc2 a1,\$19
+[ ]*[0-9a-f]+: [ ]*00b4 4d3c mfc2 a1,\$20
+[ ]*[0-9a-f]+: [ ]*00b5 4d3c mfc2 a1,\$21
+[ ]*[0-9a-f]+: [ ]*00b6 4d3c mfc2 a1,\$22
+[ ]*[0-9a-f]+: [ ]*00b7 4d3c mfc2 a1,\$23
+[ ]*[0-9a-f]+: [ ]*00b8 4d3c mfc2 a1,\$24
+[ ]*[0-9a-f]+: [ ]*00b9 4d3c mfc2 a1,\$25
+[ ]*[0-9a-f]+: [ ]*00ba 4d3c mfc2 a1,\$26
+[ ]*[0-9a-f]+: [ ]*00bb 4d3c mfc2 a1,\$27
+[ ]*[0-9a-f]+: [ ]*00bc 4d3c mfc2 a1,\$28
+[ ]*[0-9a-f]+: [ ]*00bd 4d3c mfc2 a1,\$29
+[ ]*[0-9a-f]+: [ ]*00be 4d3c mfc2 a1,\$30
+[ ]*[0-9a-f]+: [ ]*00bf 4d3c mfc2 a1,\$31
+[ ]*[0-9a-f]+: [ ]*00a0 8d3c mfhc2 a1,\$0
+[ ]*[0-9a-f]+: [ ]*00a1 8d3c mfhc2 a1,\$1
+[ ]*[0-9a-f]+: [ ]*00a2 8d3c mfhc2 a1,\$2
+[ ]*[0-9a-f]+: [ ]*00a3 8d3c mfhc2 a1,\$3
+[ ]*[0-9a-f]+: [ ]*00a4 8d3c mfhc2 a1,\$4
+[ ]*[0-9a-f]+: [ ]*00a5 8d3c mfhc2 a1,\$5
+[ ]*[0-9a-f]+: [ ]*00a6 8d3c mfhc2 a1,\$6
+[ ]*[0-9a-f]+: [ ]*00a7 8d3c mfhc2 a1,\$7
+[ ]*[0-9a-f]+: [ ]*00a8 8d3c mfhc2 a1,\$8
+[ ]*[0-9a-f]+: [ ]*00a9 8d3c mfhc2 a1,\$9
+[ ]*[0-9a-f]+: [ ]*00aa 8d3c mfhc2 a1,\$10
+[ ]*[0-9a-f]+: [ ]*00ab 8d3c mfhc2 a1,\$11
+[ ]*[0-9a-f]+: [ ]*00ac 8d3c mfhc2 a1,\$12
+[ ]*[0-9a-f]+: [ ]*00ad 8d3c mfhc2 a1,\$13
+[ ]*[0-9a-f]+: [ ]*00ae 8d3c mfhc2 a1,\$14
+[ ]*[0-9a-f]+: [ ]*00af 8d3c mfhc2 a1,\$15
+[ ]*[0-9a-f]+: [ ]*00b0 8d3c mfhc2 a1,\$16
+[ ]*[0-9a-f]+: [ ]*00b1 8d3c mfhc2 a1,\$17
+[ ]*[0-9a-f]+: [ ]*00b2 8d3c mfhc2 a1,\$18
+[ ]*[0-9a-f]+: [ ]*00b3 8d3c mfhc2 a1,\$19
+[ ]*[0-9a-f]+: [ ]*00b4 8d3c mfhc2 a1,\$20
+[ ]*[0-9a-f]+: [ ]*00b5 8d3c mfhc2 a1,\$21
+[ ]*[0-9a-f]+: [ ]*00b6 8d3c mfhc2 a1,\$22
+[ ]*[0-9a-f]+: [ ]*00b7 8d3c mfhc2 a1,\$23
+[ ]*[0-9a-f]+: [ ]*00b8 8d3c mfhc2 a1,\$24
+[ ]*[0-9a-f]+: [ ]*00b9 8d3c mfhc2 a1,\$25
+[ ]*[0-9a-f]+: [ ]*00ba 8d3c mfhc2 a1,\$26
+[ ]*[0-9a-f]+: [ ]*00bb 8d3c mfhc2 a1,\$27
+[ ]*[0-9a-f]+: [ ]*00bc 8d3c mfhc2 a1,\$28
+[ ]*[0-9a-f]+: [ ]*00bd 8d3c mfhc2 a1,\$29
+[ ]*[0-9a-f]+: [ ]*00be 8d3c mfhc2 a1,\$30
+[ ]*[0-9a-f]+: [ ]*00bf 8d3c mfhc2 a1,\$31
+[ ]*[0-9a-f]+: [ ]*00a0 5d3c mtc2 a1,\$0
+[ ]*[0-9a-f]+: [ ]*00a1 5d3c mtc2 a1,\$1
+[ ]*[0-9a-f]+: [ ]*00a2 5d3c mtc2 a1,\$2
+[ ]*[0-9a-f]+: [ ]*00a3 5d3c mtc2 a1,\$3
+[ ]*[0-9a-f]+: [ ]*00a4 5d3c mtc2 a1,\$4
+[ ]*[0-9a-f]+: [ ]*00a5 5d3c mtc2 a1,\$5
+[ ]*[0-9a-f]+: [ ]*00a6 5d3c mtc2 a1,\$6
+[ ]*[0-9a-f]+: [ ]*00a7 5d3c mtc2 a1,\$7
+[ ]*[0-9a-f]+: [ ]*00a8 5d3c mtc2 a1,\$8
+[ ]*[0-9a-f]+: [ ]*00a9 5d3c mtc2 a1,\$9
+[ ]*[0-9a-f]+: [ ]*00aa 5d3c mtc2 a1,\$10
+[ ]*[0-9a-f]+: [ ]*00ab 5d3c mtc2 a1,\$11
+[ ]*[0-9a-f]+: [ ]*00ac 5d3c mtc2 a1,\$12
+[ ]*[0-9a-f]+: [ ]*00ad 5d3c mtc2 a1,\$13
+[ ]*[0-9a-f]+: [ ]*00ae 5d3c mtc2 a1,\$14
+[ ]*[0-9a-f]+: [ ]*00af 5d3c mtc2 a1,\$15
+[ ]*[0-9a-f]+: [ ]*00b0 5d3c mtc2 a1,\$16
+[ ]*[0-9a-f]+: [ ]*00b1 5d3c mtc2 a1,\$17
+[ ]*[0-9a-f]+: [ ]*00b2 5d3c mtc2 a1,\$18
+[ ]*[0-9a-f]+: [ ]*00b3 5d3c mtc2 a1,\$19
+[ ]*[0-9a-f]+: [ ]*00b4 5d3c mtc2 a1,\$20
+[ ]*[0-9a-f]+: [ ]*00b5 5d3c mtc2 a1,\$21
+[ ]*[0-9a-f]+: [ ]*00b6 5d3c mtc2 a1,\$22
+[ ]*[0-9a-f]+: [ ]*00b7 5d3c mtc2 a1,\$23
+[ ]*[0-9a-f]+: [ ]*00b8 5d3c mtc2 a1,\$24
+[ ]*[0-9a-f]+: [ ]*00b9 5d3c mtc2 a1,\$25
+[ ]*[0-9a-f]+: [ ]*00ba 5d3c mtc2 a1,\$26
+[ ]*[0-9a-f]+: [ ]*00bb 5d3c mtc2 a1,\$27
+[ ]*[0-9a-f]+: [ ]*00bc 5d3c mtc2 a1,\$28
+[ ]*[0-9a-f]+: [ ]*00bd 5d3c mtc2 a1,\$29
+[ ]*[0-9a-f]+: [ ]*00be 5d3c mtc2 a1,\$30
+[ ]*[0-9a-f]+: [ ]*00bf 5d3c mtc2 a1,\$31
+[ ]*[0-9a-f]+: [ ]*00a0 9d3c mthc2 a1,\$0
+[ ]*[0-9a-f]+: [ ]*00a1 9d3c mthc2 a1,\$1
+[ ]*[0-9a-f]+: [ ]*00a2 9d3c mthc2 a1,\$2
+[ ]*[0-9a-f]+: [ ]*00a3 9d3c mthc2 a1,\$3
+[ ]*[0-9a-f]+: [ ]*00a4 9d3c mthc2 a1,\$4
+[ ]*[0-9a-f]+: [ ]*00a5 9d3c mthc2 a1,\$5
+[ ]*[0-9a-f]+: [ ]*00a6 9d3c mthc2 a1,\$6
+[ ]*[0-9a-f]+: [ ]*00a7 9d3c mthc2 a1,\$7
+[ ]*[0-9a-f]+: [ ]*00a8 9d3c mthc2 a1,\$8
+[ ]*[0-9a-f]+: [ ]*00a9 9d3c mthc2 a1,\$9
+[ ]*[0-9a-f]+: [ ]*00aa 9d3c mthc2 a1,\$10
+[ ]*[0-9a-f]+: [ ]*00ab 9d3c mthc2 a1,\$11
+[ ]*[0-9a-f]+: [ ]*00ac 9d3c mthc2 a1,\$12
+[ ]*[0-9a-f]+: [ ]*00ad 9d3c mthc2 a1,\$13
+[ ]*[0-9a-f]+: [ ]*00ae 9d3c mthc2 a1,\$14
+[ ]*[0-9a-f]+: [ ]*00af 9d3c mthc2 a1,\$15
+[ ]*[0-9a-f]+: [ ]*00b0 9d3c mthc2 a1,\$16
+[ ]*[0-9a-f]+: [ ]*00b1 9d3c mthc2 a1,\$17
+[ ]*[0-9a-f]+: [ ]*00b2 9d3c mthc2 a1,\$18
+[ ]*[0-9a-f]+: [ ]*00b3 9d3c mthc2 a1,\$19
+[ ]*[0-9a-f]+: [ ]*00b4 9d3c mthc2 a1,\$20
+[ ]*[0-9a-f]+: [ ]*00b5 9d3c mthc2 a1,\$21
+[ ]*[0-9a-f]+: [ ]*00b6 9d3c mthc2 a1,\$22
+[ ]*[0-9a-f]+: [ ]*00b7 9d3c mthc2 a1,\$23
+[ ]*[0-9a-f]+: [ ]*00b8 9d3c mthc2 a1,\$24
+[ ]*[0-9a-f]+: [ ]*00b9 9d3c mthc2 a1,\$25
+[ ]*[0-9a-f]+: [ ]*00ba 9d3c mthc2 a1,\$26
+[ ]*[0-9a-f]+: [ ]*00bb 9d3c mthc2 a1,\$27
+[ ]*[0-9a-f]+: [ ]*00bc 9d3c mthc2 a1,\$28
+[ ]*[0-9a-f]+: [ ]*00bd 9d3c mthc2 a1,\$29
+[ ]*[0-9a-f]+: [ ]*00be 9d3c mthc2 a1,\$30
+[ ]*[0-9a-f]+: [ ]*00bf 9d3c mthc2 a1,\$31
+[ ]*[0-9a-f]+: [ ]*2060 a000 sdc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 a000 sdc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 a004 sdc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 a004 sdc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2064 a000 sdc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*2064 a000 sdc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: [ ]*2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: [ ]*2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 a7ff sdc2 \$3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: [ ]*2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 a001 sdc2 \$3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8001 addiu at,a0,-32767
+[ ]*[0-9a-f]+: [ ]*2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 a000 sdc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2064 a7ff sdc2 \$3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5800 ori at,at,0x5800
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 a678 sdc2 \$3,-392\(at\)
+[ ]*[0-9a-f]+: [ ]*2060 8000 swc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 8000 swc2 \$3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 8004 swc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2060 8004 swc2 \$3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2064 8000 swc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*2064 8000 swc2 \$3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*3024 7fff addiu at,a0,32767
+[ ]*[0-9a-f]+: [ ]*2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: [ ]*2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 87ff swc2 \$3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8000 addiu at,a0,-32768
+[ ]*[0-9a-f]+: [ ]*2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 8001 swc2 \$3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*3024 8001 addiu at,a0,-32767
+[ ]*[0-9a-f]+: [ ]*2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 8000 swc2 \$3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2064 87ff swc2 \$3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5800 ori at,at,0x5800
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*2061 8678 swc2 \$3,-392\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2001 6000 cache 0x0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2041 1000 lwp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2041 9000 swp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3043 0000 addiu v0,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*6042 3000 ll v0,0\(v0\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*6041 b000 sc v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2021 5000 lwm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2021 d000 swm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2201 0000 lwc2 \$16,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2201 8000 swc2 \$16,0\(at\)
+[ ]*[0-9a-f]+: [ ]*03ff db7c sdbbp 0x3ff
+[ ]*[0-9a-f]+: [ ]*03ff 937c wait 0x3ff
+[ ]*[0-9a-f]+: [ ]*03ff 8b7c syscall 0x3ff
+[ ]*[0-9a-f]+: [ ]*03ff fffa cop2 0x7fffff
[ 0-9a-f]+ <fp_test>:
-[ ]*[0-9a-f]+: 5401 037b abs.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 037b abs.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 037b abs.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5442 037b abs.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 237b abs.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 237b abs.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 237b abs.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5442 237b abs.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5441 0030 add.s \$f0,\$f1,\$f2
-[ ]*[0-9a-f]+: 57fe e830 add.s \$f29,\$f30,\$f31
-[ ]*[0-9a-f]+: 57dd e830 add.s \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 57dd e830 add.s \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 5441 0130 add.d \$f0,\$f1,\$f2
-[ ]*[0-9a-f]+: 57fe e930 add.d \$f29,\$f30,\$f31
-[ ]*[0-9a-f]+: 57dd e930 add.d \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 57dd e930 add.d \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 5401 533b ceil.l.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 533b ceil.l.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 533b ceil.l.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 133b ceil.l.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 133b ceil.l.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 133b ceil.l.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 5b3b ceil.w.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 5b3b ceil.w.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 5b3b ceil.w.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 1b3b ceil.w.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 1b3b ceil.w.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 1b3b ceil.w.s \$f2,\$f2
-[ ]*[0-9a-f]+: 54a0 103b cfc1 a1,\$0
-[ ]*[0-9a-f]+: 54a1 103b cfc1 a1,\$1
-[ ]*[0-9a-f]+: 54a2 103b cfc1 a1,\$2
-[ ]*[0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ ]*[0-9a-f]+: 54a4 103b cfc1 a1,\$4
-[ ]*[0-9a-f]+: 54a5 103b cfc1 a1,\$5
-[ ]*[0-9a-f]+: 54a6 103b cfc1 a1,\$6
-[ ]*[0-9a-f]+: 54a7 103b cfc1 a1,\$7
-[ ]*[0-9a-f]+: 54a8 103b cfc1 a1,\$8
-[ ]*[0-9a-f]+: 54a9 103b cfc1 a1,\$9
-[ ]*[0-9a-f]+: 54aa 103b cfc1 a1,\$10
-[ ]*[0-9a-f]+: 54ab 103b cfc1 a1,\$11
-[ ]*[0-9a-f]+: 54ac 103b cfc1 a1,\$12
-[ ]*[0-9a-f]+: 54ad 103b cfc1 a1,\$13
-[ ]*[0-9a-f]+: 54ae 103b cfc1 a1,\$14
-[ ]*[0-9a-f]+: 54af 103b cfc1 a1,\$15
-[ ]*[0-9a-f]+: 54b0 103b cfc1 a1,\$16
-[ ]*[0-9a-f]+: 54b1 103b cfc1 a1,\$17
-[ ]*[0-9a-f]+: 54b2 103b cfc1 a1,\$18
-[ ]*[0-9a-f]+: 54b3 103b cfc1 a1,\$19
-[ ]*[0-9a-f]+: 54b4 103b cfc1 a1,\$20
-[ ]*[0-9a-f]+: 54b5 103b cfc1 a1,\$21
-[ ]*[0-9a-f]+: 54b6 103b cfc1 a1,\$22
-[ ]*[0-9a-f]+: 54b7 103b cfc1 a1,\$23
-[ ]*[0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ ]*[0-9a-f]+: 54b9 103b cfc1 a1,\$25
-[ ]*[0-9a-f]+: 54ba 103b cfc1 a1,\$26
-[ ]*[0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ ]*[0-9a-f]+: 54bc 103b cfc1 a1,\$28
-[ ]*[0-9a-f]+: 54bd 103b cfc1 a1,\$29
-[ ]*[0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ ]*[0-9a-f]+: 54bf 103b cfc1 a1,\$31
-[ ]*[0-9a-f]+: 54a0 103b cfc1 a1,\$0
-[ ]*[0-9a-f]+: 54a1 103b cfc1 a1,\$1
-[ ]*[0-9a-f]+: 54a2 103b cfc1 a1,\$2
-[ ]*[0-9a-f]+: 54a3 103b cfc1 a1,\$3
-[ ]*[0-9a-f]+: 54a4 103b cfc1 a1,\$4
-[ ]*[0-9a-f]+: 54a5 103b cfc1 a1,\$5
-[ ]*[0-9a-f]+: 54a6 103b cfc1 a1,\$6
-[ ]*[0-9a-f]+: 54a7 103b cfc1 a1,\$7
-[ ]*[0-9a-f]+: 54a8 103b cfc1 a1,\$8
-[ ]*[0-9a-f]+: 54a9 103b cfc1 a1,\$9
-[ ]*[0-9a-f]+: 54aa 103b cfc1 a1,\$10
-[ ]*[0-9a-f]+: 54ab 103b cfc1 a1,\$11
-[ ]*[0-9a-f]+: 54ac 103b cfc1 a1,\$12
-[ ]*[0-9a-f]+: 54ad 103b cfc1 a1,\$13
-[ ]*[0-9a-f]+: 54ae 103b cfc1 a1,\$14
-[ ]*[0-9a-f]+: 54af 103b cfc1 a1,\$15
-[ ]*[0-9a-f]+: 54b0 103b cfc1 a1,\$16
-[ ]*[0-9a-f]+: 54b1 103b cfc1 a1,\$17
-[ ]*[0-9a-f]+: 54b2 103b cfc1 a1,\$18
-[ ]*[0-9a-f]+: 54b3 103b cfc1 a1,\$19
-[ ]*[0-9a-f]+: 54b4 103b cfc1 a1,\$20
-[ ]*[0-9a-f]+: 54b5 103b cfc1 a1,\$21
-[ ]*[0-9a-f]+: 54b6 103b cfc1 a1,\$22
-[ ]*[0-9a-f]+: 54b7 103b cfc1 a1,\$23
-[ ]*[0-9a-f]+: 54b8 103b cfc1 a1,\$24
-[ ]*[0-9a-f]+: 54b9 103b cfc1 a1,\$25
-[ ]*[0-9a-f]+: 54ba 103b cfc1 a1,\$26
-[ ]*[0-9a-f]+: 54bb 103b cfc1 a1,\$27
-[ ]*[0-9a-f]+: 54bc 103b cfc1 a1,\$28
-[ ]*[0-9a-f]+: 54bd 103b cfc1 a1,\$29
-[ ]*[0-9a-f]+: 54be 103b cfc1 a1,\$30
-[ ]*[0-9a-f]+: 54bf 103b cfc1 a1,\$31
-[ ]*[0-9a-f]+: 00a0 cd3c cfc2 a1,\$0
-[ ]*[0-9a-f]+: 00a1 cd3c cfc2 a1,\$1
-[ ]*[0-9a-f]+: 00a2 cd3c cfc2 a1,\$2
-[ ]*[0-9a-f]+: 00a3 cd3c cfc2 a1,\$3
-[ ]*[0-9a-f]+: 00a4 cd3c cfc2 a1,\$4
-[ ]*[0-9a-f]+: 00a5 cd3c cfc2 a1,\$5
-[ ]*[0-9a-f]+: 00a6 cd3c cfc2 a1,\$6
-[ ]*[0-9a-f]+: 00a7 cd3c cfc2 a1,\$7
-[ ]*[0-9a-f]+: 00a8 cd3c cfc2 a1,\$8
-[ ]*[0-9a-f]+: 00a9 cd3c cfc2 a1,\$9
-[ ]*[0-9a-f]+: 00aa cd3c cfc2 a1,\$10
-[ ]*[0-9a-f]+: 00ab cd3c cfc2 a1,\$11
-[ ]*[0-9a-f]+: 00ac cd3c cfc2 a1,\$12
-[ ]*[0-9a-f]+: 00ad cd3c cfc2 a1,\$13
-[ ]*[0-9a-f]+: 00ae cd3c cfc2 a1,\$14
-[ ]*[0-9a-f]+: 00af cd3c cfc2 a1,\$15
-[ ]*[0-9a-f]+: 00b0 cd3c cfc2 a1,\$16
-[ ]*[0-9a-f]+: 00b1 cd3c cfc2 a1,\$17
-[ ]*[0-9a-f]+: 00b2 cd3c cfc2 a1,\$18
-[ ]*[0-9a-f]+: 00b3 cd3c cfc2 a1,\$19
-[ ]*[0-9a-f]+: 00b4 cd3c cfc2 a1,\$20
-[ ]*[0-9a-f]+: 00b5 cd3c cfc2 a1,\$21
-[ ]*[0-9a-f]+: 00b6 cd3c cfc2 a1,\$22
-[ ]*[0-9a-f]+: 00b7 cd3c cfc2 a1,\$23
-[ ]*[0-9a-f]+: 00b8 cd3c cfc2 a1,\$24
-[ ]*[0-9a-f]+: 00b9 cd3c cfc2 a1,\$25
-[ ]*[0-9a-f]+: 00ba cd3c cfc2 a1,\$26
-[ ]*[0-9a-f]+: 00bb cd3c cfc2 a1,\$27
-[ ]*[0-9a-f]+: 00bc cd3c cfc2 a1,\$28
-[ ]*[0-9a-f]+: 00bd cd3c cfc2 a1,\$29
-[ ]*[0-9a-f]+: 00be cd3c cfc2 a1,\$30
-[ ]*[0-9a-f]+: 00bf cd3c cfc2 a1,\$31
-[ ]*[0-9a-f]+: 54a0 183b ctc1 a1,\$0
-[ ]*[0-9a-f]+: 54a1 183b ctc1 a1,\$1
-[ ]*[0-9a-f]+: 54a2 183b ctc1 a1,\$2
-[ ]*[0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ ]*[0-9a-f]+: 54a4 183b ctc1 a1,\$4
-[ ]*[0-9a-f]+: 54a5 183b ctc1 a1,\$5
-[ ]*[0-9a-f]+: 54a6 183b ctc1 a1,\$6
-[ ]*[0-9a-f]+: 54a7 183b ctc1 a1,\$7
-[ ]*[0-9a-f]+: 54a8 183b ctc1 a1,\$8
-[ ]*[0-9a-f]+: 54a9 183b ctc1 a1,\$9
-[ ]*[0-9a-f]+: 54aa 183b ctc1 a1,\$10
-[ ]*[0-9a-f]+: 54ab 183b ctc1 a1,\$11
-[ ]*[0-9a-f]+: 54ac 183b ctc1 a1,\$12
-[ ]*[0-9a-f]+: 54ad 183b ctc1 a1,\$13
-[ ]*[0-9a-f]+: 54ae 183b ctc1 a1,\$14
-[ ]*[0-9a-f]+: 54af 183b ctc1 a1,\$15
-[ ]*[0-9a-f]+: 54b0 183b ctc1 a1,\$16
-[ ]*[0-9a-f]+: 54b1 183b ctc1 a1,\$17
-[ ]*[0-9a-f]+: 54b2 183b ctc1 a1,\$18
-[ ]*[0-9a-f]+: 54b3 183b ctc1 a1,\$19
-[ ]*[0-9a-f]+: 54b4 183b ctc1 a1,\$20
-[ ]*[0-9a-f]+: 54b5 183b ctc1 a1,\$21
-[ ]*[0-9a-f]+: 54b6 183b ctc1 a1,\$22
-[ ]*[0-9a-f]+: 54b7 183b ctc1 a1,\$23
-[ ]*[0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ ]*[0-9a-f]+: 54b9 183b ctc1 a1,\$25
-[ ]*[0-9a-f]+: 54ba 183b ctc1 a1,\$26
-[ ]*[0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ ]*[0-9a-f]+: 54bc 183b ctc1 a1,\$28
-[ ]*[0-9a-f]+: 54bd 183b ctc1 a1,\$29
-[ ]*[0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ ]*[0-9a-f]+: 54bf 183b ctc1 a1,\$31
-[ ]*[0-9a-f]+: 54a0 183b ctc1 a1,\$0
-[ ]*[0-9a-f]+: 54a1 183b ctc1 a1,\$1
-[ ]*[0-9a-f]+: 54a2 183b ctc1 a1,\$2
-[ ]*[0-9a-f]+: 54a3 183b ctc1 a1,\$3
-[ ]*[0-9a-f]+: 54a4 183b ctc1 a1,\$4
-[ ]*[0-9a-f]+: 54a5 183b ctc1 a1,\$5
-[ ]*[0-9a-f]+: 54a6 183b ctc1 a1,\$6
-[ ]*[0-9a-f]+: 54a7 183b ctc1 a1,\$7
-[ ]*[0-9a-f]+: 54a8 183b ctc1 a1,\$8
-[ ]*[0-9a-f]+: 54a9 183b ctc1 a1,\$9
-[ ]*[0-9a-f]+: 54aa 183b ctc1 a1,\$10
-[ ]*[0-9a-f]+: 54ab 183b ctc1 a1,\$11
-[ ]*[0-9a-f]+: 54ac 183b ctc1 a1,\$12
-[ ]*[0-9a-f]+: 54ad 183b ctc1 a1,\$13
-[ ]*[0-9a-f]+: 54ae 183b ctc1 a1,\$14
-[ ]*[0-9a-f]+: 54af 183b ctc1 a1,\$15
-[ ]*[0-9a-f]+: 54b0 183b ctc1 a1,\$16
-[ ]*[0-9a-f]+: 54b1 183b ctc1 a1,\$17
-[ ]*[0-9a-f]+: 54b2 183b ctc1 a1,\$18
-[ ]*[0-9a-f]+: 54b3 183b ctc1 a1,\$19
-[ ]*[0-9a-f]+: 54b4 183b ctc1 a1,\$20
-[ ]*[0-9a-f]+: 54b5 183b ctc1 a1,\$21
-[ ]*[0-9a-f]+: 54b6 183b ctc1 a1,\$22
-[ ]*[0-9a-f]+: 54b7 183b ctc1 a1,\$23
-[ ]*[0-9a-f]+: 54b8 183b ctc1 a1,\$24
-[ ]*[0-9a-f]+: 54b9 183b ctc1 a1,\$25
-[ ]*[0-9a-f]+: 54ba 183b ctc1 a1,\$26
-[ ]*[0-9a-f]+: 54bb 183b ctc1 a1,\$27
-[ ]*[0-9a-f]+: 54bc 183b ctc1 a1,\$28
-[ ]*[0-9a-f]+: 54bd 183b ctc1 a1,\$29
-[ ]*[0-9a-f]+: 54be 183b ctc1 a1,\$30
-[ ]*[0-9a-f]+: 54bf 183b ctc1 a1,\$31
-[ ]*[0-9a-f]+: 00a0 dd3c ctc2 a1,\$0
-[ ]*[0-9a-f]+: 00a1 dd3c ctc2 a1,\$1
-[ ]*[0-9a-f]+: 00a2 dd3c ctc2 a1,\$2
-[ ]*[0-9a-f]+: 00a3 dd3c ctc2 a1,\$3
-[ ]*[0-9a-f]+: 00a4 dd3c ctc2 a1,\$4
-[ ]*[0-9a-f]+: 00a5 dd3c ctc2 a1,\$5
-[ ]*[0-9a-f]+: 00a6 dd3c ctc2 a1,\$6
-[ ]*[0-9a-f]+: 00a7 dd3c ctc2 a1,\$7
-[ ]*[0-9a-f]+: 00a8 dd3c ctc2 a1,\$8
-[ ]*[0-9a-f]+: 00a9 dd3c ctc2 a1,\$9
-[ ]*[0-9a-f]+: 00aa dd3c ctc2 a1,\$10
-[ ]*[0-9a-f]+: 00ab dd3c ctc2 a1,\$11
-[ ]*[0-9a-f]+: 00ac dd3c ctc2 a1,\$12
-[ ]*[0-9a-f]+: 00ad dd3c ctc2 a1,\$13
-[ ]*[0-9a-f]+: 00ae dd3c ctc2 a1,\$14
-[ ]*[0-9a-f]+: 00af dd3c ctc2 a1,\$15
-[ ]*[0-9a-f]+: 00b0 dd3c ctc2 a1,\$16
-[ ]*[0-9a-f]+: 00b1 dd3c ctc2 a1,\$17
-[ ]*[0-9a-f]+: 00b2 dd3c ctc2 a1,\$18
-[ ]*[0-9a-f]+: 00b3 dd3c ctc2 a1,\$19
-[ ]*[0-9a-f]+: 00b4 dd3c ctc2 a1,\$20
-[ ]*[0-9a-f]+: 00b5 dd3c ctc2 a1,\$21
-[ ]*[0-9a-f]+: 00b6 dd3c ctc2 a1,\$22
-[ ]*[0-9a-f]+: 00b7 dd3c ctc2 a1,\$23
-[ ]*[0-9a-f]+: 00b8 dd3c ctc2 a1,\$24
-[ ]*[0-9a-f]+: 00b9 dd3c ctc2 a1,\$25
-[ ]*[0-9a-f]+: 00ba dd3c ctc2 a1,\$26
-[ ]*[0-9a-f]+: 00bb dd3c ctc2 a1,\$27
-[ ]*[0-9a-f]+: 00bc dd3c ctc2 a1,\$28
-[ ]*[0-9a-f]+: 00bd dd3c ctc2 a1,\$29
-[ ]*[0-9a-f]+: 00be dd3c ctc2 a1,\$30
-[ ]*[0-9a-f]+: 00bf dd3c ctc2 a1,\$31
-[ ]*[0-9a-f]+: 5401 537b cvt.d.l \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 537b cvt.d.l \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 537b cvt.d.l \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 137b cvt.d.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 137b cvt.d.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 137b cvt.d.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 337b cvt.d.w \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 337b cvt.d.w \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 337b cvt.d.w \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 013b cvt.l.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 013b cvt.l.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 013b cvt.l.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 413b cvt.l.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 413b cvt.l.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 413b cvt.l.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 5b7b cvt.s.l \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 5b7b cvt.s.l \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 5b7b cvt.s.l \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 1b7b cvt.s.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 1b7b cvt.s.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 1b7b cvt.s.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 3b7b cvt.s.w \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 3b7b cvt.s.w \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 3b7b cvt.s.w \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 213b cvt.s.pl \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 213b cvt.s.pl \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 213b cvt.s.pl \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 293b cvt.s.pu \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 293b cvt.s.pu \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 293b cvt.s.pu \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 093b cvt.w.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 093b cvt.w.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 093b cvt.w.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 493b cvt.w.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 493b cvt.w.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 493b cvt.w.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5441 01f0 div.d \$f0,\$f1,\$f2
-[ ]*[0-9a-f]+: 57fe e9f0 div.d \$f29,\$f30,\$f31
-[ ]*[0-9a-f]+: 57dd e9f0 div.d \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 57dd e9f0 div.d \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 5441 00f0 div.s \$f0,\$f1,\$f2
-[ ]*[0-9a-f]+: 57fe e8f0 div.s \$f29,\$f30,\$f31
-[ ]*[0-9a-f]+: 57dd e8f0 div.s \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 57dd e8f0 div.s \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 5401 433b floor.l.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 433b floor.l.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 433b floor.l.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 033b floor.l.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 033b floor.l.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 033b floor.l.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 4b3b floor.w.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 4b3b floor.w.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 4b3b floor.w.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 0b3b floor.w.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 0b3b floor.w.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 0b3b floor.w.s \$f2,\$f2
-[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: bc61 ffff ldc1 \$f3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: bc61 0001 ldc1 \$f3,1\(at\)
-[ ]*[0-9a-f]+: bc64 8001 ldc1 \$f3,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: bc64 ffff ldc1 \$f3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: bc61 5678 ldc1 \$f3,22136\(at\)
-[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: bc61 ffff ldc1 \$f3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: bc61 0001 ldc1 \$f3,1\(at\)
-[ ]*[0-9a-f]+: bc64 8001 ldc1 \$f3,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: bc61 0000 ldc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: bc64 ffff ldc1 \$f3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: bc61 5678 ldc1 \$f3,22136\(at\)
-[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: bc60 0000 ldc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: bc60 0004 ldc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: bc64 0000 ldc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: bc64 7fff ldc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: bc64 8000 ldc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
-[ ]*[0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
-[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
-[ ]*[0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
-[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9c60 0000 lwc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9c60 0004 lwc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9c64 0000 lwc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9c64 7fff lwc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 ffff lwc1 \$f3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9c64 8000 lwc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 0001 lwc1 \$f3,1\(at\)
-[ ]*[0-9a-f]+: 9c64 8001 lwc1 \$f3,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 0000 lwc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9c64 ffff lwc1 \$f3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9c61 5678 lwc1 \$f3,22136\(at\)
-[ ]*[0-9a-f]+: 54a0 203b mfc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 203b mfc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 203b mfc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 203b mfc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 203b mfc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 203b mfc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 203b mfc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 203b mfc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 203b mfc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 203b mfc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 203b mfc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 203b mfc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 203b mfc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 203b mfc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 203b mfc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 203b mfc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 203b mfc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 203b mfc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 203b mfc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 203b mfc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 203b mfc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 203b mfc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 203b mfc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 203b mfc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 203b mfc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 203b mfc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 203b mfc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 203b mfc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 203b mfc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 203b mfc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 203b mfc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 203b mfc1 a1,\$f31
-[ ]*[0-9a-f]+: 54a0 203b mfc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 203b mfc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 203b mfc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 203b mfc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 203b mfc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 203b mfc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 203b mfc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 203b mfc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 203b mfc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 203b mfc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 203b mfc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 203b mfc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 203b mfc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 203b mfc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 203b mfc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 203b mfc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 203b mfc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 203b mfc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 203b mfc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 203b mfc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 203b mfc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 203b mfc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 203b mfc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 203b mfc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 203b mfc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 203b mfc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 203b mfc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 203b mfc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 203b mfc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 203b mfc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 203b mfc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 203b mfc1 a1,\$f31
-[ ]*[0-9a-f]+: 54a0 303b mfhc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 303b mfhc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 303b mfhc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 303b mfhc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 303b mfhc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 303b mfhc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 303b mfhc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 303b mfhc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 303b mfhc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 303b mfhc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 303b mfhc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 303b mfhc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 303b mfhc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 303b mfhc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 303b mfhc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 303b mfhc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 303b mfhc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 303b mfhc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 303b mfhc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 303b mfhc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 303b mfhc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 303b mfhc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 303b mfhc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 303b mfhc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 303b mfhc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 303b mfhc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 303b mfhc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 303b mfhc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 303b mfhc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 303b mfhc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 303b mfhc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 303b mfhc1 a1,\$f31
-[ ]*[0-9a-f]+: 54a0 303b mfhc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 303b mfhc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 303b mfhc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 303b mfhc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 303b mfhc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 303b mfhc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 303b mfhc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 303b mfhc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 303b mfhc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 303b mfhc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 303b mfhc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 303b mfhc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 303b mfhc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 303b mfhc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 303b mfhc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 303b mfhc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 303b mfhc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 303b mfhc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 303b mfhc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 303b mfhc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 303b mfhc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 303b mfhc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 303b mfhc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 303b mfhc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 303b mfhc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 303b mfhc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 303b mfhc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 303b mfhc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 303b mfhc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 303b mfhc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 303b mfhc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 303b mfhc1 a1,\$f31
-[ ]*[0-9a-f]+: 5401 207b mov.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 207b mov.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5401 007b mov.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 007b mov.s \$f30,\$f31
-[ ]*[0-9a-f]+: 54a0 283b mtc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 283b mtc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 283b mtc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 283b mtc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 283b mtc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 283b mtc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 283b mtc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 283b mtc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 283b mtc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 283b mtc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 283b mtc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 283b mtc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 283b mtc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 283b mtc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 283b mtc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 283b mtc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 283b mtc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 283b mtc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 283b mtc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 283b mtc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 283b mtc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 283b mtc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 283b mtc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 283b mtc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 283b mtc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 283b mtc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 283b mtc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 283b mtc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 283b mtc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 283b mtc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 283b mtc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 283b mtc1 a1,\$f31
-[ ]*[0-9a-f]+: 54a0 283b mtc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 283b mtc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 283b mtc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 283b mtc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 283b mtc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 283b mtc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 283b mtc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 283b mtc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 283b mtc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 283b mtc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 283b mtc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 283b mtc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 283b mtc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 283b mtc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 283b mtc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 283b mtc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 283b mtc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 283b mtc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 283b mtc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 283b mtc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 283b mtc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 283b mtc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 283b mtc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 283b mtc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 283b mtc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 283b mtc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 283b mtc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 283b mtc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 283b mtc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 283b mtc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 283b mtc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 283b mtc1 a1,\$f31
-[ ]*[0-9a-f]+: 54a0 383b mthc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 383b mthc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 383b mthc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 383b mthc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 383b mthc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 383b mthc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 383b mthc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 383b mthc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 383b mthc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 383b mthc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 383b mthc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 383b mthc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 383b mthc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 383b mthc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 383b mthc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 383b mthc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 383b mthc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 383b mthc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 383b mthc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 383b mthc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 383b mthc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 383b mthc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 383b mthc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 383b mthc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 383b mthc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 383b mthc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 383b mthc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 383b mthc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 383b mthc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 383b mthc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 383b mthc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 383b mthc1 a1,\$f31
-[ ]*[0-9a-f]+: 54a0 383b mthc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 383b mthc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 383b mthc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 383b mthc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 383b mthc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 383b mthc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 383b mthc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 383b mthc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 383b mthc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 383b mthc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 383b mthc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 383b mthc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 383b mthc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 383b mthc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 383b mthc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 383b mthc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 383b mthc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 383b mthc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 383b mthc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 383b mthc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 383b mthc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 383b mthc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 383b mthc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 383b mthc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 383b mthc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 383b mthc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 383b mthc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 383b mthc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 383b mthc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 383b mthc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 383b mthc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 383b mthc1 a1,\$f31
-[ ]*[0-9a-f]+: 5441 00b0 mul.s \$f0,\$f1,\$f2
-[ ]*[0-9a-f]+: 57fe e8b0 mul.s \$f29,\$f30,\$f31
-[ ]*[0-9a-f]+: 57dd e8b0 mul.s \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 57dd e8b0 mul.s \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 5441 01b0 mul.d \$f0,\$f1,\$f2
-[ ]*[0-9a-f]+: 57fe e9b0 mul.d \$f29,\$f30,\$f31
-[ ]*[0-9a-f]+: 57dd e9b0 mul.d \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 57dd e9b0 mul.d \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 5401 0b7b neg.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 0b7b neg.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 0b7b neg.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5442 0b7b neg.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 2b7b neg.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 2b7b neg.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 2b7b neg.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5442 2b7b neg.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 123b recip.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 123b recip.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 123b recip.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 523b recip.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 523b recip.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 523b recip.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 333b round.l.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 333b round.l.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 333b round.l.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 733b round.l.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 733b round.l.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 733b round.l.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 3b3b round.w.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 3b3b round.w.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 3b3b round.w.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 7b3b round.w.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 7b3b round.w.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 7b3b round.w.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 023b rsqrt.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 023b rsqrt.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 023b rsqrt.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 423b rsqrt.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 423b rsqrt.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 423b rsqrt.d \$f2,\$f2
-[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: b861 ffff sdc1 \$f3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: b861 0001 sdc1 \$f3,1\(at\)
-[ ]*[0-9a-f]+: b864 8001 sdc1 \$f3,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: b864 ffff sdc1 \$f3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: b861 5678 sdc1 \$f3,22136\(at\)
-[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: b861 ffff sdc1 \$f3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: b861 0001 sdc1 \$f3,1\(at\)
-[ ]*[0-9a-f]+: b864 8001 sdc1 \$f3,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: b861 0000 sdc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: b864 ffff sdc1 \$f3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: b861 5678 sdc1 \$f3,22136\(at\)
-[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: b860 0000 sdc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: b860 0004 sdc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: b864 0000 sdc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: b864 7fff sdc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: b864 8000 sdc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 5401 0a3b sqrt.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 0a3b sqrt.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 0a3b sqrt.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 4a3b sqrt.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 4a3b sqrt.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 4a3b sqrt.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5441 0070 sub.s \$f0,\$f1,\$f2
-[ ]*[0-9a-f]+: 57fe e870 sub.s \$f29,\$f30,\$f31
-[ ]*[0-9a-f]+: 57dd e870 sub.s \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 57dd e870 sub.s \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 5441 0170 sub.d \$f0,\$f1,\$f2
-[ ]*[0-9a-f]+: 57fe e970 sub.d \$f29,\$f30,\$f31
-[ ]*[0-9a-f]+: 57dd e970 sub.d \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 57dd e970 sub.d \$f29,\$f29,\$f30
-[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
-[ ]*[0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
-[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
-[ ]*[0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
-[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9860 0000 swc1 \$f3,0\(zero\)
-[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9860 0004 swc1 \$f3,4\(zero\)
-[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9864 0000 swc1 \$f3,0\(a0\)
-[ ]*[0-9a-f]+: 9864 7fff swc1 \$f3,32767\(a0\)
-[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 ffff swc1 \$f3,-1\(at\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9864 8000 swc1 \$f3,-32768\(a0\)
-[ ]*[0-9a-f]+: 1020 ffff lui at,0xffff
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 0001 swc1 \$f3,1\(at\)
-[ ]*[0-9a-f]+: 9864 8001 swc1 \$f3,-32767\(a0\)
-[ ]*[0-9a-f]+: 1020 f000 lui at,0xf000
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 0000 swc1 \$f3,0\(at\)
-[ ]*[0-9a-f]+: 9864 ffff swc1 \$f3,-1\(a0\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 0081 0950 addu at,at,a0
-[ ]*[0-9a-f]+: 9861 5678 swc1 \$f3,22136\(at\)
-[ ]*[0-9a-f]+: 5401 233b trunc.l.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 233b trunc.l.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 233b trunc.l.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 633b trunc.l.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 633b trunc.l.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 633b trunc.l.d \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 2b3b trunc.w.s \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 2b3b trunc.w.s \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 2b3b trunc.w.s \$f2,\$f2
-[ ]*[0-9a-f]+: 5401 6b3b trunc.w.d \$f0,\$f1
-[ ]*[0-9a-f]+: 57df 6b3b trunc.w.d \$f30,\$f31
-[ ]*[0-9a-f]+: 5442 6b3b trunc.w.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 037b abs.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 037b abs.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 037b abs.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5442 037b abs.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 237b abs.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 237b abs.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 237b abs.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5442 237b abs.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5441 0030 add.s \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: [ ]*57fe e830 add.s \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*57dd e830 add.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*57dd e830 add.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*5441 0130 add.d \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: [ ]*57fe e930 add.d \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*57dd e930 add.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*57dd e930 add.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*5401 533b ceil.l.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 533b ceil.l.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 533b ceil.l.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 133b ceil.l.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 133b ceil.l.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 133b ceil.l.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 5b3b ceil.w.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 5b3b ceil.w.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 5b3b ceil.w.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 1b3b ceil.w.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 1b3b ceil.w.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 1b3b ceil.w.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*54a0 103b cfc1 a1,\$0
+[ ]*[0-9a-f]+: [ ]*54a1 103b cfc1 a1,\$1
+[ ]*[0-9a-f]+: [ ]*54a2 103b cfc1 a1,\$2
+[ ]*[0-9a-f]+: [ ]*54a3 103b cfc1 a1,\$3
+[ ]*[0-9a-f]+: [ ]*54a4 103b cfc1 a1,\$4
+[ ]*[0-9a-f]+: [ ]*54a5 103b cfc1 a1,\$5
+[ ]*[0-9a-f]+: [ ]*54a6 103b cfc1 a1,\$6
+[ ]*[0-9a-f]+: [ ]*54a7 103b cfc1 a1,\$7
+[ ]*[0-9a-f]+: [ ]*54a8 103b cfc1 a1,\$8
+[ ]*[0-9a-f]+: [ ]*54a9 103b cfc1 a1,\$9
+[ ]*[0-9a-f]+: [ ]*54aa 103b cfc1 a1,\$10
+[ ]*[0-9a-f]+: [ ]*54ab 103b cfc1 a1,\$11
+[ ]*[0-9a-f]+: [ ]*54ac 103b cfc1 a1,\$12
+[ ]*[0-9a-f]+: [ ]*54ad 103b cfc1 a1,\$13
+[ ]*[0-9a-f]+: [ ]*54ae 103b cfc1 a1,\$14
+[ ]*[0-9a-f]+: [ ]*54af 103b cfc1 a1,\$15
+[ ]*[0-9a-f]+: [ ]*54b0 103b cfc1 a1,\$16
+[ ]*[0-9a-f]+: [ ]*54b1 103b cfc1 a1,\$17
+[ ]*[0-9a-f]+: [ ]*54b2 103b cfc1 a1,\$18
+[ ]*[0-9a-f]+: [ ]*54b3 103b cfc1 a1,\$19
+[ ]*[0-9a-f]+: [ ]*54b4 103b cfc1 a1,\$20
+[ ]*[0-9a-f]+: [ ]*54b5 103b cfc1 a1,\$21
+[ ]*[0-9a-f]+: [ ]*54b6 103b cfc1 a1,\$22
+[ ]*[0-9a-f]+: [ ]*54b7 103b cfc1 a1,\$23
+[ ]*[0-9a-f]+: [ ]*54b8 103b cfc1 a1,\$24
+[ ]*[0-9a-f]+: [ ]*54b9 103b cfc1 a1,\$25
+[ ]*[0-9a-f]+: [ ]*54ba 103b cfc1 a1,\$26
+[ ]*[0-9a-f]+: [ ]*54bb 103b cfc1 a1,\$27
+[ ]*[0-9a-f]+: [ ]*54bc 103b cfc1 a1,\$28
+[ ]*[0-9a-f]+: [ ]*54bd 103b cfc1 a1,\$29
+[ ]*[0-9a-f]+: [ ]*54be 103b cfc1 a1,\$30
+[ ]*[0-9a-f]+: [ ]*54bf 103b cfc1 a1,\$31
+[ ]*[0-9a-f]+: [ ]*54a0 103b cfc1 a1,\$0
+[ ]*[0-9a-f]+: [ ]*54a1 103b cfc1 a1,\$1
+[ ]*[0-9a-f]+: [ ]*54a2 103b cfc1 a1,\$2
+[ ]*[0-9a-f]+: [ ]*54a3 103b cfc1 a1,\$3
+[ ]*[0-9a-f]+: [ ]*54a4 103b cfc1 a1,\$4
+[ ]*[0-9a-f]+: [ ]*54a5 103b cfc1 a1,\$5
+[ ]*[0-9a-f]+: [ ]*54a6 103b cfc1 a1,\$6
+[ ]*[0-9a-f]+: [ ]*54a7 103b cfc1 a1,\$7
+[ ]*[0-9a-f]+: [ ]*54a8 103b cfc1 a1,\$8
+[ ]*[0-9a-f]+: [ ]*54a9 103b cfc1 a1,\$9
+[ ]*[0-9a-f]+: [ ]*54aa 103b cfc1 a1,\$10
+[ ]*[0-9a-f]+: [ ]*54ab 103b cfc1 a1,\$11
+[ ]*[0-9a-f]+: [ ]*54ac 103b cfc1 a1,\$12
+[ ]*[0-9a-f]+: [ ]*54ad 103b cfc1 a1,\$13
+[ ]*[0-9a-f]+: [ ]*54ae 103b cfc1 a1,\$14
+[ ]*[0-9a-f]+: [ ]*54af 103b cfc1 a1,\$15
+[ ]*[0-9a-f]+: [ ]*54b0 103b cfc1 a1,\$16
+[ ]*[0-9a-f]+: [ ]*54b1 103b cfc1 a1,\$17
+[ ]*[0-9a-f]+: [ ]*54b2 103b cfc1 a1,\$18
+[ ]*[0-9a-f]+: [ ]*54b3 103b cfc1 a1,\$19
+[ ]*[0-9a-f]+: [ ]*54b4 103b cfc1 a1,\$20
+[ ]*[0-9a-f]+: [ ]*54b5 103b cfc1 a1,\$21
+[ ]*[0-9a-f]+: [ ]*54b6 103b cfc1 a1,\$22
+[ ]*[0-9a-f]+: [ ]*54b7 103b cfc1 a1,\$23
+[ ]*[0-9a-f]+: [ ]*54b8 103b cfc1 a1,\$24
+[ ]*[0-9a-f]+: [ ]*54b9 103b cfc1 a1,\$25
+[ ]*[0-9a-f]+: [ ]*54ba 103b cfc1 a1,\$26
+[ ]*[0-9a-f]+: [ ]*54bb 103b cfc1 a1,\$27
+[ ]*[0-9a-f]+: [ ]*54bc 103b cfc1 a1,\$28
+[ ]*[0-9a-f]+: [ ]*54bd 103b cfc1 a1,\$29
+[ ]*[0-9a-f]+: [ ]*54be 103b cfc1 a1,\$30
+[ ]*[0-9a-f]+: [ ]*54bf 103b cfc1 a1,\$31
+[ ]*[0-9a-f]+: [ ]*00a0 cd3c cfc2 a1,\$0
+[ ]*[0-9a-f]+: [ ]*00a1 cd3c cfc2 a1,\$1
+[ ]*[0-9a-f]+: [ ]*00a2 cd3c cfc2 a1,\$2
+[ ]*[0-9a-f]+: [ ]*00a3 cd3c cfc2 a1,\$3
+[ ]*[0-9a-f]+: [ ]*00a4 cd3c cfc2 a1,\$4
+[ ]*[0-9a-f]+: [ ]*00a5 cd3c cfc2 a1,\$5
+[ ]*[0-9a-f]+: [ ]*00a6 cd3c cfc2 a1,\$6
+[ ]*[0-9a-f]+: [ ]*00a7 cd3c cfc2 a1,\$7
+[ ]*[0-9a-f]+: [ ]*00a8 cd3c cfc2 a1,\$8
+[ ]*[0-9a-f]+: [ ]*00a9 cd3c cfc2 a1,\$9
+[ ]*[0-9a-f]+: [ ]*00aa cd3c cfc2 a1,\$10
+[ ]*[0-9a-f]+: [ ]*00ab cd3c cfc2 a1,\$11
+[ ]*[0-9a-f]+: [ ]*00ac cd3c cfc2 a1,\$12
+[ ]*[0-9a-f]+: [ ]*00ad cd3c cfc2 a1,\$13
+[ ]*[0-9a-f]+: [ ]*00ae cd3c cfc2 a1,\$14
+[ ]*[0-9a-f]+: [ ]*00af cd3c cfc2 a1,\$15
+[ ]*[0-9a-f]+: [ ]*00b0 cd3c cfc2 a1,\$16
+[ ]*[0-9a-f]+: [ ]*00b1 cd3c cfc2 a1,\$17
+[ ]*[0-9a-f]+: [ ]*00b2 cd3c cfc2 a1,\$18
+[ ]*[0-9a-f]+: [ ]*00b3 cd3c cfc2 a1,\$19
+[ ]*[0-9a-f]+: [ ]*00b4 cd3c cfc2 a1,\$20
+[ ]*[0-9a-f]+: [ ]*00b5 cd3c cfc2 a1,\$21
+[ ]*[0-9a-f]+: [ ]*00b6 cd3c cfc2 a1,\$22
+[ ]*[0-9a-f]+: [ ]*00b7 cd3c cfc2 a1,\$23
+[ ]*[0-9a-f]+: [ ]*00b8 cd3c cfc2 a1,\$24
+[ ]*[0-9a-f]+: [ ]*00b9 cd3c cfc2 a1,\$25
+[ ]*[0-9a-f]+: [ ]*00ba cd3c cfc2 a1,\$26
+[ ]*[0-9a-f]+: [ ]*00bb cd3c cfc2 a1,\$27
+[ ]*[0-9a-f]+: [ ]*00bc cd3c cfc2 a1,\$28
+[ ]*[0-9a-f]+: [ ]*00bd cd3c cfc2 a1,\$29
+[ ]*[0-9a-f]+: [ ]*00be cd3c cfc2 a1,\$30
+[ ]*[0-9a-f]+: [ ]*00bf cd3c cfc2 a1,\$31
+[ ]*[0-9a-f]+: [ ]*54a0 183b ctc1 a1,\$0
+[ ]*[0-9a-f]+: [ ]*54a1 183b ctc1 a1,\$1
+[ ]*[0-9a-f]+: [ ]*54a2 183b ctc1 a1,\$2
+[ ]*[0-9a-f]+: [ ]*54a3 183b ctc1 a1,\$3
+[ ]*[0-9a-f]+: [ ]*54a4 183b ctc1 a1,\$4
+[ ]*[0-9a-f]+: [ ]*54a5 183b ctc1 a1,\$5
+[ ]*[0-9a-f]+: [ ]*54a6 183b ctc1 a1,\$6
+[ ]*[0-9a-f]+: [ ]*54a7 183b ctc1 a1,\$7
+[ ]*[0-9a-f]+: [ ]*54a8 183b ctc1 a1,\$8
+[ ]*[0-9a-f]+: [ ]*54a9 183b ctc1 a1,\$9
+[ ]*[0-9a-f]+: [ ]*54aa 183b ctc1 a1,\$10
+[ ]*[0-9a-f]+: [ ]*54ab 183b ctc1 a1,\$11
+[ ]*[0-9a-f]+: [ ]*54ac 183b ctc1 a1,\$12
+[ ]*[0-9a-f]+: [ ]*54ad 183b ctc1 a1,\$13
+[ ]*[0-9a-f]+: [ ]*54ae 183b ctc1 a1,\$14
+[ ]*[0-9a-f]+: [ ]*54af 183b ctc1 a1,\$15
+[ ]*[0-9a-f]+: [ ]*54b0 183b ctc1 a1,\$16
+[ ]*[0-9a-f]+: [ ]*54b1 183b ctc1 a1,\$17
+[ ]*[0-9a-f]+: [ ]*54b2 183b ctc1 a1,\$18
+[ ]*[0-9a-f]+: [ ]*54b3 183b ctc1 a1,\$19
+[ ]*[0-9a-f]+: [ ]*54b4 183b ctc1 a1,\$20
+[ ]*[0-9a-f]+: [ ]*54b5 183b ctc1 a1,\$21
+[ ]*[0-9a-f]+: [ ]*54b6 183b ctc1 a1,\$22
+[ ]*[0-9a-f]+: [ ]*54b7 183b ctc1 a1,\$23
+[ ]*[0-9a-f]+: [ ]*54b8 183b ctc1 a1,\$24
+[ ]*[0-9a-f]+: [ ]*54b9 183b ctc1 a1,\$25
+[ ]*[0-9a-f]+: [ ]*54ba 183b ctc1 a1,\$26
+[ ]*[0-9a-f]+: [ ]*54bb 183b ctc1 a1,\$27
+[ ]*[0-9a-f]+: [ ]*54bc 183b ctc1 a1,\$28
+[ ]*[0-9a-f]+: [ ]*54bd 183b ctc1 a1,\$29
+[ ]*[0-9a-f]+: [ ]*54be 183b ctc1 a1,\$30
+[ ]*[0-9a-f]+: [ ]*54bf 183b ctc1 a1,\$31
+[ ]*[0-9a-f]+: [ ]*54a0 183b ctc1 a1,\$0
+[ ]*[0-9a-f]+: [ ]*54a1 183b ctc1 a1,\$1
+[ ]*[0-9a-f]+: [ ]*54a2 183b ctc1 a1,\$2
+[ ]*[0-9a-f]+: [ ]*54a3 183b ctc1 a1,\$3
+[ ]*[0-9a-f]+: [ ]*54a4 183b ctc1 a1,\$4
+[ ]*[0-9a-f]+: [ ]*54a5 183b ctc1 a1,\$5
+[ ]*[0-9a-f]+: [ ]*54a6 183b ctc1 a1,\$6
+[ ]*[0-9a-f]+: [ ]*54a7 183b ctc1 a1,\$7
+[ ]*[0-9a-f]+: [ ]*54a8 183b ctc1 a1,\$8
+[ ]*[0-9a-f]+: [ ]*54a9 183b ctc1 a1,\$9
+[ ]*[0-9a-f]+: [ ]*54aa 183b ctc1 a1,\$10
+[ ]*[0-9a-f]+: [ ]*54ab 183b ctc1 a1,\$11
+[ ]*[0-9a-f]+: [ ]*54ac 183b ctc1 a1,\$12
+[ ]*[0-9a-f]+: [ ]*54ad 183b ctc1 a1,\$13
+[ ]*[0-9a-f]+: [ ]*54ae 183b ctc1 a1,\$14
+[ ]*[0-9a-f]+: [ ]*54af 183b ctc1 a1,\$15
+[ ]*[0-9a-f]+: [ ]*54b0 183b ctc1 a1,\$16
+[ ]*[0-9a-f]+: [ ]*54b1 183b ctc1 a1,\$17
+[ ]*[0-9a-f]+: [ ]*54b2 183b ctc1 a1,\$18
+[ ]*[0-9a-f]+: [ ]*54b3 183b ctc1 a1,\$19
+[ ]*[0-9a-f]+: [ ]*54b4 183b ctc1 a1,\$20
+[ ]*[0-9a-f]+: [ ]*54b5 183b ctc1 a1,\$21
+[ ]*[0-9a-f]+: [ ]*54b6 183b ctc1 a1,\$22
+[ ]*[0-9a-f]+: [ ]*54b7 183b ctc1 a1,\$23
+[ ]*[0-9a-f]+: [ ]*54b8 183b ctc1 a1,\$24
+[ ]*[0-9a-f]+: [ ]*54b9 183b ctc1 a1,\$25
+[ ]*[0-9a-f]+: [ ]*54ba 183b ctc1 a1,\$26
+[ ]*[0-9a-f]+: [ ]*54bb 183b ctc1 a1,\$27
+[ ]*[0-9a-f]+: [ ]*54bc 183b ctc1 a1,\$28
+[ ]*[0-9a-f]+: [ ]*54bd 183b ctc1 a1,\$29
+[ ]*[0-9a-f]+: [ ]*54be 183b ctc1 a1,\$30
+[ ]*[0-9a-f]+: [ ]*54bf 183b ctc1 a1,\$31
+[ ]*[0-9a-f]+: [ ]*00a0 dd3c ctc2 a1,\$0
+[ ]*[0-9a-f]+: [ ]*00a1 dd3c ctc2 a1,\$1
+[ ]*[0-9a-f]+: [ ]*00a2 dd3c ctc2 a1,\$2
+[ ]*[0-9a-f]+: [ ]*00a3 dd3c ctc2 a1,\$3
+[ ]*[0-9a-f]+: [ ]*00a4 dd3c ctc2 a1,\$4
+[ ]*[0-9a-f]+: [ ]*00a5 dd3c ctc2 a1,\$5
+[ ]*[0-9a-f]+: [ ]*00a6 dd3c ctc2 a1,\$6
+[ ]*[0-9a-f]+: [ ]*00a7 dd3c ctc2 a1,\$7
+[ ]*[0-9a-f]+: [ ]*00a8 dd3c ctc2 a1,\$8
+[ ]*[0-9a-f]+: [ ]*00a9 dd3c ctc2 a1,\$9
+[ ]*[0-9a-f]+: [ ]*00aa dd3c ctc2 a1,\$10
+[ ]*[0-9a-f]+: [ ]*00ab dd3c ctc2 a1,\$11
+[ ]*[0-9a-f]+: [ ]*00ac dd3c ctc2 a1,\$12
+[ ]*[0-9a-f]+: [ ]*00ad dd3c ctc2 a1,\$13
+[ ]*[0-9a-f]+: [ ]*00ae dd3c ctc2 a1,\$14
+[ ]*[0-9a-f]+: [ ]*00af dd3c ctc2 a1,\$15
+[ ]*[0-9a-f]+: [ ]*00b0 dd3c ctc2 a1,\$16
+[ ]*[0-9a-f]+: [ ]*00b1 dd3c ctc2 a1,\$17
+[ ]*[0-9a-f]+: [ ]*00b2 dd3c ctc2 a1,\$18
+[ ]*[0-9a-f]+: [ ]*00b3 dd3c ctc2 a1,\$19
+[ ]*[0-9a-f]+: [ ]*00b4 dd3c ctc2 a1,\$20
+[ ]*[0-9a-f]+: [ ]*00b5 dd3c ctc2 a1,\$21
+[ ]*[0-9a-f]+: [ ]*00b6 dd3c ctc2 a1,\$22
+[ ]*[0-9a-f]+: [ ]*00b7 dd3c ctc2 a1,\$23
+[ ]*[0-9a-f]+: [ ]*00b8 dd3c ctc2 a1,\$24
+[ ]*[0-9a-f]+: [ ]*00b9 dd3c ctc2 a1,\$25
+[ ]*[0-9a-f]+: [ ]*00ba dd3c ctc2 a1,\$26
+[ ]*[0-9a-f]+: [ ]*00bb dd3c ctc2 a1,\$27
+[ ]*[0-9a-f]+: [ ]*00bc dd3c ctc2 a1,\$28
+[ ]*[0-9a-f]+: [ ]*00bd dd3c ctc2 a1,\$29
+[ ]*[0-9a-f]+: [ ]*00be dd3c ctc2 a1,\$30
+[ ]*[0-9a-f]+: [ ]*00bf dd3c ctc2 a1,\$31
+[ ]*[0-9a-f]+: [ ]*5401 537b cvt.d.l \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 537b cvt.d.l \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 537b cvt.d.l \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 137b cvt.d.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 137b cvt.d.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 137b cvt.d.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 337b cvt.d.w \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 337b cvt.d.w \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 337b cvt.d.w \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 013b cvt.l.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 013b cvt.l.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 013b cvt.l.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 413b cvt.l.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 413b cvt.l.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 413b cvt.l.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 5b7b cvt.s.l \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 5b7b cvt.s.l \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 5b7b cvt.s.l \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 1b7b cvt.s.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 1b7b cvt.s.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 1b7b cvt.s.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 3b7b cvt.s.w \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 3b7b cvt.s.w \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 3b7b cvt.s.w \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 213b cvt.s.pl \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 213b cvt.s.pl \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 213b cvt.s.pl \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 293b cvt.s.pu \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 293b cvt.s.pu \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 293b cvt.s.pu \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 093b cvt.w.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 093b cvt.w.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 093b cvt.w.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 493b cvt.w.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 493b cvt.w.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 493b cvt.w.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5441 01f0 div.d \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: [ ]*57fe e9f0 div.d \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*57dd e9f0 div.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*57dd e9f0 div.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*5441 00f0 div.s \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: [ ]*57fe e8f0 div.s \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*57dd e8f0 div.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*57dd e8f0 div.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*5401 433b floor.l.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 433b floor.l.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 433b floor.l.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 033b floor.l.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 033b floor.l.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 033b floor.l.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 4b3b floor.w.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 4b3b floor.w.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 4b3b floor.w.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 0b3b floor.w.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 0b3b floor.w.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 0b3b floor.w.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*bc64 7fff ldc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*bc61 ffff ldc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*bc61 0000 ldc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*bc61 0001 ldc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*bc64 8001 ldc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*bc61 0000 ldc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*bc64 ffff ldc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*bc61 5678 ldc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*bc64 7fff ldc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*bc61 ffff ldc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*bc61 0000 ldc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*bc61 0001 ldc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*bc64 8001 ldc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*bc61 0000 ldc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*bc64 ffff ldc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*bc61 5678 ldc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc60 0000 ldc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc60 0004 ldc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*bc64 0000 ldc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*bc64 7fff ldc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*bc64 8000 ldc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9c64 7fff lwc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 ffff lwc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 0001 lwc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9c64 ffff lwc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 5678 lwc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9c64 7fff lwc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 ffff lwc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 0001 lwc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9c64 ffff lwc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 5678 lwc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c60 0000 lwc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c60 0004 lwc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9c64 0000 lwc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9c64 7fff lwc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 ffff lwc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9c64 8000 lwc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 0001 lwc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*9c64 8001 lwc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 0000 lwc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9c64 ffff lwc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9c61 5678 lwc1 \$f3,22136\(at\)
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+[ ]*[0-9a-f]+: [ ]*54a4 383b mthc1 a1,\$f4
+[ ]*[0-9a-f]+: [ ]*54a5 383b mthc1 a1,\$f5
+[ ]*[0-9a-f]+: [ ]*54a6 383b mthc1 a1,\$f6
+[ ]*[0-9a-f]+: [ ]*54a7 383b mthc1 a1,\$f7
+[ ]*[0-9a-f]+: [ ]*54a8 383b mthc1 a1,\$f8
+[ ]*[0-9a-f]+: [ ]*54a9 383b mthc1 a1,\$f9
+[ ]*[0-9a-f]+: [ ]*54aa 383b mthc1 a1,\$f10
+[ ]*[0-9a-f]+: [ ]*54ab 383b mthc1 a1,\$f11
+[ ]*[0-9a-f]+: [ ]*54ac 383b mthc1 a1,\$f12
+[ ]*[0-9a-f]+: [ ]*54ad 383b mthc1 a1,\$f13
+[ ]*[0-9a-f]+: [ ]*54ae 383b mthc1 a1,\$f14
+[ ]*[0-9a-f]+: [ ]*54af 383b mthc1 a1,\$f15
+[ ]*[0-9a-f]+: [ ]*54b0 383b mthc1 a1,\$f16
+[ ]*[0-9a-f]+: [ ]*54b1 383b mthc1 a1,\$f17
+[ ]*[0-9a-f]+: [ ]*54b2 383b mthc1 a1,\$f18
+[ ]*[0-9a-f]+: [ ]*54b3 383b mthc1 a1,\$f19
+[ ]*[0-9a-f]+: [ ]*54b4 383b mthc1 a1,\$f20
+[ ]*[0-9a-f]+: [ ]*54b5 383b mthc1 a1,\$f21
+[ ]*[0-9a-f]+: [ ]*54b6 383b mthc1 a1,\$f22
+[ ]*[0-9a-f]+: [ ]*54b7 383b mthc1 a1,\$f23
+[ ]*[0-9a-f]+: [ ]*54b8 383b mthc1 a1,\$f24
+[ ]*[0-9a-f]+: [ ]*54b9 383b mthc1 a1,\$f25
+[ ]*[0-9a-f]+: [ ]*54ba 383b mthc1 a1,\$f26
+[ ]*[0-9a-f]+: [ ]*54bb 383b mthc1 a1,\$f27
+[ ]*[0-9a-f]+: [ ]*54bc 383b mthc1 a1,\$f28
+[ ]*[0-9a-f]+: [ ]*54bd 383b mthc1 a1,\$f29
+[ ]*[0-9a-f]+: [ ]*54be 383b mthc1 a1,\$f30
+[ ]*[0-9a-f]+: [ ]*54bf 383b mthc1 a1,\$f31
+[ ]*[0-9a-f]+: [ ]*54a0 383b mthc1 a1,\$f0
+[ ]*[0-9a-f]+: [ ]*54a1 383b mthc1 a1,\$f1
+[ ]*[0-9a-f]+: [ ]*54a2 383b mthc1 a1,\$f2
+[ ]*[0-9a-f]+: [ ]*54a3 383b mthc1 a1,\$f3
+[ ]*[0-9a-f]+: [ ]*54a4 383b mthc1 a1,\$f4
+[ ]*[0-9a-f]+: [ ]*54a5 383b mthc1 a1,\$f5
+[ ]*[0-9a-f]+: [ ]*54a6 383b mthc1 a1,\$f6
+[ ]*[0-9a-f]+: [ ]*54a7 383b mthc1 a1,\$f7
+[ ]*[0-9a-f]+: [ ]*54a8 383b mthc1 a1,\$f8
+[ ]*[0-9a-f]+: [ ]*54a9 383b mthc1 a1,\$f9
+[ ]*[0-9a-f]+: [ ]*54aa 383b mthc1 a1,\$f10
+[ ]*[0-9a-f]+: [ ]*54ab 383b mthc1 a1,\$f11
+[ ]*[0-9a-f]+: [ ]*54ac 383b mthc1 a1,\$f12
+[ ]*[0-9a-f]+: [ ]*54ad 383b mthc1 a1,\$f13
+[ ]*[0-9a-f]+: [ ]*54ae 383b mthc1 a1,\$f14
+[ ]*[0-9a-f]+: [ ]*54af 383b mthc1 a1,\$f15
+[ ]*[0-9a-f]+: [ ]*54b0 383b mthc1 a1,\$f16
+[ ]*[0-9a-f]+: [ ]*54b1 383b mthc1 a1,\$f17
+[ ]*[0-9a-f]+: [ ]*54b2 383b mthc1 a1,\$f18
+[ ]*[0-9a-f]+: [ ]*54b3 383b mthc1 a1,\$f19
+[ ]*[0-9a-f]+: [ ]*54b4 383b mthc1 a1,\$f20
+[ ]*[0-9a-f]+: [ ]*54b5 383b mthc1 a1,\$f21
+[ ]*[0-9a-f]+: [ ]*54b6 383b mthc1 a1,\$f22
+[ ]*[0-9a-f]+: [ ]*54b7 383b mthc1 a1,\$f23
+[ ]*[0-9a-f]+: [ ]*54b8 383b mthc1 a1,\$f24
+[ ]*[0-9a-f]+: [ ]*54b9 383b mthc1 a1,\$f25
+[ ]*[0-9a-f]+: [ ]*54ba 383b mthc1 a1,\$f26
+[ ]*[0-9a-f]+: [ ]*54bb 383b mthc1 a1,\$f27
+[ ]*[0-9a-f]+: [ ]*54bc 383b mthc1 a1,\$f28
+[ ]*[0-9a-f]+: [ ]*54bd 383b mthc1 a1,\$f29
+[ ]*[0-9a-f]+: [ ]*54be 383b mthc1 a1,\$f30
+[ ]*[0-9a-f]+: [ ]*54bf 383b mthc1 a1,\$f31
+[ ]*[0-9a-f]+: [ ]*5441 00b0 mul.s \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: [ ]*57fe e8b0 mul.s \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*57dd e8b0 mul.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*57dd e8b0 mul.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*5441 01b0 mul.d \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: [ ]*57fe e9b0 mul.d \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*57dd e9b0 mul.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*57dd e9b0 mul.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*5401 0b7b neg.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 0b7b neg.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 0b7b neg.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5442 0b7b neg.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 2b7b neg.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 2b7b neg.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 2b7b neg.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5442 2b7b neg.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 123b recip.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 123b recip.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 123b recip.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 523b recip.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 523b recip.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 523b recip.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 333b round.l.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 333b round.l.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 333b round.l.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 733b round.l.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 733b round.l.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 733b round.l.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 3b3b round.w.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 3b3b round.w.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 3b3b round.w.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 7b3b round.w.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 7b3b round.w.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 7b3b round.w.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 023b rsqrt.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 023b rsqrt.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 023b rsqrt.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 423b rsqrt.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 423b rsqrt.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 423b rsqrt.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*b864 7fff sdc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*b864 8000 sdc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*b861 ffff sdc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*b861 0000 sdc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*b864 8000 sdc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*b861 0001 sdc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*b864 8001 sdc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*b861 0000 sdc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*b864 ffff sdc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*b861 5678 sdc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*b864 7fff sdc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*b864 8000 sdc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*b861 ffff sdc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*b861 0000 sdc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*b864 8000 sdc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*b861 0001 sdc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*b864 8001 sdc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*b861 0000 sdc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*b864 ffff sdc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*b861 5678 sdc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*b860 0000 sdc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*b860 0004 sdc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*b864 0000 sdc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*b864 7fff sdc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*b864 8000 sdc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*5401 0a3b sqrt.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 0a3b sqrt.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 0a3b sqrt.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 4a3b sqrt.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 4a3b sqrt.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 4a3b sqrt.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5441 0070 sub.s \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: [ ]*57fe e870 sub.s \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*57dd e870 sub.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*57dd e870 sub.s \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*5441 0170 sub.d \$f0,\$f1,\$f2
+[ ]*[0-9a-f]+: [ ]*57fe e970 sub.d \$f29,\$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*57dd e970 sub.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*57dd e970 sub.d \$f29,\$f29,\$f30
+[ ]*[0-9a-f]+: [ ]*9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9864 7fff swc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 ffff swc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 0001 swc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*9864 8001 swc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9864 ffff swc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 5678 swc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9864 7fff swc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 ffff swc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 0001 swc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*9864 8001 swc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9864 ffff swc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 5678 swc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9860 0000 swc1 \$f3,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9860 0004 swc1 \$f3,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9864 0000 swc1 \$f3,0\(a0\)
+[ ]*[0-9a-f]+: [ ]*9864 7fff swc1 \$f3,32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 ffff swc1 \$f3,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9864 8000 swc1 \$f3,-32768\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 ffff lui at,0xffff
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 0001 swc1 \$f3,1\(at\)
+[ ]*[0-9a-f]+: [ ]*9864 8001 swc1 \$f3,-32767\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 f000 lui at,0xf000
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 0000 swc1 \$f3,0\(at\)
+[ ]*[0-9a-f]+: [ ]*9864 ffff swc1 \$f3,-1\(a0\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*0081 0950 addu at,at,a0
+[ ]*[0-9a-f]+: [ ]*9861 5678 swc1 \$f3,22136\(at\)
+[ ]*[0-9a-f]+: [ ]*5401 233b trunc.l.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 233b trunc.l.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 233b trunc.l.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 633b trunc.l.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 633b trunc.l.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 633b trunc.l.d \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 2b3b trunc.w.s \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 2b3b trunc.w.s \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 2b3b trunc.w.s \$f2,\$f2
+[ ]*[0-9a-f]+: [ ]*5401 6b3b trunc.w.d \$f0,\$f1
+[ ]*[0-9a-f]+: [ ]*57df 6b3b trunc.w.d \$f30,\$f31
+[ ]*[0-9a-f]+: [ ]*5442 6b3b trunc.w.d \$f2,\$f2
[ 0-9a-f]+ <test_mips64>:
-[ ]*[0-9a-f]+: 0c43 move v0,v1
-[ ]*[0-9a-f]+: f463 fffe bgezc v1,31ea <.*>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_4
-[ ]*[0-9a-f]+: 5860 1190 dneg v0,v1
+[ ]*[0-9a-f]+: [ ]*0c43 move v0,v1
+[ ]*[0-9a-f]+: [ ]*f463 fffe bgezc v1,31d2 <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_4
+[ ]*[0-9a-f]+: [ ]*5860 1190 dneg v0,v1
[ 0-9a-f]+ <\.L\^\_4>:
-[ ]*[0-9a-f]+: f442 fffe bgezc v0,31f2 <\.L\^\_4>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_5
-[ ]*[0-9a-f]+: 5840 1190 dneg v0,v0
+[ ]*[0-9a-f]+: [ ]*f442 fffe bgezc v0,31da <\.L\^\_4>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_5
+[ ]*[0-9a-f]+: [ ]*5840 1190 dneg v0,v0
[ 0-9a-f]+ <\.L\^\_5>:
-[ ]*[0-9a-f]+: f442 fffe bgezc v0,31fa <\.L\^\_5>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_6
-[ ]*[0-9a-f]+: 5840 1190 dneg v0,v0
+[ ]*[0-9a-f]+: [ ]*f442 fffe bgezc v0,31e2 <\.L\^\_5>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 \.L\^\_6
+[ ]*[0-9a-f]+: [ ]*5840 1190 dneg v0,v0
[ 0-9a-f]+ <\.L\^\_6>:
-[ ]*[0-9a-f]+: 5883 1110 dadd v0,v1,a0
-[ ]*[0-9a-f]+: 5bfe e910 dadd sp,s8,ra
-[ ]*[0-9a-f]+: 5862 1110 dadd v0,v0,v1
-[ ]*[0-9a-f]+: 5862 1110 dadd v0,v0,v1
-[ ]*[0-9a-f]+: 5c43 0000 daddiu v0,v1,0
-[ ]*[0-9a-f]+: 5c43 8000 daddiu v0,v1,-32768
-[ ]*[0-9a-f]+: 5c43 7fff daddiu v0,v1,32767
-[ ]*[0-9a-f]+: 5c42 7fff daddiu v0,v0,32767
-[ ]*[0-9a-f]+: 5c42 7fff daddiu v0,v0,32767
-[ ]*[0-9a-f]+: 5883 1150 daddu v0,v1,a0
-[ ]*[0-9a-f]+: 5bfe e950 daddu sp,s8,ra
-[ ]*[0-9a-f]+: 5862 1150 daddu v0,v0,v1
-[ ]*[0-9a-f]+: 5862 1150 daddu v0,v0,v1
-[ ]*[0-9a-f]+: 5803 1150 move v0,v1
-[ ]*[0-9a-f]+: 5c43 0000 daddiu v0,v1,0
-[ ]*[0-9a-f]+: 5c43 0001 daddiu v0,v1,1
-[ ]*[0-9a-f]+: 5c43 7fff daddiu v0,v1,32767
-[ ]*[0-9a-f]+: 5c43 8000 daddiu v0,v1,-32768
-[ ]*[0-9a-f]+: 5020 ffff li at,0xffff
-[ ]*[0-9a-f]+: 5823 1150 daddu v0,v1,at
-[ ]*[0-9a-f]+: 5843 4b3c dclo v0,v1
-[ ]*[0-9a-f]+: 5862 4b3c dclo v1,v0
-[ ]*[0-9a-f]+: 5843 5b3c dclz v0,v1
-[ ]*[0-9a-f]+: 5862 5b3c dclz v1,v0
-[ ]*[0-9a-f]+: 5862 0118 ddiv zero,v0,v1
-[ ]*[0-9a-f]+: 5bfe 0118 ddiv zero,s8,ra
-[ ]*[0-9a-f]+: 5803 1118 ddiv v0,v1,zero
-[ ]*[0-9a-f]+: 5883 1118 ddiv v0,v1,a0
-[ ]*[0-9a-f]+: 5862 0198 ddivu zero,v0,v1
-[ ]*[0-9a-f]+: 5bfe 0198 ddivu zero,s8,ra
-[ ]*[0-9a-f]+: 5803 1198 ddivu v0,v1,zero
-[ ]*[0-9a-f]+: 5883 1198 ddivu v0,v1,a0
-[ ]*[0-9a-f]+: 5843 07ec dext v0,v1,0x1f,0x1
-[ ]*[0-9a-f]+: 5843 f82c dext v0,v1,0x0,0x20
-[ ]*[0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21
-[ ]*[0-9a-f]+: 5843 07e4 dext v0,v1,0x1f,0x21
-[ ]*[0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa
-[ ]*[0-9a-f]+: 5843 4854 dext v0,v1,0x21,0xa
-[ ]*[0-9a-f]+: 5843 ffcc dins v0,v1,0x1f,0x1
-[ ]*[0-9a-f]+: 5843 f80c dins v0,v1,0x0,0x20
-[ ]*[0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21
-[ ]*[0-9a-f]+: 5843 ffc4 dins v0,v1,0x1f,0x21
-[ ]*[0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa
-[ ]*[0-9a-f]+: 5843 5074 dins v0,v1,0x21,0xa
-[ ]*[0-9a-f]+: 1040 0000 lui v0,0x0
- [0-9a-f]+: R_MICROMIPS_HI16 test
-[ ]*[0-9a-f]+: 3042 0000 addiu v0,v0,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 1040 0000 lui v0,0x0
- [0-9a-f]+: R_MICROMIPS_HI16 test
-[ ]*[0-9a-f]+: 3042 0000 addiu v0,v0,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 3040 8000 li v0,-32768
-[ ]*[0-9a-f]+: 3040 7fff li v0,32767
-[ ]*[0-9a-f]+: 5040 ffff li v0,0xffff
-[ ]*[0-9a-f]+: 1040 1234 lui v0,0x1234
-[ ]*[0-9a-f]+: 5042 5678 ori v0,v0,0x5678
-[ ]*[0-9a-f]+: 5840 00fc dmfc0 v0,c0_index
-[ ]*[0-9a-f]+: 5841 00fc dmfc0 v0,c0_random
-[ ]*[0-9a-f]+: 5842 00fc dmfc0 v0,c0_entrylo0
-[ ]*[0-9a-f]+: 5843 00fc dmfc0 v0,c0_entrylo1
-[ ]*[0-9a-f]+: 5844 00fc dmfc0 v0,c0_context
-[ ]*[0-9a-f]+: 5845 00fc dmfc0 v0,c0_pagemask
-[ ]*[0-9a-f]+: 5846 00fc dmfc0 v0,c0_wired
-[ ]*[0-9a-f]+: 5847 00fc dmfc0 v0,c0_hwrena
-[ ]*[0-9a-f]+: 5848 00fc dmfc0 v0,c0_badvaddr
-[ ]*[0-9a-f]+: 5849 00fc dmfc0 v0,c0_count
-[ ]*[0-9a-f]+: 584a 00fc dmfc0 v0,c0_entryhi
-[ ]*[0-9a-f]+: 584b 00fc dmfc0 v0,c0_compare
-[ ]*[0-9a-f]+: 584c 00fc dmfc0 v0,c0_status
-[ ]*[0-9a-f]+: 584d 00fc dmfc0 v0,c0_cause
-[ ]*[0-9a-f]+: 584e 00fc dmfc0 v0,c0_epc
-[ ]*[0-9a-f]+: 584f 00fc dmfc0 v0,c0_prid
-[ ]*[0-9a-f]+: 5850 00fc dmfc0 v0,c0_config
-[ ]*[0-9a-f]+: 5851 00fc dmfc0 v0,c0_lladdr
-[ ]*[0-9a-f]+: 5852 00fc dmfc0 v0,c0_watchlo
-[ ]*[0-9a-f]+: 5853 00fc dmfc0 v0,c0_watchhi
-[ ]*[0-9a-f]+: 5854 00fc dmfc0 v0,c0_xcontext
-[ ]*[0-9a-f]+: 5855 00fc dmfc0 v0,\$21
-[ ]*[0-9a-f]+: 5856 00fc dmfc0 v0,\$22
-[ ]*[0-9a-f]+: 5857 00fc dmfc0 v0,c0_debug
-[ ]*[0-9a-f]+: 5858 00fc dmfc0 v0,c0_depc
-[ ]*[0-9a-f]+: 5859 00fc dmfc0 v0,c0_perfcnt
-[ ]*[0-9a-f]+: 585a 00fc dmfc0 v0,c0_errctl
-[ ]*[0-9a-f]+: 585b 00fc dmfc0 v0,c0_cacheerr
-[ ]*[0-9a-f]+: 585c 00fc dmfc0 v0,c0_taglo
-[ ]*[0-9a-f]+: 585d 00fc dmfc0 v0,c0_taghi
-[ ]*[0-9a-f]+: 585e 00fc dmfc0 v0,c0_errorepc
-[ ]*[0-9a-f]+: 585f 00fc dmfc0 v0,c0_desave
-[ ]*[0-9a-f]+: 5840 00fc dmfc0 v0,c0_index
-[ ]*[0-9a-f]+: 5840 08fc dmfc0 v0,c0_mvpcontrol
-[ ]*[0-9a-f]+: 5840 10fc dmfc0 v0,c0_mvpconf0
-[ ]*[0-9a-f]+: 5840 18fc dmfc0 v0,c0_mvpconf1
-[ ]*[0-9a-f]+: 5840 20fc dmfc0 v0,\$0,4
-[ ]*[0-9a-f]+: 5840 28fc dmfc0 v0,\$0,5
-[ ]*[0-9a-f]+: 5840 30fc dmfc0 v0,\$0,6
-[ ]*[0-9a-f]+: 5840 38fc dmfc0 v0,\$0,7
-[ ]*[0-9a-f]+: 5841 00fc dmfc0 v0,c0_random
-[ ]*[0-9a-f]+: 5841 08fc dmfc0 v0,c0_vpecontrol
-[ ]*[0-9a-f]+: 5841 10fc dmfc0 v0,c0_vpeconf0
-[ ]*[0-9a-f]+: 5841 18fc dmfc0 v0,c0_vpeconf1
-[ ]*[0-9a-f]+: 5841 20fc dmfc0 v0,c0_yqmask
-[ ]*[0-9a-f]+: 5841 28fc dmfc0 v0,c0_vpeschedule
-[ ]*[0-9a-f]+: 5841 30fc dmfc0 v0,c0_vpeschefback
-[ ]*[0-9a-f]+: 5841 38fc dmfc0 v0,\$1,7
-[ ]*[0-9a-f]+: 5842 00fc dmfc0 v0,c0_entrylo0
-[ ]*[0-9a-f]+: 5842 08fc dmfc0 v0,c0_tcstatus
-[ ]*[0-9a-f]+: 5842 10fc dmfc0 v0,c0_tcbind
-[ ]*[0-9a-f]+: 5842 18fc dmfc0 v0,c0_tcrestart
-[ ]*[0-9a-f]+: 5842 20fc dmfc0 v0,c0_tchalt
-[ ]*[0-9a-f]+: 5842 28fc dmfc0 v0,c0_tccontext
-[ ]*[0-9a-f]+: 5842 30fc dmfc0 v0,c0_tcschedule
-[ ]*[0-9a-f]+: 5842 38fc dmfc0 v0,c0_tcschefback
-[ ]*[0-9a-f]+: 5840 02fc dmtc0 v0,c0_index
-[ ]*[0-9a-f]+: 5841 02fc dmtc0 v0,c0_random
-[ ]*[0-9a-f]+: 5842 02fc dmtc0 v0,c0_entrylo0
-[ ]*[0-9a-f]+: 5843 02fc dmtc0 v0,c0_entrylo1
-[ ]*[0-9a-f]+: 5844 02fc dmtc0 v0,c0_context
-[ ]*[0-9a-f]+: 5845 02fc dmtc0 v0,c0_pagemask
-[ ]*[0-9a-f]+: 5846 02fc dmtc0 v0,c0_wired
-[ ]*[0-9a-f]+: 5847 02fc dmtc0 v0,c0_hwrena
-[ ]*[0-9a-f]+: 5848 02fc dmtc0 v0,c0_badvaddr
-[ ]*[0-9a-f]+: 5849 02fc dmtc0 v0,c0_count
-[ ]*[0-9a-f]+: 584a 02fc dmtc0 v0,c0_entryhi
-[ ]*[0-9a-f]+: 584b 02fc dmtc0 v0,c0_compare
-[ ]*[0-9a-f]+: 584c 02fc dmtc0 v0,c0_status
-[ ]*[0-9a-f]+: 584d 02fc dmtc0 v0,c0_cause
-[ ]*[0-9a-f]+: 584e 02fc dmtc0 v0,c0_epc
-[ ]*[0-9a-f]+: 584f 02fc dmtc0 v0,c0_prid
-[ ]*[0-9a-f]+: 5850 02fc dmtc0 v0,c0_config
-[ ]*[0-9a-f]+: 5851 02fc dmtc0 v0,c0_lladdr
-[ ]*[0-9a-f]+: 5852 02fc dmtc0 v0,c0_watchlo
-[ ]*[0-9a-f]+: 5853 02fc dmtc0 v0,c0_watchhi
-[ ]*[0-9a-f]+: 5854 02fc dmtc0 v0,c0_xcontext
-[ ]*[0-9a-f]+: 5855 02fc dmtc0 v0,\$21
-[ ]*[0-9a-f]+: 5856 02fc dmtc0 v0,\$22
-[ ]*[0-9a-f]+: 5857 02fc dmtc0 v0,c0_debug
-[ ]*[0-9a-f]+: 5858 02fc dmtc0 v0,c0_depc
-[ ]*[0-9a-f]+: 5859 02fc dmtc0 v0,c0_perfcnt
-[ ]*[0-9a-f]+: 585a 02fc dmtc0 v0,c0_errctl
-[ ]*[0-9a-f]+: 585b 02fc dmtc0 v0,c0_cacheerr
-[ ]*[0-9a-f]+: 585c 02fc dmtc0 v0,c0_taglo
-[ ]*[0-9a-f]+: 585d 02fc dmtc0 v0,c0_taghi
-[ ]*[0-9a-f]+: 585e 02fc dmtc0 v0,c0_errorepc
-[ ]*[0-9a-f]+: 585f 02fc dmtc0 v0,c0_desave
-[ ]*[0-9a-f]+: 5840 02fc dmtc0 v0,c0_index
-[ ]*[0-9a-f]+: 5840 0afc dmtc0 v0,c0_mvpcontrol
-[ ]*[0-9a-f]+: 5840 12fc dmtc0 v0,c0_mvpconf0
-[ ]*[0-9a-f]+: 5840 1afc dmtc0 v0,c0_mvpconf1
-[ ]*[0-9a-f]+: 5840 22fc dmtc0 v0,\$0,4
-[ ]*[0-9a-f]+: 5840 2afc dmtc0 v0,\$0,5
-[ ]*[0-9a-f]+: 5840 32fc dmtc0 v0,\$0,6
-[ ]*[0-9a-f]+: 5840 3afc dmtc0 v0,\$0,7
-[ ]*[0-9a-f]+: 5841 02fc dmtc0 v0,c0_random
-[ ]*[0-9a-f]+: 5841 0afc dmtc0 v0,c0_vpecontrol
-[ ]*[0-9a-f]+: 5841 12fc dmtc0 v0,c0_vpeconf0
-[ ]*[0-9a-f]+: 5841 1afc dmtc0 v0,c0_vpeconf1
-[ ]*[0-9a-f]+: 5841 22fc dmtc0 v0,c0_yqmask
-[ ]*[0-9a-f]+: 5841 2afc dmtc0 v0,c0_vpeschedule
-[ ]*[0-9a-f]+: 5841 32fc dmtc0 v0,c0_vpeschefback
-[ ]*[0-9a-f]+: 5841 3afc dmtc0 v0,\$1,7
-[ ]*[0-9a-f]+: 5842 02fc dmtc0 v0,c0_entrylo0
-[ ]*[0-9a-f]+: 5842 0afc dmtc0 v0,c0_tcstatus
-[ ]*[0-9a-f]+: 5842 12fc dmtc0 v0,c0_tcbind
-[ ]*[0-9a-f]+: 5842 1afc dmtc0 v0,c0_tcrestart
-[ ]*[0-9a-f]+: 5842 22fc dmtc0 v0,c0_tchalt
-[ ]*[0-9a-f]+: 5842 2afc dmtc0 v0,c0_tccontext
-[ ]*[0-9a-f]+: 5842 32fc dmtc0 v0,c0_tcschedule
-[ ]*[0-9a-f]+: 5842 3afc dmtc0 v0,c0_tcschefback
-[ ]*[0-9a-f]+: 54a0 243b dmfc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 243b dmfc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 243b dmfc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 243b dmfc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 243b dmfc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 243b dmfc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 243b dmfc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 243b dmfc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 243b dmfc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 243b dmfc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 243b dmfc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 243b dmfc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 243b dmfc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 243b dmfc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 243b dmfc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 243b dmfc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 243b dmfc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 243b dmfc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 243b dmfc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 243b dmfc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 243b dmfc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 243b dmfc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 243b dmfc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 243b dmfc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 243b dmfc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 243b dmfc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 243b dmfc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 243b dmfc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 243b dmfc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 243b dmfc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
-[ ]*[0-9a-f]+: 54a0 243b dmfc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 243b dmfc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 243b dmfc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 243b dmfc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 243b dmfc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 243b dmfc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 243b dmfc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 243b dmfc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 243b dmfc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 243b dmfc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 243b dmfc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 243b dmfc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 243b dmfc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 243b dmfc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 243b dmfc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 243b dmfc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 243b dmfc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 243b dmfc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 243b dmfc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 243b dmfc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 243b dmfc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 243b dmfc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 243b dmfc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 243b dmfc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 243b dmfc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 243b dmfc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 243b dmfc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 243b dmfc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 243b dmfc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 243b dmfc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 243b dmfc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 243b dmfc1 a1,\$f31
-[ ]*[0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
-[ ]*[0-9a-f]+: 54a0 2c3b dmtc1 a1,\$f0
-[ ]*[0-9a-f]+: 54a1 2c3b dmtc1 a1,\$f1
-[ ]*[0-9a-f]+: 54a2 2c3b dmtc1 a1,\$f2
-[ ]*[0-9a-f]+: 54a3 2c3b dmtc1 a1,\$f3
-[ ]*[0-9a-f]+: 54a4 2c3b dmtc1 a1,\$f4
-[ ]*[0-9a-f]+: 54a5 2c3b dmtc1 a1,\$f5
-[ ]*[0-9a-f]+: 54a6 2c3b dmtc1 a1,\$f6
-[ ]*[0-9a-f]+: 54a7 2c3b dmtc1 a1,\$f7
-[ ]*[0-9a-f]+: 54a8 2c3b dmtc1 a1,\$f8
-[ ]*[0-9a-f]+: 54a9 2c3b dmtc1 a1,\$f9
-[ ]*[0-9a-f]+: 54aa 2c3b dmtc1 a1,\$f10
-[ ]*[0-9a-f]+: 54ab 2c3b dmtc1 a1,\$f11
-[ ]*[0-9a-f]+: 54ac 2c3b dmtc1 a1,\$f12
-[ ]*[0-9a-f]+: 54ad 2c3b dmtc1 a1,\$f13
-[ ]*[0-9a-f]+: 54ae 2c3b dmtc1 a1,\$f14
-[ ]*[0-9a-f]+: 54af 2c3b dmtc1 a1,\$f15
-[ ]*[0-9a-f]+: 54b0 2c3b dmtc1 a1,\$f16
-[ ]*[0-9a-f]+: 54b1 2c3b dmtc1 a1,\$f17
-[ ]*[0-9a-f]+: 54b2 2c3b dmtc1 a1,\$f18
-[ ]*[0-9a-f]+: 54b3 2c3b dmtc1 a1,\$f19
-[ ]*[0-9a-f]+: 54b4 2c3b dmtc1 a1,\$f20
-[ ]*[0-9a-f]+: 54b5 2c3b dmtc1 a1,\$f21
-[ ]*[0-9a-f]+: 54b6 2c3b dmtc1 a1,\$f22
-[ ]*[0-9a-f]+: 54b7 2c3b dmtc1 a1,\$f23
-[ ]*[0-9a-f]+: 54b8 2c3b dmtc1 a1,\$f24
-[ ]*[0-9a-f]+: 54b9 2c3b dmtc1 a1,\$f25
-[ ]*[0-9a-f]+: 54ba 2c3b dmtc1 a1,\$f26
-[ ]*[0-9a-f]+: 54bb 2c3b dmtc1 a1,\$f27
-[ ]*[0-9a-f]+: 54bc 2c3b dmtc1 a1,\$f28
-[ ]*[0-9a-f]+: 54bd 2c3b dmtc1 a1,\$f29
-[ ]*[0-9a-f]+: 54be 2c3b dmtc1 a1,\$f30
-[ ]*[0-9a-f]+: 54bf 2c3b dmtc1 a1,\$f31
-[ ]*[0-9a-f]+: 0040 6d3c dmfc2 v0,\$0
-[ ]*[0-9a-f]+: 0041 6d3c dmfc2 v0,\$1
-[ ]*[0-9a-f]+: 0042 6d3c dmfc2 v0,\$2
-[ ]*[0-9a-f]+: 0043 6d3c dmfc2 v0,\$3
-[ ]*[0-9a-f]+: 0044 6d3c dmfc2 v0,\$4
-[ ]*[0-9a-f]+: 0045 6d3c dmfc2 v0,\$5
-[ ]*[0-9a-f]+: 0046 6d3c dmfc2 v0,\$6
-[ ]*[0-9a-f]+: 0047 6d3c dmfc2 v0,\$7
-[ ]*[0-9a-f]+: 0048 6d3c dmfc2 v0,\$8
-[ ]*[0-9a-f]+: 0049 6d3c dmfc2 v0,\$9
-[ ]*[0-9a-f]+: 004a 6d3c dmfc2 v0,\$10
-[ ]*[0-9a-f]+: 004b 6d3c dmfc2 v0,\$11
-[ ]*[0-9a-f]+: 004c 6d3c dmfc2 v0,\$12
-[ ]*[0-9a-f]+: 004d 6d3c dmfc2 v0,\$13
-[ ]*[0-9a-f]+: 004e 6d3c dmfc2 v0,\$14
-[ ]*[0-9a-f]+: 004f 6d3c dmfc2 v0,\$15
-[ ]*[0-9a-f]+: 0050 6d3c dmfc2 v0,\$16
-[ ]*[0-9a-f]+: 0051 6d3c dmfc2 v0,\$17
-[ ]*[0-9a-f]+: 0052 6d3c dmfc2 v0,\$18
-[ ]*[0-9a-f]+: 0053 6d3c dmfc2 v0,\$19
-[ ]*[0-9a-f]+: 0054 6d3c dmfc2 v0,\$20
-[ ]*[0-9a-f]+: 0055 6d3c dmfc2 v0,\$21
-[ ]*[0-9a-f]+: 0056 6d3c dmfc2 v0,\$22
-[ ]*[0-9a-f]+: 0057 6d3c dmfc2 v0,\$23
-[ ]*[0-9a-f]+: 0058 6d3c dmfc2 v0,\$24
-[ ]*[0-9a-f]+: 0059 6d3c dmfc2 v0,\$25
-[ ]*[0-9a-f]+: 005a 6d3c dmfc2 v0,\$26
-[ ]*[0-9a-f]+: 005b 6d3c dmfc2 v0,\$27
-[ ]*[0-9a-f]+: 005c 6d3c dmfc2 v0,\$28
-[ ]*[0-9a-f]+: 005d 6d3c dmfc2 v0,\$29
-[ ]*[0-9a-f]+: 005e 6d3c dmfc2 v0,\$30
-[ ]*[0-9a-f]+: 005f 6d3c dmfc2 v0,\$31
-[ ]*[0-9a-f]+: 0040 7d3c dmtc2 v0,\$0
-[ ]*[0-9a-f]+: 0041 7d3c dmtc2 v0,\$1
-[ ]*[0-9a-f]+: 0042 7d3c dmtc2 v0,\$2
-[ ]*[0-9a-f]+: 0043 7d3c dmtc2 v0,\$3
-[ ]*[0-9a-f]+: 0044 7d3c dmtc2 v0,\$4
-[ ]*[0-9a-f]+: 0045 7d3c dmtc2 v0,\$5
-[ ]*[0-9a-f]+: 0046 7d3c dmtc2 v0,\$6
-[ ]*[0-9a-f]+: 0047 7d3c dmtc2 v0,\$7
-[ ]*[0-9a-f]+: 0048 7d3c dmtc2 v0,\$8
-[ ]*[0-9a-f]+: 0049 7d3c dmtc2 v0,\$9
-[ ]*[0-9a-f]+: 004a 7d3c dmtc2 v0,\$10
-[ ]*[0-9a-f]+: 004b 7d3c dmtc2 v0,\$11
-[ ]*[0-9a-f]+: 004c 7d3c dmtc2 v0,\$12
-[ ]*[0-9a-f]+: 004d 7d3c dmtc2 v0,\$13
-[ ]*[0-9a-f]+: 004e 7d3c dmtc2 v0,\$14
-[ ]*[0-9a-f]+: 004f 7d3c dmtc2 v0,\$15
-[ ]*[0-9a-f]+: 0050 7d3c dmtc2 v0,\$16
-[ ]*[0-9a-f]+: 0051 7d3c dmtc2 v0,\$17
-[ ]*[0-9a-f]+: 0052 7d3c dmtc2 v0,\$18
-[ ]*[0-9a-f]+: 0053 7d3c dmtc2 v0,\$19
-[ ]*[0-9a-f]+: 0054 7d3c dmtc2 v0,\$20
-[ ]*[0-9a-f]+: 0055 7d3c dmtc2 v0,\$21
-[ ]*[0-9a-f]+: 0056 7d3c dmtc2 v0,\$22
-[ ]*[0-9a-f]+: 0057 7d3c dmtc2 v0,\$23
-[ ]*[0-9a-f]+: 0058 7d3c dmtc2 v0,\$24
-[ ]*[0-9a-f]+: 0059 7d3c dmtc2 v0,\$25
-[ ]*[0-9a-f]+: 005a 7d3c dmtc2 v0,\$26
-[ ]*[0-9a-f]+: 005b 7d3c dmtc2 v0,\$27
-[ ]*[0-9a-f]+: 005c 7d3c dmtc2 v0,\$28
-[ ]*[0-9a-f]+: 005d 7d3c dmtc2 v0,\$29
-[ ]*[0-9a-f]+: 005e 7d3c dmtc2 v0,\$30
-[ ]*[0-9a-f]+: 005f 7d3c dmtc2 v0,\$31
-[ ]*[0-9a-f]+: 5883 1018 dmul v0,v1,a0
-[ ]*[0-9a-f]+: 5880 11d0 dnegu v0,a0
-[ ]*[0-9a-f]+: 5862 10d0 drorv v0,v1,v0
-[ ]*[0-9a-f]+: 5880 09d0 dnegu at,a0
-[ ]*[0-9a-f]+: 5841 10d0 drorv v0,v0,at
-[ ]*[0-9a-f]+: 5843 e0c8 dror32 v0,v1,0x1c
-[ ]*[0-9a-f]+: 5864 10d0 drorv v0,v1,a0
-[ ]*[0-9a-f]+: 5843 20c0 dror v0,v1,0x4
-[ ]*[0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
-[ ]*[0-9a-f]+: 5864 10d0 drorv v0,v1,a0
-[ ]*[0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
-[ ]*[0-9a-f]+: 5880 11d0 dnegu v0,a0
-[ ]*[0-9a-f]+: 5862 10d0 drorv v0,v1,v0
-[ ]*[0-9a-f]+: 5880 09d0 dnegu at,a0
-[ ]*[0-9a-f]+: 5841 10d0 drorv v0,v0,at
-[ ]*[0-9a-f]+: 5843 e0c8 dror32 v0,v1,0x1c
-[ ]*[0-9a-f]+: 5864 10d0 drorv v0,v1,a0
-[ ]*[0-9a-f]+: 5843 20c0 dror v0,v1,0x4
-[ ]*[0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
-[ ]*[0-9a-f]+: 5864 10d0 drorv v0,v1,a0
-[ ]*[0-9a-f]+: 5843 20c8 dror32 v0,v1,0x4
-[ ]*[0-9a-f]+: 5843 7b3c dsbh v0,v1
-[ ]*[0-9a-f]+: 5842 7b3c dsbh v0,v0
-[ ]*[0-9a-f]+: 5842 7b3c dsbh v0,v0
-[ ]*[0-9a-f]+: 5843 fb3c dshd v0,v1
-[ ]*[0-9a-f]+: 5842 fb3c dshd v0,v0
-[ ]*[0-9a-f]+: 5842 fb3c dshd v0,v0
-[ ]*[0-9a-f]+: 5864 1010 dsllv v0,v1,a0
-[ ]*[0-9a-f]+: 5843 f808 dsll32 v0,v1,0x1f
-[ ]*[0-9a-f]+: 5864 1010 dsllv v0,v1,a0
-[ ]*[0-9a-f]+: 5843 f808 dsll32 v0,v1,0x1f
-[ ]*[0-9a-f]+: 5843 f800 dsll v0,v1,0x1f
-[ ]*[0-9a-f]+: 5864 1090 dsrav v0,v1,a0
-[ ]*[0-9a-f]+: 5843 2088 dsra32 v0,v1,0x4
-[ ]*[0-9a-f]+: 5864 1090 dsrav v0,v1,a0
-[ ]*[0-9a-f]+: 5843 2088 dsra32 v0,v1,0x4
-[ ]*[0-9a-f]+: 5843 2080 dsra v0,v1,0x4
-[ ]*[0-9a-f]+: 5864 1050 dsrlv v0,v1,a0
-[ ]*[0-9a-f]+: 5843 f848 dsrl32 v0,v1,0x1f
-[ ]*[0-9a-f]+: 5864 1050 dsrlv v0,v1,a0
-[ ]*[0-9a-f]+: 5843 2048 dsrl32 v0,v1,0x4
-[ ]*[0-9a-f]+: 5843 2040 dsrl v0,v1,0x4
-[ ]*[0-9a-f]+: 5883 1190 dsub v0,v1,a0
-[ ]*[0-9a-f]+: 5bfe e990 dsub sp,s8,ra
-[ ]*[0-9a-f]+: 5862 1190 dsub v0,v0,v1
-[ ]*[0-9a-f]+: 5862 1190 dsub v0,v0,v1
-[ ]*[0-9a-f]+: 5883 11d0 dsubu v0,v1,a0
-[ ]*[0-9a-f]+: 5bfe e9d0 dsubu sp,s8,ra
-[ ]*[0-9a-f]+: 5862 11d0 dsubu v0,v0,v1
-[ ]*[0-9a-f]+: 5862 11d0 dsubu v0,v0,v1
-[ ]*[0-9a-f]+: 5c43 edcc daddiu v0,v1,-4660
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5678 ori at,at,0x5678
-[ ]*[0-9a-f]+: 5823 11d0 dsubu v0,v1,at
-[ ]*[0-9a-f]+: dc40 0000 ld v0,0\(zero\)
-[ ]*[0-9a-f]+: dc40 0004 ld v0,4\(zero\)
-[ ]*[0-9a-f]+: dc40 0000 ld v0,0\(zero\)
-[ ]*[0-9a-f]+: dc40 0000 ld v0,0\(zero\)
-[ ]*[0-9a-f]+: dc40 0004 ld v0,4\(zero\)
-[ ]*[0-9a-f]+: dc43 0004 ld v0,4\(v1\)
-[ ]*[0-9a-f]+: dc43 8000 ld v0,-32768\(v1\)
-[ ]*[0-9a-f]+: dc43 7fff ld v0,32767\(v1\)
-[ ]*[0-9a-f]+: 6040 7000 lld v0,0\(zero\)
-[ ]*[0-9a-f]+: 6040 7004 lld v0,4\(zero\)
-[ ]*[0-9a-f]+: 6040 7000 lld v0,0\(zero\)
-[ ]*[0-9a-f]+: 6040 7000 lld v0,0\(zero\)
-[ ]*[0-9a-f]+: 6040 7004 lld v0,4\(zero\)
-[ ]*[0-9a-f]+: 6043 7004 lld v0,4\(v1\)
-[ ]*[0-9a-f]+: 6043 7100 lld v0,-256\(v1\)
-[ ]*[0-9a-f]+: 6043 70ff lld v0,255\(v1\)
-[ ]*[0-9a-f]+: 3043 8000 addiu v0,v1,-32768
-[ ]*[0-9a-f]+: 6042 7000 lld v0,0\(v0\)
-[ ]*[0-9a-f]+: 1040 1234 lui v0,0x1234
-[ ]*[0-9a-f]+: 5042 5600 ori v0,v0,0x5600
-[ ]*[0-9a-f]+: 0062 1150 addu v0,v0,v1
-[ ]*[0-9a-f]+: 6042 7078 lld v0,120\(v0\)
-[ ]*[0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
-[ ]*[0-9a-f]+: 6040 e004 lwu v0,4\(zero\)
-[ ]*[0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
-[ ]*[0-9a-f]+: 6040 e000 lwu v0,0\(zero\)
-[ ]*[0-9a-f]+: 6040 e004 lwu v0,4\(zero\)
-[ ]*[0-9a-f]+: 6043 e004 lwu v0,4\(v1\)
-[ ]*[0-9a-f]+: 6043 ee00 lwu v0,-512\(v1\)
-[ ]*[0-9a-f]+: 6043 e1ff lwu v0,511\(v1\)
-[ ]*[0-9a-f]+: 3043 8000 addiu v0,v1,-32768
-[ ]*[0-9a-f]+: 6042 e000 lwu v0,0\(v0\)
-[ ]*[0-9a-f]+: 1040 1234 lui v0,0x1234
-[ ]*[0-9a-f]+: 5042 5000 ori v0,v0,0x5000
-[ ]*[0-9a-f]+: 0062 1150 addu v0,v0,v1
-[ ]*[0-9a-f]+: 6042 e678 lwu v0,1656\(v0\)
-[ ]*[0-9a-f]+: 6040 f000 scd v0,0\(zero\)
-[ ]*[0-9a-f]+: 6040 f004 scd v0,4\(zero\)
-[ ]*[0-9a-f]+: 6040 f000 scd v0,0\(zero\)
-[ ]*[0-9a-f]+: 6040 f000 scd v0,0\(zero\)
-[ ]*[0-9a-f]+: 6040 f004 scd v0,4\(zero\)
-[ ]*[0-9a-f]+: 6043 f004 scd v0,4\(v1\)
-[ ]*[0-9a-f]+: 6043 f100 scd v0,-256\(v1\)
-[ ]*[0-9a-f]+: 6043 f0ff scd v0,255\(v1\)
-[ ]*[0-9a-f]+: 3023 8000 addiu at,v1,-32768
-[ ]*[0-9a-f]+: 6041 f000 scd v0,0\(at\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5600 ori at,at,0x5600
-[ ]*[0-9a-f]+: 0061 0950 addu at,at,v1
-[ ]*[0-9a-f]+: 6041 f078 scd v0,120\(at\)
-[ ]*[0-9a-f]+: d840 0000 sd v0,0\(zero\)
-[ ]*[0-9a-f]+: d840 0004 sd v0,4\(zero\)
-[ ]*[0-9a-f]+: d840 0000 sd v0,0\(zero\)
-[ ]*[0-9a-f]+: d840 0000 sd v0,0\(zero\)
-[ ]*[0-9a-f]+: d840 0004 sd v0,4\(zero\)
-[ ]*[0-9a-f]+: d843 0004 sd v0,4\(v1\)
-[ ]*[0-9a-f]+: d843 8000 sd v0,-32768\(v1\)
-[ ]*[0-9a-f]+: d843 7fff sd v0,32767\(v1\)
-[ ]*[0-9a-f]+: 2020 7000 ldm s0,0\(zero\)
-[ ]*[0-9a-f]+: 2020 7004 ldm s0,4\(zero\)
-[ ]*[0-9a-f]+: 2025 7000 ldm s0,0\(a1\)
-[ ]*[0-9a-f]+: 2025 77ff ldm s0,2047\(a1\)
-[ ]*[0-9a-f]+: 2045 77ff ldm s0-s1,2047\(a1\)
-[ ]*[0-9a-f]+: 2065 77ff ldm s0-s2,2047\(a1\)
-[ ]*[0-9a-f]+: 2085 77ff ldm s0-s3,2047\(a1\)
-[ ]*[0-9a-f]+: 20a5 77ff ldm s0-s4,2047\(a1\)
-[ ]*[0-9a-f]+: 20c5 77ff ldm s0-s5,2047\(a1\)
-[ ]*[0-9a-f]+: 20e5 77ff ldm s0-s6,2047\(a1\)
-[ ]*[0-9a-f]+: 2105 77ff ldm s0-s7,2047\(a1\)
-[ ]*[0-9a-f]+: 2125 77ff ldm s0-s7,s8,2047\(a1\)
-[ ]*[0-9a-f]+: 2205 77ff ldm ra,2047\(a1\)
-[ ]*[0-9a-f]+: 2225 7000 ldm s0,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2245 7000 ldm s0-s1,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2265 7000 ldm s0-s2,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2285 7000 ldm s0-s3,ra,0\(a1\)
-[ ]*[0-9a-f]+: 22a5 7000 ldm s0-s4,ra,0\(a1\)
-[ ]*[0-9a-f]+: 22c5 7000 ldm s0-s5,ra,0\(a1\)
-[ ]*[0-9a-f]+: 22e5 7000 ldm s0-s6,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2305 7000 ldm s0-s7,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2325 7000 ldm s0-s7,s8,ra,0\(a1\)
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 2021 7000 ldm s0,0\(at\)
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 2021 7000 ldm s0,0\(at\)
-[ ]*[0-9a-f]+: 2020 7000 ldm s0,0\(zero\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
-[ ]*[0-9a-f]+: 303d 8000 addiu at,sp,-32768
-[ ]*[0-9a-f]+: 2021 7000 ldm s0,0\(at\)
-[ ]*[0-9a-f]+: 303d 7fff addiu at,sp,32767
-[ ]*[0-9a-f]+: 2021 7000 ldm s0,0\(at\)
-[ ]*[0-9a-f]+: 203d 7000 ldm s0,0\(sp\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 03a1 0950 addu at,at,sp
-[ ]*[0-9a-f]+: 2021 7fff ldm s0,-1\(at\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5000 ori at,at,0x5000
-[ ]*[0-9a-f]+: 03a1 0950 addu at,at,sp
-[ ]*[0-9a-f]+: 2021 7678 ldm s0,1656\(at\)
-[ ]*[0-9a-f]+: 2040 4000 ldp v0,0\(zero\)
-[ ]*[0-9a-f]+: 2040 4004 ldp v0,4\(zero\)
-[ ]*[0-9a-f]+: 205d 4000 ldp v0,0\(sp\)
-[ ]*[0-9a-f]+: 205d 4000 ldp v0,0\(sp\)
-[ ]*[0-9a-f]+: 2043 4800 ldp v0,-2048\(v1\)
-[ ]*[0-9a-f]+: 2043 47ff ldp v0,2047\(v1\)
-[ ]*[0-9a-f]+: 3023 8000 addiu at,v1,-32768
-[ ]*[0-9a-f]+: 2041 4000 ldp v0,0\(at\)
-[ ]*[0-9a-f]+: 3023 7fff addiu at,v1,32767
-[ ]*[0-9a-f]+: 2041 4000 ldp v0,0\(at\)
-[ ]*[0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0061 0950 addu at,at,v1
-[ ]*[0-9a-f]+: 2041 4fff ldp v0,-1\(at\)
-[ ]*[0-9a-f]+: 3060 8000 li v1,-32768
-[ ]*[0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
-[ ]*[0-9a-f]+: 3060 7fff li v1,32767
-[ ]*[0-9a-f]+: 2043 4000 ldp v0,0\(v1\)
-[ ]*[0-9a-f]+: 1060 0001 lui v1,0x1
-[ ]*[0-9a-f]+: 2043 4fff ldp v0,-1\(v1\)
-[ ]*[0-9a-f]+: 1060 1234 lui v1,0x1234
-[ ]*[0-9a-f]+: 5063 5000 ori v1,v1,0x5000
-[ ]*[0-9a-f]+: 2043 4678 ldp v0,1656\(v1\)
-[ ]*[0-9a-f]+: 2020 f000 sdm s0,0\(zero\)
-[ ]*[0-9a-f]+: 2020 f004 sdm s0,4\(zero\)
-[ ]*[0-9a-f]+: 2025 f000 sdm s0,0\(a1\)
-[ ]*[0-9a-f]+: 2025 f7ff sdm s0,2047\(a1\)
-[ ]*[0-9a-f]+: 2045 f7ff sdm s0-s1,2047\(a1\)
-[ ]*[0-9a-f]+: 2065 f7ff sdm s0-s2,2047\(a1\)
-[ ]*[0-9a-f]+: 2085 f7ff sdm s0-s3,2047\(a1\)
-[ ]*[0-9a-f]+: 20a5 f7ff sdm s0-s4,2047\(a1\)
-[ ]*[0-9a-f]+: 20c5 f7ff sdm s0-s5,2047\(a1\)
-[ ]*[0-9a-f]+: 20e5 f7ff sdm s0-s6,2047\(a1\)
-[ ]*[0-9a-f]+: 2105 f7ff sdm s0-s7,2047\(a1\)
-[ ]*[0-9a-f]+: 2125 f7ff sdm s0-s7,s8,2047\(a1\)
-[ ]*[0-9a-f]+: 2205 f7ff sdm ra,2047\(a1\)
-[ ]*[0-9a-f]+: 2225 f000 sdm s0,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2245 f000 sdm s0-s1,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2265 f000 sdm s0-s2,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2285 f000 sdm s0-s3,ra,0\(a1\)
-[ ]*[0-9a-f]+: 22a5 f000 sdm s0-s4,ra,0\(a1\)
-[ ]*[0-9a-f]+: 22c5 f000 sdm s0-s5,ra,0\(a1\)
-[ ]*[0-9a-f]+: 22e5 f000 sdm s0-s6,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2305 f000 sdm s0-s7,ra,0\(a1\)
-[ ]*[0-9a-f]+: 2325 f000 sdm s0-s7,s8,ra,0\(a1\)
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 2021 f000 sdm s0,0\(at\)
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 2021 f000 sdm s0,0\(at\)
-[ ]*[0-9a-f]+: 2020 f000 sdm s0,0\(zero\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
-[ ]*[0-9a-f]+: 303d 8000 addiu at,sp,-32768
-[ ]*[0-9a-f]+: 2021 f000 sdm s0,0\(at\)
-[ ]*[0-9a-f]+: 303d 7fff addiu at,sp,32767
-[ ]*[0-9a-f]+: 2021 f000 sdm s0,0\(at\)
-[ ]*[0-9a-f]+: 203d f000 sdm s0,0\(sp\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 03a1 0950 addu at,at,sp
-[ ]*[0-9a-f]+: 2021 ffff sdm s0,-1\(at\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5000 ori at,at,0x5000
-[ ]*[0-9a-f]+: 03a1 0950 addu at,at,sp
-[ ]*[0-9a-f]+: 2021 f678 sdm s0,1656\(at\)
-[ ]*[0-9a-f]+: 2040 c000 sdp v0,0\(zero\)
-[ ]*[0-9a-f]+: 2040 c004 sdp v0,4\(zero\)
-[ ]*[0-9a-f]+: 205d c000 sdp v0,0\(sp\)
-[ ]*[0-9a-f]+: 205d c000 sdp v0,0\(sp\)
-[ ]*[0-9a-f]+: 2043 c800 sdp v0,-2048\(v1\)
-[ ]*[0-9a-f]+: 2043 c7ff sdp v0,2047\(v1\)
-[ ]*[0-9a-f]+: 3023 8000 addiu at,v1,-32768
-[ ]*[0-9a-f]+: 2041 c000 sdp v0,0\(at\)
-[ ]*[0-9a-f]+: 3023 7fff addiu at,v1,32767
-[ ]*[0-9a-f]+: 2041 c000 sdp v0,0\(at\)
-[ ]*[0-9a-f]+: 2043 c000 sdp v0,0\(v1\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 0061 0950 addu at,at,v1
-[ ]*[0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
-[ ]*[0-9a-f]+: 3020 8000 li at,-32768
-[ ]*[0-9a-f]+: 2041 c000 sdp v0,0\(at\)
-[ ]*[0-9a-f]+: 3020 7fff li at,32767
-[ ]*[0-9a-f]+: 2041 c000 sdp v0,0\(at\)
-[ ]*[0-9a-f]+: 1020 0001 lui at,0x1
-[ ]*[0-9a-f]+: 2041 cfff sdp v0,-1\(at\)
-[ ]*[0-9a-f]+: 1020 1234 lui at,0x1234
-[ ]*[0-9a-f]+: 5021 5000 ori at,at,0x5000
-[ ]*[0-9a-f]+: 2041 c678 sdp v0,1656\(at\)
-[ ]*[0-9a-f]+: 3203 0000 addiu s0,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 6210 7000 lld s0,0\(s0\)
-[ ]*[0-9a-f]+: 3203 0000 addiu s0,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 6210 e000 lwu s0,0\(s0\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 6201 f000 scd s0,0\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2021 7000 ldm s0,0\(at\)
-[ ]*[0-9a-f]+: 3223 0000 addiu s1,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2211 4000 ldp s0,0\(s1\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2021 f000 sdm s0,0\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2201 c000 sdp s0,0\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2201 2000 ldc2 \$16,0\(at\)
-[ ]*[0-9a-f]+: 3023 0000 addiu at,v1,0
- [0-9a-f]+: R_MICROMIPS_LO16 test
-[ ]*[0-9a-f]+: 2201 a000 sdc2 \$16,0\(at\)
+[ ]*[0-9a-f]+: [ ]*5883 1110 dadd v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*5bfe e910 dadd sp,s8,ra
+[ ]*[0-9a-f]+: [ ]*5862 1110 dadd v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*5862 1110 dadd v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*5c43 0000 daddiu v0,v1,0
+[ ]*[0-9a-f]+: [ ]*5c43 8000 daddiu v0,v1,-32768
+[ ]*[0-9a-f]+: [ ]*5c43 7fff daddiu v0,v1,32767
+[ ]*[0-9a-f]+: [ ]*5c42 7fff daddiu v0,v0,32767
+[ ]*[0-9a-f]+: [ ]*5c42 7fff daddiu v0,v0,32767
+[ ]*[0-9a-f]+: [ ]*5883 1150 daddu v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*5bfe e950 daddu sp,s8,ra
+[ ]*[0-9a-f]+: [ ]*5862 1150 daddu v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*5862 1150 daddu v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*5803 1150 move v0,v1
+[ ]*[0-9a-f]+: [ ]*5c43 0000 daddiu v0,v1,0
+[ ]*[0-9a-f]+: [ ]*5c43 0001 daddiu v0,v1,1
+[ ]*[0-9a-f]+: [ ]*5c43 7fff daddiu v0,v1,32767
+[ ]*[0-9a-f]+: [ ]*5c43 8000 daddiu v0,v1,-32768
+[ ]*[0-9a-f]+: [ ]*5020 ffff li at,0xffff
+[ ]*[0-9a-f]+: [ ]*5823 1150 daddu v0,v1,at
+[ ]*[0-9a-f]+: [ ]*5843 4b3c dclo v0,v1
+[ ]*[0-9a-f]+: [ ]*5862 4b3c dclo v1,v0
+[ ]*[0-9a-f]+: [ ]*5843 5b3c dclz v0,v1
+[ ]*[0-9a-f]+: [ ]*5862 5b3c dclz v1,v0
+[ ]*[0-9a-f]+: [ ]*5862 0118 ddiv zero,v0,v1
+[ ]*[0-9a-f]+: [ ]*5bfe 0118 ddiv zero,s8,ra
+[ ]*[0-9a-f]+: [ ]*5803 1118 ddiv v0,v1,zero
+[ ]*[0-9a-f]+: [ ]*5883 1118 ddiv v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*5862 0198 ddivu zero,v0,v1
+[ ]*[0-9a-f]+: [ ]*5bfe 0198 ddivu zero,s8,ra
+[ ]*[0-9a-f]+: [ ]*5803 1198 ddivu v0,v1,zero
+[ ]*[0-9a-f]+: [ ]*5883 1198 ddivu v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*5843 07ec dext v0,v1,0x1f,0x1
+[ ]*[0-9a-f]+: [ ]*5843 f82c dext v0,v1,0x0,0x20
+[ ]*[0-9a-f]+: [ ]*5843 07e4 dext v0,v1,0x1f,0x21
+[ ]*[0-9a-f]+: [ ]*5843 07e4 dext v0,v1,0x1f,0x21
+[ ]*[0-9a-f]+: [ ]*5843 4854 dext v0,v1,0x21,0xa
+[ ]*[0-9a-f]+: [ ]*5843 4854 dext v0,v1,0x21,0xa
+[ ]*[0-9a-f]+: [ ]*5843 ffcc dins v0,v1,0x1f,0x1
+[ ]*[0-9a-f]+: [ ]*5843 f80c dins v0,v1,0x0,0x20
+[ ]*[0-9a-f]+: [ ]*5843 ffc4 dins v0,v1,0x1f,0x21
+[ ]*[0-9a-f]+: [ ]*5843 ffc4 dins v0,v1,0x1f,0x21
+[ ]*[0-9a-f]+: [ ]*5843 5074 dins v0,v1,0x21,0xa
+[ ]*[0-9a-f]+: [ ]*5843 5074 dins v0,v1,0x21,0xa
+[ ]*[0-9a-f]+: [ ]*1040 0000 lui v0,0x0
+ [ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ ]*[0-9a-f]+: [ ]*3042 0000 addiu v0,v0,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*1040 0000 lui v0,0x0
+ [ ]*[0-9a-f]+: R_MICROMIPS_HI16 test
+[ ]*[0-9a-f]+: [ ]*3042 0000 addiu v0,v0,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*3040 8000 li v0,-32768
+[ ]*[0-9a-f]+: [ ]*3040 7fff li v0,32767
+[ ]*[0-9a-f]+: [ ]*5040 ffff li v0,0xffff
+[ ]*[0-9a-f]+: [ ]*1040 1234 lui v0,0x1234
+[ ]*[0-9a-f]+: [ ]*5042 5678 ori v0,v0,0x5678
+[ ]*[0-9a-f]+: [ ]*5840 00fc dmfc0 v0,c0_index
+[ ]*[0-9a-f]+: [ ]*5841 00fc dmfc0 v0,c0_random
+[ ]*[0-9a-f]+: [ ]*5842 00fc dmfc0 v0,c0_entrylo0
+[ ]*[0-9a-f]+: [ ]*5843 00fc dmfc0 v0,c0_entrylo1
+[ ]*[0-9a-f]+: [ ]*5844 00fc dmfc0 v0,c0_context
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+[ ]*[0-9a-f]+: [ ]*5846 00fc dmfc0 v0,c0_wired
+[ ]*[0-9a-f]+: [ ]*5847 00fc dmfc0 v0,c0_hwrena
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+[ ]*[0-9a-f]+: [ ]*584b 00fc dmfc0 v0,c0_compare
+[ ]*[0-9a-f]+: [ ]*584c 00fc dmfc0 v0,c0_status
+[ ]*[0-9a-f]+: [ ]*584d 00fc dmfc0 v0,c0_cause
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+[ ]*[0-9a-f]+: [ ]*584f 00fc dmfc0 v0,c0_prid
+[ ]*[0-9a-f]+: [ ]*5850 00fc dmfc0 v0,c0_config
+[ ]*[0-9a-f]+: [ ]*5851 00fc dmfc0 v0,c0_lladdr
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+[ ]*[0-9a-f]+: [ ]*5854 00fc dmfc0 v0,c0_xcontext
+[ ]*[0-9a-f]+: [ ]*5855 00fc dmfc0 v0,\$21
+[ ]*[0-9a-f]+: [ ]*5856 00fc dmfc0 v0,\$22
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+[ ]*[0-9a-f]+: [ ]*585a 00fc dmfc0 v0,c0_errctl
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+[ ]*[0-9a-f]+: [ ]*5840 20fc dmfc0 v0,\$0,4
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+[ ]*[0-9a-f]+: [ ]*5840 30fc dmfc0 v0,\$0,6
+[ ]*[0-9a-f]+: [ ]*5840 38fc dmfc0 v0,\$0,7
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+[ ]*[0-9a-f]+: [ ]*5841 38fc dmfc0 v0,\$1,7
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+[ ]*[0-9a-f]+: [ ]*5842 28fc dmfc0 v0,c0_tccontext
+[ ]*[0-9a-f]+: [ ]*5842 30fc dmfc0 v0,c0_tcschedule
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+[ ]*[0-9a-f]+: [ ]*5883 1190 dsub v0,v1,a0
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+[ ]*[0-9a-f]+: [ ]*5862 1190 dsub v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*5862 1190 dsub v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*5883 11d0 dsubu v0,v1,a0
+[ ]*[0-9a-f]+: [ ]*5bfe e9d0 dsubu sp,s8,ra
+[ ]*[0-9a-f]+: [ ]*5862 11d0 dsubu v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*5862 11d0 dsubu v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*5c43 edcc daddiu v0,v1,-4660
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5678 ori at,at,0x5678
+[ ]*[0-9a-f]+: [ ]*5823 11d0 dsubu v0,v1,at
+[ ]*[0-9a-f]+: [ ]*dc40 0000 ld v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*dc40 0004 ld v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*dc40 0000 ld v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*dc40 0000 ld v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*dc40 0004 ld v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*dc43 0004 ld v0,4\(v1\)
+[ ]*[0-9a-f]+: [ ]*dc43 8000 ld v0,-32768\(v1\)
+[ ]*[0-9a-f]+: [ ]*dc43 7fff ld v0,32767\(v1\)
+[ ]*[0-9a-f]+: [ ]*6040 7000 lld v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 7004 lld v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 7000 lld v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 7000 lld v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 7004 lld v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*6043 7004 lld v0,4\(v1\)
+[ ]*[0-9a-f]+: [ ]*6043 7100 lld v0,-256\(v1\)
+[ ]*[0-9a-f]+: [ ]*6043 70ff lld v0,255\(v1\)
+[ ]*[0-9a-f]+: [ ]*3043 8000 addiu v0,v1,-32768
+[ ]*[0-9a-f]+: [ ]*6042 7000 lld v0,0\(v0\)
+[ ]*[0-9a-f]+: [ ]*1040 1234 lui v0,0x1234
+[ ]*[0-9a-f]+: [ ]*5042 5600 ori v0,v0,0x5600
+[ ]*[0-9a-f]+: [ ]*0062 1150 addu v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*6042 7078 lld v0,120\(v0\)
+[ ]*[0-9a-f]+: [ ]*6040 e000 lwu v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 e004 lwu v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 e000 lwu v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 e000 lwu v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 e004 lwu v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*6043 e004 lwu v0,4\(v1\)
+[ ]*[0-9a-f]+: [ ]*6043 ee00 lwu v0,-512\(v1\)
+[ ]*[0-9a-f]+: [ ]*6043 e1ff lwu v0,511\(v1\)
+[ ]*[0-9a-f]+: [ ]*3043 8000 addiu v0,v1,-32768
+[ ]*[0-9a-f]+: [ ]*6042 e000 lwu v0,0\(v0\)
+[ ]*[0-9a-f]+: [ ]*1040 1234 lui v0,0x1234
+[ ]*[0-9a-f]+: [ ]*5042 5000 ori v0,v0,0x5000
+[ ]*[0-9a-f]+: [ ]*0062 1150 addu v0,v0,v1
+[ ]*[0-9a-f]+: [ ]*6042 e678 lwu v0,1656\(v0\)
+[ ]*[0-9a-f]+: [ ]*6040 f000 scd v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 f004 scd v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 f000 scd v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 f000 scd v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*6040 f004 scd v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*6043 f004 scd v0,4\(v1\)
+[ ]*[0-9a-f]+: [ ]*6043 f100 scd v0,-256\(v1\)
+[ ]*[0-9a-f]+: [ ]*6043 f0ff scd v0,255\(v1\)
+[ ]*[0-9a-f]+: [ ]*3023 8000 addiu at,v1,-32768
+[ ]*[0-9a-f]+: [ ]*6041 f000 scd v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5600 ori at,at,0x5600
+[ ]*[0-9a-f]+: [ ]*0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: [ ]*6041 f078 scd v0,120\(at\)
+[ ]*[0-9a-f]+: [ ]*d840 0000 sd v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*d840 0004 sd v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*d840 0000 sd v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*d840 0000 sd v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*d840 0004 sd v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*d843 0004 sd v0,4\(v1\)
+[ ]*[0-9a-f]+: [ ]*d843 8000 sd v0,-32768\(v1\)
+[ ]*[0-9a-f]+: [ ]*d843 7fff sd v0,32767\(v1\)
+[ ]*[0-9a-f]+: [ ]*2020 7000 ldm s0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2020 7004 ldm s0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2025 7000 ldm s0,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2025 77ff ldm s0,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2045 77ff ldm s0-s1,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2065 77ff ldm s0-s2,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2085 77ff ldm s0-s3,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*20a5 77ff ldm s0-s4,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*20c5 77ff ldm s0-s5,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*20e5 77ff ldm s0-s6,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2105 77ff ldm s0-s7,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2125 77ff ldm s0-s7,s8,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2205 77ff ldm ra,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2225 7000 ldm s0,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2245 7000 ldm s0-s1,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2265 7000 ldm s0-s2,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2285 7000 ldm s0-s3,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*22a5 7000 ldm s0-s4,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*22c5 7000 ldm s0-s5,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*22e5 7000 ldm s0-s6,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2305 7000 ldm s0-s7,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2325 7000 ldm s0-s7,s8,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*2021 7000 ldm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*2021 7000 ldm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2020 7000 ldm s0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*2021 7fff ldm s0,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*303d 8000 addiu at,sp,-32768
+[ ]*[0-9a-f]+: [ ]*2021 7000 ldm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*303d 7fff addiu at,sp,32767
+[ ]*[0-9a-f]+: [ ]*2021 7000 ldm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*203d 7000 ldm s0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*03a1 0950 addu at,at,sp
+[ ]*[0-9a-f]+: [ ]*2021 7fff ldm s0,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5000 ori at,at,0x5000
+[ ]*[0-9a-f]+: [ ]*03a1 0950 addu at,at,sp
+[ ]*[0-9a-f]+: [ ]*2021 7678 ldm s0,1656\(at\)
+[ ]*[0-9a-f]+: [ ]*2040 4000 ldp v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2040 4004 ldp v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*205d 4000 ldp v0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*205d 4000 ldp v0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*2043 4800 ldp v0,-2048\(v1\)
+[ ]*[0-9a-f]+: [ ]*2043 47ff ldp v0,2047\(v1\)
+[ ]*[0-9a-f]+: [ ]*3023 8000 addiu at,v1,-32768
+[ ]*[0-9a-f]+: [ ]*2041 4000 ldp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 7fff addiu at,v1,32767
+[ ]*[0-9a-f]+: [ ]*2041 4000 ldp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2043 4000 ldp v0,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: [ ]*2041 4fff ldp v0,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*3060 8000 li v1,-32768
+[ ]*[0-9a-f]+: [ ]*2043 4000 ldp v0,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*3060 7fff li v1,32767
+[ ]*[0-9a-f]+: [ ]*2043 4000 ldp v0,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 0001 lui v1,0x1
+[ ]*[0-9a-f]+: [ ]*2043 4fff ldp v0,-1\(v1\)
+[ ]*[0-9a-f]+: [ ]*1060 1234 lui v1,0x1234
+[ ]*[0-9a-f]+: [ ]*5063 5000 ori v1,v1,0x5000
+[ ]*[0-9a-f]+: [ ]*2043 4678 ldp v0,1656\(v1\)
+[ ]*[0-9a-f]+: [ ]*2020 f000 sdm s0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2020 f004 sdm s0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*2025 f000 sdm s0,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2025 f7ff sdm s0,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2045 f7ff sdm s0-s1,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2065 f7ff sdm s0-s2,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2085 f7ff sdm s0-s3,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*20a5 f7ff sdm s0-s4,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*20c5 f7ff sdm s0-s5,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*20e5 f7ff sdm s0-s6,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2105 f7ff sdm s0-s7,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2125 f7ff sdm s0-s7,s8,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2205 f7ff sdm ra,2047\(a1\)
+[ ]*[0-9a-f]+: [ ]*2225 f000 sdm s0,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2245 f000 sdm s0-s1,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2265 f000 sdm s0-s2,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2285 f000 sdm s0-s3,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*22a5 f000 sdm s0-s4,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*22c5 f000 sdm s0-s5,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*22e5 f000 sdm s0-s6,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2305 f000 sdm s0-s7,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*2325 f000 sdm s0-s7,s8,ra,0\(a1\)
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*2021 f000 sdm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*2021 f000 sdm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2020 f000 sdm s0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*2021 ffff sdm s0,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*303d 8000 addiu at,sp,-32768
+[ ]*[0-9a-f]+: [ ]*2021 f000 sdm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*303d 7fff addiu at,sp,32767
+[ ]*[0-9a-f]+: [ ]*2021 f000 sdm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*203d f000 sdm s0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*03a1 0950 addu at,at,sp
+[ ]*[0-9a-f]+: [ ]*2021 ffff sdm s0,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5000 ori at,at,0x5000
+[ ]*[0-9a-f]+: [ ]*03a1 0950 addu at,at,sp
+[ ]*[0-9a-f]+: [ ]*2021 f678 sdm s0,1656\(at\)
+[ ]*[0-9a-f]+: [ ]*2040 c000 sdp v0,0\(zero\)
+[ ]*[0-9a-f]+: [ ]*2040 c004 sdp v0,4\(zero\)
+[ ]*[0-9a-f]+: [ ]*205d c000 sdp v0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*205d c000 sdp v0,0\(sp\)
+[ ]*[0-9a-f]+: [ ]*2043 c800 sdp v0,-2048\(v1\)
+[ ]*[0-9a-f]+: [ ]*2043 c7ff sdp v0,2047\(v1\)
+[ ]*[0-9a-f]+: [ ]*3023 8000 addiu at,v1,-32768
+[ ]*[0-9a-f]+: [ ]*2041 c000 sdp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 7fff addiu at,v1,32767
+[ ]*[0-9a-f]+: [ ]*2041 c000 sdp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*2043 c000 sdp v0,0\(v1\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*0061 0950 addu at,at,v1
+[ ]*[0-9a-f]+: [ ]*2041 cfff sdp v0,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 8000 li at,-32768
+[ ]*[0-9a-f]+: [ ]*2041 c000 sdp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3020 7fff li at,32767
+[ ]*[0-9a-f]+: [ ]*2041 c000 sdp v0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 0001 lui at,0x1
+[ ]*[0-9a-f]+: [ ]*2041 cfff sdp v0,-1\(at\)
+[ ]*[0-9a-f]+: [ ]*1020 1234 lui at,0x1234
+[ ]*[0-9a-f]+: [ ]*5021 5000 ori at,at,0x5000
+[ ]*[0-9a-f]+: [ ]*2041 c678 sdp v0,1656\(at\)
+[ ]*[0-9a-f]+: [ ]*3203 0000 addiu s0,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*6210 7000 lld s0,0\(s0\)
+[ ]*[0-9a-f]+: [ ]*3203 0000 addiu s0,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*6210 e000 lwu s0,0\(s0\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*6201 f000 scd s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2021 7000 ldm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3223 0000 addiu s1,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2211 4000 ldp s0,0\(s1\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2021 f000 sdm s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2201 c000 sdp s0,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2201 2000 ldc2 \$16,0\(at\)
+[ ]*[0-9a-f]+: [ ]*3023 0000 addiu at,v1,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_LO16 test
+[ ]*[0-9a-f]+: [ ]*2201 a000 sdc2 \$16,0\(at\)
[ 0-9a-f]+ <test_delay_slot>:
-[ ]*[0-9a-f]+: b3fe 0000 sltiu ra,s8,0
- [0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
-[ ]*[0-9a-f]+: c063 fffe bgezalc v1,3ba2 <.*>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
-[ ]*[0-9a-f]+: e063 fffe bltzalc v1,3ba6 <.*>
- [0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
-[ ]*[0-9a-f]+: b3fe 0000 sltiu ra,s8,0
- [0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
-[ ]*[0-9a-f]+: 444b jalrc v0
-[ ]*[0-9a-f]+: 03e2 0f3c jalrc v0
-[ ]*[0-9a-f]+: 0c00 nop
-[ ]*[0-9a-f]+: 4443 jrc v0
-[ ]*[0-9a-f]+: 8002 0000 jrc v0
-[ ]*[0-9a-f]+: 03e2 1f3c jalrc.hb v0
-[ ]*[0-9a-f]+: 0002 1f3c jrc.hb v0
-[ ]*[0-9a-f]+: b3fe 0000 sltiu ra,s8,0
- [0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
-[ ]*[0-9a-f]+: 444b jalrc v0
-[ ]*[0-9a-f]+: 03e2 0f3c jalrc v0
+[ ]*[0-9a-f]+: [ ]*b3fe 0000 sltiu ra,s8,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
+[ ]*[0-9a-f]+: [ ]*c063 fffe bgezalc v1,3b8a <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ ]*[0-9a-f]+: [ ]*e063 fffe bltzalc v1,3b8e <.*>
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 test_delay_slot
+[ ]*[0-9a-f]+: [ ]*b3fe 0000 sltiu ra,s8,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
+[ ]*[0-9a-f]+: [ ]*444b jalrc v0
+[ ]*[0-9a-f]+: [ ]*03e2 0f3c jalrc v0
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*4443 jrc v0
+[ ]*[0-9a-f]+: [ ]*8002 0000 jrc v0
+[ ]*[0-9a-f]+: [ ]*03e2 1f3c jalrc.hb v0
+[ ]*[0-9a-f]+: [ ]*0002 1f3c jrc.hb v0
+[ ]*[0-9a-f]+: [ ]*b3fe 0000 sltiu ra,s8,0
+ [ ]*[0-9a-f]+: R_MICROMIPS_PC26_S1 test_delay_slot
+[ ]*[0-9a-f]+: [ ]*444b jalrc v0
+[ ]*[0-9a-f]+: [ ]*03e2 0f3c jalrc v0
[ 0-9a-f]+ <test_spec102>:
-[ ]*[0-9a-f]+: 6540 lw v0,-256\(gp\)
-[ ]*[0-9a-f]+: 65c0 lw v1,-256\(gp\)
-[ ]*[0-9a-f]+: 6640 lw a0,-256\(gp\)
-[ ]*[0-9a-f]+: 66c0 lw a1,-256\(gp\)
-[ ]*[0-9a-f]+: 6740 lw a2,-256\(gp\)
-[ ]*[0-9a-f]+: 67c0 lw a3,-256\(gp\)
-[ ]*[0-9a-f]+: 6440 lw s0,-256\(gp\)
-[ ]*[0-9a-f]+: 64c0 lw s1,-256\(gp\)
-[ ]*[0-9a-f]+: 64c1 lw s1,-252\(gp\)
-[ ]*[0-9a-f]+: 64ff lw s1,-4\(gp\)
-[ ]*[0-9a-f]+: 6480 lw s1,0\(gp\)
-[ ]*[0-9a-f]+: 6481 lw s1,4\(gp\)
-[ ]*[0-9a-f]+: 64be lw s1,248\(gp\)
-[ ]*[0-9a-f]+: 64bf lw s1,252\(gp\)
-[ ]*[0-9a-f]+: fe3c 0100 lw s1,256\(gp\)
-[ ]*[0-9a-f]+: fe3c fefc lw s1,-260\(gp\)
-[ ]*[0-9a-f]+: fe3c 0001 lw s1,1\(gp\)
-[ ]*[0-9a-f]+: fe3c 0002 lw s1,2\(gp\)
-[ ]*[0-9a-f]+: fe3c 0003 lw s1,3\(gp\)
-[ ]*[0-9a-f]+: fe3c ffff lw s1,-1\(gp\)
-[ ]*[0-9a-f]+: fe3c fffe lw s1,-2\(gp\)
-[ ]*[0-9a-f]+: fe3c fffd lw s1,-3\(gp\)
-[ ]*[0-9a-f]+: fe3b 0000 lw s1,0\(k1\)
-[ ]*[0-9a-f]+: 7840 0000 lapc v0,3c0c <.*>
-[ ]*[0-9a-f]+: 7860 0000 lapc v1,3c10 <.*>
-[ ]*[0-9a-f]+: 7880 0000 lapc a0,3c14 <.*>
-[ ]*[0-9a-f]+: 78a0 0000 lapc a1,3c18 <.*>
-[ ]*[0-9a-f]+: 78c0 0000 lapc a2,3c1c <.*>
-[ ]*[0-9a-f]+: 78e0 0000 lapc a3,3c20 <.*>
-[ ]*[0-9a-f]+: 7a00 0000 lapc s0,3c24 <.*>
-[ ]*[0-9a-f]+: 7a20 0000 lapc s1,3c28 <.*>
-[ ]*[0-9a-f]+: 7a23 ffff lapc s1,103c28 <.*>
-[ ]*[0-9a-f]+: 7a24 0000 lapc s1,fff03c30 <.*>
-[ ]*[0-9a-f]+: 7840 0000 lapc v0,3c34 <.*>
-[ ]*[0-9a-f]+: 7860 0000 lapc v1,3c38 <.*>
-[ ]*[0-9a-f]+: 7880 0000 lapc a0,3c3c <.*>
-[ ]*[0-9a-f]+: 78a0 0000 lapc a1,3c40 <.*>
-[ ]*[0-9a-f]+: 78c0 0000 lapc a2,3c44 <.*>
-[ ]*[0-9a-f]+: 78e0 0000 lapc a3,3c48 <.*>
-[ ]*[0-9a-f]+: 7a00 0000 lapc s0,3c4c <.*>
-[ ]*[0-9a-f]+: 7a20 0000 lapc s1,3c50 <.*>
-[ ]*[0-9a-f]+: 7a23 ffff lapc s1,103c50 <.*>
-[ ]*[0-9a-f]+: 7a24 0000 lapc s1,fff03c58 <.*>
+[ ]*[0-9a-f]+: [ ]*6540 lw v0,-256\(gp\)
+[ ]*[0-9a-f]+: [ ]*65c0 lw v1,-256\(gp\)
+[ ]*[0-9a-f]+: [ ]*6640 lw a0,-256\(gp\)
+[ ]*[0-9a-f]+: [ ]*66c0 lw a1,-256\(gp\)
+[ ]*[0-9a-f]+: [ ]*6740 lw a2,-256\(gp\)
+[ ]*[0-9a-f]+: [ ]*67c0 lw a3,-256\(gp\)
+[ ]*[0-9a-f]+: [ ]*6440 lw s0,-256\(gp\)
+[ ]*[0-9a-f]+: [ ]*64c0 lw s1,-256\(gp\)
+[ ]*[0-9a-f]+: [ ]*64c1 lw s1,-252\(gp\)
+[ ]*[0-9a-f]+: [ ]*64ff lw s1,-4\(gp\)
+[ ]*[0-9a-f]+: [ ]*6480 lw s1,0\(gp\)
+[ ]*[0-9a-f]+: [ ]*6481 lw s1,4\(gp\)
+[ ]*[0-9a-f]+: [ ]*64be lw s1,248\(gp\)
+[ ]*[0-9a-f]+: [ ]*64bf lw s1,252\(gp\)
+[ ]*[0-9a-f]+: [ ]*fe3c 0100 lw s1,256\(gp\)
+[ ]*[0-9a-f]+: [ ]*fe3c fefc lw s1,-260\(gp\)
+[ ]*[0-9a-f]+: [ ]*fe3c 0001 lw s1,1\(gp\)
+[ ]*[0-9a-f]+: [ ]*fe3c 0002 lw s1,2\(gp\)
+[ ]*[0-9a-f]+: [ ]*fe3c 0003 lw s1,3\(gp\)
+[ ]*[0-9a-f]+: [ ]*fe3c ffff lw s1,-1\(gp\)
+[ ]*[0-9a-f]+: [ ]*fe3c fffe lw s1,-2\(gp\)
+[ ]*[0-9a-f]+: [ ]*fe3c fffd lw s1,-3\(gp\)
+[ ]*[0-9a-f]+: [ ]*fe3b 0000 lw s1,0\(k1\)
+[ ]*[0-9a-f]+: [ ]*7840 0000 lapc v0,3bf4 <.*>
+[ ]*[0-9a-f]+: [ ]*7860 0000 lapc v1,3bf8 <.*>
+[ ]*[0-9a-f]+: [ ]*7880 0000 lapc a0,3bfc <.*>
+[ ]*[0-9a-f]+: [ ]*78a0 0000 lapc a1,3c00 <.*>
+[ ]*[0-9a-f]+: [ ]*78c0 0000 lapc a2,3c04 <.*>
+[ ]*[0-9a-f]+: [ ]*78e0 0000 lapc a3,3c08 <.*>
+[ ]*[0-9a-f]+: [ ]*7a00 0000 lapc s0,3c0c <.*>
+[ ]*[0-9a-f]+: [ ]*7a20 0000 lapc s1,3c10 <.*>
+[ ]*[0-9a-f]+: [ ]*7a23 ffff lapc s1,103c10 <.*>
+[ ]*[0-9a-f]+: [ ]*7a24 0000 lapc s1,fff03c18 <.*>
+[ ]*[0-9a-f]+: [ ]*7840 0000 lapc v0,3c1c <.*>
+[ ]*[0-9a-f]+: [ ]*7860 0000 lapc v1,3c20 <.*>
+[ ]*[0-9a-f]+: [ ]*7880 0000 lapc a0,3c24 <.*>
+[ ]*[0-9a-f]+: [ ]*78a0 0000 lapc a1,3c28 <.*>
+[ ]*[0-9a-f]+: [ ]*78c0 0000 lapc a2,3c2c <.*>
+[ ]*[0-9a-f]+: [ ]*78e0 0000 lapc a3,3c30 <.*>
+[ ]*[0-9a-f]+: [ ]*7a00 0000 lapc s0,3c34 <.*>
+[ ]*[0-9a-f]+: [ ]*7a20 0000 lapc s1,3c38 <.*>
+[ ]*[0-9a-f]+: [ ]*7a23 ffff lapc s1,103c38 <.*>
+[ ]*[0-9a-f]+: [ ]*7a24 0000 lapc s1,fff03c40 <.*>
[ 0-9a-f]+ <test_spec107>:
-[ ]*[0-9a-f]+: 4404 movep a1,a2,zero,zero
-[ ]*[0-9a-f]+: 4484 movep a1,a3,zero,zero
-[ ]*[0-9a-f]+: 4504 movep a2,a3,zero,zero
-[ ]*[0-9a-f]+: 4584 movep a0,s5,zero,zero
-[ ]*[0-9a-f]+: 4604 movep a0,s6,zero,zero
-[ ]*[0-9a-f]+: 4684 movep a0,a1,zero,zero
-[ ]*[0-9a-f]+: 4704 movep a0,a2,zero,zero
-[ ]*[0-9a-f]+: 4784 movep a0,a3,zero,zero
-[ ]*[0-9a-f]+: 4785 movep a0,a3,s1,zero
-[ ]*[0-9a-f]+: 4786 movep a0,a3,v0,zero
-[ ]*[0-9a-f]+: 4787 movep a0,a3,v1,zero
-[ ]*[0-9a-f]+: 478c movep a0,a3,s0,zero
-[ ]*[0-9a-f]+: 478d movep a0,a3,s2,zero
-[ ]*[0-9a-f]+: 478e movep a0,a3,s3,zero
-[ ]*[0-9a-f]+: 478f movep a0,a3,s4,zero
-[ ]*[0-9a-f]+: 479f movep a0,a3,s4,s1
-[ ]*[0-9a-f]+: 47af movep a0,a3,s4,v0
-[ ]*[0-9a-f]+: 47bf movep a0,a3,s4,v1
-[ ]*[0-9a-f]+: 47cf movep a0,a3,s4,s0
-[ ]*[0-9a-f]+: 47df movep a0,a3,s4,s2
-[ ]*[0-9a-f]+: 47ef movep a0,a3,s4,s3
-[ ]*[0-9a-f]+: 47ff movep a0,a3,s4,s4
-[ ]*[0-9a-f]+: 0c00 nop
-[ ]*[0-9a-f]+: 0000 0000 nop
+[ ]*[0-9a-f]+: [ ]*4404 movep a1,a2,zero,zero
+[ ]*[0-9a-f]+: [ ]*4484 movep a1,a3,zero,zero
+[ ]*[0-9a-f]+: [ ]*4504 movep a2,a3,zero,zero
+[ ]*[0-9a-f]+: [ ]*4584 movep a0,s5,zero,zero
+[ ]*[0-9a-f]+: [ ]*4604 movep a0,s6,zero,zero
+[ ]*[0-9a-f]+: [ ]*4684 movep a0,a1,zero,zero
+[ ]*[0-9a-f]+: [ ]*4704 movep a0,a2,zero,zero
+[ ]*[0-9a-f]+: [ ]*4784 movep a0,a3,zero,zero
+[ ]*[0-9a-f]+: [ ]*4785 movep a0,a3,s1,zero
+[ ]*[0-9a-f]+: [ ]*4786 movep a0,a3,v0,zero
+[ ]*[0-9a-f]+: [ ]*4787 movep a0,a3,v1,zero
+[ ]*[0-9a-f]+: [ ]*478c movep a0,a3,s0,zero
+[ ]*[0-9a-f]+: [ ]*478d movep a0,a3,s2,zero
+[ ]*[0-9a-f]+: [ ]*478e movep a0,a3,s3,zero
+[ ]*[0-9a-f]+: [ ]*478f movep a0,a3,s4,zero
+[ ]*[0-9a-f]+: [ ]*479f movep a0,a3,s4,s1
+[ ]*[0-9a-f]+: [ ]*47af movep a0,a3,s4,v0
+[ ]*[0-9a-f]+: [ ]*47bf movep a0,a3,s4,v1
+[ ]*[0-9a-f]+: [ ]*47cf movep a0,a3,s4,s0
+[ ]*[0-9a-f]+: [ ]*47df movep a0,a3,s4,s2
+[ ]*[0-9a-f]+: [ ]*47ef movep a0,a3,s4,s3
+[ ]*[0-9a-f]+: [ ]*47ff movep a0,a3,s4,s4
+[ ]*[0-9a-f]+: [ ]*0c00 nop
+[ ]*[0-9a-f]+: [ ]*0000 0000 nop
#pass
--
2.34.1
^ permalink raw reply [flat|nested] 26+ messages in thread