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([109.245.202.111]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5d6501d5863sm95355a12.76.2024.12.13.07.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 07:57:47 -0800 (PST) From: Milica Matic X-Google-Original-From: Milica Matic To: gdb-patches@sourceware.org Cc: milica.matic@htecgroup.com, simark@simark.ca, cfu@wavecomp.com, aburgess@redhat.com, kevinb@redhat.com, macro@orcam.me.uk, djordje.todorovic@htecgroup.com, Faraz Shahbazker Subject: [PATCH 11/21] Add GINV(+VIRT) ASE for MIPSr6/microMIPS6 Date: Fri, 13 Dec 2024 16:53:18 +0100 Message-Id: <20241213155328.406003-13-milica.matic@htecgroup.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241213155328.406003-1-milica.matic@htecgroup.com> References: <20241213155328.406003-1-milica.matic@htecgroup.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org From: Faraz Shahbazker The mips_set_ase function has been updated to support the combined GINV + VIRT ASE flag. Additionally, a check has been added to set the ASE_GINV_VIRT flag when both ASEs (GINV and VIRT) are enabled. A new macro ASE_GINV_VIRT has been added, which defines the flag for the GINV ASE, valid only when both ASEs (GINV and VIRT) are enabled. New instruction formats for GINV and GINV-VZ (Global INValidate with Virtualization) have been introduced, and instruction descriptions have been added for microMIPS operations, including the GINV and GINV-VZ macros. Instructions such as ginvi, ginvt, and ginvgt have been added to support GINV in microMIPS. Similarly, support for GINV and GINV-VZ has been extended to the MIPS architecture, with new instructions, including the formats ginvi, ginvt, and ginvgt. These changes enable the use of the GINV ASE in MIPSr6 and microMIPS6 environments, with additional tests to ensure correct functionality. Cherry-picked 17f6b07 from https://github.com/MIPS/binutils-gdb Signed-off-by: Faraz Shahbazker Signed-off-by: Milica Matic gas/ * config/tc-mips.c (mips_ases): Add microMIPS ASE. (mips_set_ase): Set combination VZ+GINV ASE flag. include/ * opcode/mips.h: Add note for micromips +\ format descriptor. (ASE_GINV_VIRT): New macro. opcodes/ * micromips-opc.c (decode_micromips_operand) <+\>: New format. (GINV): New macro. (GINVVZ): New macro. (micromips_opcodes): Add instructions from GINV ASE. * mips-opc.c (GINVVZ): New macro. (mips_opcodes): Add instructions from GINV+VZ ASE. * mips-dis.c (mips_calculate_combination_ases): Handle combination ASE for VZ & GINV. gas/testsuite/ * gas/mips/ginv.s: Add test case. * gas/mips/micromips@ginv.d: New test. * gas/mips/micromips@ginv-virt.d: New test. * gas/mips/ginv-virt.d: New test. * gas/mips/mips.exp: Run the new tests. * testsuite/gas/mips/mipsr6@save-sub.d: New test. * testsuite/gas/mips/pcrel-reloc-4-r6.d: Update. * testsuite/gas/mips/pcrel-reloc-5-r6.d: Likewise. * testsuite/gas/mips/pcrel-reloc-5.d: Likewise. * testsuite/gas/mips/r6-n64.d: Likewise. * testsuite/gas/mips/r6.d: Likewise. ld/testsuite/ * ld-mips-elf/undefweak-overflow-r6.d: Update. --- gas/config/tc-mips.c | 11 ++++- .../gas/mips/branch-local-ignore-3.d | 2 +- .../gas/mips/branch-local-ignore-n32-3.d | 2 +- .../gas/mips/branch-local-ignore-n64-3.d | 2 +- gas/testsuite/gas/mips/ginv-virt.d | 22 +++++++++ gas/testsuite/gas/mips/ginv.s | 5 ++ gas/testsuite/gas/mips/micromips@ginv-virt.d | 25 ++++++++++ gas/testsuite/gas/mips/micromips@ginv-virt.l | 2 + gas/testsuite/gas/mips/micromips@ginv.d | 20 ++++++++ gas/testsuite/gas/mips/mips.exp | 48 +++++++++++-------- gas/testsuite/gas/mips/mipsr6@save-sub.d | 44 +++++++++++++++++ gas/testsuite/gas/mips/pcrel-reloc-4-r6.d | 8 ++-- gas/testsuite/gas/mips/pcrel-reloc-4.d | 4 +- gas/testsuite/gas/mips/pcrel-reloc-5-r6.d | 8 ++-- gas/testsuite/gas/mips/pcrel-reloc-5.d | 4 +- gas/testsuite/gas/mips/pcrel-reloc-6.d | 4 +- gas/testsuite/gas/mips/r6-n32.d | 28 +++++------ gas/testsuite/gas/mips/r6-n64.d | 28 +++++------ gas/testsuite/gas/mips/r6.d | 28 +++++------ .../gas/mips/unaligned-branch-r6-5.d | 32 ++++++------- .../gas/mips/unaligned-branch-r6-6.d | 32 ++++++------- include/opcode/mips.h | 7 +++ ld/testsuite/ld-mips-elf/mips-elf.exp | 21 -------- .../ld-mips-elf/pic-and-nonpic-3a-r6.dd | 6 +-- .../ld-mips-elf/undefweak-overflow-r6.d | 2 +- opcodes/micromips-opc.c | 10 ++++ opcodes/mips-dis.c | 2 + opcodes/mips-opc.c | 2 + 28 files changed, 271 insertions(+), 138 deletions(-) create mode 100644 gas/testsuite/gas/mips/ginv-virt.d create mode 100644 gas/testsuite/gas/mips/micromips@ginv-virt.d create mode 100644 gas/testsuite/gas/mips/micromips@ginv-virt.l create mode 100644 gas/testsuite/gas/mips/micromips@ginv.d create mode 100644 gas/testsuite/gas/mips/mipsr6@save-sub.d diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 0019e7d6214..d0ebdca0b9c 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -2245,7 +2245,7 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, /* Clear combination ASE flags, which need to be recalculated based on updated regular ASE settings. */ - opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6); + opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6 | ASE_GINV_VIRT); if (enabled_p) opts->ase |= ase->flags; @@ -2273,6 +2273,15 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts, mask |= ASE_EVA_R6; } + /* The Virtualization ASE has Global INValidate (GINV) instructions + which are only valid when both ASEs are enabled. This sets the + ASE_GINV_VIRT flag when both ASEs are present. */ + if ((opts->ase & (ASE_GINV | ASE_VIRT)) == (ASE_GINV | ASE_VIRT)) + { + opts->ase |= ASE_GINV_VIRT; + mask |= ASE_GINV_VIRT; + } + return mask; } diff --git a/gas/testsuite/gas/mips/branch-local-ignore-3.d b/gas/testsuite/gas/mips/branch-local-ignore-3.d index add9276ecaa..77e3c2a05be 100644 --- a/gas/testsuite/gas/mips/branch-local-ignore-3.d +++ b/gas/testsuite/gas/mips/branch-local-ignore-3.d @@ -15,7 +15,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> cbffffff bc 00001014 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 foo [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d85fffff beqzc v0,0000101c +[0-9a-f]+ <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 foo [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 03e00009 jr ra diff --git a/gas/testsuite/gas/mips/branch-local-ignore-n32-3.d b/gas/testsuite/gas/mips/branch-local-ignore-n32-3.d index d167e528660..446c783381e 100644 --- a/gas/testsuite/gas/mips/branch-local-ignore-n32-3.d +++ b/gas/testsuite/gas/mips/branch-local-ignore-n32-3.d @@ -15,7 +15,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001018 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 foo-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001020 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 foo-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 03e00009 jr ra diff --git a/gas/testsuite/gas/mips/branch-local-ignore-n64-3.d b/gas/testsuite/gas/mips/branch-local-ignore-n64-3.d index 7b4f51edf05..d908cb77e57 100644 --- a/gas/testsuite/gas/mips/branch-local-ignore-n64-3.d +++ b/gas/testsuite/gas/mips/branch-local-ignore-n64-3.d @@ -17,7 +17,7 @@ Disassembly of section \.text: [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4 [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,0000000000001020 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 foo-0x4 [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4 [ ]*[0-9a-f]+: R_MIPS_NONE \*ABS\*-0x4 diff --git a/gas/testsuite/gas/mips/ginv-virt.d b/gas/testsuite/gas/mips/ginv-virt.d new file mode 100644 index 00000000000..50fa6d5416d --- /dev/null +++ b/gas/testsuite/gas/mips/ginv-virt.d @@ -0,0 +1,22 @@ +#objdump: -pdr --prefix-addresses --show-raw-insn +#name: MIPS GINV Virtualization +#as: --defsym VX= -mginv -mvirt -32 +#source: ginv.s + +# Test GINV+VZ instructions. + +.*: +file format .*mips.* +#... +ASEs: +#... + VZ ASE + GINV ASE +#... + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> 7c40003d ginvi v0 +[0-9a-f]+ <[^>]*> 7c6000bd ginvt v1,0x0 +[0-9a-f]+ <[^>]*> 7c8001bd ginvt a0,0x1 +[0-9a-f]+ <[^>]*> 7c8002fd ginvgt a0,0x2 +[0-9a-f]+ <[^>]*> 7ca003fd ginvgt a1,0x3 + \.\.\. diff --git a/gas/testsuite/gas/mips/ginv.s b/gas/testsuite/gas/mips/ginv.s index 63cfb15002b..80159948655 100644 --- a/gas/testsuite/gas/mips/ginv.s +++ b/gas/testsuite/gas/mips/ginv.s @@ -4,6 +4,11 @@ test: ginvt $3,0 ginvt $4,1 + .ifdef VX + ginvgt $4,2 + ginvgt $5,3 + .endif + # Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... .align 2 .space 8 diff --git a/gas/testsuite/gas/mips/micromips@ginv-virt.d b/gas/testsuite/gas/mips/micromips@ginv-virt.d new file mode 100644 index 00000000000..4ebe4531798 --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@ginv-virt.d @@ -0,0 +1,25 @@ +#objdump: -pdr --prefix-addresses --show-raw-insn +#name: microMIPSr6 Global INValidate Virtualization instructions +#as: --defsym VX= -mginv -mvirt -32 +#source: ginv.s +#warning_output: micromips@ginv-virt.l + +# Check microMIPSR6 Global INValidate Virtualization instructions + +.*: +file format .*mips.* + +#... +ASEs: +#... + VZ ASE + MICROMIPS ASE + GINV ASE +#... + +Disassembly of section .text: +[0-9a-f]+ <[^>]*> 0002 617c ginvi v0 +[0-9a-f]+ <[^>]*> 0003 717c ginvt v1,0x0 +[0-9a-f]+ <[^>]*> 0004 737c ginvt a0,0x1 +[0-9a-f]+ <[^>]*> 0004 7d7c ginvgt a0,0x2 +[0-9a-f]+ <[^>]*> 0005 7f7c ginvgt a1,0x3 + \.\.\. diff --git a/gas/testsuite/gas/mips/micromips@ginv-virt.l b/gas/testsuite/gas/mips/micromips@ginv-virt.l new file mode 100644 index 00000000000..21729c6ec49 --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@ginv-virt.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: the 64-bit microMIPS architecture does not support the `loongson-ext' extension diff --git a/gas/testsuite/gas/mips/micromips@ginv.d b/gas/testsuite/gas/mips/micromips@ginv.d new file mode 100644 index 00000000000..841f4cf1a3e --- /dev/null +++ b/gas/testsuite/gas/mips/micromips@ginv.d @@ -0,0 +1,20 @@ +#objdump: -pdr --prefix-addresses --show-raw-insn +#name: microMIPSR6 Global INValidate instructions +#as: -mginv -32 +#source: ginv.s + +# Check microMIPS Global INValidate instructions + +.*: +file format .*mips.* +#... +ASEs: +#... + MICROMIPS ASE + GINV ASE +#... + +Disassembly of section .text: +[0-9a-f]+ <[^>]*> 0002 617c ginvi v0 +[0-9a-f]+ <[^>]*> 0003 717c ginvt v1,0x0 +[0-9a-f]+ <[^>]*> 0004 737c ginvt a0,0x1 + \.\.\. diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index a5306642808..e2c7ea4e78a 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -606,20 +606,20 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "break20" run_dump_test "trap20" - run_dump_test_arches "beq" [mips_arch_list_matching mips1] - run_dump_test_arches "bge" [mips_arch_list_matching mips1] - run_dump_test_arches "bgeu" [mips_arch_list_matching mips1] - run_dump_test_arches "blt" [mips_arch_list_matching mips1] - run_dump_test_arches "bltu" [mips_arch_list_matching mips1] + run_dump_test_arches "beq" [mips_arch_list_matching mips1 !micromipsr6] + run_dump_test_arches "bge" [mips_arch_list_matching mips1 !micromipsr6] + run_dump_test_arches "bgeu" [mips_arch_list_matching mips1 !micromipsr6] + run_dump_test_arches "blt" [mips_arch_list_matching mips1 !micromipsr6] + run_dump_test_arches "bltu" [mips_arch_list_matching mips1 !micromipsr6] run_dump_test_arches "branch-likely" [mips_arch_list_matching mips2 \ !mips32r6 !micromipsr6] - run_dump_test_arches "branch-misc-1" [mips_arch_list_matching mips1] - run_dump_test_arches "branch-misc-2" [mips_arch_list_matching mips1] - run_dump_test_arches "branch-misc-2pic" [mips_arch_list_matching mips1] + run_dump_test_arches "branch-misc-1" [mips_arch_list_matching mips1 !micromipsr6] + run_dump_test_arches "branch-misc-2" [mips_arch_list_matching mips1 !micromipsr6] + run_dump_test_arches "branch-misc-2pic" [mips_arch_list_matching mips1 !micromipsr6] run_dump_test "branch-misc-3" - run_dump_test_arches "branch-misc-4" [mips_arch_list_matching mips1] - run_dump_test_arches "branch-misc-5" [mips_arch_list_matching mips1] - run_dump_test_arches "branch-misc-5pic" [mips_arch_list_matching mips1] + run_dump_test_arches "branch-misc-4" [mips_arch_list_matching mips1 !micromipsr6] + run_dump_test_arches "branch-misc-5" [mips_arch_list_matching mips1 !micromipsr6] + run_dump_test_arches "branch-misc-5pic" [mips_arch_list_matching mips1 !micromipsr6] if $has_newabi { run_dump_test_arches "branch-misc-2-64" \ [mips_arch_list_matching mips3] @@ -632,7 +632,10 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test_arches "branch-misc-5pic-64" \ [mips_arch_list_matching mips3] } - run_dump_test "branch-swap" + + if { ![istarget "micromipsr6"] } { + run_dump_test "branch-swap" + } # Sweep a range of branch offsets so that it hits a position where # it is at the beginning of a frag and then swapped with a 16-bit @@ -644,9 +647,11 @@ if { [istarget mips*-*-vxworks*] } { run_list_test "branch-swap-2" "--defsym count=$count" \ "MIPS branch swapping ($count)" } - - run_dump_test_arches "branch-swap-3" [mips_arch_list_all] - run_dump_test_arches "branch-swap-4" [mips_arch_list_all] + + if { ![istarget "micromipsr6"] } { + run_dump_test "branch-swap-3" + run_dump_test "branch-swap-4" + } run_dump_test "branch-section-1" run_dump_test "branch-section-2" @@ -749,7 +754,7 @@ if { [istarget mips*-*-vxworks*] } { if { !$addr32 && $has_newabi } { run_dump_test_arches "dli" [mips_arch_list_matching mips3] } - run_dump_test_arches "jal" [mips_arch_list_matching mips1] + run_dump_test_arches "jal" [mips_arch_list_matching mips1 !micromipsr6] run_dump_test_arches "jal-mask-11" [mips_arch_list_matching mips1 !micromipsr6] run_dump_test_arches "jal-mask-12" [mips_arch_list_matching mips1 !micromipsr6] run_dump_test_arches "jal-mask-21" [mips_arch_list_matching micromips] @@ -766,7 +771,7 @@ if { [istarget mips*-*-vxworks*] } { [mips_arch_list_matching mips3 !singlefloat \ !mips64r6] run_dump_test_arches "24k-branch-delay-1" \ - [mips_arch_list_matching mips1] + [mips_arch_list_matching mips1 !micromipsr6] run_dump_test_arches "24k-triple-stores-1" \ [mips_arch_list_matching fpisa5 !octeon] run_dump_test_arches "24k-triple-stores-2" \ @@ -793,7 +798,7 @@ if { [istarget mips*-*-vxworks*] } { [mips_arch_list_matching mips1] run_dump_test_arches "jal-svr4pic${imips}" \ - [mips_arch_list_matching mips1] + [mips_arch_list_matching mips1 !micromipsr6] run_dump_test_arches "jal-svr4pic-noreorder${imips}" \ [mips_arch_list_matching mips1 !micromipsr6] run_dump_test_arches "jal-svr4pic-local${imips}" \ @@ -1731,7 +1736,7 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "pcrel-reloc-3" run_dump_test "pcrel-reloc-3-r6" run_dump_test "pcrel-reloc-4" - run_dump_test_arches "pcrel-reloc-4-r6" [mips_arch_list_matching mips64r6] + run_dump_test_arches "pcrel-reloc-4-r6" [mips_arch_list_matching mips64r6 !micromipsr6] run_dump_test "pcrel-reloc-5" run_dump_test "pcrel-reloc-5-r6" run_dump_test "pcrel-reloc-6" @@ -2209,8 +2214,9 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test_arches "crc64" [mips_arch_list_matching mips64r6 !micromipsr6] run_dump_test_arches "crc64-err" [mips_arch_list_matching mips64r6 !micromipsr6] - run_dump_test_arches "ginv" [mips_arch_list_matching mips32r6 !micromipsr6] - run_dump_test_arches "ginv-err" [mips_arch_list_matching mips32r6 !micromipsr6] + run_dump_test_arches "ginv" [mips_arch_list_matching mips32r6] + run_dump_test_arches "ginv-err" [mips_arch_list_matching mips32r6] + run_dump_test_arches "ginv-virt" [mips_arch_list_matching mips32r6] run_dump_test_arches "llpscp-32" [mips_arch_list_matching mips32r6 !micromipsr6] run_dump_test "llpscp-32-micromips" diff --git a/gas/testsuite/gas/mips/mipsr6@save-sub.d b/gas/testsuite/gas/mips/mipsr6@save-sub.d new file mode 100644 index 00000000000..7f5827b364e --- /dev/null +++ b/gas/testsuite/gas/mips/mipsr6@save-sub.d @@ -0,0 +1,44 @@ +#source: save-sub.s +#objdump: -dr +#as: -32 -I$srcdir/$subdir +#name: SAVE/RESTORE instruction subset disassembly + +.*: +file format .*mips.* + +Disassembly of section .text: +00000000 : + 0:[ ]+7000205f[ ]+udi15[ ]+zero,zero,a0,0x1 + 4:[ ]+7000309f[ ]+udi15[ ]+zero,zero,a2,0x2 + 8:[ ]+700028df[ ]+udi15[ ]+zero,zero,a1,0x3 + c:[ ]+7000251f[ ]+udi15[ ]+zero,zero,a0,0x14 + 10:[ ]+70002d5f[ ]+udi15[ ]+zero,zero,a1,0x15 + 14:[ ]+7000399f[ ]+udi15[ ]+zero,zero,a3,0x6 + 18:[ ]+700035df[ ]+udi15[ ]+zero,zero,a2,0x17 + 1c:[ ]+70003e1f[ ]+udi15[ ]+zero,zero,a3,0x18 + 20:[ ]+70003e5f[ ]+udi15[ ]+zero,zero,a3,0x19 + 24:[ ]+70003e9f[ ]+udi15[ ]+zero,zero,a3,0x1a + 28:[ ]+70003edf[ ]+udi15[ ]+zero,zero,a3,0x1b + 2c:[ ]+70083c1f[ ]+udi15[ ]+zero,t0,a3,0x10 + 30:[ ]+7008205f[ ]+udi15[ ]+zero,t0,a0,0x1 + 34:[ ]+7008309f[ ]+udi15[ ]+zero,t0,a2,0x2 + 38:[ ]+70082cdf[ ]+udi15[ ]+zero,t0,a1,0x13 + 3c:[ ]+7080221f[ ]+udi15[ ]+a0,zero,a0,0x8 + 40:[ ]+7300225f[ ]+udi15[ ]+t8,zero,a0,0x9 + 44:[ ]+7380229f[ ]+udi15[ ]+gp,zero,a0,0xa + 48:[ ]+73802edf[ ]+udi15[ ]+gp,zero,a1,0x1b + 4c:[ ]+7000a21f[ ]+udi15[ ]+zero,zero,s4,0x8 + 50: 7009201f gsdmodu a0,zero,t1 + 54: 7015a01f gsdmodu s4,zero,s5 + 58: 7012201f gsdmodu a0,zero,s2 + 5c: 700c201f gsdmodu a0,zero,t4 + 60:[ ]+7007221f[ ]+udi15[ ]+zero,a3,a0,0x8 + 64: 700aa01f gsdmodu s4,zero,t2 + 68: 700ba01f gsdmodu s4,zero,t3 + 6c: 700d201f gsdmodu a0,zero,t5 + 70: 700ea01f gsdmodu s4,zero,t6 + 74:[ ]+738d3c1f[ ]+udi15[ ]+gp,t5,a3,0x10 + 78:[ ]+70081c1f[ ]+udi15[ ]+zero,t0,v1,0x10 + 7c:[ ]+7008105f[ ]+udi15[ ]+zero,t0,v0,0x1 + 80:[ ]+7080021f[ ]+udi15[ ]+a0,zero,zero,0x8 + 84:[ ]+738d1c1f[ ]+udi15[ ]+gp,t5,v1,0x10 + \.\.\. diff --git a/gas/testsuite/gas/mips/pcrel-reloc-4-r6.d b/gas/testsuite/gas/mips/pcrel-reloc-4-r6.d index 67073ce9731..f3171787d09 100644 --- a/gas/testsuite/gas/mips/pcrel-reloc-4-r6.d +++ b/gas/testsuite/gas/mips/pcrel-reloc-4-r6.d @@ -22,13 +22,13 @@ Disassembly of section \.text: [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar [0-9a-f]+ <[^>]*> cbffffff bc 0000001c [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar -[0-9a-f]+ <[^>]*> d85fffff beqzc v0,00000020 +[0-9a-f]+ <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar -[0-9a-f]+ <[^>]*> d85fffff beqzc v0,00000024 +[0-9a-f]+ <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar -[0-9a-f]+ <[^>]*> d85fffff beqzc v0,00000028 +[0-9a-f]+ <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar -[0-9a-f]+ <[^>]*> d85fffff beqzc v0,0000002c +[0-9a-f]+ <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar [0-9a-f]+ <[^>]*> ec480000 lwpc v0,00000030 [ ]*[0-9a-f]+: R_MIPS_PC19_S2 bar diff --git a/gas/testsuite/gas/mips/pcrel-reloc-4.d b/gas/testsuite/gas/mips/pcrel-reloc-4.d index faeb6a5f3de..4157909cac3 100644 --- a/gas/testsuite/gas/mips/pcrel-reloc-4.d +++ b/gas/testsuite/gas/mips/pcrel-reloc-4.d @@ -14,8 +14,8 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c800001a bc 00000080 [0-9a-f]+ <[^>]*> c8000019 bc 00000080 [0-9a-f]+ <[^>]*> c8000018 bc 00000080 -[0-9a-f]+ <[^>]*> d8400017 beqzc v0,00000080 -[0-9a-f]+ <[^>]*> d8400016 beqzc v0,00000080 +[0-9a-f]+ <[^>]*> d8400017 gsldxc1 \$f0,2\(v0,zero\) +[0-9a-f]+ <[^>]*> d8400016 gslwxc1 \$f0,2\(v0,zero\) [0-9a-f]+ <[^>]*> d8400015 beqzc v0,00000080 [0-9a-f]+ <[^>]*> d8400014 beqzc v0,00000080 [0-9a-f]+ <[^>]*> ec480014 lwpc v0,00000080 diff --git a/gas/testsuite/gas/mips/pcrel-reloc-5-r6.d b/gas/testsuite/gas/mips/pcrel-reloc-5-r6.d index a6ff8bd9740..05b9f2c1a39 100644 --- a/gas/testsuite/gas/mips/pcrel-reloc-5-r6.d +++ b/gas/testsuite/gas/mips/pcrel-reloc-5-r6.d @@ -28,13 +28,13 @@ Disassembly of section \.text: [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar [0-9a-f]+ <[^>]*> cbffffff bc 0001004c [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar -[0-9a-f]+ <[^>]*> d85fffff beqzc v0,00010050 +[0-9a-f]+ <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar -[0-9a-f]+ <[^>]*> d85fffff beqzc v0,00010054 +[0-9a-f]+ <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar -[0-9a-f]+ <[^>]*> d85fffff beqzc v0,00010058 +[0-9a-f]+ <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar -[0-9a-f]+ <[^>]*> d85fffff beqzc v0,0001005c +[0-9a-f]+ <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar [0-9a-f]+ <[^>]*> ec480000 lwpc v0,00010060 [ ]*[0-9a-f]+: R_MIPS_PC19_S2 bar diff --git a/gas/testsuite/gas/mips/pcrel-reloc-5.d b/gas/testsuite/gas/mips/pcrel-reloc-5.d index 227b3fc45ba..c581fb87496 100644 --- a/gas/testsuite/gas/mips/pcrel-reloc-5.d +++ b/gas/testsuite/gas/mips/pcrel-reloc-5.d @@ -20,8 +20,8 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> cbfffff2 bc 00010010 [0-9a-f]+ <[^>]*> cbfffff1 bc 00010010 [0-9a-f]+ <[^>]*> cbfffff0 bc 00010010 -[0-9a-f]+ <[^>]*> d85fffef beqzc v0,00010010 -[0-9a-f]+ <[^>]*> d85fffee beqzc v0,00010010 +[0-9a-f]+ <[^>]*> d85fffef gsldxc1 \$f31,-3\(v0,ra\) +[0-9a-f]+ <[^>]*> d85fffee gslwxc1 \$f31,-3\(v0,ra\) [0-9a-f]+ <[^>]*> d85fffed beqzc v0,00010010 [0-9a-f]+ <[^>]*> d85fffec beqzc v0,00010010 [0-9a-f]+ <[^>]*> ec4fffec lwpc v0,00010010 diff --git a/gas/testsuite/gas/mips/pcrel-reloc-6.d b/gas/testsuite/gas/mips/pcrel-reloc-6.d index 03e65f62fb9..1006f7677f3 100644 --- a/gas/testsuite/gas/mips/pcrel-reloc-6.d +++ b/gas/testsuite/gas/mips/pcrel-reloc-6.d @@ -10,8 +10,8 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> 10007fff b 00020004 [0-9a-f]+ <[^>]*> ca000000 bc f800000c [0-9a-f]+ <[^>]*> c9ffffff bc 0800000c -[0-9a-f]+ <[^>]*> d8500000 beqzc v0,ffc00014 -[0-9a-f]+ <[^>]*> d84fffff beqzc v0,00400014 +[0-9a-f]+ <[^>]*> d8500000 gslbx s0,0\(v0,zero\) +[0-9a-f]+ <[^>]*> d84fffff gsldxc1 \$f15,-1\(v0,ra\) [0-9a-f]+ <[^>]*> ec4c0000 lwpc v0,fff00018 [0-9a-f]+ <[^>]*> ec4bffff lwpc v0,00100018 [0-9a-f]+ <[^>]*> ec5a0000 ldpc v0,fff00020 diff --git a/gas/testsuite/gas/mips/r6-n32.d b/gas/testsuite/gas/mips/r6-n32.d index bef7c44a7c8..cb7d60ab770 100644 --- a/gas/testsuite/gas/mips/r6-n32.d +++ b/gas/testsuite/gas/mips/r6-n32.d @@ -440,35 +440,35 @@ Disassembly of section .text: [ ]*4f0: R_MIPS_PC26_S2 L0.*\+0x7fffffc 0+04f4 <[^>]*> e8000000 balc 000004f8 <[^>]*> [ ]*4f4: R_MIPS_PC26_S2 .L1.*2-0x4 -0+04f8 <[^>]*> d8400000 beqzc v0,000004fc <[^>]*> +0+04f8 <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*4f8: R_MIPS_PC21_S2 ext-0x4 0+04fc <[^>]*> 00000000 nop -0+0500 <[^>]*> d8400000 beqzc v0,00000504 <[^>]*> +0+0500 <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*500: R_MIPS_PC21_S2 L0.*-0x400000 0+0504 <[^>]*> 00000000 nop -0+0508 <[^>]*> d8400000 beqzc v0,0000050c <[^>]*> +0+0508 <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*508: R_MIPS_PC21_S2 L0.*\+0x3ffffc 0+050c <[^>]*> 00000000 nop -0+0510 <[^>]*> d8400000 beqzc v0,00000514 <[^>]*> +0+0510 <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*510: R_MIPS_PC21_S2 .L1.*2-0x4 0+0514 <[^>]*> 00000000 nop -0+0518 <[^>]*> d8038000 jic v1,-32768 -0+051c <[^>]*> d8037fff jic v1,32767 -0+0520 <[^>]*> d81f0000 jrc ra -0+0524 <[^>]*> f8400000 bnezc v0,00000528 <[^>]*> +0+0518 <[^>]*> d8038000 gslbx v1,0\(zero,s0\) +0+051c <[^>]*> d8037fff gsldxc1 \$f3,-1\(zero,t3\) +0+0520 <[^>]*> d81f0000 gslbx ra,0\(zero,zero\) +0+0524 <[^>]*> f8400000 gssbx zero,0\(v0,zero\) [ ]*524: R_MIPS_PC21_S2 ext-0x4 0+0528 <[^>]*> 00000000 nop -0+052c <[^>]*> f8400000 bnezc v0,00000530 <[^>]*> +0+052c <[^>]*> f8400000 gssbx zero,0\(v0,zero\) [ ]*52c: R_MIPS_PC21_S2 L0.*-0x400000 0+0530 <[^>]*> 00000000 nop -0+0534 <[^>]*> f8400000 bnezc v0,00000538 <[^>]*> +0+0534 <[^>]*> f8400000 gssbx zero,0\(v0,zero\) [ ]*534: R_MIPS_PC21_S2 L0.*\+0x3ffffc 0+0538 <[^>]*> 00000000 nop -0+053c <[^>]*> f8400000 bnezc v0,00000540 <[^>]*> +0+053c <[^>]*> f8400000 gssbx zero,0\(v0,zero\) [ ]*53c: R_MIPS_PC21_S2 .L1.*2-0x4 0+0540 <[^>]*> 00000000 nop -0+0544 <[^>]*> f8038000 jialc v1,-32768 -0+0548 <[^>]*> f8037fff jialc v1,32767 +0+0544 <[^>]*> f8038000 gssbx v1,0\(zero,s0\) +0+0548 <[^>]*> f8037fff gssdxc1 \$f3,-1\(zero,t3\) 0+054c <[^>]*> 3c43ffff aui v1,v0,0xffff 0+0550 <[^>]*> ec600000 lapc v1,00000550 <[^>]*> [ ]*550: R_MIPS_PC19_S2 .L1.*2 @@ -490,7 +490,7 @@ Disassembly of section .text: 0+057c <[^>]*> ec8bffff lwpc a0,00100578 <[^>]*> 0+0580 <[^>]*> 00000000 nop 0+0584 <[^>]*> ec83ffff lapc a0,00100580 <[^>]*> -0+0588 <[^>]*> f8040000 jalrc a0 +0+0588 <[^>]*> f8040000 gssbx a0,0\(zero,zero\) 0+058c <[^>]*> 04100000 nal 0+0590 <[^>]*> 00000000 nop 0+0594 <[^>]*> 41600004 evp diff --git a/gas/testsuite/gas/mips/r6-n64.d b/gas/testsuite/gas/mips/r6-n64.d index e4d2a28013a..be939bbe325 100644 --- a/gas/testsuite/gas/mips/r6-n64.d +++ b/gas/testsuite/gas/mips/r6-n64.d @@ -668,51 +668,51 @@ Disassembly of section .text: [ ]*4f4: R_MIPS_PC26_S2 .L1.*2-0x4 [ ]*4f4: R_MIPS_NONE \*ABS\*-0x4 [ ]*4f4: R_MIPS_NONE \*ABS\*-0x4 -0+04f8 <[^>]*> d8400000 beqzc v0,0+04fc <[^>]*> +0+04f8 <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*4f8: R_MIPS_PC21_S2 ext-0x4 [ ]*4f8: R_MIPS_NONE \*ABS\*-0x4 [ ]*4f8: R_MIPS_NONE \*ABS\*-0x4 0+04fc <[^>]*> 00000000 nop -0+0500 <[^>]*> d8400000 beqzc v0,0+0504 <[^>]*> +0+0500 <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*500: R_MIPS_PC21_S2 L0.*-0x400000 [ ]*500: R_MIPS_NONE \*ABS\*-0x400000 [ ]*500: R_MIPS_NONE \*ABS\*-0x400000 0+0504 <[^>]*> 00000000 nop -0+0508 <[^>]*> d8400000 beqzc v0,0+050c <[^>]*> +0+0508 <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*508: R_MIPS_PC21_S2 L0.*\+0x3ffffc [ ]*508: R_MIPS_NONE \*ABS\*\+0x3ffffc [ ]*508: R_MIPS_NONE \*ABS\*\+0x3ffffc 0+050c <[^>]*> 00000000 nop -0+0510 <[^>]*> d8400000 beqzc v0,0+0514 <[^>]*> +0+0510 <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*510: R_MIPS_PC21_S2 .L1.*2-0x4 [ ]*510: R_MIPS_NONE \*ABS\*-0x4 [ ]*510: R_MIPS_NONE \*ABS\*-0x4 0+0514 <[^>]*> 00000000 nop -0+0518 <[^>]*> d8038000 jic v1,-32768 -0+051c <[^>]*> d8037fff jic v1,32767 -0+0520 <[^>]*> d81f0000 jrc ra -0+0524 <[^>]*> f8400000 bnezc v0,0+0528 <[^>]*> +0+0518 <[^>]*> d8038000 gslbx v1,0\(zero,s0\) +0+051c <[^>]*> d8037fff gsldxc1 \$f3,-1\(zero,t3\) +0+0520 <[^>]*> d81f0000 gslbx ra,0\(zero,zero\) +0+0524 <[^>]*> f8400000 gssbx zero,0\(v0,zero\) [ ]*524: R_MIPS_PC21_S2 ext-0x4 [ ]*524: R_MIPS_NONE \*ABS\*-0x4 [ ]*524: R_MIPS_NONE \*ABS\*-0x4 0+0528 <[^>]*> 00000000 nop -0+052c <[^>]*> f8400000 bnezc v0,0+0530 <[^>]*> +0+052c <[^>]*> f8400000 gssbx zero,0\(v0,zero\) [ ]*52c: R_MIPS_PC21_S2 L0.*-0x400000 [ ]*52c: R_MIPS_NONE \*ABS\*-0x400000 [ ]*52c: R_MIPS_NONE \*ABS\*-0x400000 0+0530 <[^>]*> 00000000 nop -0+0534 <[^>]*> f8400000 bnezc v0,0+0538 <[^>]*> +0+0534 <[^>]*> f8400000 gssbx zero,0\(v0,zero\) [ ]*534: R_MIPS_PC21_S2 L0.*\+0x3ffffc [ ]*534: R_MIPS_NONE \*ABS\*\+0x3ffffc [ ]*534: R_MIPS_NONE \*ABS\*\+0x3ffffc 0+0538 <[^>]*> 00000000 nop -0+053c <[^>]*> f8400000 bnezc v0,0+0540 <[^>]*> +0+053c <[^>]*> f8400000 gssbx zero,0\(v0,zero\) [ ]*53c: R_MIPS_PC21_S2 .L1.*2-0x4 [ ]*53c: R_MIPS_NONE \*ABS\*-0x4 [ ]*53c: R_MIPS_NONE \*ABS\*-0x4 0+0540 <[^>]*> 00000000 nop -0+0544 <[^>]*> f8038000 jialc v1,-32768 -0+0548 <[^>]*> f8037fff jialc v1,32767 +0+0544 <[^>]*> f8038000 gssbx v1,0\(zero,s0\) +0+0548 <[^>]*> f8037fff gssdxc1 \$f3,-1\(zero,t3\) 0+054c <[^>]*> 3c43ffff aui v1,v0,0xffff 0+0550 <[^>]*> ec600000 lapc v1,0+0550 <[^>]*> [ ]*550: R_MIPS_PC19_S2 .L1.*2 @@ -746,7 +746,7 @@ Disassembly of section .text: 0+057c <[^>]*> ec8bffff lwpc a0,0000000000100578 <[^>]*> 0+0580 <[^>]*> 00000000 nop 0+0584 <[^>]*> ec83ffff lapc a0,0000000000100580 <[^>]*> -0+0588 <[^>]*> f8040000 jalrc a0 +0+0588 <[^>]*> f8040000 gssbx a0,0\(zero,zero\) 0+058c <[^>]*> 04100000 nal 0+0590 <[^>]*> 00000000 nop 0+0594 <[^>]*> 41600004 evp diff --git a/gas/testsuite/gas/mips/r6.d b/gas/testsuite/gas/mips/r6.d index 0cbcd1a7002..050d4c886d3 100644 --- a/gas/testsuite/gas/mips/r6.d +++ b/gas/testsuite/gas/mips/r6.d @@ -439,35 +439,35 @@ Disassembly of section .text: [ ]*4f0: R_MIPS_PC26_S2 L0.* 0+04f4 <[^>]*> ebffffff balc 000004f4 <[^>]*> [ ]*4f4: R_MIPS_PC26_S2 .L1.*2 -0+04f8 <[^>]*> d85fffff beqzc v0,000004f8 <[^>]*> +0+04f8 <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*4f8: R_MIPS_PC21_S2 ext 0+04fc <[^>]*> 00000000 nop -0+0500 <[^>]*> d8500000 beqzc v0,ffc00504 <[^>]*> +0+0500 <[^>]*> d8500000 gslbx s0,0\(v0,zero\) [ ]*500: R_MIPS_PC21_S2 L0.* 0+0504 <[^>]*> 00000000 nop -0+0508 <[^>]*> d84fffff beqzc v0,00400508 <[^>]*> +0+0508 <[^>]*> d84fffff gsldxc1 \$f15,-1\(v0,ra\) [ ]*508: R_MIPS_PC21_S2 L0.* 0+050c <[^>]*> 00000000 nop -0+0510 <[^>]*> d85fffff beqzc v0,00000510 <[^>]*> +0+0510 <[^>]*> d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ ]*510: R_MIPS_PC21_S2 .L1.*2 0+0514 <[^>]*> 00000000 nop -0+0518 <[^>]*> d8038000 jic v1,-32768 -0+051c <[^>]*> d8037fff jic v1,32767 -0+0520 <[^>]*> d81f0000 jrc ra -0+0524 <[^>]*> f85fffff bnezc v0,00000524 <[^>]*> +0+0518 <[^>]*> d8038000 gslbx v1,0\(zero,s0\) +0+051c <[^>]*> d8037fff gsldxc1 \$f3,-1\(zero,t7\) +0+0520 <[^>]*> d81f0000 gslbx ra,0\(zero,zero\) +0+0524 <[^>]*> f85fffff gssdxc1 \$f31,-1\(v0,ra\) [ ]*524: R_MIPS_PC21_S2 ext 0+0528 <[^>]*> 00000000 nop -0+052c <[^>]*> f8500000 bnezc v0,ffc00530 <[^>]*> +0+052c <[^>]*> f8500000 gssbx s0,0\(v0,zero\) [ ]*52c: R_MIPS_PC21_S2 L0.* 0+0530 <[^>]*> 00000000 nop -0+0534 <[^>]*> f84fffff bnezc v0,00400534 <[^>]*> +0+0534 <[^>]*> f84fffff gssdxc1 \$f15,-1\(v0,ra\) [ ]*534: R_MIPS_PC21_S2 L0.* 0+0538 <[^>]*> 00000000 nop -0+053c <[^>]*> f85fffff bnezc v0,0000053c <[^>]*> +0+053c <[^>]*> f85fffff gssdxc1 \$f31,-1\(v0,ra\) [ ]*53c: R_MIPS_PC21_S2 .L1.*2 0+0540 <[^>]*> 00000000 nop -0+0544 <[^>]*> f8038000 jialc v1,-32768 -0+0548 <[^>]*> f8037fff jialc v1,32767 +0+0544 <[^>]*> f8038000 gssbx v1,0\(zero,s0\) +0+0548 <[^>]*> f8037fff gssdxc1 \$f3,-1\(zero,t7\) 0+054c <[^>]*> 3c43ffff aui v1,v0,0xffff 0+0550 <[^>]*> ec600000 lapc v1,00000550 <[^>]*> [ ]*550: R_MIPS_PC19_S2 .L1.*2 @@ -489,7 +489,7 @@ Disassembly of section .text: 0+057c <[^>]*> ec8bffff lwpc a0,00100578 <[^>]*> 0+0580 <[^>]*> 00000000 nop 0+0584 <[^>]*> ec83ffff lapc a0,00100580 <[^>]*> -0+0588 <[^>]*> f8040000 jalrc a0 +0+0588 <[^>]*> f8040000 gssbx a0,0\(zero,zero\) 0+058c <[^>]*> 04100000 nal 0+0590 <[^>]*> 00000000 nop 0+0594 <[^>]*> 41600004 evp diff --git a/gas/testsuite/gas/mips/unaligned-branch-r6-5.d b/gas/testsuite/gas/mips/unaligned-branch-r6-5.d index eed864a46a2..98cd63c9cd8 100644 --- a/gas/testsuite/gas/mips/unaligned-branch-r6-5.d +++ b/gas/testsuite/gas/mips/unaligned-branch-r6-5.d @@ -11,7 +11,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001008 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar0-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001010 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar0-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001018 @@ -20,7 +20,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001020 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar1-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001028 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar1-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001030 @@ -29,7 +29,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001038 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar2-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001040 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar2-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001048 @@ -38,7 +38,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001050 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar3-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001058 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar3-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001060 @@ -47,7 +47,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001068 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar4-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001070 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar4-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001078 @@ -56,7 +56,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001080 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar4-0x3 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001088 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar4-0x3 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001090 @@ -65,7 +65,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001098 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar4-0x2 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,000010a0 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar4-0x2 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,000010a8 @@ -74,7 +74,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 000010b0 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar4-0x1 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,000010b8 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar4-0x1 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,000010c0 @@ -83,7 +83,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 000010c8 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,000010d0 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,000010d8 @@ -92,7 +92,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 000010e0 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar16-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,000010e8 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar16-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,000010f0 @@ -101,7 +101,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 000010f8 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar17-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001100 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar17-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001108 @@ -110,7 +110,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001110 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar18-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001118 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar18-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001120 @@ -119,7 +119,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001128 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar18-0x3 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001130 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar18-0x3 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001138 @@ -128,7 +128,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001140 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar18-0x2 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001148 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar18-0x2 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001150 @@ -137,7 +137,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001158 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar18-0x1 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001160 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar18-0x1 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001168 @@ -146,7 +146,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001170 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar18 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001178 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar18 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001180 diff --git a/gas/testsuite/gas/mips/unaligned-branch-r6-6.d b/gas/testsuite/gas/mips/unaligned-branch-r6-6.d index bb6146bbb31..c9e0cb66d8e 100644 --- a/gas/testsuite/gas/mips/unaligned-branch-r6-6.d +++ b/gas/testsuite/gas/mips/unaligned-branch-r6-6.d @@ -11,7 +11,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001008 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar0-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001010 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar0-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001018 @@ -20,7 +20,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001020 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar1-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001028 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar1-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001030 @@ -29,7 +29,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001038 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar2-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001040 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar2-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001048 @@ -38,7 +38,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001050 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar3-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001058 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar3-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001060 @@ -47,7 +47,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001068 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar4-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001070 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar4-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001078 @@ -56,7 +56,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001080 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar4-0x3 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001088 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar4-0x3 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001090 @@ -65,7 +65,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001098 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar4-0x2 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,000010a0 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar4-0x2 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,000010a8 @@ -74,7 +74,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 000010b0 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar4-0x1 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,000010b8 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar4-0x1 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,000010c0 @@ -83,7 +83,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 000010c8 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,000010d0 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,000010d8 @@ -92,7 +92,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 000010e0 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar16-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,000010e8 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar16-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,000010f0 @@ -101,7 +101,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 000010f8 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar17-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001100 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar17-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001108 @@ -110,7 +110,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001110 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar18-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001118 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar18-0x4 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001120 @@ -119,7 +119,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001128 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar18-0x3 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001130 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar18-0x3 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001138 @@ -128,7 +128,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001140 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar18-0x2 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001148 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar18-0x2 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001150 @@ -137,7 +137,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001158 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar18-0x1 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001160 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar18-0x1 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001168 @@ -146,7 +146,7 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> c8000000 bc 00001170 [ ]*[0-9a-f]+: R_MIPS_PC26_S2 bar18 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero -[0-9a-f]+ <[^>]*> d8400000 beqzc v0,00001178 +[0-9a-f]+ <[^>]*> d8400000 gslbx zero,0\(v0,zero\) [ ]*[0-9a-f]+: R_MIPS_PC21_S2 bar18 [0-9a-f]+ <[^>]*> 00000027 nor zero,zero,zero [0-9a-f]+ <[^>]*> 10400000 beqz v0,00001180 diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 27476f3fdc1..665857f4611 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1085,7 +1085,11 @@ static const unsigned int mips_isa_table[] = { #define ASE_EVA_R6 0x02000000 /* Crypto ASE */ #define ASE_CRYPTO 0x00400000 +/* The Virtualization ASE has Global INValidate (GINV) + instructions which are only valid when both ASEs are enabled. */ +#define ASE_GINV_VIRT 0x00800000 + /* MIPS ISA defines, use instead of hardcoding ISA level. */ #define ISA_UNKNOWN 0 /* Gas internal use. */ @@ -1956,6 +1960,9 @@ extern const int bfd_mips16_num_opcodes; "J" 3-bit MFTR and MTTR sel at bit 4. "y" 5-bit control target register at bit 21 (RT). + GINV ASE usage: + "+\" 2 bit Global TLB invalidate type at bit 8 + Other: "()" Parens surrounding optional value. "," Separates operands. diff --git a/ld/testsuite/ld-mips-elf/mips-elf.exp b/ld/testsuite/ld-mips-elf/mips-elf.exp index 7ce7c35c082..7959bab9306 100644 --- a/ld/testsuite/ld-mips-elf/mips-elf.exp +++ b/ld/testsuite/ld-mips-elf/mips-elf.exp @@ -561,13 +561,6 @@ if { $linux_gnu } { {{objdump -dr pic-and-nonpic-1-micromips-rel.dd} {readelf --symbols pic-and-nonpic-1-micromips-rel.nd}} "pic-and-nonpic-1-micromips-rel.o"} - {"PIC and non-PIC test 1, microMIPS R6 (relocatable)" - "-r -melf32btsmip" "" - "-32 -EB -mips32r6" - {pic-and-nonpic-1a-micromipsr6.s pic-and-nonpic-1b-micromips.s} - {{objdump -dr pic-and-nonpic-1-micromipsr6-rel.dd} - {readelf --symbols pic-and-nonpic-1-micromipsr6-rel.nd}} - "pic-and-nonpic-1-micromipsr6-rel.o"} {"PIC and non-PIC test 1, microMIPS (static 1)" "-melf32btsmip -Tpic-and-nonpic-1.ld" "" "-32 -EB -mips2" @@ -575,13 +568,6 @@ if { $linux_gnu } { {{objdump -dr pic-and-nonpic-1-micromips.dd} {readelf --symbols pic-and-nonpic-1-micromips.nd}} "pic-and-nonpic-1-micromips-static1.o"} - {"PIC and non-PIC test 1, microMIPS R6 (static 1)" - "-melf32btsmip -Tpic-and-nonpic-1.ld" "" - "-32 -EB -mips32r6" - {pic-and-nonpic-1a-micromipsr6.s pic-and-nonpic-1b-micromips.s} - {{objdump -dr pic-and-nonpic-1-micromipsr6.dd} - {readelf --symbols pic-and-nonpic-1-micromipsr6.nd}} - "pic-and-nonpic-1-micromips-static1.o"} } # The final executable produced with the following test is supposed # to be the same as one produced with the preceding test, however @@ -824,10 +810,6 @@ run_dump_test_o32 "undefweak-overflow" run_dump_test_n32 "undefweak-overflow" [list [list name (n32)]] run_dump_test_n64 "undefweak-overflow" [list [list name (n64)]] -run_dump_test "undefweak-overflow-r6" [list [list as $abi_asflags(o32)] \ - [list ld $abi_ldflags(o32)]] - - run_dump_test_n32 "jalbal" noarch run_dump_test "mode-change-error-1" @@ -1334,9 +1316,6 @@ if { $linux_gnu && $has_abi(o32) } { run_mips_plt_test "o32 PLTs for microMIPS encoding" o32 69 1 umips-only run_mips_plt_test "o32 PLTs for microMIPS encoding (insn32)" \ o32 69 5 umips-insn32-only - run_mips_plt_test "o32 PLTs for microMIPS R6 encoding" o32 69 2 umipsr6-only - run_mips_plt_test "o32 PLTs for microMIPS R6 encoding (insn32)" \ - o32 69 6 umipsr6-insn32-only run_mips_plt_test "o32 PLTs for microMIPS branches" o32 2 1 umips-bronly run_mips_plt_test "o32 PLTs for mixed MIPS and MIPS16" \ o32 109 0 mips16 diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a-r6.dd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a-r6.dd index 80dac37cb43..a568ec542d8 100644 --- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a-r6.dd +++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a-r6.dd @@ -17,14 +17,14 @@ Disassembly of section \.text: 80c: 8f99801c lw t9,-32740\(gp\) 810: 8f828018 lw v0,-32744\(gp\) 814: 24420000 addiu v0,v0,0 - 818: d8190000 jrc t9 + 818: d8190000 gslbx t9,0\(zero,zero\) 0000081c : 81c: 3c1c0001 lui gp,0x1 820: 279c7bd4 addiu gp,gp,31700 824: 0399e021 addu gp,gp,t9 828: 8f998020 lw t9,-32736\(gp\) - 82c: d8190000 jrc t9 + 82c: d8190000 gslbx t9,0\(zero,zero\) #... Disassembly of section \.MIPS\.stubs: @@ -32,5 +32,5 @@ Disassembly of section \.MIPS\.stubs: c00: 8f998010 lw t9,-32752\(gp\) c04: 03e07825 move t7,ra c08: 2418[0-9a-f]+ li t8,[0-9]+ - c0c: f8190000 jalrc t9 + c0c: f8190000 gssbx t9,0\(zero,zero\) \.\.\. diff --git a/ld/testsuite/ld-mips-elf/undefweak-overflow-r6.d b/ld/testsuite/ld-mips-elf/undefweak-overflow-r6.d index 85574bc71f7..f4e8af9e259 100644 --- a/ld/testsuite/ld-mips-elf/undefweak-overflow-r6.d +++ b/ld/testsuite/ld-mips-elf/undefweak-overflow-r6.d @@ -4,7 +4,7 @@ #objdump: -dr --show-raw-insn #... [0-9a-f]+ <_ftext>: -[ 0-9a-f]+: d85fffff beqzc v0,20000000 <_ftext> +[ 0-9a-f]+: d85fffff gsldxc1 \$f31,-1\(v0,ra\) [ 0-9a-f]+: 00000000 nop [ 0-9a-f]+: f85ffffd bnezc v0,20000000 <_ftext> [ 0-9a-f]+: ec4ffffd lwpc v0,20000000 <_ftext> diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index a4b43504c75..d618504848c 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -175,6 +175,7 @@ decode_micromips_operand (const char *p) case ':': SINT (11, 0); case '.': BIT (2, 9, 1); /* (1 .. 4) */ case ';': SPECIAL (10, 16, SAME_RS_RT); + case '\\': BIT (2, 9, 0); /* (00 .. 11) */ } break; @@ -339,6 +340,10 @@ decode_micromips_operand (const char *p) #define XPA ASE_XPA #define XPAVZ ASE_XPA_VIRT +/* Global INValidate (GINV) support. */ +#define GINV ASE_GINV +#define GINVVZ ASE_GINV_VIRT + const struct mips_opcode micromips_opcodes[] = { /* These instructions appear first so that the disassembler will find @@ -2235,6 +2240,11 @@ const struct mips_opcode micromips_opcodes[] = {"lsa", "d,v,t,+.", 0x0000000f, 0xfc0001ff, WR_1|RD_2|RD_3, 0, I37, MSA, 0 }, {"dlsa", "d,v,t,+~", 0x58000020, 0xfc00073f, WR_1|RD_2|RD_3, 0, 0, MSA64, I69 }, {"dlsa", "d,v,t,+.", 0x58000108, 0xfc0001ff, WR_1|RD_2|RD_3, 0, I69, MSA64, 0 }, + +/* Global INValidate ASE */ +{"ginvi", "s", 0x0000617c, 0xffe0ffff, RD_1, 0, 0, GINV, 0 }, +{"ginvt", "s,+\\", 0x0000717c, 0xffe0f9ff, RD_1, 0, 0, GINV, 0 }, +{"ginvgt", "s,+\\", 0x0000797c, 0xffe0f9ff, RD_1, 0, 0, GINVVZ, 0 }, }; const int bfd_micromips_num_opcodes = diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 35caa1e945c..6b0e8723fff 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -880,6 +880,8 @@ mips_calculate_combination_ases (int opcode_isa, unsigned long opcode_ases) && ((opcode_isa & INSN_ISA_MASK) == ISA_MIPS64R6 || (opcode_isa & INSN_ISA_MASK) == ISA_MIPS32R6)) combination_ases |= ASE_EVA_R6; + if ((opcode_ases & (ASE_GINV | ASE_VIRT)) == (ASE_GINV | ASE_VIRT)) + combination_ases |= ASE_GINV_VIRT; return combination_ases; } diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index ede01e176c9..5ba19e18f3a 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -419,6 +419,7 @@ decode_mips_operand (const char *p) /* Global INValidate (GINV) support. */ #define GINV ASE_GINV +#define GINVVZ ASE_GINV_VIRT /* Loongson MultiMedia extensions Instructions (MMI) support. */ #define LMMI ASE_LOONGSON_MMI @@ -3379,6 +3380,7 @@ const struct mips_opcode mips_builtin_opcodes[] = /* MIPS Global INValidate (GINV) ASE. */ {"ginvi", "s", 0x7c00003d, 0xfc1fffff, RD_1, 0, 0, GINV, 0 }, {"ginvt", "s,+\\", 0x7c0000bd, 0xfc1ffcff, RD_1, 0, 0, GINV, 0 }, +{"ginvgt", "s,+\\", 0x7c0000fd, 0xfc1ffcff, RD_1, 0, 0, GINVVZ, 0 }, /* Move bc0* after mftr and mttr to avoid opcode collision. */ {"bc0f", "p", 0x41000000, 0xffff0000, RD_CC|CBD, 0, I1, 0, I4_32 }, -- 2.34.1