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([109.245.202.111]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5d6501d5863sm95355a12.76.2024.12.13.07.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 07:57:51 -0800 (PST) From: Milica Matic X-Google-Original-From: Milica Matic To: gdb-patches@sourceware.org Cc: milica.matic@htecgroup.com, simark@simark.ca, cfu@wavecomp.com, aburgess@redhat.com, kevinb@redhat.com, macro@orcam.me.uk, djordje.todorovic@htecgroup.com, Andrew Bennett , Faraz Shahbazker Subject: [PATCH 13/21] MIPS: Update encoding of d16mule MXU instruction Date: Fri, 13 Dec 2024 16:53:20 +0100 Message-Id: <20241213155328.406003-15-milica.matic@htecgroup.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241213155328.406003-1-milica.matic@htecgroup.com> References: <20241213155328.406003-1-milica.matic@htecgroup.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org From: Andrew Bennett The code for the d16mule instruction has been modified to encode an additional operand (xr4) in the instruction. This is reflected in the new line of code for encoding, which now uses the mask 0xff00003f instead of the previous 0xff3c003f, allowing for better precision in operand encoding. In the file gas/testsuite/gas/mips/mxu.s, the operand arguments for the d16mule instruction have been changed to now include the additional operand xr4 for each of the instruction options. Cherry-picked bc381d4 from https://github.com/MIPS/binutils-gdb Signed-off-by: Andrew Bennett Signed-off-by: Faraz Shahbazker Signed-off-by: Milica Matic --- gas/testsuite/gas/mips/mxu.d | 16 ++++++++-------- gas/testsuite/gas/mips/mxu.s | 18 +++++++++--------- opcodes/mips-opc.c | 2 +- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/gas/testsuite/gas/mips/mxu.d b/gas/testsuite/gas/mips/mxu.d index 68a54ccb671..507bd9b6b3a 100644 --- a/gas/testsuite/gas/mips/mxu.d +++ b/gas/testsuite/gas/mips/mxu.d @@ -190,14 +190,14 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> 7040c849 d16mulf xr1,xr2,xr3,LW [0-9a-f]+ <[^>]*> 7080c849 d16mulf xr1,xr2,xr3,HW [0-9a-f]+ <[^>]*> 70c0c849 d16mulf xr1,xr2,xr3,XW -[0-9a-f]+ <[^>]*> 7100c849 d16mule xr1,xr2,xr3,WW -[0-9a-f]+ <[^>]*> 7140c849 d16mule xr1,xr2,xr3,LW -[0-9a-f]+ <[^>]*> 7180c849 d16mule xr1,xr2,xr3,HW -[0-9a-f]+ <[^>]*> 71c0c849 d16mule xr1,xr2,xr3,XW -[0-9a-f]+ <[^>]*> 7100c849 d16mule xr1,xr2,xr3,WW -[0-9a-f]+ <[^>]*> 7140c849 d16mule xr1,xr2,xr3,LW -[0-9a-f]+ <[^>]*> 7180c849 d16mule xr1,xr2,xr3,HW -[0-9a-f]+ <[^>]*> 71c0c849 d16mule xr1,xr2,xr3,XW +[0-9a-f]+ <[^>]*> 7110c849 d16mule xr1,xr2,xr3,xr4,WW +[0-9a-f]+ <[^>]*> 7150c849 d16mule xr1,xr2,xr3,xr4,LW +[0-9a-f]+ <[^>]*> 7190c849 d16mule xr1,xr2,xr3,xr4,HW +[0-9a-f]+ <[^>]*> 71d0c849 d16mule xr1,xr2,xr3,xr4,XW +[0-9a-f]+ <[^>]*> 7110c849 d16mule xr1,xr2,xr3,xr4,WW +[0-9a-f]+ <[^>]*> 7150c849 d16mule xr1,xr2,xr3,xr4,LW +[0-9a-f]+ <[^>]*> 7190c849 d16mule xr1,xr2,xr3,xr4,HW +[0-9a-f]+ <[^>]*> 71d0c849 d16mule xr1,xr2,xr3,xr4,XW [0-9a-f]+ <[^>]*> 7010c84d s16mad xr1,xr2,xr3,xr4,A,WW [0-9a-f]+ <[^>]*> 7050c84d s16mad xr1,xr2,xr3,xr4,A,LW [0-9a-f]+ <[^>]*> 7090c84d s16mad xr1,xr2,xr3,xr4,A,HW diff --git a/gas/testsuite/gas/mips/mxu.s b/gas/testsuite/gas/mips/mxu.s index 76504516e65..f9643d0624c 100644 --- a/gas/testsuite/gas/mips/mxu.s +++ b/gas/testsuite/gas/mips/mxu.s @@ -138,15 +138,15 @@ test_mxu: d16mulf xr1, xr2, xr3, 2 d16mulf xr1, xr2, xr3, 3 - d16mule xr1, xr2, xr3, WW - d16mule xr1, xr2, xr3, LW - d16mule xr1, xr2, xr3, HW - d16mule xr1, xr2, xr3, XW - - d16mule xr1, xr2, xr3, 0 - d16mule xr1, xr2, xr3, 1 - d16mule xr1, xr2, xr3, 2 - d16mule xr1, xr2, xr3, 3 + d16mule xr1, xr2, xr3, xr4, WW + d16mule xr1, xr2, xr3, xr4, LW + d16mule xr1, xr2, xr3, xr4, HW + d16mule xr1, xr2, xr3, xr4, XW + + d16mule xr1, xr2, xr3, xr4, 0 + d16mule xr1, xr2, xr3, xr4, 1 + d16mule xr1, xr2, xr3, xr4, 2 + d16mule xr1, xr2, xr3, xr4, 3 s16mad xr1, xr2, xr3, xr4,A,WW s16mad xr1, xr2, xr3, xr4,A,LW diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 19fd841c873..6a4fd20a9da 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -3245,7 +3245,7 @@ const struct mips_opcode mips_builtin_opcodes[] = /* MXU Extension. */ {"d16mul", "`=,`b,`c,`d,`o", 0x70000008, 0xff00003f, TRAP, 0, 0, MXU, 0 }, {"d16mulf", "`=,`b,`c,`o", 0x70000009, 0xff3c003f, TRAP, 0, 0, MXU, 0 }, -{"d16mule", "`=,`b,`c,`o", 0x71000009, 0xff3c003f, TRAP, 0, 0, MXU, 0 }, +{"d16mule", "`=,`b,`c,`d,`o", 0x71000009, 0xff00003f, TRAP, 0, 0, MXU, 0 }, {"d16mac", "`=,`b,`c,`d,`a,`o", 0x7000000a, 0xfc00003f, TRAP, 0, 0, MXU, 0 }, {"d16macf", "`=,`b,`c,`d,`a,`o", 0x7000000b, 0xfc00003f, TRAP, 0, 0, MXU, 0 }, {"d16madl", "`=,`b,`c,`d,`a,`o", 0x7000000c, 0xfc00003f, TRAP, 0, 0, MXU, 0 }, -- 2.34.1