From: Milica Matic <milicamatic05@gmail.com>
To: gdb-patches@sourceware.org
Cc: milica.matic@htecgroup.com, simark@simark.ca, cfu@wavecomp.com,
aburgess@redhat.com, kevinb@redhat.com, macro@orcam.me.uk,
djordje.todorovic@htecgroup.com,
Andrew Bennett <andrew.bennett@imgtec.com>,
Faraz Shahbazker <fshahbazker@wavecomp.com>
Subject: [PATCH 13/21] MIPS: Update encoding of d16mule MXU instruction
Date: Fri, 13 Dec 2024 16:53:20 +0100 [thread overview]
Message-ID: <20241213155328.406003-15-milica.matic@htecgroup.com> (raw)
In-Reply-To: <20241213155328.406003-1-milica.matic@htecgroup.com>
From: Andrew Bennett <andrew.bennett@imgtec.com>
The code for the d16mule instruction has been modified to encode an
additional operand (xr4) in the instruction. This is reflected in the
new line of code for encoding, which now uses the mask 0xff00003f
instead of the previous 0xff3c003f, allowing for better precision in
operand encoding. In the file gas/testsuite/gas/mips/mxu.s, the operand
arguments for the d16mule instruction have been changed to now include
the additional operand xr4 for each of the instruction options.
Cherry-picked bc381d4
from https://github.com/MIPS/binutils-gdb
Signed-off-by: Andrew Bennett <andrew.bennett@imgtec.com>
Signed-off-by: Faraz Shahbazker <fshahbazker@wavecomp.com>
Signed-off-by: Milica Matic <milica.matic@htecgroup.com>
---
gas/testsuite/gas/mips/mxu.d | 16 ++++++++--------
gas/testsuite/gas/mips/mxu.s | 18 +++++++++---------
opcodes/mips-opc.c | 2 +-
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/gas/testsuite/gas/mips/mxu.d b/gas/testsuite/gas/mips/mxu.d
index 68a54ccb671..507bd9b6b3a 100644
--- a/gas/testsuite/gas/mips/mxu.d
+++ b/gas/testsuite/gas/mips/mxu.d
@@ -190,14 +190,14 @@ Disassembly of section \.text:
[0-9a-f]+ <[^>]*> 7040c849 d16mulf xr1,xr2,xr3,LW
[0-9a-f]+ <[^>]*> 7080c849 d16mulf xr1,xr2,xr3,HW
[0-9a-f]+ <[^>]*> 70c0c849 d16mulf xr1,xr2,xr3,XW
-[0-9a-f]+ <[^>]*> 7100c849 d16mule xr1,xr2,xr3,WW
-[0-9a-f]+ <[^>]*> 7140c849 d16mule xr1,xr2,xr3,LW
-[0-9a-f]+ <[^>]*> 7180c849 d16mule xr1,xr2,xr3,HW
-[0-9a-f]+ <[^>]*> 71c0c849 d16mule xr1,xr2,xr3,XW
-[0-9a-f]+ <[^>]*> 7100c849 d16mule xr1,xr2,xr3,WW
-[0-9a-f]+ <[^>]*> 7140c849 d16mule xr1,xr2,xr3,LW
-[0-9a-f]+ <[^>]*> 7180c849 d16mule xr1,xr2,xr3,HW
-[0-9a-f]+ <[^>]*> 71c0c849 d16mule xr1,xr2,xr3,XW
+[0-9a-f]+ <[^>]*> 7110c849 d16mule xr1,xr2,xr3,xr4,WW
+[0-9a-f]+ <[^>]*> 7150c849 d16mule xr1,xr2,xr3,xr4,LW
+[0-9a-f]+ <[^>]*> 7190c849 d16mule xr1,xr2,xr3,xr4,HW
+[0-9a-f]+ <[^>]*> 71d0c849 d16mule xr1,xr2,xr3,xr4,XW
+[0-9a-f]+ <[^>]*> 7110c849 d16mule xr1,xr2,xr3,xr4,WW
+[0-9a-f]+ <[^>]*> 7150c849 d16mule xr1,xr2,xr3,xr4,LW
+[0-9a-f]+ <[^>]*> 7190c849 d16mule xr1,xr2,xr3,xr4,HW
+[0-9a-f]+ <[^>]*> 71d0c849 d16mule xr1,xr2,xr3,xr4,XW
[0-9a-f]+ <[^>]*> 7010c84d s16mad xr1,xr2,xr3,xr4,A,WW
[0-9a-f]+ <[^>]*> 7050c84d s16mad xr1,xr2,xr3,xr4,A,LW
[0-9a-f]+ <[^>]*> 7090c84d s16mad xr1,xr2,xr3,xr4,A,HW
diff --git a/gas/testsuite/gas/mips/mxu.s b/gas/testsuite/gas/mips/mxu.s
index 76504516e65..f9643d0624c 100644
--- a/gas/testsuite/gas/mips/mxu.s
+++ b/gas/testsuite/gas/mips/mxu.s
@@ -138,15 +138,15 @@ test_mxu:
d16mulf xr1, xr2, xr3, 2
d16mulf xr1, xr2, xr3, 3
- d16mule xr1, xr2, xr3, WW
- d16mule xr1, xr2, xr3, LW
- d16mule xr1, xr2, xr3, HW
- d16mule xr1, xr2, xr3, XW
-
- d16mule xr1, xr2, xr3, 0
- d16mule xr1, xr2, xr3, 1
- d16mule xr1, xr2, xr3, 2
- d16mule xr1, xr2, xr3, 3
+ d16mule xr1, xr2, xr3, xr4, WW
+ d16mule xr1, xr2, xr3, xr4, LW
+ d16mule xr1, xr2, xr3, xr4, HW
+ d16mule xr1, xr2, xr3, xr4, XW
+
+ d16mule xr1, xr2, xr3, xr4, 0
+ d16mule xr1, xr2, xr3, xr4, 1
+ d16mule xr1, xr2, xr3, xr4, 2
+ d16mule xr1, xr2, xr3, xr4, 3
s16mad xr1, xr2, xr3, xr4,A,WW
s16mad xr1, xr2, xr3, xr4,A,LW
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 19fd841c873..6a4fd20a9da 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -3245,7 +3245,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
/* MXU Extension. */
{"d16mul", "`=,`b,`c,`d,`o", 0x70000008, 0xff00003f, TRAP, 0, 0, MXU, 0 },
{"d16mulf", "`=,`b,`c,`o", 0x70000009, 0xff3c003f, TRAP, 0, 0, MXU, 0 },
-{"d16mule", "`=,`b,`c,`o", 0x71000009, 0xff3c003f, TRAP, 0, 0, MXU, 0 },
+{"d16mule", "`=,`b,`c,`d,`o", 0x71000009, 0xff00003f, TRAP, 0, 0, MXU, 0 },
{"d16mac", "`=,`b,`c,`d,`a,`o", 0x7000000a, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
{"d16macf", "`=,`b,`c,`d,`a,`o", 0x7000000b, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
{"d16madl", "`=,`b,`c,`d,`a,`o", 0x7000000c, 0xfc00003f, TRAP, 0, 0, MXU, 0 },
--
2.34.1
next prev parent reply other threads:[~2024-12-13 16:08 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-13 15:53 [PATCH 0/21] Integrate MIPS-Specific Support into Official binutils-gdb Milica Matic
2024-12-13 15:53 ` [PATCH 00/21] " Milica Matic
2024-12-13 15:53 ` [PATCH 01/21] Don't adjust microMIPS HI/LO rel section-relative Milica Matic
2024-12-13 15:53 ` [PATCH 02/21] Add new relocations for microMIPSR6 Milica Matic
2024-12-13 15:53 ` [PATCH 03/21] Improve WARN for $0 constraint on MIPSR6 branches Milica Matic
2024-12-13 15:53 ` [PATCH 04/21] Instruction mapping support (pre-R6 to R6) Milica Matic
2024-12-13 15:53 ` [PATCH 05/21] Add microMIPSR6 support Milica Matic
2024-12-13 15:53 ` [PATCH 06/21] Update branch relaxation Milica Matic
2024-12-13 15:53 ` [PATCH 07/21] Add --user-defined-sdata-sections Milica Matic
2024-12-13 15:53 ` [PATCH 08/21] Disassembler fix Milica Matic
2024-12-13 15:53 ` [PATCH 09/21] MIPS: Add CRYPTO ASE support Milica Matic
2024-12-13 15:53 ` [PATCH 10/21] Add the m6201 architecture Milica Matic
2024-12-13 15:53 ` [PATCH 11/21] Add GINV(+VIRT) ASE for MIPSr6/microMIPS6 Milica Matic
2024-12-13 15:53 ` [PATCH 12/21] Implement the XBurst MXU extensions Milica Matic
2024-12-13 15:53 ` Milica Matic [this message]
2024-12-13 15:53 ` [PATCH 14/21] Re-arrange MXU code blocks and add comments Milica Matic
2024-12-13 15:53 ` [PATCH 15/21] Accept MCU mapped string operands as constants Milica Matic
2024-12-13 15:53 ` [PATCH 16/21] Fix addr2line mapping - garbage collected modules Milica Matic
2024-12-13 15:53 ` [PATCH 17/21] Extend trap macros to handle immediate zero Milica Matic
2024-12-13 15:53 ` [PATCH 18/21] Fix failing test cases for linux and 64-bit target Milica Matic
2024-12-13 15:53 ` [PATCH 19/21] Remove exec permission tc-mips.c Milica Matic
2024-12-13 15:53 ` [PATCH 20/21] Workaround for line info in compressed MIPS func Milica Matic
2024-12-13 15:53 ` [PATCH 21/21] Fix gold linker build issues for mingw Milica Matic
2025-01-07 21:18 ` [PATCH 0/21] Integrate MIPS-Specific Support into Official binutils-gdb Kevin Buettner
2025-01-09 1:11 ` [EXTERNAL]Re: " Chao-ying Fu
2025-01-07 21:31 ` Kevin Buettner
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