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([109.245.202.111]) by smtp.googlemail.com with ESMTPSA id 4fb4d7f45d1cf-5d6501d5863sm95355a12.76.2024.12.13.07.57.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Dec 2024 07:57:36 -0800 (PST) From: Milica Matic X-Google-Original-From: Milica Matic To: gdb-patches@sourceware.org Cc: milica.matic@htecgroup.com, simark@simark.ca, cfu@wavecomp.com, aburgess@redhat.com, kevinb@redhat.com, macro@orcam.me.uk, djordje.todorovic@htecgroup.com, Robert Suchanek , Faraz Shahbazker Subject: [PATCH 04/21] Instruction mapping support (pre-R6 to R6). Date: Fri, 13 Dec 2024 16:53:11 +0100 Message-Id: <20241213155328.406003-6-milica.matic@htecgroup.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241213155328.406003-1-milica.matic@htecgroup.com> References: <20241213155328.406003-1-milica.matic@htecgroup.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org From: Robert Suchanek Enhancing MIPS R6 support in the assembler by providing reliable mapping between pre-R6 and R6 instructions, along with mechanisms for detecting and addressing potential issues in optimizations. Add function is_isa_r6. Cherry-picked 6ebc24a from https://github.com/MIPS/binutils-gdb Signed-off-by: Robert Suchanek Signed-off-by: Faraz Shahbazker Signed-off-by: Milica Matic Conflicts: gas/config/tc-mips.c include/opcode/mips.h opcodes/mips-dis.c --- gas/config/tc-mips.c | 34 +++++++++++++++++++++++++++++++++- include/opcode/mips.h | 2 ++ opcodes/mips-dis.c | 19 +++++++++++++++---- 3 files changed, 50 insertions(+), 5 deletions(-) diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index f135745be4d..ddaa0bd5efc 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -7743,6 +7743,37 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr, address_expr->X_add_number); *reloc_type = BFD_RELOC_UNUSED; } + else if (mips_opts.micromips + && ISA_IS_R6 (mips_opts.isa) + /* microMIPS pre-R6 to R6 branch/jump instruction mapping in + noreorder block is restricted to have only a nop in the delay + slot. */ + && compact_branch_p (&history[0]) + && (history[0].insn_mo->pinfo2 & INSN2_CONVERTED_TO_COMPACT) + && history[0].noreorder_p + && strcmp (ip->insn_mo->name, "nop") != 0) + { + as_bad (_("unable to convert `%s' to its compact form because it has a non NOP " + "instruction (`%s') in its delay slot. Please move the delay slot " + "instruction before the branch and disable noreorder."), + history[0].insn_mo->name, ip->insn_mo->name); + add_fixed_insn (ip); + } + else if (mips_opts.micromips + && ISA_IS_R6 (mips_opts.isa) + && history[0].noreorder_p + && (strcmp (history[0].insn_mo->name, "bal") == 0 + || strcmp (history[0].insn_mo->name, "jal") == 0 + || strcmp (history[0].insn_mo->name, "jalr") == 0 + || strcmp (history[0].insn_mo->name, "bgezal") == 0 + || strcmp (history[0].insn_mo->name, "bltzal") == 0)) + { + as_bad (_("unable to convert `%s' to its compact form because the link register " + "would have a different value. Please move the delay slot instruction " + "before the branch and disable noreorder."), + history[0].insn_mo->name); + add_fixed_insn (ip); + } else if (mips_opts.micromips && address_expr && ((relax32 && *reloc_type == BFD_RELOC_16_PCREL_S2) @@ -8076,8 +8107,9 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr, } /* If we have just completed an unconditional branch, clear the history. */ - if ((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) + if (((delayed_branch_p (&history[1]) && uncond_branch_p (&history[1])) || (compact_branch_p (&history[0]) && uncond_branch_p (&history[0]))) + && !(history[0].insn_mo->pinfo2 & INSN2_CONVERTED_TO_COMPACT)) { unsigned int i; diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 4a5d3638c87..bd247ffd0f0 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -887,6 +887,8 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) encoding is needed or otherwise the final EXTEND entry will apply, for the disassembly of the prefix only. */ #define INSN2_SHORT_ONLY 0x00010000 +/* This indicates pre-R6 instructions mapped to R6 ones. */ +#define INSN2_CONVERTED_TO_COMPACT 0x00020000 /* Masks used to mark instructions to indicate which MIPS ISA level they were introduced in. INSN_ISA_MASK masks an enumeration that diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index ad5ec8ab9b2..4861150d0dd 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -818,6 +818,17 @@ is_micromips (Elf_Internal_Ehdr *header) return 0; } +/* Check if ISA is R6. */ + +static inline int +is_isa_r6 (unsigned long isa) +{ + if ((isa & INSN_ISA_MASK) == ISA_MIPS32R6 + || ((isa & INSN_ISA_MASK) == ISA_MIPS64R6)) + return 1; + return 0; +} + /* Convert ASE flags from .MIPS.abiflags to internal values. */ static unsigned long @@ -2041,10 +2052,10 @@ print_insn_mips (bfd_vma memaddr, && (word & op->mask) == op->match) { /* We always disassemble the jalx instruction, except for MIPS r6. */ - if (!opcode_is_member (op, mips_isa, mips_ase, mips_processor) - && (strcmp (op->name, "jalx") - || (mips_isa & INSN_ISA_MASK) == ISA_MIPS32R6 - || (mips_isa & INSN_ISA_MASK) == ISA_MIPS64R6)) + if ((!opcode_is_member (op, mips_isa, mips_ase, mips_processor) + && (strcmp (op->name, "jalx") || is_isa_r6 (mips_isa))) + || (is_isa_r6 (op->membership) + && (op->pinfo2 & INSN2_CONVERTED_TO_COMPACT))) continue; /* Figure out instruction type and branch delay information. */ -- 2.34.1