* [PATCH 09/18] sim: or1k: regenerate sim files
2016-11-23 22:14 [PATCH 00/18] sim: port for OpenRISC Stafford Horne
` (5 preceding siblings ...)
2016-11-23 22:16 ` [PATCH 06/18] sim: or1k: fix branching and exceptions in sim Stafford Horne
@ 2016-11-23 22:16 ` Stafford Horne
2016-11-23 22:16 ` [PATCH 01/18] sim: cgen: add rem (remainder) function (needed for OR1K lf.rem.[sd]) Stafford Horne
` (10 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Stafford Horne @ 2016-11-23 22:16 UTC (permalink / raw)
To: gdb-patches; +Cc: openrisc, Peter Gavin
From: Peter Gavin <pgavin@gmail.com>
sim/or1k/ChangeLog:
* cpu32.c: regenerate
* cpu32.h: ditto
* cpu64.c: ditto
* cpu64.h: ditto
* decode32.c: ditto
* decode32.h: ditto
* decode64.c: ditto
* decode64.h: ditto
* model32.c: ditto
* sem32.c: ditto
* sem32-switch.c: ditto
* sem64.c: ditto
* sem64-switch.c: ditto
---
sim/or1k/ChangeLog | 16 ++++
sim/or1k/cpu32.c | 16 ++++
sim/or1k/cpu32.h | 36 ++++-----
sim/or1k/cpu64.c | 16 ++++
sim/or1k/cpu64.h | 36 ++++-----
sim/or1k/decode32.c | 197 ++++++++++++++++++-----------------------------
sim/or1k/decode32.h | 31 ++++----
sim/or1k/decode64.c | 201 +++++++++++++++++++-----------------------------
sim/or1k/decode64.h | 33 ++++----
sim/or1k/model32.c | 152 ++++++++++++++++++------------------
sim/or1k/sem32-switch.c | 138 ++++++++++++++++-----------------
sim/or1k/sem32.c | 170 ++++++++++++++++++++--------------------
sim/or1k/sem64-switch.c | 138 ++++++++++++++++-----------------
sim/or1k/sem64.c | 170 ++++++++++++++++++++--------------------
14 files changed, 633 insertions(+), 717 deletions(-)
diff --git a/sim/or1k/ChangeLog b/sim/or1k/ChangeLog
index 5d120fe..c1038c3 100644
--- a/sim/or1k/ChangeLog
+++ b/sim/or1k/ChangeLog
@@ -1,5 +1,21 @@
2012-06-22 Peter Gavin <pgavin@gmail.com>
+ * cpu32.c: regenerate
+ * cpu32.h: ditto
+ * cpu64.c: ditto
+ * cpu64.h: ditto
+ * decode32.c: ditto
+ * decode32.h: ditto
+ * decode64.c: ditto
+ * decode64.h: ditto
+ * model32.c: ditto
+ * sem32.c: ditto
+ * sem32-switch.c: ditto
+ * sem64.c: ditto
+ * sem64-switch.c: ditto
+
+2012-06-22 Peter Gavin <pgavin@gmail.com>
+
* or1k.c:
(or1k32bf_fl1) fix bug
diff --git a/sim/or1k/cpu32.c b/sim/or1k/cpu32.c
index d503534..36b4040 100644
--- a/sim/or1k/cpu32.c
+++ b/sim/or1k/cpu32.c
@@ -9292,6 +9292,22 @@ or1k32bf_h_mac_machi_set (SIM_CPU *current_cpu, USI newval)
SET_H_MAC_MACHI (newval);
}
+/* Get the value of h-tick-ttmr. */
+
+USI
+or1k32bf_h_tick_ttmr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_TICK_TTMR ();
+}
+
+/* Set a value for h-tick-ttmr. */
+
+void
+or1k32bf_h_tick_ttmr_set (SIM_CPU *current_cpu, USI newval)
+{
+ SET_H_TICK_TTMR (newval);
+}
+
/* Get the value of h-sys-vr-rev. */
USI
diff --git a/sim/or1k/cpu32.h b/sim/or1k/cpu32.h
index e3a8276..a31a935 100644
--- a/sim/or1k/cpu32.h
+++ b/sim/or1k/cpu32.h
@@ -2944,6 +2944,11 @@ SET_H_SPR (ORSI (SLLSI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACLO), (x));\
do { \
SET_H_SPR (ORSI (SLLSI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACHI), (x));\
;} while (0)
+#define GET_H_TICK_TTMR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_TICK, 11), SPR_INDEX_TICK_TTMR))
+#define SET_H_TICK_TTMR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_TICK, 11), SPR_INDEX_TICK_TTMR), (x));\
+;} while (0)
#define GET_H_SYS_VR_REV() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), 5, 0)
#define SET_H_SYS_VR_REV(x) \
do { \
@@ -4364,6 +4369,8 @@ USI or1k32bf_h_mac_maclo_get (SIM_CPU *);
void or1k32bf_h_mac_maclo_set (SIM_CPU *, USI);
USI or1k32bf_h_mac_machi_get (SIM_CPU *);
void or1k32bf_h_mac_machi_set (SIM_CPU *, USI);
+USI or1k32bf_h_tick_ttmr_get (SIM_CPU *);
+void or1k32bf_h_tick_ttmr_set (SIM_CPU *, USI);
USI or1k32bf_h_sys_vr_rev_get (SIM_CPU *);
void or1k32bf_h_sys_vr_rev_set (SIM_CPU *, USI);
USI or1k32bf_h_sys_vr_cfg_get (SIM_CPU *);
@@ -4822,14 +4829,14 @@ struct scache {
f_resv_7_4 = EXTRACT_LSB0_UINT (insn, 32, 7, 4); \
f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-#define EXTRACT_IFMT_L_SFGTU_VARS \
+#define EXTRACT_IFMT_L_SFGTS_VARS \
UINT f_opcode; \
UINT f_op_25_5; \
UINT f_r2; \
UINT f_r3; \
UINT f_resv_10_11; \
unsigned int length;
-#define EXTRACT_IFMT_L_SFGTU_CODE \
+#define EXTRACT_IFMT_L_SFGTS_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
@@ -4837,19 +4844,6 @@ struct scache {
f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
f_resv_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
-#define EXTRACT_IFMT_L_SFGTUI_VARS \
- UINT f_opcode; \
- UINT f_op_25_5; \
- UINT f_r2; \
- UINT f_uimm16; \
- unsigned int length;
-#define EXTRACT_IFMT_L_SFGTUI_CODE \
- length = 4; \
- f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
- f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
- f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
- f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
-
#define EXTRACT_IFMT_L_SFGTSI_VARS \
UINT f_opcode; \
UINT f_op_25_5; \
@@ -4882,20 +4876,16 @@ struct scache {
#define EXTRACT_IFMT_L_MACI_VARS \
UINT f_opcode; \
- UINT f_resv_20_5; \
+ UINT f_resv_25_5; \
UINT f_r2; \
- UINT f_imm16_25_5; \
- UINT f_imm16_10_11; \
- INT f_simm16_split; \
+ INT f_simm16; \
unsigned int length;
#define EXTRACT_IFMT_L_MACI_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
- f_resv_20_5 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
- f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
- f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
- f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));\
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
#define EXTRACT_IFMT_LF_ADD_S_VARS \
UINT f_opcode; \
diff --git a/sim/or1k/cpu64.c b/sim/or1k/cpu64.c
index 1cb4487..cd25e89 100644
--- a/sim/or1k/cpu64.c
+++ b/sim/or1k/cpu64.c
@@ -9308,6 +9308,22 @@ or1k64bf_h_mac_machi_set (SIM_CPU *current_cpu, UDI newval)
SET_H_MAC_MACHI (newval);
}
+/* Get the value of h-tick-ttmr. */
+
+UDI
+or1k64bf_h_tick_ttmr_get (SIM_CPU *current_cpu)
+{
+ return GET_H_TICK_TTMR ();
+}
+
+/* Set a value for h-tick-ttmr. */
+
+void
+or1k64bf_h_tick_ttmr_set (SIM_CPU *current_cpu, UDI newval)
+{
+ SET_H_TICK_TTMR (newval);
+}
+
/* Get the value of h-sys-vr-rev. */
UDI
diff --git a/sim/or1k/cpu64.h b/sim/or1k/cpu64.h
index c17c960..5bfbf9e 100644
--- a/sim/or1k/cpu64.h
+++ b/sim/or1k/cpu64.h
@@ -2949,6 +2949,11 @@ SET_H_SPR (ORDI (SLLDI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACLO), (x));\
do { \
SET_H_SPR (ORDI (SLLDI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACHI), (x));\
;} while (0)
+#define GET_H_TICK_TTMR() GET_H_SPR (ORDI (SLLDI (SPR_GROUP_TICK, 11), SPR_INDEX_TICK_TTMR))
+#define SET_H_TICK_TTMR(x) \
+do { \
+SET_H_SPR (ORDI (SLLDI (SPR_GROUP_TICK, 11), SPR_INDEX_TICK_TTMR), (x));\
+;} while (0)
#define GET_H_SYS_VR_REV() or1k64bf_h_spr_field_get_raw (current_cpu, ORDI (SLLDI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), 5, 0)
#define SET_H_SYS_VR_REV(x) \
do { \
@@ -4371,6 +4376,8 @@ UDI or1k64bf_h_mac_maclo_get (SIM_CPU *);
void or1k64bf_h_mac_maclo_set (SIM_CPU *, UDI);
UDI or1k64bf_h_mac_machi_get (SIM_CPU *);
void or1k64bf_h_mac_machi_set (SIM_CPU *, UDI);
+UDI or1k64bf_h_tick_ttmr_get (SIM_CPU *);
+void or1k64bf_h_tick_ttmr_set (SIM_CPU *, UDI);
UDI or1k64bf_h_sys_vr_rev_get (SIM_CPU *);
void or1k64bf_h_sys_vr_rev_set (SIM_CPU *, UDI);
UDI or1k64bf_h_sys_vr_cfg_get (SIM_CPU *);
@@ -4821,14 +4828,14 @@ struct scache {
f_resv_7_4 = EXTRACT_LSB0_UINT (insn, 32, 7, 4); \
f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
-#define EXTRACT_IFMT_L_SFGTU_VARS \
+#define EXTRACT_IFMT_L_SFGTS_VARS \
UINT f_opcode; \
UINT f_op_25_5; \
UINT f_r2; \
UINT f_r3; \
UINT f_resv_10_11; \
unsigned int length;
-#define EXTRACT_IFMT_L_SFGTU_CODE \
+#define EXTRACT_IFMT_L_SFGTS_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
@@ -4836,19 +4843,6 @@ struct scache {
f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
f_resv_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
-#define EXTRACT_IFMT_L_SFGTUI_VARS \
- UINT f_opcode; \
- UINT f_op_25_5; \
- UINT f_r2; \
- UINT f_uimm16; \
- unsigned int length;
-#define EXTRACT_IFMT_L_SFGTUI_CODE \
- length = 4; \
- f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
- f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
- f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
- f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
-
#define EXTRACT_IFMT_L_SFGTSI_VARS \
UINT f_opcode; \
UINT f_op_25_5; \
@@ -4881,20 +4875,16 @@ struct scache {
#define EXTRACT_IFMT_L_MACI_VARS \
UINT f_opcode; \
- UINT f_resv_20_5; \
+ UINT f_resv_25_5; \
UINT f_r2; \
- UINT f_imm16_25_5; \
- UINT f_imm16_10_11; \
- INT f_simm16_split; \
+ INT f_simm16; \
unsigned int length;
#define EXTRACT_IFMT_L_MACI_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
- f_resv_20_5 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
- f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
- f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
- f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));\
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
#define EXTRACT_IFMT_LF_ADD_S_VARS \
UINT f_opcode; \
diff --git a/sim/or1k/decode32.c b/sim/or1k/decode32.c
index b04bfb4..04b29f4 100644
--- a/sim/or1k/decode32.c
+++ b/sim/or1k/decode32.c
@@ -54,7 +54,7 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_L_BF, OR1K32BF_INSN_L_BF, OR1K32BF_SFMT_L_BNF },
{ OR1K_INSN_L_TRAP, OR1K32BF_INSN_L_TRAP, OR1K32BF_SFMT_L_TRAP },
{ OR1K_INSN_L_SYS, OR1K32BF_INSN_L_SYS, OR1K32BF_SFMT_L_TRAP },
- { OR1K_INSN_L_RFE, OR1K32BF_INSN_L_RFE, OR1K32BF_SFMT_L_TRAP },
+ { OR1K_INSN_L_RFE, OR1K32BF_INSN_L_RFE, OR1K32BF_SFMT_L_RFE },
{ OR1K_INSN_L_NOP_IMM, OR1K32BF_INSN_L_NOP_IMM, OR1K32BF_SFMT_L_NOP_IMM },
{ OR1K_INSN_L_MOVHI, OR1K32BF_INSN_L_MOVHI, OR1K32BF_SFMT_L_MOVHI },
{ OR1K_INSN_L_MACRC, OR1K32BF_INSN_L_MACRC, OR1K32BF_SFMT_L_MACRC },
@@ -89,8 +89,8 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_L_DIVU, OR1K32BF_INSN_L_DIVU, OR1K32BF_SFMT_L_DIV },
{ OR1K_INSN_L_FF1, OR1K32BF_INSN_L_FF1, OR1K32BF_SFMT_L_FF1 },
{ OR1K_INSN_L_FL1, OR1K32BF_INSN_L_FL1, OR1K32BF_SFMT_L_FF1 },
- { OR1K_INSN_L_ANDI, OR1K32BF_INSN_L_ANDI, OR1K32BF_SFMT_L_ANDI },
- { OR1K_INSN_L_ORI, OR1K32BF_INSN_L_ORI, OR1K32BF_SFMT_L_ANDI },
+ { OR1K_INSN_L_ANDI, OR1K32BF_INSN_L_ANDI, OR1K32BF_SFMT_L_MFSPR },
+ { OR1K_INSN_L_ORI, OR1K32BF_INSN_L_ORI, OR1K32BF_SFMT_L_MFSPR },
{ OR1K_INSN_L_XORI, OR1K32BF_INSN_L_XORI, OR1K32BF_SFMT_L_XORI },
{ OR1K_INSN_L_ADDI, OR1K32BF_INSN_L_ADDI, OR1K32BF_SFMT_L_ADDI },
{ OR1K_INSN_L_ADDIC, OR1K32BF_INSN_L_ADDIC, OR1K32BF_SFMT_L_ADDIC },
@@ -102,37 +102,37 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_L_EXTWS, OR1K32BF_INSN_L_EXTWS, OR1K32BF_SFMT_L_EXTHS },
{ OR1K_INSN_L_EXTWZ, OR1K32BF_INSN_L_EXTWZ, OR1K32BF_SFMT_L_EXTHS },
{ OR1K_INSN_L_CMOV, OR1K32BF_INSN_L_CMOV, OR1K32BF_SFMT_L_CMOV },
- { OR1K_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTU, OR1K32BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEU, OR1K32BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTU, OR1K32BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEU, OR1K32BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFGTS, OR1K32BF_INSN_L_SFGTS, OR1K32BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFGES, OR1K32BF_INSN_L_SFGES, OR1K32BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFLTS, OR1K32BF_INSN_L_SFLTS, OR1K32BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFLES, OR1K32BF_INSN_L_SFLES, OR1K32BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_SFMT_L_SFGTUI },
- { OR1K_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_SFMT_L_SFGTUI },
- { OR1K_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_SFMT_L_SFGTUI },
- { OR1K_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_SFMT_L_SFGTUI },
+ { OR1K_INSN_L_SFGTS, OR1K32BF_INSN_L_SFGTS, OR1K32BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFGTSI, OR1K32BF_INSN_L_SFGTSI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTU, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFGES, OR1K32BF_INSN_L_SFGES, OR1K32BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFGESI, OR1K32BF_INSN_L_SFGESI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEU, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFLTS, OR1K32BF_INSN_L_SFLTS, OR1K32BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFLTSI, OR1K32BF_INSN_L_SFLTSI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTU, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFLES, OR1K32BF_INSN_L_SFLES, OR1K32BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFLESI, OR1K32BF_INSN_L_SFLESI, OR1K32BF_SFMT_L_SFGTSI },
- { OR1K_INSN_L_SFEQ, OR1K32BF_INSN_L_SFEQ, OR1K32BF_SFMT_L_SFGTU },
+ { OR1K_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEU, OR1K32BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFEQ, OR1K32BF_INSN_L_SFEQ, OR1K32BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFEQI, OR1K32BF_INSN_L_SFEQI, OR1K32BF_SFMT_L_SFGTSI },
- { OR1K_INSN_L_SFNE, OR1K32BF_INSN_L_SFNE, OR1K32BF_SFMT_L_SFGTU },
+ { OR1K_INSN_L_SFNE, OR1K32BF_INSN_L_SFNE, OR1K32BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFNEI, OR1K32BF_INSN_L_SFNEI, OR1K32BF_SFMT_L_SFGTSI },
{ OR1K_INSN_L_MAC, OR1K32BF_INSN_L_MAC, OR1K32BF_SFMT_L_MAC },
{ OR1K_INSN_L_MSB, OR1K32BF_INSN_L_MSB, OR1K32BF_SFMT_L_MAC },
{ OR1K_INSN_L_MACI, OR1K32BF_INSN_L_MACI, OR1K32BF_SFMT_L_MACI },
- { OR1K_INSN_L_CUST1, OR1K32BF_INSN_L_CUST1, OR1K32BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST2, OR1K32BF_INSN_L_CUST2, OR1K32BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST3, OR1K32BF_INSN_L_CUST3, OR1K32BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST4, OR1K32BF_INSN_L_CUST4, OR1K32BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST5, OR1K32BF_INSN_L_CUST5, OR1K32BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST6, OR1K32BF_INSN_L_CUST6, OR1K32BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST7, OR1K32BF_INSN_L_CUST7, OR1K32BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST8, OR1K32BF_INSN_L_CUST8, OR1K32BF_SFMT_L_CUST1 },
+ { OR1K_INSN_L_CUST1, OR1K32BF_INSN_L_CUST1, OR1K32BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST2, OR1K32BF_INSN_L_CUST2, OR1K32BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST3, OR1K32BF_INSN_L_CUST3, OR1K32BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST4, OR1K32BF_INSN_L_CUST4, OR1K32BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST5, OR1K32BF_INSN_L_CUST5, OR1K32BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST6, OR1K32BF_INSN_L_CUST6, OR1K32BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST7, OR1K32BF_INSN_L_CUST7, OR1K32BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST8, OR1K32BF_INSN_L_CUST8, OR1K32BF_SFMT_L_RFE },
{ OR1K_INSN_LF_ADD_S, OR1K32BF_INSN_LF_ADD_S, OR1K32BF_SFMT_LF_ADD_S },
{ OR1K_INSN_LF_SUB_S, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_SFMT_LF_ADD_S },
{ OR1K_INSN_LF_MUL_S, OR1K32BF_INSN_LF_MUL_S, OR1K32BF_SFMT_LF_ADD_S },
@@ -147,7 +147,7 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_LF_LT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_SFMT_LF_EQ_S },
{ OR1K_INSN_LF_LE_S, OR1K32BF_INSN_LF_LE_S, OR1K32BF_SFMT_LF_EQ_S },
{ OR1K_INSN_LF_MADD_S, OR1K32BF_INSN_LF_MADD_S, OR1K32BF_SFMT_LF_MADD_S },
- { OR1K_INSN_LF_CUST1_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_SFMT_L_CUST1 },
+ { OR1K_INSN_LF_CUST1_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_SFMT_L_RFE },
};
static const struct insn_sem or1k32bf_insn_sem_invalid =
@@ -490,7 +490,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
}
case 288 :
if ((entire_insn & 0xffffffff) == 0x24000000)
- { itype = OR1K32BF_INSN_L_RFE; goto extract_sfmt_l_trap; }
+ { itype = OR1K32BF_INSN_L_RFE; goto extract_sfmt_l_rfe; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 544 :
if ((entire_insn & 0xffff07ff) == 0x44000000)
@@ -532,24 +532,24 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 637 : /* fall through */
case 638 : /* fall through */
case 639 :
- if ((entire_insn & 0xfc1f0000) == 0x4c000000)
+ if ((entire_insn & 0xffe00000) == 0x4c000000)
{ itype = OR1K32BF_INSN_L_MACI; goto extract_sfmt_l_maci; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 896 :
if ((entire_insn & 0xffffffff) == 0x70000000)
- { itype = OR1K32BF_INSN_L_CUST1; goto extract_sfmt_l_cust1; }
+ { itype = OR1K32BF_INSN_L_CUST1; goto extract_sfmt_l_rfe; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 928 :
if ((entire_insn & 0xffffffff) == 0x74000000)
- { itype = OR1K32BF_INSN_L_CUST2; goto extract_sfmt_l_cust1; }
+ { itype = OR1K32BF_INSN_L_CUST2; goto extract_sfmt_l_rfe; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 960 :
if ((entire_insn & 0xffffffff) == 0x78000000)
- { itype = OR1K32BF_INSN_L_CUST3; goto extract_sfmt_l_cust1; }
+ { itype = OR1K32BF_INSN_L_CUST3; goto extract_sfmt_l_rfe; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 992 :
if ((entire_insn & 0xffffffff) == 0x7c000000)
- { itype = OR1K32BF_INSN_L_CUST4; goto extract_sfmt_l_cust1; }
+ { itype = OR1K32BF_INSN_L_CUST4; goto extract_sfmt_l_rfe; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1056 : /* fall through */
case 1057 : /* fall through */
@@ -838,7 +838,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 1340 : /* fall through */
case 1341 : /* fall through */
case 1342 : /* fall through */
- case 1343 : itype = OR1K32BF_INSN_L_ANDI; goto extract_sfmt_l_andi;
+ case 1343 : itype = OR1K32BF_INSN_L_ANDI; goto extract_sfmt_l_mfspr;
case 1344 : /* fall through */
case 1345 : /* fall through */
case 1346 : /* fall through */
@@ -870,7 +870,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 1372 : /* fall through */
case 1373 : /* fall through */
case 1374 : /* fall through */
- case 1375 : itype = OR1K32BF_INSN_L_ORI; goto extract_sfmt_l_andi;
+ case 1375 : itype = OR1K32BF_INSN_L_ORI; goto extract_sfmt_l_mfspr;
case 1376 : /* fall through */
case 1377 : /* fall through */
case 1378 : /* fall through */
@@ -1075,19 +1075,19 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2 :
if ((entire_insn & 0xffe00000) == 0xbc400000)
- { itype = OR1K32BF_INSN_L_SFGTUI; goto extract_sfmt_l_sfgtui; }
+ { itype = OR1K32BF_INSN_L_SFGTUI; goto extract_sfmt_l_sfgtsi; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 3 :
if ((entire_insn & 0xffe00000) == 0xbc600000)
- { itype = OR1K32BF_INSN_L_SFGEUI; goto extract_sfmt_l_sfgtui; }
+ { itype = OR1K32BF_INSN_L_SFGEUI; goto extract_sfmt_l_sfgtsi; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 4 :
if ((entire_insn & 0xffe00000) == 0xbc800000)
- { itype = OR1K32BF_INSN_L_SFLTUI; goto extract_sfmt_l_sfgtui; }
+ { itype = OR1K32BF_INSN_L_SFLTUI; goto extract_sfmt_l_sfgtsi; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 5 :
if ((entire_insn & 0xffe00000) == 0xbca00000)
- { itype = OR1K32BF_INSN_L_SFLEUI; goto extract_sfmt_l_sfgtui; }
+ { itype = OR1K32BF_INSN_L_SFLEUI; goto extract_sfmt_l_sfgtsi; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 10 :
if ((entire_insn & 0xffe00000) == 0xbd400000)
@@ -1206,7 +1206,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1616 :
if ((entire_insn & 0xffe007ff) == 0xc80000d0)
- { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_cust1; }
+ { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_rfe; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1696 : /* fall through */
case 1697 : /* fall through */
@@ -1443,62 +1443,62 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0xe4000000)
- { itype = OR1K32BF_INSN_L_SFEQ; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K32BF_INSN_L_SFEQ; goto extract_sfmt_l_sfgts; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0xe4200000)
- { itype = OR1K32BF_INSN_L_SFNE; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K32BF_INSN_L_SFNE; goto extract_sfmt_l_sfgts; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2 :
if ((entire_insn & 0xffe007ff) == 0xe4400000)
- { itype = OR1K32BF_INSN_L_SFGTU; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K32BF_INSN_L_SFGTU; goto extract_sfmt_l_sfgts; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 3 :
if ((entire_insn & 0xffe007ff) == 0xe4600000)
- { itype = OR1K32BF_INSN_L_SFGEU; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K32BF_INSN_L_SFGEU; goto extract_sfmt_l_sfgts; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 4 :
if ((entire_insn & 0xffe007ff) == 0xe4800000)
- { itype = OR1K32BF_INSN_L_SFLTU; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K32BF_INSN_L_SFLTU; goto extract_sfmt_l_sfgts; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 5 :
if ((entire_insn & 0xffe007ff) == 0xe4a00000)
- { itype = OR1K32BF_INSN_L_SFLEU; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K32BF_INSN_L_SFLEU; goto extract_sfmt_l_sfgts; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 10 :
if ((entire_insn & 0xffe007ff) == 0xe5400000)
- { itype = OR1K32BF_INSN_L_SFGTS; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K32BF_INSN_L_SFGTS; goto extract_sfmt_l_sfgts; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 11 :
if ((entire_insn & 0xffe007ff) == 0xe5600000)
- { itype = OR1K32BF_INSN_L_SFGES; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K32BF_INSN_L_SFGES; goto extract_sfmt_l_sfgts; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 12 :
if ((entire_insn & 0xffe007ff) == 0xe5800000)
- { itype = OR1K32BF_INSN_L_SFLTS; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K32BF_INSN_L_SFLTS; goto extract_sfmt_l_sfgts; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 13 :
if ((entire_insn & 0xffe007ff) == 0xe5a00000)
- { itype = OR1K32BF_INSN_L_SFLES; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K32BF_INSN_L_SFLES; goto extract_sfmt_l_sfgts; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
case 1920 :
if ((entire_insn & 0xffffffff) == 0xf0000000)
- { itype = OR1K32BF_INSN_L_CUST5; goto extract_sfmt_l_cust1; }
+ { itype = OR1K32BF_INSN_L_CUST5; goto extract_sfmt_l_rfe; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1952 :
if ((entire_insn & 0xffffffff) == 0xf4000000)
- { itype = OR1K32BF_INSN_L_CUST6; goto extract_sfmt_l_cust1; }
+ { itype = OR1K32BF_INSN_L_CUST6; goto extract_sfmt_l_rfe; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1984 :
if ((entire_insn & 0xffffffff) == 0xf8000000)
- { itype = OR1K32BF_INSN_L_CUST7; goto extract_sfmt_l_cust1; }
+ { itype = OR1K32BF_INSN_L_CUST7; goto extract_sfmt_l_rfe; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2016 :
if ((entire_insn & 0xffffffff) == 0xfc000000)
- { itype = OR1K32BF_INSN_L_CUST8; goto extract_sfmt_l_cust1; }
+ { itype = OR1K32BF_INSN_L_CUST8; goto extract_sfmt_l_rfe; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -1618,6 +1618,19 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
+ extract_sfmt_l_rfe:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_rfe", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
extract_sfmt_l_nop_imm:
{
const IDESC *idesc = &or1k32bf_insn_data[itype];
@@ -1686,10 +1699,10 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
/* Record the fields for the semantic handler. */
- FLD (f_r1) = f_r1;
FLD (f_r2) = f_r2;
FLD (f_uimm16) = f_uimm16;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_mfspr", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, (char *) 0));
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_mfspr", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
#undef FLD
return idesc;
@@ -2099,29 +2112,6 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
- extract_sfmt_l_andi:
- {
- const IDESC *idesc = &or1k32bf_insn_data[itype];
- CGEN_INSN_WORD insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
- UINT f_r1;
- UINT f_r2;
- UINT f_uimm16;
-
- f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
- f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
- f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
-
- /* Record the fields for the semantic handler. */
- FLD (f_r2) = f_r2;
- FLD (f_uimm16) = f_uimm16;
- FLD (f_r1) = f_r1;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_andi", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
-
-#undef FLD
- return idesc;
- }
-
extract_sfmt_l_xori:
{
const IDESC *idesc = &or1k32bf_insn_data[itype];
@@ -2234,7 +2224,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
- extract_sfmt_l_sfgtu:
+ extract_sfmt_l_sfgts:
{
const IDESC *idesc = &or1k32bf_insn_data[itype];
CGEN_INSN_WORD insn = entire_insn;
@@ -2248,27 +2238,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
FLD (f_r3) = f_r3;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sfgtu", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
-
-#undef FLD
- return idesc;
- }
-
- extract_sfmt_l_sfgtui:
- {
- const IDESC *idesc = &or1k32bf_insn_data[itype];
- CGEN_INSN_WORD insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
- UINT f_r2;
- UINT f_uimm16;
-
- f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
- f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
-
- /* Record the fields for the semantic handler. */
- FLD (f_r2) = f_r2;
- FLD (f_uimm16) = f_uimm16;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sfgtui", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, (char *) 0));
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sfgts", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
#undef FLD
return idesc;
@@ -2318,34 +2288,17 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
const IDESC *idesc = &or1k32bf_insn_data[itype];
CGEN_INSN_WORD insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_l_sw.f
- UINT f_imm16_25_5;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
UINT f_r2;
- UINT f_imm16_10_11;
- INT f_simm16_split;
+ INT f_simm16;
- f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
- f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11);
- f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
- FLD (f_simm16_split) = f_simm16_split;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_maci", "f_r2 0x%x", 'x', f_r2, "f_simm16_split 0x%x", 'x', f_simm16_split, (char *) 0));
-
-#undef FLD
- return idesc;
- }
-
- extract_sfmt_l_cust1:
- {
- const IDESC *idesc = &or1k32bf_insn_data[itype];
-#define FLD(f) abuf->fields.sfmt_empty.f
-
-
- /* Record the fields for the semantic handler. */
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_cust1", (char *) 0));
+ FLD (f_simm16) = f_simm16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_maci", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, (char *) 0));
#undef FLD
return idesc;
diff --git a/sim/or1k/decode32.h b/sim/or1k/decode32.h
index 56f4669..a854856 100644
--- a/sim/or1k/decode32.h
+++ b/sim/or1k/decode32.h
@@ -49,11 +49,11 @@ typedef enum or1k32bf_insn_type {
, OR1K32BF_INSN_L_FL1, OR1K32BF_INSN_L_ANDI, OR1K32BF_INSN_L_ORI, OR1K32BF_INSN_L_XORI
, OR1K32BF_INSN_L_ADDI, OR1K32BF_INSN_L_ADDIC, OR1K32BF_INSN_L_MULI, OR1K32BF_INSN_L_EXTHS
, OR1K32BF_INSN_L_EXTBS, OR1K32BF_INSN_L_EXTHZ, OR1K32BF_INSN_L_EXTBZ, OR1K32BF_INSN_L_EXTWS
- , OR1K32BF_INSN_L_EXTWZ, OR1K32BF_INSN_L_CMOV, OR1K32BF_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGEU
- , OR1K32BF_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLEU, OR1K32BF_INSN_L_SFGTS, OR1K32BF_INSN_L_SFGES
- , OR1K32BF_INSN_L_SFLTS, OR1K32BF_INSN_L_SFLES, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGEUI
- , OR1K32BF_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFGTSI, OR1K32BF_INSN_L_SFGESI
- , OR1K32BF_INSN_L_SFLTSI, OR1K32BF_INSN_L_SFLESI, OR1K32BF_INSN_L_SFEQ, OR1K32BF_INSN_L_SFEQI
+ , OR1K32BF_INSN_L_EXTWZ, OR1K32BF_INSN_L_CMOV, OR1K32BF_INSN_L_SFGTS, OR1K32BF_INSN_L_SFGTSI
+ , OR1K32BF_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGES, OR1K32BF_INSN_L_SFGESI
+ , OR1K32BF_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFLTS, OR1K32BF_INSN_L_SFLTSI
+ , OR1K32BF_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLES, OR1K32BF_INSN_L_SFLESI
+ , OR1K32BF_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFEQ, OR1K32BF_INSN_L_SFEQI
, OR1K32BF_INSN_L_SFNE, OR1K32BF_INSN_L_SFNEI, OR1K32BF_INSN_L_MAC, OR1K32BF_INSN_L_MSB
, OR1K32BF_INSN_L_MACI, OR1K32BF_INSN_L_CUST1, OR1K32BF_INSN_L_CUST2, OR1K32BF_INSN_L_CUST3
, OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5, OR1K32BF_INSN_L_CUST6, OR1K32BF_INSN_L_CUST7
@@ -67,17 +67,16 @@ typedef enum or1k32bf_insn_type {
/* Enum declaration for semantic formats in cpu family or1k32bf. */
typedef enum or1k32bf_sfmt_type {
OR1K32BF_SFMT_EMPTY, OR1K32BF_SFMT_L_J, OR1K32BF_SFMT_L_JAL, OR1K32BF_SFMT_L_JR
- , OR1K32BF_SFMT_L_JALR, OR1K32BF_SFMT_L_BNF, OR1K32BF_SFMT_L_TRAP, OR1K32BF_SFMT_L_NOP_IMM
- , OR1K32BF_SFMT_L_MOVHI, OR1K32BF_SFMT_L_MACRC, OR1K32BF_SFMT_L_MFSPR, OR1K32BF_SFMT_L_MTSPR
- , OR1K32BF_SFMT_L_LWZ, OR1K32BF_SFMT_L_LWS, OR1K32BF_SFMT_L_LBZ, OR1K32BF_SFMT_L_LBS
- , OR1K32BF_SFMT_L_LHZ, OR1K32BF_SFMT_L_LHS, OR1K32BF_SFMT_L_SW, OR1K32BF_SFMT_L_SB
- , OR1K32BF_SFMT_L_SH, OR1K32BF_SFMT_L_SLL, OR1K32BF_SFMT_L_SLLI, OR1K32BF_SFMT_L_AND
- , OR1K32BF_SFMT_L_ADD, OR1K32BF_SFMT_L_ADDC, OR1K32BF_SFMT_L_DIV, OR1K32BF_SFMT_L_FF1
- , OR1K32BF_SFMT_L_ANDI, OR1K32BF_SFMT_L_XORI, OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC
- , OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV, OR1K32BF_SFMT_L_SFGTU, OR1K32BF_SFMT_L_SFGTUI
- , OR1K32BF_SFMT_L_SFGTSI, OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI, OR1K32BF_SFMT_L_CUST1
- , OR1K32BF_SFMT_LF_ADD_S, OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S
- , OR1K32BF_SFMT_LF_MADD_S
+ , OR1K32BF_SFMT_L_JALR, OR1K32BF_SFMT_L_BNF, OR1K32BF_SFMT_L_TRAP, OR1K32BF_SFMT_L_RFE
+ , OR1K32BF_SFMT_L_NOP_IMM, OR1K32BF_SFMT_L_MOVHI, OR1K32BF_SFMT_L_MACRC, OR1K32BF_SFMT_L_MFSPR
+ , OR1K32BF_SFMT_L_MTSPR, OR1K32BF_SFMT_L_LWZ, OR1K32BF_SFMT_L_LWS, OR1K32BF_SFMT_L_LBZ
+ , OR1K32BF_SFMT_L_LBS, OR1K32BF_SFMT_L_LHZ, OR1K32BF_SFMT_L_LHS, OR1K32BF_SFMT_L_SW
+ , OR1K32BF_SFMT_L_SB, OR1K32BF_SFMT_L_SH, OR1K32BF_SFMT_L_SLL, OR1K32BF_SFMT_L_SLLI
+ , OR1K32BF_SFMT_L_AND, OR1K32BF_SFMT_L_ADD, OR1K32BF_SFMT_L_ADDC, OR1K32BF_SFMT_L_DIV
+ , OR1K32BF_SFMT_L_FF1, OR1K32BF_SFMT_L_XORI, OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC
+ , OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV, OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI
+ , OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI, OR1K32BF_SFMT_LF_ADD_S, OR1K32BF_SFMT_LF_ITOF_S
+ , OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S, OR1K32BF_SFMT_LF_MADD_S
} OR1K32BF_SFMT_TYPE;
/* Function unit handlers (user written). */
diff --git a/sim/or1k/decode64.c b/sim/or1k/decode64.c
index b3c774d9..752fa13 100644
--- a/sim/or1k/decode64.c
+++ b/sim/or1k/decode64.c
@@ -54,7 +54,7 @@ static const struct insn_sem or1k64bf_insn_sem[] =
{ OR1K_INSN_L_BF, OR1K64BF_INSN_L_BF, OR1K64BF_SFMT_L_BNF },
{ OR1K_INSN_L_TRAP, OR1K64BF_INSN_L_TRAP, OR1K64BF_SFMT_L_TRAP },
{ OR1K_INSN_L_SYS, OR1K64BF_INSN_L_SYS, OR1K64BF_SFMT_L_TRAP },
- { OR1K_INSN_L_RFE, OR1K64BF_INSN_L_RFE, OR1K64BF_SFMT_L_TRAP },
+ { OR1K_INSN_L_RFE, OR1K64BF_INSN_L_RFE, OR1K64BF_SFMT_L_RFE },
{ OR1K_INSN_L_NOP_IMM, OR1K64BF_INSN_L_NOP_IMM, OR1K64BF_SFMT_L_NOP_IMM },
{ OR1K_INSN_L_MOVHI, OR1K64BF_INSN_L_MOVHI, OR1K64BF_SFMT_L_MOVHI },
{ OR1K_INSN_L_MACRC, OR1K64BF_INSN_L_MACRC, OR1K64BF_SFMT_L_MACRC },
@@ -89,8 +89,8 @@ static const struct insn_sem or1k64bf_insn_sem[] =
{ OR1K_INSN_L_DIVU, OR1K64BF_INSN_L_DIVU, OR1K64BF_SFMT_L_DIV },
{ OR1K_INSN_L_FF1, OR1K64BF_INSN_L_FF1, OR1K64BF_SFMT_L_FF1 },
{ OR1K_INSN_L_FL1, OR1K64BF_INSN_L_FL1, OR1K64BF_SFMT_L_FF1 },
- { OR1K_INSN_L_ANDI, OR1K64BF_INSN_L_ANDI, OR1K64BF_SFMT_L_ANDI },
- { OR1K_INSN_L_ORI, OR1K64BF_INSN_L_ORI, OR1K64BF_SFMT_L_ANDI },
+ { OR1K_INSN_L_ANDI, OR1K64BF_INSN_L_ANDI, OR1K64BF_SFMT_L_MFSPR },
+ { OR1K_INSN_L_ORI, OR1K64BF_INSN_L_ORI, OR1K64BF_SFMT_L_MFSPR },
{ OR1K_INSN_L_XORI, OR1K64BF_INSN_L_XORI, OR1K64BF_SFMT_L_XORI },
{ OR1K_INSN_L_ADDI, OR1K64BF_INSN_L_ADDI, OR1K64BF_SFMT_L_ADDI },
{ OR1K_INSN_L_ADDIC, OR1K64BF_INSN_L_ADDIC, OR1K64BF_SFMT_L_ADDIC },
@@ -102,37 +102,37 @@ static const struct insn_sem or1k64bf_insn_sem[] =
{ OR1K_INSN_L_EXTWS, OR1K64BF_INSN_L_EXTWS, OR1K64BF_SFMT_L_EXTHS },
{ OR1K_INSN_L_EXTWZ, OR1K64BF_INSN_L_EXTWZ, OR1K64BF_SFMT_L_EXTHS },
{ OR1K_INSN_L_CMOV, OR1K64BF_INSN_L_CMOV, OR1K64BF_SFMT_L_CMOV },
- { OR1K_INSN_L_SFGTU, OR1K64BF_INSN_L_SFGTU, OR1K64BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFGEU, OR1K64BF_INSN_L_SFGEU, OR1K64BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFLTU, OR1K64BF_INSN_L_SFLTU, OR1K64BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFLEU, OR1K64BF_INSN_L_SFLEU, OR1K64BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFGTS, OR1K64BF_INSN_L_SFGTS, OR1K64BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFGES, OR1K64BF_INSN_L_SFGES, OR1K64BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFLTS, OR1K64BF_INSN_L_SFLTS, OR1K64BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFLES, OR1K64BF_INSN_L_SFLES, OR1K64BF_SFMT_L_SFGTU },
- { OR1K_INSN_L_SFGTUI, OR1K64BF_INSN_L_SFGTUI, OR1K64BF_SFMT_L_SFGTUI },
- { OR1K_INSN_L_SFGEUI, OR1K64BF_INSN_L_SFGEUI, OR1K64BF_SFMT_L_SFGTUI },
- { OR1K_INSN_L_SFLTUI, OR1K64BF_INSN_L_SFLTUI, OR1K64BF_SFMT_L_SFGTUI },
- { OR1K_INSN_L_SFLEUI, OR1K64BF_INSN_L_SFLEUI, OR1K64BF_SFMT_L_SFGTUI },
+ { OR1K_INSN_L_SFGTS, OR1K64BF_INSN_L_SFGTS, OR1K64BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFGTSI, OR1K64BF_INSN_L_SFGTSI, OR1K64BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFGTU, OR1K64BF_INSN_L_SFGTU, OR1K64BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFGTUI, OR1K64BF_INSN_L_SFGTUI, OR1K64BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFGES, OR1K64BF_INSN_L_SFGES, OR1K64BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFGESI, OR1K64BF_INSN_L_SFGESI, OR1K64BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFGEU, OR1K64BF_INSN_L_SFGEU, OR1K64BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFGEUI, OR1K64BF_INSN_L_SFGEUI, OR1K64BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFLTS, OR1K64BF_INSN_L_SFLTS, OR1K64BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFLTSI, OR1K64BF_INSN_L_SFLTSI, OR1K64BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFLTU, OR1K64BF_INSN_L_SFLTU, OR1K64BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFLTUI, OR1K64BF_INSN_L_SFLTUI, OR1K64BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFLES, OR1K64BF_INSN_L_SFLES, OR1K64BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFLESI, OR1K64BF_INSN_L_SFLESI, OR1K64BF_SFMT_L_SFGTSI },
- { OR1K_INSN_L_SFEQ, OR1K64BF_INSN_L_SFEQ, OR1K64BF_SFMT_L_SFGTU },
+ { OR1K_INSN_L_SFLEU, OR1K64BF_INSN_L_SFLEU, OR1K64BF_SFMT_L_SFGTS },
+ { OR1K_INSN_L_SFLEUI, OR1K64BF_INSN_L_SFLEUI, OR1K64BF_SFMT_L_SFGTSI },
+ { OR1K_INSN_L_SFEQ, OR1K64BF_INSN_L_SFEQ, OR1K64BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFEQI, OR1K64BF_INSN_L_SFEQI, OR1K64BF_SFMT_L_SFGTSI },
- { OR1K_INSN_L_SFNE, OR1K64BF_INSN_L_SFNE, OR1K64BF_SFMT_L_SFGTU },
+ { OR1K_INSN_L_SFNE, OR1K64BF_INSN_L_SFNE, OR1K64BF_SFMT_L_SFGTS },
{ OR1K_INSN_L_SFNEI, OR1K64BF_INSN_L_SFNEI, OR1K64BF_SFMT_L_SFGTSI },
{ OR1K_INSN_L_MAC, OR1K64BF_INSN_L_MAC, OR1K64BF_SFMT_L_MAC },
{ OR1K_INSN_L_MSB, OR1K64BF_INSN_L_MSB, OR1K64BF_SFMT_L_MAC },
{ OR1K_INSN_L_MACI, OR1K64BF_INSN_L_MACI, OR1K64BF_SFMT_L_MACI },
- { OR1K_INSN_L_CUST1, OR1K64BF_INSN_L_CUST1, OR1K64BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST2, OR1K64BF_INSN_L_CUST2, OR1K64BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST3, OR1K64BF_INSN_L_CUST3, OR1K64BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST4, OR1K64BF_INSN_L_CUST4, OR1K64BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST5, OR1K64BF_INSN_L_CUST5, OR1K64BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST6, OR1K64BF_INSN_L_CUST6, OR1K64BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST7, OR1K64BF_INSN_L_CUST7, OR1K64BF_SFMT_L_CUST1 },
- { OR1K_INSN_L_CUST8, OR1K64BF_INSN_L_CUST8, OR1K64BF_SFMT_L_CUST1 },
+ { OR1K_INSN_L_CUST1, OR1K64BF_INSN_L_CUST1, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST2, OR1K64BF_INSN_L_CUST2, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST3, OR1K64BF_INSN_L_CUST3, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST4, OR1K64BF_INSN_L_CUST4, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST5, OR1K64BF_INSN_L_CUST5, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST6, OR1K64BF_INSN_L_CUST6, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST7, OR1K64BF_INSN_L_CUST7, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST8, OR1K64BF_INSN_L_CUST8, OR1K64BF_SFMT_L_RFE },
{ OR1K_INSN_LF_ADD_S, OR1K64BF_INSN_LF_ADD_S, OR1K64BF_SFMT_LF_ADD_S },
{ OR1K_INSN_LF_ADD_D, OR1K64BF_INSN_LF_ADD_D, OR1K64BF_SFMT_LF_ADD_D },
{ OR1K_INSN_LF_SUB_S, OR1K64BF_INSN_LF_SUB_S, OR1K64BF_SFMT_LF_ADD_S },
@@ -161,8 +161,8 @@ static const struct insn_sem or1k64bf_insn_sem[] =
{ OR1K_INSN_LF_LE_D, OR1K64BF_INSN_LF_LE_D, OR1K64BF_SFMT_LF_EQ_D },
{ OR1K_INSN_LF_MADD_S, OR1K64BF_INSN_LF_MADD_S, OR1K64BF_SFMT_LF_MADD_S },
{ OR1K_INSN_LF_MADD_D, OR1K64BF_INSN_LF_MADD_D, OR1K64BF_SFMT_LF_MADD_D },
- { OR1K_INSN_LF_CUST1_S, OR1K64BF_INSN_LF_CUST1_S, OR1K64BF_SFMT_L_CUST1 },
- { OR1K_INSN_LF_CUST1_D, OR1K64BF_INSN_LF_CUST1_D, OR1K64BF_SFMT_L_CUST1 },
+ { OR1K_INSN_LF_CUST1_S, OR1K64BF_INSN_LF_CUST1_S, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_LF_CUST1_D, OR1K64BF_INSN_LF_CUST1_D, OR1K64BF_SFMT_L_RFE },
};
static const struct insn_sem or1k64bf_insn_sem_invalid =
@@ -505,7 +505,7 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
}
case 288 :
if ((entire_insn & 0xffffffff) == 0x24000000)
- { itype = OR1K64BF_INSN_L_RFE; goto extract_sfmt_l_trap; }
+ { itype = OR1K64BF_INSN_L_RFE; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 544 :
if ((entire_insn & 0xffff07ff) == 0x44000000)
@@ -547,24 +547,24 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 637 : /* fall through */
case 638 : /* fall through */
case 639 :
- if ((entire_insn & 0xfc1f0000) == 0x4c000000)
+ if ((entire_insn & 0xffe00000) == 0x4c000000)
{ itype = OR1K64BF_INSN_L_MACI; goto extract_sfmt_l_maci; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 896 :
if ((entire_insn & 0xffffffff) == 0x70000000)
- { itype = OR1K64BF_INSN_L_CUST1; goto extract_sfmt_l_cust1; }
+ { itype = OR1K64BF_INSN_L_CUST1; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 928 :
if ((entire_insn & 0xffffffff) == 0x74000000)
- { itype = OR1K64BF_INSN_L_CUST2; goto extract_sfmt_l_cust1; }
+ { itype = OR1K64BF_INSN_L_CUST2; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 960 :
if ((entire_insn & 0xffffffff) == 0x78000000)
- { itype = OR1K64BF_INSN_L_CUST3; goto extract_sfmt_l_cust1; }
+ { itype = OR1K64BF_INSN_L_CUST3; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 992 :
if ((entire_insn & 0xffffffff) == 0x7c000000)
- { itype = OR1K64BF_INSN_L_CUST4; goto extract_sfmt_l_cust1; }
+ { itype = OR1K64BF_INSN_L_CUST4; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1056 : /* fall through */
case 1057 : /* fall through */
@@ -853,7 +853,7 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 1340 : /* fall through */
case 1341 : /* fall through */
case 1342 : /* fall through */
- case 1343 : itype = OR1K64BF_INSN_L_ANDI; goto extract_sfmt_l_andi;
+ case 1343 : itype = OR1K64BF_INSN_L_ANDI; goto extract_sfmt_l_mfspr;
case 1344 : /* fall through */
case 1345 : /* fall through */
case 1346 : /* fall through */
@@ -885,7 +885,7 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
case 1372 : /* fall through */
case 1373 : /* fall through */
case 1374 : /* fall through */
- case 1375 : itype = OR1K64BF_INSN_L_ORI; goto extract_sfmt_l_andi;
+ case 1375 : itype = OR1K64BF_INSN_L_ORI; goto extract_sfmt_l_mfspr;
case 1376 : /* fall through */
case 1377 : /* fall through */
case 1378 : /* fall through */
@@ -1083,19 +1083,19 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2 :
if ((entire_insn & 0xffe00000) == 0xbc400000)
- { itype = OR1K64BF_INSN_L_SFGTUI; goto extract_sfmt_l_sfgtui; }
+ { itype = OR1K64BF_INSN_L_SFGTUI; goto extract_sfmt_l_sfgtsi; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 3 :
if ((entire_insn & 0xffe00000) == 0xbc600000)
- { itype = OR1K64BF_INSN_L_SFGEUI; goto extract_sfmt_l_sfgtui; }
+ { itype = OR1K64BF_INSN_L_SFGEUI; goto extract_sfmt_l_sfgtsi; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 4 :
if ((entire_insn & 0xffe00000) == 0xbc800000)
- { itype = OR1K64BF_INSN_L_SFLTUI; goto extract_sfmt_l_sfgtui; }
+ { itype = OR1K64BF_INSN_L_SFLTUI; goto extract_sfmt_l_sfgtsi; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 5 :
if ((entire_insn & 0xffe00000) == 0xbca00000)
- { itype = OR1K64BF_INSN_L_SFLEUI; goto extract_sfmt_l_sfgtui; }
+ { itype = OR1K64BF_INSN_L_SFLEUI; goto extract_sfmt_l_sfgtsi; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 10 :
if ((entire_insn & 0xffe00000) == 0xbd400000)
@@ -1167,7 +1167,7 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 7 :
if ((entire_insn & 0xffe007ff) == 0xc80000e0)
- { itype = OR1K64BF_INSN_LF_CUST1_D; goto extract_sfmt_l_cust1; }
+ { itype = OR1K64BF_INSN_LF_CUST1_D; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -1235,7 +1235,7 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 3 :
if ((entire_insn & 0xffe007ff) == 0xc80000d0)
- { itype = OR1K64BF_INSN_LF_CUST1_S; goto extract_sfmt_l_cust1; }
+ { itype = OR1K64BF_INSN_LF_CUST1_S; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -1519,62 +1519,62 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
case 0 :
if ((entire_insn & 0xffe007ff) == 0xe4000000)
- { itype = OR1K64BF_INSN_L_SFEQ; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K64BF_INSN_L_SFEQ; goto extract_sfmt_l_sfgts; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1 :
if ((entire_insn & 0xffe007ff) == 0xe4200000)
- { itype = OR1K64BF_INSN_L_SFNE; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K64BF_INSN_L_SFNE; goto extract_sfmt_l_sfgts; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2 :
if ((entire_insn & 0xffe007ff) == 0xe4400000)
- { itype = OR1K64BF_INSN_L_SFGTU; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K64BF_INSN_L_SFGTU; goto extract_sfmt_l_sfgts; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 3 :
if ((entire_insn & 0xffe007ff) == 0xe4600000)
- { itype = OR1K64BF_INSN_L_SFGEU; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K64BF_INSN_L_SFGEU; goto extract_sfmt_l_sfgts; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 4 :
if ((entire_insn & 0xffe007ff) == 0xe4800000)
- { itype = OR1K64BF_INSN_L_SFLTU; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K64BF_INSN_L_SFLTU; goto extract_sfmt_l_sfgts; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 5 :
if ((entire_insn & 0xffe007ff) == 0xe4a00000)
- { itype = OR1K64BF_INSN_L_SFLEU; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K64BF_INSN_L_SFLEU; goto extract_sfmt_l_sfgts; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 10 :
if ((entire_insn & 0xffe007ff) == 0xe5400000)
- { itype = OR1K64BF_INSN_L_SFGTS; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K64BF_INSN_L_SFGTS; goto extract_sfmt_l_sfgts; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 11 :
if ((entire_insn & 0xffe007ff) == 0xe5600000)
- { itype = OR1K64BF_INSN_L_SFGES; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K64BF_INSN_L_SFGES; goto extract_sfmt_l_sfgts; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 12 :
if ((entire_insn & 0xffe007ff) == 0xe5800000)
- { itype = OR1K64BF_INSN_L_SFLTS; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K64BF_INSN_L_SFLTS; goto extract_sfmt_l_sfgts; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 13 :
if ((entire_insn & 0xffe007ff) == 0xe5a00000)
- { itype = OR1K64BF_INSN_L_SFLES; goto extract_sfmt_l_sfgtu; }
+ { itype = OR1K64BF_INSN_L_SFLES; goto extract_sfmt_l_sfgts; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
case 1920 :
if ((entire_insn & 0xffffffff) == 0xf0000000)
- { itype = OR1K64BF_INSN_L_CUST5; goto extract_sfmt_l_cust1; }
+ { itype = OR1K64BF_INSN_L_CUST5; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1952 :
if ((entire_insn & 0xffffffff) == 0xf4000000)
- { itype = OR1K64BF_INSN_L_CUST6; goto extract_sfmt_l_cust1; }
+ { itype = OR1K64BF_INSN_L_CUST6; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1984 :
if ((entire_insn & 0xffffffff) == 0xf8000000)
- { itype = OR1K64BF_INSN_L_CUST7; goto extract_sfmt_l_cust1; }
+ { itype = OR1K64BF_INSN_L_CUST7; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2016 :
if ((entire_insn & 0xffffffff) == 0xfc000000)
- { itype = OR1K64BF_INSN_L_CUST8; goto extract_sfmt_l_cust1; }
+ { itype = OR1K64BF_INSN_L_CUST8; goto extract_sfmt_l_rfe; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -1694,6 +1694,19 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
+ extract_sfmt_l_rfe:
+ {
+ const IDESC *idesc = &or1k64bf_insn_data[itype];
+#define FLD(f) abuf->fields.sfmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_rfe", (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
extract_sfmt_l_nop_imm:
{
const IDESC *idesc = &or1k64bf_insn_data[itype];
@@ -1762,10 +1775,10 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
/* Record the fields for the semantic handler. */
- FLD (f_r1) = f_r1;
FLD (f_r2) = f_r2;
FLD (f_uimm16) = f_uimm16;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_mfspr", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, (char *) 0));
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_mfspr", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
#undef FLD
return idesc;
@@ -2175,29 +2188,6 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
- extract_sfmt_l_andi:
- {
- const IDESC *idesc = &or1k64bf_insn_data[itype];
- CGEN_INSN_WORD insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
- UINT f_r1;
- UINT f_r2;
- UINT f_uimm16;
-
- f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
- f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
- f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
-
- /* Record the fields for the semantic handler. */
- FLD (f_r2) = f_r2;
- FLD (f_uimm16) = f_uimm16;
- FLD (f_r1) = f_r1;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_andi", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
-
-#undef FLD
- return idesc;
- }
-
extract_sfmt_l_xori:
{
const IDESC *idesc = &or1k64bf_insn_data[itype];
@@ -2310,7 +2300,7 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
- extract_sfmt_l_sfgtu:
+ extract_sfmt_l_sfgts:
{
const IDESC *idesc = &or1k64bf_insn_data[itype];
CGEN_INSN_WORD insn = entire_insn;
@@ -2324,27 +2314,7 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
FLD (f_r3) = f_r3;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sfgtu", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
-
-#undef FLD
- return idesc;
- }
-
- extract_sfmt_l_sfgtui:
- {
- const IDESC *idesc = &or1k64bf_insn_data[itype];
- CGEN_INSN_WORD insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
- UINT f_r2;
- UINT f_uimm16;
-
- f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
- f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16);
-
- /* Record the fields for the semantic handler. */
- FLD (f_r2) = f_r2;
- FLD (f_uimm16) = f_uimm16;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sfgtui", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, (char *) 0));
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_sfgts", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, (char *) 0));
#undef FLD
return idesc;
@@ -2394,34 +2364,17 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
{
const IDESC *idesc = &or1k64bf_insn_data[itype];
CGEN_INSN_WORD insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_l_sw.f
- UINT f_imm16_25_5;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
UINT f_r2;
- UINT f_imm16_10_11;
- INT f_simm16_split;
+ INT f_simm16;
- f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
- f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11);
- f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
/* Record the fields for the semantic handler. */
FLD (f_r2) = f_r2;
- FLD (f_simm16_split) = f_simm16_split;
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_maci", "f_r2 0x%x", 'x', f_r2, "f_simm16_split 0x%x", 'x', f_simm16_split, (char *) 0));
-
-#undef FLD
- return idesc;
- }
-
- extract_sfmt_l_cust1:
- {
- const IDESC *idesc = &or1k64bf_insn_data[itype];
-#define FLD(f) abuf->fields.sfmt_empty.f
-
-
- /* Record the fields for the semantic handler. */
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_cust1", (char *) 0));
+ FLD (f_simm16) = f_simm16;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_maci", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, (char *) 0));
#undef FLD
return idesc;
diff --git a/sim/or1k/decode64.h b/sim/or1k/decode64.h
index a5f5806..db5f56f 100644
--- a/sim/or1k/decode64.h
+++ b/sim/or1k/decode64.h
@@ -49,11 +49,11 @@ typedef enum or1k64bf_insn_type {
, OR1K64BF_INSN_L_FL1, OR1K64BF_INSN_L_ANDI, OR1K64BF_INSN_L_ORI, OR1K64BF_INSN_L_XORI
, OR1K64BF_INSN_L_ADDI, OR1K64BF_INSN_L_ADDIC, OR1K64BF_INSN_L_MULI, OR1K64BF_INSN_L_EXTHS
, OR1K64BF_INSN_L_EXTBS, OR1K64BF_INSN_L_EXTHZ, OR1K64BF_INSN_L_EXTBZ, OR1K64BF_INSN_L_EXTWS
- , OR1K64BF_INSN_L_EXTWZ, OR1K64BF_INSN_L_CMOV, OR1K64BF_INSN_L_SFGTU, OR1K64BF_INSN_L_SFGEU
- , OR1K64BF_INSN_L_SFLTU, OR1K64BF_INSN_L_SFLEU, OR1K64BF_INSN_L_SFGTS, OR1K64BF_INSN_L_SFGES
- , OR1K64BF_INSN_L_SFLTS, OR1K64BF_INSN_L_SFLES, OR1K64BF_INSN_L_SFGTUI, OR1K64BF_INSN_L_SFGEUI
- , OR1K64BF_INSN_L_SFLTUI, OR1K64BF_INSN_L_SFLEUI, OR1K64BF_INSN_L_SFGTSI, OR1K64BF_INSN_L_SFGESI
- , OR1K64BF_INSN_L_SFLTSI, OR1K64BF_INSN_L_SFLESI, OR1K64BF_INSN_L_SFEQ, OR1K64BF_INSN_L_SFEQI
+ , OR1K64BF_INSN_L_EXTWZ, OR1K64BF_INSN_L_CMOV, OR1K64BF_INSN_L_SFGTS, OR1K64BF_INSN_L_SFGTSI
+ , OR1K64BF_INSN_L_SFGTU, OR1K64BF_INSN_L_SFGTUI, OR1K64BF_INSN_L_SFGES, OR1K64BF_INSN_L_SFGESI
+ , OR1K64BF_INSN_L_SFGEU, OR1K64BF_INSN_L_SFGEUI, OR1K64BF_INSN_L_SFLTS, OR1K64BF_INSN_L_SFLTSI
+ , OR1K64BF_INSN_L_SFLTU, OR1K64BF_INSN_L_SFLTUI, OR1K64BF_INSN_L_SFLES, OR1K64BF_INSN_L_SFLESI
+ , OR1K64BF_INSN_L_SFLEU, OR1K64BF_INSN_L_SFLEUI, OR1K64BF_INSN_L_SFEQ, OR1K64BF_INSN_L_SFEQI
, OR1K64BF_INSN_L_SFNE, OR1K64BF_INSN_L_SFNEI, OR1K64BF_INSN_L_MAC, OR1K64BF_INSN_L_MSB
, OR1K64BF_INSN_L_MACI, OR1K64BF_INSN_L_CUST1, OR1K64BF_INSN_L_CUST2, OR1K64BF_INSN_L_CUST3
, OR1K64BF_INSN_L_CUST4, OR1K64BF_INSN_L_CUST5, OR1K64BF_INSN_L_CUST6, OR1K64BF_INSN_L_CUST7
@@ -70,18 +70,17 @@ typedef enum or1k64bf_insn_type {
/* Enum declaration for semantic formats in cpu family or1k64bf. */
typedef enum or1k64bf_sfmt_type {
OR1K64BF_SFMT_EMPTY, OR1K64BF_SFMT_L_J, OR1K64BF_SFMT_L_JAL, OR1K64BF_SFMT_L_JR
- , OR1K64BF_SFMT_L_JALR, OR1K64BF_SFMT_L_BNF, OR1K64BF_SFMT_L_TRAP, OR1K64BF_SFMT_L_NOP_IMM
- , OR1K64BF_SFMT_L_MOVHI, OR1K64BF_SFMT_L_MACRC, OR1K64BF_SFMT_L_MFSPR, OR1K64BF_SFMT_L_MTSPR
- , OR1K64BF_SFMT_L_LWZ, OR1K64BF_SFMT_L_LWS, OR1K64BF_SFMT_L_LBZ, OR1K64BF_SFMT_L_LBS
- , OR1K64BF_SFMT_L_LHZ, OR1K64BF_SFMT_L_LHS, OR1K64BF_SFMT_L_SW, OR1K64BF_SFMT_L_SB
- , OR1K64BF_SFMT_L_SH, OR1K64BF_SFMT_L_SLL, OR1K64BF_SFMT_L_SLLI, OR1K64BF_SFMT_L_AND
- , OR1K64BF_SFMT_L_ADD, OR1K64BF_SFMT_L_ADDC, OR1K64BF_SFMT_L_DIV, OR1K64BF_SFMT_L_FF1
- , OR1K64BF_SFMT_L_ANDI, OR1K64BF_SFMT_L_XORI, OR1K64BF_SFMT_L_ADDI, OR1K64BF_SFMT_L_ADDIC
- , OR1K64BF_SFMT_L_EXTHS, OR1K64BF_SFMT_L_CMOV, OR1K64BF_SFMT_L_SFGTU, OR1K64BF_SFMT_L_SFGTUI
- , OR1K64BF_SFMT_L_SFGTSI, OR1K64BF_SFMT_L_MAC, OR1K64BF_SFMT_L_MACI, OR1K64BF_SFMT_L_CUST1
- , OR1K64BF_SFMT_LF_ADD_S, OR1K64BF_SFMT_LF_ADD_D, OR1K64BF_SFMT_LF_ITOF_S, OR1K64BF_SFMT_LF_ITOF_D
- , OR1K64BF_SFMT_LF_FTOI_S, OR1K64BF_SFMT_LF_FTOI_D, OR1K64BF_SFMT_LF_EQ_S, OR1K64BF_SFMT_LF_EQ_D
- , OR1K64BF_SFMT_LF_MADD_S, OR1K64BF_SFMT_LF_MADD_D
+ , OR1K64BF_SFMT_L_JALR, OR1K64BF_SFMT_L_BNF, OR1K64BF_SFMT_L_TRAP, OR1K64BF_SFMT_L_RFE
+ , OR1K64BF_SFMT_L_NOP_IMM, OR1K64BF_SFMT_L_MOVHI, OR1K64BF_SFMT_L_MACRC, OR1K64BF_SFMT_L_MFSPR
+ , OR1K64BF_SFMT_L_MTSPR, OR1K64BF_SFMT_L_LWZ, OR1K64BF_SFMT_L_LWS, OR1K64BF_SFMT_L_LBZ
+ , OR1K64BF_SFMT_L_LBS, OR1K64BF_SFMT_L_LHZ, OR1K64BF_SFMT_L_LHS, OR1K64BF_SFMT_L_SW
+ , OR1K64BF_SFMT_L_SB, OR1K64BF_SFMT_L_SH, OR1K64BF_SFMT_L_SLL, OR1K64BF_SFMT_L_SLLI
+ , OR1K64BF_SFMT_L_AND, OR1K64BF_SFMT_L_ADD, OR1K64BF_SFMT_L_ADDC, OR1K64BF_SFMT_L_DIV
+ , OR1K64BF_SFMT_L_FF1, OR1K64BF_SFMT_L_XORI, OR1K64BF_SFMT_L_ADDI, OR1K64BF_SFMT_L_ADDIC
+ , OR1K64BF_SFMT_L_EXTHS, OR1K64BF_SFMT_L_CMOV, OR1K64BF_SFMT_L_SFGTS, OR1K64BF_SFMT_L_SFGTSI
+ , OR1K64BF_SFMT_L_MAC, OR1K64BF_SFMT_L_MACI, OR1K64BF_SFMT_LF_ADD_S, OR1K64BF_SFMT_LF_ADD_D
+ , OR1K64BF_SFMT_LF_ITOF_S, OR1K64BF_SFMT_LF_ITOF_D, OR1K64BF_SFMT_LF_FTOI_S, OR1K64BF_SFMT_LF_FTOI_D
+ , OR1K64BF_SFMT_LF_EQ_S, OR1K64BF_SFMT_LF_EQ_D, OR1K64BF_SFMT_LF_MADD_S, OR1K64BF_SFMT_LF_MADD_D
} OR1K64BF_SFMT_TYPE;
/* Function unit handlers (user written). */
diff --git a/sim/or1k/model32.c b/sim/or1k/model32.c
index 7a1a1b6..72c0d61 100644
--- a/sim/or1k/model32.c
+++ b/sim/or1k/model32.c
@@ -931,7 +931,7 @@ model_or1200_l_cmov (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -947,9 +947,9 @@ model_or1200_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -963,7 +963,7 @@ model_or1200_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -979,9 +979,9 @@ model_or1200_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -995,7 +995,7 @@ model_or1200_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1011,9 +1011,9 @@ model_or1200_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1027,7 +1027,7 @@ model_or1200_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1043,9 +1043,9 @@ model_or1200_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1059,9 +1059,9 @@ model_or1200_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1075,9 +1075,9 @@ model_or1200_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1091,9 +1091,9 @@ model_or1200_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1107,9 +1107,9 @@ model_or1200_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1123,9 +1123,9 @@ model_or1200_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1139,7 +1139,7 @@ model_or1200_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sflesi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1155,9 +1155,9 @@ model_or1200_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -1171,7 +1171,7 @@ model_or1200_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200_l_sflesi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -1285,7 +1285,7 @@ model_or1200_l_msb (SIM_CPU *current_cpu, void *sem_arg)
static int
model_or1200_l_maci (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sw.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2563,7 +2563,7 @@ model_or1200nd_l_cmov (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2579,9 +2579,9 @@ model_or1200nd_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2595,7 +2595,7 @@ model_or1200nd_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgtu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2611,9 +2611,9 @@ model_or1200nd_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2627,7 +2627,7 @@ model_or1200nd_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2643,9 +2643,9 @@ model_or1200nd_l_sfgts (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2659,7 +2659,7 @@ model_or1200nd_l_sfges (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgeu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2675,9 +2675,9 @@ model_or1200nd_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2691,9 +2691,9 @@ model_or1200nd_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sflts (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2707,9 +2707,9 @@ model_or1200nd_l_sfgtui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2723,9 +2723,9 @@ model_or1200nd_l_sfgeui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfltu (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2739,9 +2739,9 @@ model_or1200nd_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfltui (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2755,9 +2755,9 @@ model_or1200nd_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfles (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2771,7 +2771,7 @@ model_or1200nd_l_sfgtsi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sflesi (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2787,9 +2787,9 @@ model_or1200nd_l_sfgesi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfleu (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -2803,7 +2803,7 @@ model_or1200nd_l_sfltsi (SIM_CPU *current_cpu, void *sem_arg)
}
static int
-model_or1200nd_l_sflesi (SIM_CPU *current_cpu, void *sem_arg)
+model_or1200nd_l_sfleui (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
@@ -2917,7 +2917,7 @@ model_or1200nd_l_msb (SIM_CPU *current_cpu, void *sem_arg)
static int
model_or1200nd_l_maci (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sw.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
@@ -3366,22 +3366,22 @@ static const INSN_TIMING or1200_timing[] = {
{ OR1K32BF_INSN_L_EXTWS, model_or1200_l_extws, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_EXTWZ, model_or1200_l_extwz, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_CMOV, model_or1200_l_cmov, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFGTU, model_or1200_l_sfgtu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFGEU, model_or1200_l_sfgeu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLTU, model_or1200_l_sfltu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLEU, model_or1200_l_sfleu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFGTS, model_or1200_l_sfgts, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFGES, model_or1200_l_sfges, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLTS, model_or1200_l_sflts, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLES, model_or1200_l_sfles, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFGTUI, model_or1200_l_sfgtui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFGEUI, model_or1200_l_sfgeui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLTUI, model_or1200_l_sfltui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLEUI, model_or1200_l_sfleui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFGTSI, model_or1200_l_sfgtsi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTU, model_or1200_l_sfgtu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTUI, model_or1200_l_sfgtui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGES, model_or1200_l_sfges, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFGESI, model_or1200_l_sfgesi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGEU, model_or1200_l_sfgeu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGEUI, model_or1200_l_sfgeui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTS, model_or1200_l_sflts, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFLTSI, model_or1200_l_sfltsi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTU, model_or1200_l_sfltu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTUI, model_or1200_l_sfltui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLES, model_or1200_l_sfles, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFLESI, model_or1200_l_sflesi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLEU, model_or1200_l_sfleu, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLEUI, model_or1200_l_sfleui, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFEQ, model_or1200_l_sfeq, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFEQI, model_or1200_l_sfeqi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFNE, model_or1200_l_sfne, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
@@ -3479,22 +3479,22 @@ static const INSN_TIMING or1200nd_timing[] = {
{ OR1K32BF_INSN_L_EXTWS, model_or1200nd_l_extws, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_EXTWZ, model_or1200nd_l_extwz, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_CMOV, model_or1200nd_l_cmov, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFGTU, model_or1200nd_l_sfgtu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFGEU, model_or1200nd_l_sfgeu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLTU, model_or1200nd_l_sfltu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLEU, model_or1200nd_l_sfleu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFGTS, model_or1200nd_l_sfgts, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFGES, model_or1200nd_l_sfges, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLTS, model_or1200nd_l_sflts, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLES, model_or1200nd_l_sfles, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFGTUI, model_or1200nd_l_sfgtui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFGEUI, model_or1200nd_l_sfgeui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLTUI, model_or1200nd_l_sfltui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
- { OR1K32BF_INSN_L_SFLEUI, model_or1200nd_l_sfleui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFGTSI, model_or1200nd_l_sfgtsi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTU, model_or1200nd_l_sfgtu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGTUI, model_or1200nd_l_sfgtui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGES, model_or1200nd_l_sfges, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFGESI, model_or1200nd_l_sfgesi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGEU, model_or1200nd_l_sfgeu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFGEUI, model_or1200nd_l_sfgeui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTS, model_or1200nd_l_sflts, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFLTSI, model_or1200nd_l_sfltsi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTU, model_or1200nd_l_sfltu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLTUI, model_or1200nd_l_sfltui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLES, model_or1200nd_l_sfles, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFLESI, model_or1200nd_l_sflesi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLEU, model_or1200nd_l_sfleu, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SFLEUI, model_or1200nd_l_sfleui, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFEQ, model_or1200nd_l_sfeq, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFEQI, model_or1200nd_l_sfeqi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SFNE, model_or1200nd_l_sfne, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
diff --git a/sim/or1k/sem32-switch.c b/sim/or1k/sem32-switch.c
index e708fe1..7d3d97f 100644
--- a/sim/or1k/sem32-switch.c
+++ b/sim/or1k/sem32-switch.c
@@ -94,22 +94,22 @@ This file is part of the GNU simulators.
{ OR1K32BF_INSN_L_EXTWS, && case_sem_INSN_L_EXTWS },
{ OR1K32BF_INSN_L_EXTWZ, && case_sem_INSN_L_EXTWZ },
{ OR1K32BF_INSN_L_CMOV, && case_sem_INSN_L_CMOV },
- { OR1K32BF_INSN_L_SFGTU, && case_sem_INSN_L_SFGTU },
- { OR1K32BF_INSN_L_SFGEU, && case_sem_INSN_L_SFGEU },
- { OR1K32BF_INSN_L_SFLTU, && case_sem_INSN_L_SFLTU },
- { OR1K32BF_INSN_L_SFLEU, && case_sem_INSN_L_SFLEU },
{ OR1K32BF_INSN_L_SFGTS, && case_sem_INSN_L_SFGTS },
- { OR1K32BF_INSN_L_SFGES, && case_sem_INSN_L_SFGES },
- { OR1K32BF_INSN_L_SFLTS, && case_sem_INSN_L_SFLTS },
- { OR1K32BF_INSN_L_SFLES, && case_sem_INSN_L_SFLES },
- { OR1K32BF_INSN_L_SFGTUI, && case_sem_INSN_L_SFGTUI },
- { OR1K32BF_INSN_L_SFGEUI, && case_sem_INSN_L_SFGEUI },
- { OR1K32BF_INSN_L_SFLTUI, && case_sem_INSN_L_SFLTUI },
- { OR1K32BF_INSN_L_SFLEUI, && case_sem_INSN_L_SFLEUI },
{ OR1K32BF_INSN_L_SFGTSI, && case_sem_INSN_L_SFGTSI },
+ { OR1K32BF_INSN_L_SFGTU, && case_sem_INSN_L_SFGTU },
+ { OR1K32BF_INSN_L_SFGTUI, && case_sem_INSN_L_SFGTUI },
+ { OR1K32BF_INSN_L_SFGES, && case_sem_INSN_L_SFGES },
{ OR1K32BF_INSN_L_SFGESI, && case_sem_INSN_L_SFGESI },
+ { OR1K32BF_INSN_L_SFGEU, && case_sem_INSN_L_SFGEU },
+ { OR1K32BF_INSN_L_SFGEUI, && case_sem_INSN_L_SFGEUI },
+ { OR1K32BF_INSN_L_SFLTS, && case_sem_INSN_L_SFLTS },
{ OR1K32BF_INSN_L_SFLTSI, && case_sem_INSN_L_SFLTSI },
+ { OR1K32BF_INSN_L_SFLTU, && case_sem_INSN_L_SFLTU },
+ { OR1K32BF_INSN_L_SFLTUI, && case_sem_INSN_L_SFLTUI },
+ { OR1K32BF_INSN_L_SFLES, && case_sem_INSN_L_SFLES },
{ OR1K32BF_INSN_L_SFLESI, && case_sem_INSN_L_SFLESI },
+ { OR1K32BF_INSN_L_SFLEU, && case_sem_INSN_L_SFLEU },
+ { OR1K32BF_INSN_L_SFLEUI, && case_sem_INSN_L_SFLEUI },
{ OR1K32BF_INSN_L_SFEQ, && case_sem_INSN_L_SFEQ },
{ OR1K32BF_INSN_L_SFEQI, && case_sem_INSN_L_SFEQI },
{ OR1K32BF_INSN_L_SFNE, && case_sem_INSN_L_SFNE },
@@ -596,7 +596,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-or1k32bf_rfe (current_cpu, pc);
+or1k32bf_rfe (current_cpu);
#undef FLD
}
@@ -646,22 +646,18 @@ or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI temp0;USI temp1;USI temp2;
- temp0 = GET_H_MAC_MACLO ();
- temp1 = 0;
- temp2 = 0;
{
- USI opval = temp0;
+ USI opval = GET_H_MAC_MACLO ();
SET_H_GPR (FLD (f_r1), opval);
TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
- USI opval = temp1;
+ USI opval = 0;
SET_H_MAC_MACLO (opval);
TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
{
- USI opval = temp2;
+ USI opval = 0;
SET_H_MAC_MACHI (opval);
TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
@@ -681,7 +677,7 @@ or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = or1k32bf_mfspr (current_cpu, pc, FLD (f_r1), ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
+ USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
SET_H_GPR (FLD (f_r1), opval);
TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
@@ -699,7 +695,7 @@ or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-or1k32bf_mtspr (current_cpu, pc, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
+or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
#undef FLD
}
@@ -1171,12 +1167,12 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
BI tmp_tmp_sys_sr_cy;
tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
{
- BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), GET_H_SYS_SR_CY ());
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), GET_H_SYS_SR_CY ());
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
@@ -1334,7 +1330,7 @@ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- USI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
@@ -1508,12 +1504,12 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
BI tmp_tmp_sys_sr_cy;
tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
{
- BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), GET_H_SYS_SR_CY ());
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), GET_H_SYS_SR_CY ());
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
@@ -1712,7 +1708,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGTU) : /* l.sfgtu $rA,$rB */
+ CASE (sem, INSN_L_SFGTS) : /* l.sfgts $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1722,7 +1718,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1731,17 +1727,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGEU) : /* l.sfgeu $rA,$rB */
+ CASE (sem, INSN_L_SFGTSI) : /* l.sfgtsi $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1750,7 +1746,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLTU) : /* l.sfltu $rA,$rB */
+ CASE (sem, INSN_L_SFGTU) : /* l.sfgtu $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1760,7 +1756,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1769,17 +1765,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLEU) : /* l.sfleu $rA,$rB */
+ CASE (sem, INSN_L_SFGTUI) : /* l.sfgtui $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1788,7 +1784,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGTS) : /* l.sfgts $rA,$rB */
+ CASE (sem, INSN_L_SFGES) : /* l.sfges $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1798,7 +1794,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1807,17 +1803,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGES) : /* l.sfges $rA,$rB */
+ CASE (sem, INSN_L_SFGESI) : /* l.sfgesi $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1826,7 +1822,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLTS) : /* l.sflts $rA,$rB */
+ CASE (sem, INSN_L_SFGEU) : /* l.sfgeu $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1836,7 +1832,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1845,17 +1841,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLES) : /* l.sfles $rA,$rB */
+ CASE (sem, INSN_L_SFGEUI) : /* l.sfgeui $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1864,17 +1860,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGTUI) : /* l.sfgtui $rA,$uimm16 */
+ CASE (sem, INSN_L_SFLTS) : /* l.sflts $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1883,17 +1879,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGEUI) : /* l.sfgeui $rA,$uimm16 */
+ CASE (sem, INSN_L_SFLTSI) : /* l.sfltsi $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1902,17 +1898,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLTUI) : /* l.sfltui $rA,$uimm16 */
+ CASE (sem, INSN_L_SFLTU) : /* l.sfltu $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1921,17 +1917,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLEUI) : /* l.sfleui $rA,$uimm16 */
+ CASE (sem, INSN_L_SFLTUI) : /* l.sfltui $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1940,17 +1936,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGTSI) : /* l.sfgtsi $rA,${simm16} */
+ CASE (sem, INSN_L_SFLES) : /* l.sfles $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1959,7 +1955,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGESI) : /* l.sfgesi $rA,${simm16} */
+ CASE (sem, INSN_L_SFLESI) : /* l.sflesi $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1969,7 +1965,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1978,17 +1974,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLTSI) : /* l.sfltsi $rA,${simm16} */
+ CASE (sem, INSN_L_SFLEU) : /* l.sfleu $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1997,7 +1993,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLESI) : /* l.sflesi $rA,${simm16} */
+ CASE (sem, INSN_L_SFLEUI) : /* l.sfleui $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2007,7 +2003,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -2152,11 +2148,11 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16-split} */
+ CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_sw.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -2164,7 +2160,7 @@ if (GET_H_SYS_SR_F ()) {
{
SI tmp_prod;
DI tmp_result;
- tmp_prod = MULSI (EXTSISI (FLD (f_simm16_split)), GET_H_GPR (FLD (f_r2)));
+ tmp_prod = MULSI (EXTSISI (FLD (f_simm16)), GET_H_GPR (FLD (f_r2)));
tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
{
SI opval = SUBWORDDISI (tmp_result, 0);
diff --git a/sim/or1k/sem32.c b/sim/or1k/sem32.c
index 0ea1db3..e8cbcc9 100644
--- a/sim/or1k/sem32.c
+++ b/sim/or1k/sem32.c
@@ -472,7 +472,7 @@ SEM_FN_NAME (or1k32bf,l_rfe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-or1k32bf_rfe (current_cpu, pc);
+or1k32bf_rfe (current_cpu);
return vpc;
#undef FLD
@@ -528,22 +528,18 @@ SEM_FN_NAME (or1k32bf,l_macrc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI temp0;USI temp1;USI temp2;
- temp0 = GET_H_MAC_MACLO ();
- temp1 = 0;
- temp2 = 0;
{
- USI opval = temp0;
+ USI opval = GET_H_MAC_MACLO ();
SET_H_GPR (FLD (f_r1), opval);
TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
- USI opval = temp1;
+ USI opval = 0;
SET_H_MAC_MACLO (opval);
TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
{
- USI opval = temp2;
+ USI opval = 0;
SET_H_MAC_MACHI (opval);
TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
@@ -565,7 +561,7 @@ SEM_FN_NAME (or1k32bf,l_mfspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = or1k32bf_mfspr (current_cpu, pc, FLD (f_r1), ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
+ USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
SET_H_GPR (FLD (f_r1), opval);
TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
@@ -585,7 +581,7 @@ SEM_FN_NAME (or1k32bf,l_mtspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-or1k32bf_mtspr (current_cpu, pc, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
+or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
return vpc;
#undef FLD
@@ -1103,12 +1099,12 @@ SEM_FN_NAME (or1k32bf,l_addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
BI tmp_tmp_sys_sr_cy;
tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
{
- BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), GET_H_SYS_SR_CY ());
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), GET_H_SYS_SR_CY ());
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
@@ -1274,7 +1270,7 @@ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- USI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
@@ -1462,12 +1458,12 @@ SEM_FN_NAME (or1k32bf,l_addic) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
BI tmp_tmp_sys_sr_cy;
tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
{
- BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), GET_H_SYS_SR_CY ());
+ BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), GET_H_SYS_SR_CY ());
+ BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
@@ -1682,10 +1678,10 @@ if (GET_H_SYS_SR_F ()) {
#undef FLD
}
-/* l-sfgtu: l.sfgtu $rA,$rB */
+/* l-sfgts: l.sfgts $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1694,7 +1690,7 @@ SEM_FN_NAME (or1k32bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1703,19 +1699,19 @@ SEM_FN_NAME (or1k32bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgeu: l.sfgeu $rA,$rB */
+/* l-sfgtsi: l.sfgtsi $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfgtsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1724,10 +1720,10 @@ SEM_FN_NAME (or1k32bf,l_sfgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfltu: l.sfltu $rA,$rB */
+/* l-sfgtu: l.sfgtu $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1736,7 +1732,7 @@ SEM_FN_NAME (or1k32bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1745,19 +1741,19 @@ SEM_FN_NAME (or1k32bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfleu: l.sfleu $rA,$rB */
+/* l-sfgtui: l.sfgtui $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfgtui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1766,10 +1762,10 @@ SEM_FN_NAME (or1k32bf,l_sfleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgts: l.sfgts $rA,$rB */
+/* l-sfges: l.sfges $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1778,7 +1774,7 @@ SEM_FN_NAME (or1k32bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1787,19 +1783,19 @@ SEM_FN_NAME (or1k32bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfges: l.sfges $rA,$rB */
+/* l-sfgesi: l.sfgesi $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1808,10 +1804,10 @@ SEM_FN_NAME (or1k32bf,l_sfges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sflts: l.sflts $rA,$rB */
+/* l-sfgeu: l.sfgeu $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1820,7 +1816,7 @@ SEM_FN_NAME (or1k32bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1829,19 +1825,19 @@ SEM_FN_NAME (or1k32bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfles: l.sfles $rA,$rB */
+/* l-sfgeui: l.sfgeui $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfles) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1850,19 +1846,19 @@ SEM_FN_NAME (or1k32bf,l_sfles) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgtui: l.sfgtui $rA,$uimm16 */
+/* l-sflts: l.sflts $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfgtui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1871,19 +1867,19 @@ SEM_FN_NAME (or1k32bf,l_sfgtui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgeui: l.sfgeui $rA,$uimm16 */
+/* l-sfltsi: l.sfltsi $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfltsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1892,19 +1888,19 @@ SEM_FN_NAME (or1k32bf,l_sfgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfltui: l.sfltui $rA,$uimm16 */
+/* l-sfltu: l.sfltu $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfltui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1913,19 +1909,19 @@ SEM_FN_NAME (or1k32bf,l_sfltui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfleui: l.sfleui $rA,$uimm16 */
+/* l-sfltui: l.sfltui $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfleui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfltui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
+ USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1934,19 +1930,19 @@ SEM_FN_NAME (or1k32bf,l_sfleui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgtsi: l.sfgtsi $rA,${simm16} */
+/* l-sfles: l.sfles $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfgtsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfles) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1955,10 +1951,10 @@ SEM_FN_NAME (or1k32bf,l_sfgtsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgesi: l.sfgesi $rA,${simm16} */
+/* l-sflesi: l.sflesi $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sflesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1967,7 +1963,7 @@ SEM_FN_NAME (or1k32bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1976,19 +1972,19 @@ SEM_FN_NAME (or1k32bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfltsi: l.sfltsi $rA,${simm16} */
+/* l-sfleu: l.sfleu $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sfltsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -1997,10 +1993,10 @@ SEM_FN_NAME (or1k32bf,l_sfltsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sflesi: l.sflesi $rA,${simm16} */
+/* l-sfleui: l.sfleui $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k32bf,l_sflesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k32bf,l_sfleui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2009,7 +2005,7 @@ SEM_FN_NAME (or1k32bf,l_sflesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
+ USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
@@ -2166,12 +2162,12 @@ SEM_FN_NAME (or1k32bf,l_msb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-maci: l.maci $rA,${simm16-split} */
+/* l-maci: l.maci $rA,${simm16} */
static SEM_PC
SEM_FN_NAME (or1k32bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sw.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
@@ -2180,7 +2176,7 @@ SEM_FN_NAME (or1k32bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI tmp_prod;
DI tmp_result;
- tmp_prod = MULSI (EXTSISI (FLD (f_simm16_split)), GET_H_GPR (FLD (f_r2)));
+ tmp_prod = MULSI (EXTSISI (FLD (f_simm16)), GET_H_GPR (FLD (f_r2)));
tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTSIDI (tmp_prod));
{
SI opval = SUBWORDDISI (tmp_result, 0);
@@ -2710,22 +2706,22 @@ static const struct sem_fn_desc sem_fns[] = {
{ OR1K32BF_INSN_L_EXTWS, SEM_FN_NAME (or1k32bf,l_extws) },
{ OR1K32BF_INSN_L_EXTWZ, SEM_FN_NAME (or1k32bf,l_extwz) },
{ OR1K32BF_INSN_L_CMOV, SEM_FN_NAME (or1k32bf,l_cmov) },
- { OR1K32BF_INSN_L_SFGTU, SEM_FN_NAME (or1k32bf,l_sfgtu) },
- { OR1K32BF_INSN_L_SFGEU, SEM_FN_NAME (or1k32bf,l_sfgeu) },
- { OR1K32BF_INSN_L_SFLTU, SEM_FN_NAME (or1k32bf,l_sfltu) },
- { OR1K32BF_INSN_L_SFLEU, SEM_FN_NAME (or1k32bf,l_sfleu) },
{ OR1K32BF_INSN_L_SFGTS, SEM_FN_NAME (or1k32bf,l_sfgts) },
- { OR1K32BF_INSN_L_SFGES, SEM_FN_NAME (or1k32bf,l_sfges) },
- { OR1K32BF_INSN_L_SFLTS, SEM_FN_NAME (or1k32bf,l_sflts) },
- { OR1K32BF_INSN_L_SFLES, SEM_FN_NAME (or1k32bf,l_sfles) },
- { OR1K32BF_INSN_L_SFGTUI, SEM_FN_NAME (or1k32bf,l_sfgtui) },
- { OR1K32BF_INSN_L_SFGEUI, SEM_FN_NAME (or1k32bf,l_sfgeui) },
- { OR1K32BF_INSN_L_SFLTUI, SEM_FN_NAME (or1k32bf,l_sfltui) },
- { OR1K32BF_INSN_L_SFLEUI, SEM_FN_NAME (or1k32bf,l_sfleui) },
{ OR1K32BF_INSN_L_SFGTSI, SEM_FN_NAME (or1k32bf,l_sfgtsi) },
+ { OR1K32BF_INSN_L_SFGTU, SEM_FN_NAME (or1k32bf,l_sfgtu) },
+ { OR1K32BF_INSN_L_SFGTUI, SEM_FN_NAME (or1k32bf,l_sfgtui) },
+ { OR1K32BF_INSN_L_SFGES, SEM_FN_NAME (or1k32bf,l_sfges) },
{ OR1K32BF_INSN_L_SFGESI, SEM_FN_NAME (or1k32bf,l_sfgesi) },
+ { OR1K32BF_INSN_L_SFGEU, SEM_FN_NAME (or1k32bf,l_sfgeu) },
+ { OR1K32BF_INSN_L_SFGEUI, SEM_FN_NAME (or1k32bf,l_sfgeui) },
+ { OR1K32BF_INSN_L_SFLTS, SEM_FN_NAME (or1k32bf,l_sflts) },
{ OR1K32BF_INSN_L_SFLTSI, SEM_FN_NAME (or1k32bf,l_sfltsi) },
+ { OR1K32BF_INSN_L_SFLTU, SEM_FN_NAME (or1k32bf,l_sfltu) },
+ { OR1K32BF_INSN_L_SFLTUI, SEM_FN_NAME (or1k32bf,l_sfltui) },
+ { OR1K32BF_INSN_L_SFLES, SEM_FN_NAME (or1k32bf,l_sfles) },
{ OR1K32BF_INSN_L_SFLESI, SEM_FN_NAME (or1k32bf,l_sflesi) },
+ { OR1K32BF_INSN_L_SFLEU, SEM_FN_NAME (or1k32bf,l_sfleu) },
+ { OR1K32BF_INSN_L_SFLEUI, SEM_FN_NAME (or1k32bf,l_sfleui) },
{ OR1K32BF_INSN_L_SFEQ, SEM_FN_NAME (or1k32bf,l_sfeq) },
{ OR1K32BF_INSN_L_SFEQI, SEM_FN_NAME (or1k32bf,l_sfeqi) },
{ OR1K32BF_INSN_L_SFNE, SEM_FN_NAME (or1k32bf,l_sfne) },
diff --git a/sim/or1k/sem64-switch.c b/sim/or1k/sem64-switch.c
index 3a60670..9de4e16 100644
--- a/sim/or1k/sem64-switch.c
+++ b/sim/or1k/sem64-switch.c
@@ -94,22 +94,22 @@ This file is part of the GNU simulators.
{ OR1K64BF_INSN_L_EXTWS, && case_sem_INSN_L_EXTWS },
{ OR1K64BF_INSN_L_EXTWZ, && case_sem_INSN_L_EXTWZ },
{ OR1K64BF_INSN_L_CMOV, && case_sem_INSN_L_CMOV },
- { OR1K64BF_INSN_L_SFGTU, && case_sem_INSN_L_SFGTU },
- { OR1K64BF_INSN_L_SFGEU, && case_sem_INSN_L_SFGEU },
- { OR1K64BF_INSN_L_SFLTU, && case_sem_INSN_L_SFLTU },
- { OR1K64BF_INSN_L_SFLEU, && case_sem_INSN_L_SFLEU },
{ OR1K64BF_INSN_L_SFGTS, && case_sem_INSN_L_SFGTS },
- { OR1K64BF_INSN_L_SFGES, && case_sem_INSN_L_SFGES },
- { OR1K64BF_INSN_L_SFLTS, && case_sem_INSN_L_SFLTS },
- { OR1K64BF_INSN_L_SFLES, && case_sem_INSN_L_SFLES },
- { OR1K64BF_INSN_L_SFGTUI, && case_sem_INSN_L_SFGTUI },
- { OR1K64BF_INSN_L_SFGEUI, && case_sem_INSN_L_SFGEUI },
- { OR1K64BF_INSN_L_SFLTUI, && case_sem_INSN_L_SFLTUI },
- { OR1K64BF_INSN_L_SFLEUI, && case_sem_INSN_L_SFLEUI },
{ OR1K64BF_INSN_L_SFGTSI, && case_sem_INSN_L_SFGTSI },
+ { OR1K64BF_INSN_L_SFGTU, && case_sem_INSN_L_SFGTU },
+ { OR1K64BF_INSN_L_SFGTUI, && case_sem_INSN_L_SFGTUI },
+ { OR1K64BF_INSN_L_SFGES, && case_sem_INSN_L_SFGES },
{ OR1K64BF_INSN_L_SFGESI, && case_sem_INSN_L_SFGESI },
+ { OR1K64BF_INSN_L_SFGEU, && case_sem_INSN_L_SFGEU },
+ { OR1K64BF_INSN_L_SFGEUI, && case_sem_INSN_L_SFGEUI },
+ { OR1K64BF_INSN_L_SFLTS, && case_sem_INSN_L_SFLTS },
{ OR1K64BF_INSN_L_SFLTSI, && case_sem_INSN_L_SFLTSI },
+ { OR1K64BF_INSN_L_SFLTU, && case_sem_INSN_L_SFLTU },
+ { OR1K64BF_INSN_L_SFLTUI, && case_sem_INSN_L_SFLTUI },
+ { OR1K64BF_INSN_L_SFLES, && case_sem_INSN_L_SFLES },
{ OR1K64BF_INSN_L_SFLESI, && case_sem_INSN_L_SFLESI },
+ { OR1K64BF_INSN_L_SFLEU, && case_sem_INSN_L_SFLEU },
+ { OR1K64BF_INSN_L_SFLEUI, && case_sem_INSN_L_SFLEUI },
{ OR1K64BF_INSN_L_SFEQ, && case_sem_INSN_L_SFEQ },
{ OR1K64BF_INSN_L_SFEQI, && case_sem_INSN_L_SFEQI },
{ OR1K64BF_INSN_L_SFNE, && case_sem_INSN_L_SFNE },
@@ -611,7 +611,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-or1k64bf_rfe (current_cpu, pc);
+or1k64bf_rfe (current_cpu);
#undef FLD
}
@@ -661,22 +661,18 @@ or1k64bf_nop (current_cpu, ZEXTSIDI (FLD (f_uimm16)));
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI temp0;UDI temp1;UDI temp2;
- temp0 = GET_H_MAC_MACLO ();
- temp1 = 0;
- temp2 = 0;
{
- UDI opval = temp0;
+ UDI opval = GET_H_MAC_MACLO ();
SET_H_GPR (FLD (f_r1), opval);
TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
{
- UDI opval = temp1;
+ UDI opval = 0;
SET_H_MAC_MACLO (opval);
TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'D', opval);
}
{
- UDI opval = temp2;
+ UDI opval = 0;
SET_H_MAC_MACHI (opval);
TRACE_RESULT (current_cpu, abuf, "mac-machi", 'D', opval);
}
@@ -696,7 +692,7 @@ or1k64bf_nop (current_cpu, ZEXTSIDI (FLD (f_uimm16)));
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = or1k64bf_mfspr (current_cpu, pc, FLD (f_r1), ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16))));
+ UDI opval = or1k64bf_mfspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16))));
SET_H_GPR (FLD (f_r1), opval);
TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
@@ -714,7 +710,7 @@ or1k64bf_nop (current_cpu, ZEXTSIDI (FLD (f_uimm16)));
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-or1k64bf_mtspr (current_cpu, pc, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
+or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
#undef FLD
}
@@ -1186,12 +1182,12 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
BI tmp_tmp_sys_sr_cy;
tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
{
- BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), GET_H_SYS_SR_CY ());
+ BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), GET_H_SYS_SR_CY ());
+ BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
@@ -1349,7 +1345,7 @@ if (NEDI (GET_H_GPR (FLD (f_r3)), 0)) {
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- UDI opval = DIVDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = UDIVDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
@@ -1523,12 +1519,12 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
BI tmp_tmp_sys_sr_cy;
tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
{
- BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), GET_H_SYS_SR_CY ());
+ BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), GET_H_SYS_SR_CY ());
+ BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
@@ -1727,7 +1723,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGTU) : /* l.sfgtu $rA,$rB */
+ CASE (sem, INSN_L_SFGTS) : /* l.sfgts $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1737,7 +1733,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1746,17 +1742,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGEU) : /* l.sfgeu $rA,$rB */
+ CASE (sem, INSN_L_SFGTSI) : /* l.sfgtsi $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1765,7 +1761,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLTU) : /* l.sfltu $rA,$rB */
+ CASE (sem, INSN_L_SFGTU) : /* l.sfgtu $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1775,7 +1771,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1784,17 +1780,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLEU) : /* l.sfleu $rA,$rB */
+ CASE (sem, INSN_L_SFGTUI) : /* l.sfgtui $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1803,7 +1799,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGTS) : /* l.sfgts $rA,$rB */
+ CASE (sem, INSN_L_SFGES) : /* l.sfges $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1813,7 +1809,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1822,17 +1818,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGES) : /* l.sfges $rA,$rB */
+ CASE (sem, INSN_L_SFGESI) : /* l.sfgesi $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1841,7 +1837,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLTS) : /* l.sflts $rA,$rB */
+ CASE (sem, INSN_L_SFGEU) : /* l.sfgeu $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1851,7 +1847,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1860,17 +1856,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLES) : /* l.sfles $rA,$rB */
+ CASE (sem, INSN_L_SFGEUI) : /* l.sfgeui $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1879,17 +1875,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGTUI) : /* l.sfgtui $rA,$uimm16 */
+ CASE (sem, INSN_L_SFLTS) : /* l.sflts $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
+ UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1898,17 +1894,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGEUI) : /* l.sfgeui $rA,$uimm16 */
+ CASE (sem, INSN_L_SFLTSI) : /* l.sfltsi $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
+ UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1917,17 +1913,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLTUI) : /* l.sfltui $rA,$uimm16 */
+ CASE (sem, INSN_L_SFLTU) : /* l.sfltu $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
+ UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1936,17 +1932,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLEUI) : /* l.sfleui $rA,$uimm16 */
+ CASE (sem, INSN_L_SFLTUI) : /* l.sfltui $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
+ UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1955,17 +1951,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGTSI) : /* l.sfgtsi $rA,${simm16} */
+ CASE (sem, INSN_L_SFLES) : /* l.sfles $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
+ UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1974,7 +1970,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFGESI) : /* l.sfgesi $rA,${simm16} */
+ CASE (sem, INSN_L_SFLESI) : /* l.sflesi $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1984,7 +1980,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
+ UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1993,17 +1989,17 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLTSI) : /* l.sfltsi $rA,${simm16} */
+ CASE (sem, INSN_L_SFLEU) : /* l.sfleu $rA,$rB */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
+ UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -2012,7 +2008,7 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_SFLESI) : /* l.sflesi $rA,${simm16} */
+ CASE (sem, INSN_L_SFLEUI) : /* l.sfleui $rA,$simm16 */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2022,7 +2018,7 @@ if (GET_H_SYS_SR_F ()) {
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
+ UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -2167,11 +2163,11 @@ if (GET_H_SYS_SR_F ()) {
}
NEXT (vpc);
- CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16-split} */
+ CASE (sem, INSN_L_MACI) : /* l.maci $rA,${simm16} */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
-#define FLD(f) abuf->fields.sfmt_l_sw.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
@@ -2179,7 +2175,7 @@ if (GET_H_SYS_SR_F ()) {
{
DI tmp_prod;
DI tmp_result;
- tmp_prod = MULDI (EXTSIDI (FLD (f_simm16_split)), GET_H_GPR (FLD (f_r2)));
+ tmp_prod = MULDI (EXTSIDI (FLD (f_simm16)), GET_H_GPR (FLD (f_r2)));
tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTDIDI (tmp_prod));
{
SI opval = SUBWORDDISI (tmp_result, 0);
diff --git a/sim/or1k/sem64.c b/sim/or1k/sem64.c
index 12dd361..08bc8bb 100644
--- a/sim/or1k/sem64.c
+++ b/sim/or1k/sem64.c
@@ -472,7 +472,7 @@ SEM_FN_NAME (or1k64bf,l_rfe) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-or1k64bf_rfe (current_cpu, pc);
+or1k64bf_rfe (current_cpu);
return vpc;
#undef FLD
@@ -528,22 +528,18 @@ SEM_FN_NAME (or1k64bf,l_macrc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI temp0;UDI temp1;UDI temp2;
- temp0 = GET_H_MAC_MACLO ();
- temp1 = 0;
- temp2 = 0;
{
- UDI opval = temp0;
+ UDI opval = GET_H_MAC_MACLO ();
SET_H_GPR (FLD (f_r1), opval);
TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
{
- UDI opval = temp1;
+ UDI opval = 0;
SET_H_MAC_MACLO (opval);
TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'D', opval);
}
{
- UDI opval = temp2;
+ UDI opval = 0;
SET_H_MAC_MACHI (opval);
TRACE_RESULT (current_cpu, abuf, "mac-machi", 'D', opval);
}
@@ -565,7 +561,7 @@ SEM_FN_NAME (or1k64bf,l_mfspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = or1k64bf_mfspr (current_cpu, pc, FLD (f_r1), ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16))));
+ UDI opval = or1k64bf_mfspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16))));
SET_H_GPR (FLD (f_r1), opval);
TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
@@ -585,7 +581,7 @@ SEM_FN_NAME (or1k64bf,l_mtspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
-or1k64bf_mtspr (current_cpu, pc, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
+or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16_split))), GET_H_GPR (FLD (f_r3)));
return vpc;
#undef FLD
@@ -1103,12 +1099,12 @@ SEM_FN_NAME (or1k64bf,l_addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
BI tmp_tmp_sys_sr_cy;
tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
{
- BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), GET_H_SYS_SR_CY ());
+ BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), GET_H_SYS_SR_CY ());
+ BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
@@ -1274,7 +1270,7 @@ if (NEDI (GET_H_GPR (FLD (f_r3)), 0)) {
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- UDI opval = DIVDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = UDIVDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
@@ -1462,12 +1458,12 @@ SEM_FN_NAME (or1k64bf,l_addic) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
BI tmp_tmp_sys_sr_cy;
tmp_tmp_sys_sr_cy = GET_H_SYS_SR_CY ();
{
- BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), GET_H_SYS_SR_CY ());
+ BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
- BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), GET_H_SYS_SR_CY ());
+ BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
@@ -1682,10 +1678,10 @@ if (GET_H_SYS_SR_F ()) {
#undef FLD
}
-/* l-sfgtu: l.sfgtu $rA,$rB */
+/* l-sfgts: l.sfgts $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1694,7 +1690,7 @@ SEM_FN_NAME (or1k64bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1703,19 +1699,19 @@ SEM_FN_NAME (or1k64bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgeu: l.sfgeu $rA,$rB */
+/* l-sfgtsi: l.sfgtsi $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfgtsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1724,10 +1720,10 @@ SEM_FN_NAME (or1k64bf,l_sfgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfltu: l.sfltu $rA,$rB */
+/* l-sfgtu: l.sfgtu $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1736,7 +1732,7 @@ SEM_FN_NAME (or1k64bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1745,19 +1741,19 @@ SEM_FN_NAME (or1k64bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfleu: l.sfleu $rA,$rB */
+/* l-sfgtui: l.sfgtui $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfgtui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1766,10 +1762,10 @@ SEM_FN_NAME (or1k64bf,l_sfleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgts: l.sfgts $rA,$rB */
+/* l-sfges: l.sfges $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1778,7 +1774,7 @@ SEM_FN_NAME (or1k64bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1787,19 +1783,19 @@ SEM_FN_NAME (or1k64bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfges: l.sfges $rA,$rB */
+/* l-sfgesi: l.sfgesi $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1808,10 +1804,10 @@ SEM_FN_NAME (or1k64bf,l_sfges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sflts: l.sflts $rA,$rB */
+/* l-sfgeu: l.sfgeu $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1820,7 +1816,7 @@ SEM_FN_NAME (or1k64bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1829,19 +1825,19 @@ SEM_FN_NAME (or1k64bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfles: l.sfles $rA,$rB */
+/* l-sfgeui: l.sfgeui $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfles) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sll.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
+ UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1850,19 +1846,19 @@ SEM_FN_NAME (or1k64bf,l_sfles) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgtui: l.sfgtui $rA,$uimm16 */
+/* l-sflts: l.sflts $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfgtui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
+ UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1871,19 +1867,19 @@ SEM_FN_NAME (or1k64bf,l_sfgtui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgeui: l.sfgeui $rA,$uimm16 */
+/* l-sfltsi: l.sfltsi $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfltsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
+ UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1892,19 +1888,19 @@ SEM_FN_NAME (or1k64bf,l_sfgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfltui: l.sfltui $rA,$uimm16 */
+/* l-sfltu: l.sfltu $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfltui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
+ UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1913,19 +1909,19 @@ SEM_FN_NAME (or1k64bf,l_sfltui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfleui: l.sfleui $rA,$uimm16 */
+/* l-sfltui: l.sfltui $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfleui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfltui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_mfspr.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
+ UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1934,19 +1930,19 @@ SEM_FN_NAME (or1k64bf,l_sfleui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgtsi: l.sfgtsi $rA,${simm16} */
+/* l-sfles: l.sfles $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfgtsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfles) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
+ UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1955,10 +1951,10 @@ SEM_FN_NAME (or1k64bf,l_sfgtsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfgesi: l.sfgesi $rA,${simm16} */
+/* l-sflesi: l.sflesi $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sflesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -1967,7 +1963,7 @@ SEM_FN_NAME (or1k64bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
+ UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1976,19 +1972,19 @@ SEM_FN_NAME (or1k64bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sfltsi: l.sfltsi $rA,${simm16} */
+/* l-sfleu: l.sfleu $rA,$rB */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sfltsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_lwz.f
+#define FLD(f) abuf->fields.sfmt_l_sll.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
+ UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -1997,10 +1993,10 @@ SEM_FN_NAME (or1k64bf,l_sfltsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-sflesi: l.sflesi $rA,${simm16} */
+/* l-sfleui: l.sfleui $rA,$simm16 */
static SEM_PC
-SEM_FN_NAME (or1k64bf,l_sflesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+SEM_FN_NAME (or1k64bf,l_sfleui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
@@ -2009,7 +2005,7 @@ SEM_FN_NAME (or1k64bf,l_sflesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
{
- UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
+ UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
@@ -2166,12 +2162,12 @@ SEM_FN_NAME (or1k64bf,l_msb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
#undef FLD
}
-/* l-maci: l.maci $rA,${simm16-split} */
+/* l-maci: l.maci $rA,${simm16} */
static SEM_PC
SEM_FN_NAME (or1k64bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_l_sw.f
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
int UNUSED written = 0;
IADDR UNUSED pc = abuf->addr;
@@ -2180,7 +2176,7 @@ SEM_FN_NAME (or1k64bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DI tmp_prod;
DI tmp_result;
- tmp_prod = MULDI (EXTSIDI (FLD (f_simm16_split)), GET_H_GPR (FLD (f_r2)));
+ tmp_prod = MULDI (EXTSIDI (FLD (f_simm16)), GET_H_GPR (FLD (f_r2)));
tmp_result = ADDDI (JOINSIDI (GET_H_MAC_MACHI (), GET_H_MAC_MACLO ()), EXTDIDI (tmp_prod));
{
SI opval = SUBWORDDISI (tmp_result, 0);
@@ -3021,22 +3017,22 @@ static const struct sem_fn_desc sem_fns[] = {
{ OR1K64BF_INSN_L_EXTWS, SEM_FN_NAME (or1k64bf,l_extws) },
{ OR1K64BF_INSN_L_EXTWZ, SEM_FN_NAME (or1k64bf,l_extwz) },
{ OR1K64BF_INSN_L_CMOV, SEM_FN_NAME (or1k64bf,l_cmov) },
- { OR1K64BF_INSN_L_SFGTU, SEM_FN_NAME (or1k64bf,l_sfgtu) },
- { OR1K64BF_INSN_L_SFGEU, SEM_FN_NAME (or1k64bf,l_sfgeu) },
- { OR1K64BF_INSN_L_SFLTU, SEM_FN_NAME (or1k64bf,l_sfltu) },
- { OR1K64BF_INSN_L_SFLEU, SEM_FN_NAME (or1k64bf,l_sfleu) },
{ OR1K64BF_INSN_L_SFGTS, SEM_FN_NAME (or1k64bf,l_sfgts) },
- { OR1K64BF_INSN_L_SFGES, SEM_FN_NAME (or1k64bf,l_sfges) },
- { OR1K64BF_INSN_L_SFLTS, SEM_FN_NAME (or1k64bf,l_sflts) },
- { OR1K64BF_INSN_L_SFLES, SEM_FN_NAME (or1k64bf,l_sfles) },
- { OR1K64BF_INSN_L_SFGTUI, SEM_FN_NAME (or1k64bf,l_sfgtui) },
- { OR1K64BF_INSN_L_SFGEUI, SEM_FN_NAME (or1k64bf,l_sfgeui) },
- { OR1K64BF_INSN_L_SFLTUI, SEM_FN_NAME (or1k64bf,l_sfltui) },
- { OR1K64BF_INSN_L_SFLEUI, SEM_FN_NAME (or1k64bf,l_sfleui) },
{ OR1K64BF_INSN_L_SFGTSI, SEM_FN_NAME (or1k64bf,l_sfgtsi) },
+ { OR1K64BF_INSN_L_SFGTU, SEM_FN_NAME (or1k64bf,l_sfgtu) },
+ { OR1K64BF_INSN_L_SFGTUI, SEM_FN_NAME (or1k64bf,l_sfgtui) },
+ { OR1K64BF_INSN_L_SFGES, SEM_FN_NAME (or1k64bf,l_sfges) },
{ OR1K64BF_INSN_L_SFGESI, SEM_FN_NAME (or1k64bf,l_sfgesi) },
+ { OR1K64BF_INSN_L_SFGEU, SEM_FN_NAME (or1k64bf,l_sfgeu) },
+ { OR1K64BF_INSN_L_SFGEUI, SEM_FN_NAME (or1k64bf,l_sfgeui) },
+ { OR1K64BF_INSN_L_SFLTS, SEM_FN_NAME (or1k64bf,l_sflts) },
{ OR1K64BF_INSN_L_SFLTSI, SEM_FN_NAME (or1k64bf,l_sfltsi) },
+ { OR1K64BF_INSN_L_SFLTU, SEM_FN_NAME (or1k64bf,l_sfltu) },
+ { OR1K64BF_INSN_L_SFLTUI, SEM_FN_NAME (or1k64bf,l_sfltui) },
+ { OR1K64BF_INSN_L_SFLES, SEM_FN_NAME (or1k64bf,l_sfles) },
{ OR1K64BF_INSN_L_SFLESI, SEM_FN_NAME (or1k64bf,l_sflesi) },
+ { OR1K64BF_INSN_L_SFLEU, SEM_FN_NAME (or1k64bf,l_sfleu) },
+ { OR1K64BF_INSN_L_SFLEUI, SEM_FN_NAME (or1k64bf,l_sfleui) },
{ OR1K64BF_INSN_L_SFEQ, SEM_FN_NAME (or1k64bf,l_sfeq) },
{ OR1K64BF_INSN_L_SFEQI, SEM_FN_NAME (or1k64bf,l_sfeqi) },
{ OR1K64BF_INSN_L_SFNE, SEM_FN_NAME (or1k64bf,l_sfne) },
--
2.7.4
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 10/18] sim: testsuite: add testsuite for or1k sim
2016-11-23 22:14 [PATCH 00/18] sim: port for OpenRISC Stafford Horne
` (7 preceding siblings ...)
2016-11-23 22:16 ` [PATCH 01/18] sim: cgen: add rem (remainder) function (needed for OR1K lf.rem.[sd]) Stafford Horne
@ 2016-11-23 22:16 ` Stafford Horne
2016-11-23 22:16 ` [PATCH 12/18] sim: or1k: Get or1k sim building with latest sim common Stafford Horne
` (8 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Stafford Horne @ 2016-11-23 22:16 UTC (permalink / raw)
To: gdb-patches; +Cc: openrisc, Peter Gavin
From: Peter Gavin <pgavin@gmail.com>
* sim/testsuite/ChangeLog-OR1K:
* add testsuite for or1k
---
sim/testsuite/sim/or1k/add.S | 546 +++++++++++++++++
sim/testsuite/sim/or1k/alltests.exp | 19 +
sim/testsuite/sim/or1k/and.S | 208 +++++++
sim/testsuite/sim/or1k/basic.S | 535 +++++++++++++++++
sim/testsuite/sim/or1k/div.S | 198 +++++++
sim/testsuite/sim/or1k/ext.S | 251 ++++++++
sim/testsuite/sim/or1k/find.S | 119 ++++
sim/testsuite/sim/or1k/flag.S | 405 +++++++++++++
sim/testsuite/sim/or1k/jump.S | 121 ++++
sim/testsuite/sim/or1k/load.S | 373 ++++++++++++
sim/testsuite/sim/or1k/mac.S | 785 +++++++++++++++++++++++++
sim/testsuite/sim/or1k/mfspr.S | 196 ++++++
sim/testsuite/sim/or1k/mul.S | 277 +++++++++
sim/testsuite/sim/or1k/or.S | 207 +++++++
sim/testsuite/sim/or1k/or1k-asm-test-env.h | 61 ++
sim/testsuite/sim/or1k/or1k-asm-test-helpers.h | 134 +++++
sim/testsuite/sim/or1k/or1k-asm-test.h | 258 ++++++++
sim/testsuite/sim/or1k/or1k-asm.h | 20 +
sim/testsuite/sim/or1k/or1k-test.ld | 57 ++
sim/testsuite/sim/or1k/ror.S | 186 ++++++
sim/testsuite/sim/or1k/shift.S | 572 ++++++++++++++++++
sim/testsuite/sim/or1k/spr-defs.h | 590 +++++++++++++++++++
sim/testsuite/sim/or1k/sub.S | 176 ++++++
sim/testsuite/sim/or1k/xor.S | 210 +++++++
24 files changed, 6504 insertions(+)
create mode 100644 sim/testsuite/sim/or1k/add.S
create mode 100644 sim/testsuite/sim/or1k/alltests.exp
create mode 100644 sim/testsuite/sim/or1k/and.S
create mode 100644 sim/testsuite/sim/or1k/basic.S
create mode 100644 sim/testsuite/sim/or1k/div.S
create mode 100644 sim/testsuite/sim/or1k/ext.S
create mode 100644 sim/testsuite/sim/or1k/find.S
create mode 100644 sim/testsuite/sim/or1k/flag.S
create mode 100644 sim/testsuite/sim/or1k/jump.S
create mode 100644 sim/testsuite/sim/or1k/load.S
create mode 100644 sim/testsuite/sim/or1k/mac.S
create mode 100644 sim/testsuite/sim/or1k/mfspr.S
create mode 100644 sim/testsuite/sim/or1k/mul.S
create mode 100644 sim/testsuite/sim/or1k/or.S
create mode 100644 sim/testsuite/sim/or1k/or1k-asm-test-env.h
create mode 100644 sim/testsuite/sim/or1k/or1k-asm-test-helpers.h
create mode 100644 sim/testsuite/sim/or1k/or1k-asm-test.h
create mode 100644 sim/testsuite/sim/or1k/or1k-asm.h
create mode 100644 sim/testsuite/sim/or1k/or1k-test.ld
create mode 100644 sim/testsuite/sim/or1k/ror.S
create mode 100644 sim/testsuite/sim/or1k/shift.S
create mode 100644 sim/testsuite/sim/or1k/spr-defs.h
create mode 100644 sim/testsuite/sim/or1k/sub.S
create mode 100644 sim/testsuite/sim/or1k/xor.S
diff --git a/sim/testsuite/sim/or1k/add.S b/sim/testsuite/sim/or1k/add.S
new file mode 100644
index 0000000..ee565c3
--- /dev/null
+++ b/sim/testsuite/sim/or1k/add.S
@@ -0,0 +1,546 @@
+/* Tests instructions l.add, l.addc, l.addi and l.addic
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x00000001);\n
+# output: report(0x00000002);\n
+# output: report(0x00000003);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: report(0x00000002);\n
+# output: report(0x00000003);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0xfffffffe);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x40000000);\n
+# output: report(0x3fffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x40000000);\n
+# output: report(0x40000000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xc0000000);\n
+# output: report(0xc0000000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xbfffffff);\n
+# output: report(0xbfffffff);\n
+# output: report(0x7ffffffe);\n
+# output: report(0x00000001);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0xfffffffe);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: report(0x00000002);\n
+# output: report(0x00000003);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0xfffffffe);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x40000000);\n
+# output: report(0x3fffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x40000000);\n
+# output: report(0x3fffffff);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x40000000);\n
+# output: report(0x40000000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xc0000000);\n
+# output: report(0xc0000000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xc0000000);\n
+# output: report(0xbfffffff);\n
+# output: report(0x80000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xbfffffff);\n
+# output: report(0xbfffffff);\n
+# output: report(0x7ffffffe);\n
+# output: report(0x00000001);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0xfffffffe);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: report(0x00000002);\n
+# output: report(0x00000003);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: report(0x00000002);\n
+# output: report(0x00000003);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0x0000fffe);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x7fff8000);\n
+# output: report(0x00007fff);\n
+# output: report(0x7fffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x7fffc000);\n
+# output: report(0x00004000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x80008000);\n
+# output: report(0x00008000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x80007fff);\n
+# output: report(0x00008000);\n
+# output: report(0x7fffffff);\n
+# output: report(0x00000001);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0x0000fffe);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: report(0x00000002);\n
+# output: report(0x00000003);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0x0000fffe);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x7fff8000);\n
+# output: report(0x00007fff);\n
+# output: report(0x7fffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x7fff8000);\n
+# output: report(0x00007fff);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x7fffc000);\n
+# output: report(0x00004000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: report(0x0000ffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x80008000);\n
+# output: report(0x00008000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x80007fff);\n
+# output: report(0x00008000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x80007fff);\n
+# output: report(0x00008000);\n
+# output: report(0x7fffffff);\n
+# output: report(0x00000001);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0x0000fffe);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: report(0x0000ffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .exception_vectors
+
+ // Alignment exception.
+ .org 0x600
+ // TODO: print out address of instruction that caused the problem
+
+ // Range exception.
+ .org 0xb00
+
+ // TODO: The stack safety zone is not taken into consideration.
+
+ // The handling is a bit dubious at present. We just patch the instruction with l.nop and
+ // restart. This will go wrong in branch delay slots. Really we need to single
+
+ // step past and then continue.
+
+
+ // TODO: do we need to patch the instruction? Can we not skip it somehow?
+
+ PUSH r2
+ PUSH r3
+
+ MOVE_FROM_SPR r2, SPR_EPCR_BASE // Address of the instruction that caused the problem.
+
+ LOAD_IMMEDIATE r3, 0x15000000 // Opcode for l.nop
+ l.sw -4(r2), r3 // TODO: temporary, remove at the end
+ l.sw 0(r2), r3
+ l.sw +4(r2), r3 // TODO: temporary, remove at the end
+
+ POP r3
+ POP r2
+
+ l.rfe
+
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // ----------- Test l.add -----------
+
+ // Add two small positive numbers
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 1, 2
+
+ // The carry flag should be ignored.
+ TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.add, 1, 2
+
+ // Add two small negative numbers, which should set the carry flag but not the overflow flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, -1, -2
+
+ // Add two quite large positive numbers. Should set neither the overflow nor the carry flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, 0x3fffffff
+
+ // Add two large positive numbers. Should set the overflow, but not the carry flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, 0x40000000
+
+ // Add two quite large negative numbers. Should set the carry, but not the overflow flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, -1073741824, -1073741824 // -1073741824 = 0xC0000000
+
+ // Add two large negative numbers. Should set both the overflow and carry flags.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xbfffffff, 0xbfffffff
+
+
+ // ------ Check that range exceptions are triggered.
+
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // TODO: Disabled at the moment, as this test fails against the ORPSoC V2 core.
+ // Check that an overflow alone causes a RANGE Exception.
+ // TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0x40000000, 0x40000000
+
+ // Check that a carry alone does not cause a RANGE Exception.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xffffffff, 0xfffffffe
+
+ // TODO: Disabled at the moment, as this test fails against the ORPSoC V2 core.
+ // Check that carry and overflow together cause an exception.
+ // TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.add, 0xbfffffff, 0xbfffffff
+
+ CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+
+ // ----------- Test l.addc -----------
+
+ // Add two small positive numbers
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 1, 2
+
+ // Add two small negative numbers. Sets the carry flag but not the overflow flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1, -2
+
+ // Add two quite large positive numbers. Should set neither the overflow nor the carry flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, 0x3fffffff
+
+ // Add two quite large positive numbers with a carry in. Should set the overflow but not the carry flag.
+ TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x40000000, 0x3fffffff
+
+ // Add two large positive numbers. Should set the overflow, but not the carry flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, 0x40000000
+
+ // Add the largest unsigned value to zero with a carry. This potentially can break a
+ // simplistic test for carry that does not consider the carry flag properly. Do it both ways around.
+ // TODO: investigate why this test is failing
+ TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, -1, 0
+ TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0, -1
+
+ // Add two quite large negative numbers. Should set the carry, but not the overflow flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1073741824, -1073741824 // -1073741824 = 0xC0000000
+
+ // Add two quite large negative numbers that would overflow, with a carry that just avoids
+ // the overflow. Should set the carry, but not the overflow flag.
+ TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, -1073741824, -1073741825 // -1073741824 = 0xC0000000, -1073741825 = 0xBFFFFFFF
+
+ // Add two large negative numbers. Should set both the overflow and carry flags.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, -1073741825, -1073741825
+
+
+ // ------ Check that range exceptions are triggered.
+
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // TODO: Disabled at the moment, as this test fails against the ORPSoC V2 core.
+ // Check that an overflow alone causes a RANGE Exception, even when it
+ // is the carry that causes the overflow.
+ // TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0x40000000, 0x40000000
+ // TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x40000000, 0x3fffffff
+
+ // Check that a carry alone does not cause a RANGE Exception, even when it is the carry that causes the overflow.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0xffffffff, 0xfffffffe
+ TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.addc, 0x00000000, 0xffffffff
+
+ // TODO: Disabled at the moment, as this test fails against the ORPSoC V2 core.
+ // Check that carry and overflow together cause an exception.
+ // TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.addc, 0xbfffffff, 0xbfffffff
+
+ CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+
+ // ----------- Test l.addi -----------
+
+ // Add two small positive numbers
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 1, 2
+
+ // Check carry in is ignored.
+ TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addi, 1, 2
+
+ // Add two small negative numbers. Sets the carry flag but not the overflow flag.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0xffffffff, 0xfffe
+
+ // Add two quite large positive numbers. Should set neither the overflow nor the carry flag.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fff8000, 0x7fff
+
+ // Add two large positive numbers. Should set the overflow, but not the carry flag.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fffc000, 0x4000
+
+ // Add two quite large negative numbers. Should set the carry, but not the overflow flag.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80008000, 0x8000
+
+ // Add two large negative numbers. Should set both the overflow and carry flags.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80007fff, 0x8000
+
+ // ------ Check that range exceptions are triggered.
+
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // TODO: Disabled at the moment, as this test fails against the ORPSoC V2 core.
+ // Check that an overflow alone causes a RANGE Exception.
+ // TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x7fffc000, 0x4000
+
+ // Check that a carry alone does not cause a RANGE Exception.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0xffffffff, 0xfffe
+
+ // TODO: Disabled at the moment, as this test fails against the ORPSoC V2 core.
+ // Check that carry and overflow together cause an exception.
+ // TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addi, 0x80007fff, 0x8000
+
+ CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+
+ // ----------- Test l.addi -----------
+
+ // Add two small positive numbers
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 1, 2
+
+ // Add two small negative numbers. Sets the carry flag but not the overflow flag.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0xffffffff, 0xfffe
+
+ // Add two quite large positive numbers. Should set neither the overflow nor the carry flag.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fff8000, 0x7fff
+
+ // Add two quite large positive numbers with a carry in. Should set the overflow but not the carry flag.
+ TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x7fff8000, 0x7fff
+
+ // Add two large positive numbers. Should set the overflow, but not the carry flag.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fffc000, 0x4000
+
+ // Add the largest unsigned value to zero with a carry. This potentially can break a simplistic
+ // test for carry that does not consider the carry flag properly. Do it both ways around.
+ TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0xffffffff, 0x0000
+ TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x00000000, 0xffff
+
+ // Add two quite large negative numbers. Should set the carry, but not the overflow flag.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80008000, 0x8000
+
+ // Add two quite large negative numbers that would overflow, with a carry that just avoids the overflow.
+ // Should set the carry, but not the overflow flag. flag.
+ TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x80007fff, 0x8000
+
+ // Add two large negative numbers. Should set both the overflow and carry flags.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80007fff, 0x8000
+
+ // ------ Check that range exceptions are triggered.
+
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // Check that an overflow alone causes a RANGE Exception, even when it
+ // is the carry that causes the overflow.
+ // TODO: Disabled at the moment, as this test fails against the ORPSoC V2 core.
+ // TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x7fffc000, 0x4000
+ // TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x7fffc000, 0x3fff
+
+ // Check that a carry alone does not cause a RANGE Exception, even
+ // when it is the carry that causes the overflow.
+ TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0xffffffff, 0xfffe
+ TEST_INST_FF_I32_I16 SPR_SR_CY, SPR_SR_OV, l.addic, 0x00000000, 0xffff
+
+ // Check that carry and overflow together cause an exception.
+ // TEST_INST_FF_I32_I16 0, SPR_SR_CY | SPR_SR_OV, l.addic, 0x80007fff, 0x8000
+
+ CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/alltests.exp b/sim/testsuite/sim/or1k/alltests.exp
new file mode 100644
index 0000000..f10379e
--- /dev/null
+++ b/sim/testsuite/sim/or1k/alltests.exp
@@ -0,0 +1,19 @@
+# OR1K simulator testsuite.
+
+if [istarget or1k*-*-*] {
+
+ set all_machs "or1k"
+
+ global global_ld_options
+ set global_ld_options "-T $srcdir/$subdir/or1k-test.ld"
+
+ foreach src [lsort [glob -nocomplain $srcdir/$subdir/*.S]] {
+
+ if ![runtest_file_p $runtests $src] {
+ continue
+ }
+
+ run_sim_test $src $all_machs
+ }
+
+}
\ No newline at end of file
diff --git a/sim/testsuite/sim/or1k/and.S b/sim/testsuite/sim/or1k/and.S
new file mode 100644
index 0000000..6552474
--- /dev/null
+++ b/sim/testsuite/sim/or1k/and.S
@@ -0,0 +1,208 @@
+/* Tests instructions l.and, l.andi
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0xaaaaaaaa);\n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x55555555);\n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0xc4c70f07);\n
+# output: report(0x44400004);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x38f0f83b);\n
+# output: report(0x30800803);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0x0000ffff);\n
+# output: report(0x0000ffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x0000aaaa);\n
+# output: report(0x0000aaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x00005555);\n
+# output: report(0x00005555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00005555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000f83);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000f07);\n
+# output: report(0x00000004);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000f83b);\n
+# output: report(0x00000803);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+ // Always set OVE. We should never trigger an exception, even if this bit is set.
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // Test the l.and instruction with a range of operands.
+
+ TEST_INST_I32_I32 l.and, 0x00000000, 0x00000000
+ TEST_INST_I32_I32 l.and, 0xffffffff, 0xffffffff
+ TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0x00000000
+ TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0xaaaaaaaa
+ TEST_INST_I32_I32 l.and, 0x55555555, 0x00000000
+ TEST_INST_I32_I32 l.and, 0x55555555, 0x55555555
+ TEST_INST_I32_I32 l.and, 0xaaaaaaaa, 0x55555555
+ TEST_INST_I32_I32 l.and, 0x4c70f07c, 0xb38f0f83
+ TEST_INST_I32_I32 l.and, 0x4c70f07c, 0xc4c70f07
+ TEST_INST_I32_I32 l.and, 0xb38f0f83, 0x38f0f83b
+
+ // Test the l.andi instruction with a range of operands.
+
+ TEST_INST_I32_I16 l.andi, 0x00000000, 0x0000
+ TEST_INST_I32_I16 l.andi, 0xffffffff, 0xffff
+ TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0x0000
+ TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0xaaaa
+ TEST_INST_I32_I16 l.andi, 0x55555555, 0x0000
+ TEST_INST_I32_I16 l.andi, 0x55555555, 0x5555
+ TEST_INST_I32_I16 l.andi, 0xaaaaaaaa, 0x5555
+ TEST_INST_I32_I16 l.andi, 0x4c70f07c, 0x0f83
+ TEST_INST_I32_I16 l.andi, 0x4c70f07c, 0x0f07
+ TEST_INST_I32_I16 l.andi, 0xb38f0f83, 0xf83b
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/basic.S b/sim/testsuite/sim/or1k/basic.S
new file mode 100644
index 0000000..1e349a0
--- /dev/null
+++ b/sim/testsuite/sim/or1k/basic.S
@@ -0,0 +1,535 @@
+/* Tests some basic CPU instructions.
+
+ Copyright (C) 1999-2006 OpenCores
+ Contributors various OpenCores participants
+ Copyright (C) 2010 Embecosm Limited
+ Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ Copyright (C) 2012 R. Diez
+
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+# mach: or1k
+# output: report(0xffff0012);\n
+# output: report(0x12352af7);\n
+# output: report(0x7ffffffe);\n
+# output: report(0xffffa5a7);\n
+# output: report(0x000fffff);\n
+# output: report(0x00002800);\n
+# output: report(0x00000009);\n
+# output: report(0xdeaddead);\n
+# output: report(0xffff0000);\n
+# output: report(0x12345678);\n
+# output: report(0xabcdf0bd);\n
+# output: exit(0)\n
+
+#include "or1k-asm-test-env.h"
+
+#define FIRST_RAM_ADDR 0x00000000
+
+
+ STANDARD_TEST_HEADER
+
+ // -------- Early test begin.
+
+ // Do this test upfront, as it modifies STACK_POINTER_R1.
+
+ l.addi r1 , r0 , 0x1
+ l.addi r2 , r1 , 0x2
+ l.addi r3 , r2 , 0x4
+ l.addi r4 , r3 , 0x8
+ l.addi r5 , r4 , 0x10
+ l.addi r6 , r5 , 0x20
+ l.addi r7 , r6 , 0x40
+ l.addi r8 , r7 , 0x80
+ l.addi r9 , r8 , 0x100
+ l.addi r10, r9 , 0x200
+ l.addi r11, r10, 0x400
+ l.addi r12, r11, 0x800
+ l.addi r13, r12, 0x1000
+ l.addi r14, r13, 0x2000
+ l.addi r15, r14, 0x4000
+ l.addi r16, r15, 0x8000
+
+ l.sub r31, r0 , r1
+ l.sub r30, r31, r2
+ l.sub r29, r30, r3
+ l.sub r28, r29, r4
+ l.sub r27, r28, r5
+ l.sub r26, r27, r6
+ l.sub r25, r26, r7
+ l.sub r24, r25, r8
+ l.sub r23, r24, r9
+ l.sub r22, r23, r10
+ l.sub r21, r22, r11
+ l.sub r20, r21, r12
+ l.sub r19, r20, r13
+ l.sub r18, r19, r14
+ l.sub r17, r18, r15
+ l.sub r16, r17, r16
+
+ // We cannot use REPORT_REG_TO_CONSOLE here, as the stack is not set up yet.
+ MOVE_REG NOP_REPORT_R3, r16
+ REPORT_TO_CONSOLE // Should be 0xffff0012
+
+ // -------- Early test end.
+
+ STANDARD_TEST_BODY
+
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+ // ------ Read and write from RAM -----
+
+ LOAD_IMMEDIATE r31, FIRST_RAM_ADDR
+ l.sw 0(r31), r16
+
+ l.movhi r3,0x1234
+ l.ori r3,r3,0x5678
+
+ l.sw 4(r31),r3
+
+ l.lbz r4,4(r31)
+ l.add r8,r8,r4
+ l.sb 11(r31),r4
+ l.lbz r4,5(r31)
+ l.add r8,r8,r4
+ l.sb 10(r31),r4
+ l.lbz r4,6(r31)
+ l.add r8,r8,r4
+ l.sb 9(r31),r4
+ l.lbz r4,7(r31)
+ l.add r8,r8,r4
+ l.sb 8(r31),r4
+
+ l.lbs r4,8(r31)
+ l.add r8,r8,r4
+ l.sb 7(r31),r4
+ l.lbs r4,9(r31)
+ l.add r8,r8,r4
+ l.sb 6(r31),r4
+ l.lbs r4,10(r31)
+ l.add r8,r8,r4
+ l.sb 5(r31),r4
+ l.lbs r4,11(r31)
+ l.add r8,r8,r4
+ l.sb 4(r31),r4
+
+ l.lhz r4,4(r31)
+ l.add r8,r8,r4
+ l.sh 10(r31),r4
+ l.lhz r4,6(r31)
+ l.add r8,r8,r4
+ l.sh 8(r31),r4
+
+ l.lhs r4,8(r31)
+ l.add r8,r8,r4
+ l.sh 6(r31),r4
+ l.lhs r4,10(r31)
+ l.add r8,r8,r4
+ l.sh 4(r31),r4
+
+ l.lwz r4,4(r31)
+ l.add r8,r8,r4
+
+ REPORT_REG_TO_CONSOLE r8 // Should be 0x12352af7
+
+ l.lwz r9,0(r31)
+ l.add r8,r9,r8
+ l.sw 0(r31),r8
+
+
+ // ------ Do some arithmetic operations -----
+
+ l.addi r3,r0,1
+ l.addi r4,r0,2
+ l.addi r5,r0,-1
+ l.addi r6,r0,-1
+ l.addi r8,r0,0
+
+ l.sub r7,r5,r3
+ l.sub r8,r3,r5
+ l.add r8,r8,r7
+
+ l.div r7,r7,r4
+ l.add r9,r3,r4
+ l.mul r7,r9,r7
+ l.divu r7,r7,r4
+ l.add r8,r8,r7
+
+ REPORT_REG_TO_CONSOLE r8 // Should be 0x7ffffffe
+
+ l.lwz r9,0(r31)
+ l.add r8,r9,r8
+ l.sw 0(r31),r8
+
+
+ // ------ Do some logical operations -----
+
+ l.addi r3,r0,1
+ l.addi r4,r0,2
+ l.addi r5,r0,-1
+ l.addi r6,r0,-1
+ l.addi r8,r0,0
+
+ l.andi r8,r8,1
+ l.and r8,r8,r3
+
+ l.xori r8,r5,0xa5a5
+ l.xor r8,r8,r5
+
+ l.ori r8,r8,2
+ l.or r8,r8,r4
+
+ REPORT_REG_TO_CONSOLE r8 // Should be 0xffffa5a7
+
+ l.lwz r9,0(r31)
+ l.add r8,r9,r8
+ l.sw 0(r31),r8
+
+
+ // ------ Do some shifting operations -----
+
+ l.addi r3,r0,1
+ l.addi r4,r0,2
+ l.addi r5,r0,-1
+ l.addi r6,r0,-1
+ l.addi r8,r0,0
+
+ l.slli r8,r5,6
+ l.sll r8,r8,r4
+
+ l.srli r8,r8,6
+ l.srl r8,r8,r4
+
+ l.srai r8,r8,2
+ l.sra r8,r8,r4
+
+ REPORT_REG_TO_CONSOLE r8 // Should be 0x000fffff
+
+ l.lwz r9,0(r31)
+ l.add r8,r9,r8
+ l.sw 0(r31),r8
+
+
+ // ------ Test the CPU flag -----
+
+ l.addi r3,r0,1
+ l.addi r4,r0,-2
+ l.addi r8,r0,0
+
+ l.sfeq r3,r3
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfeq r3,r4
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfeqi r3,1
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfeqi r3,-2
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfne r3,r3
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfne r3,r4
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfnei r3,1
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfnei r3,-2
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgtu r3,r3
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgtu r3,r4
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgtui r3,1
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgtui r3,-2
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgeu r3,r3
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgeu r3,r4
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgeui r3,1
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgeui r3,-2
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfltu r3,r3
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfltu r3,r4
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfltui r3,1
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfltui r3,-2
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfleu r3,r3
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfleu r3,r4
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfleui r3,1
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfleui r3,-2
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgts r3,r3
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgts r3,r4
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgtsi r3,1
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgtsi r3,-2
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfges r3,r3
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfges r3,r4
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgesi r3,1
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfgesi r3,-2
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sflts r3,r3
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sflts r3,r4
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfltsi r3,1
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfltsi r3,-2
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfles r3,r3
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sfles r3,r4
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sflesi r3,1
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ l.sflesi r3,-2
+ l.mfspr r5,r0,17
+ l.andi r4,r5,0x200
+ l.add r8,r8,r4
+
+ REPORT_REG_TO_CONSOLE r8 // Should be 0x00002800
+
+ l.lwz r9,0(r31)
+ l.add r8,r9,r8
+ l.sw 0(r31),r8
+
+
+ // ------ Test the jump instructions -----
+
+ l.addi r8,r0,0
+
+ OR1K_DELAYED(
+ OR1K_INST(l.addi r8,r8,1),
+ OR1K_INST(l.j _T1)
+ )
+
+_T2: OR1K_DELAYED(
+ OR1K_INST(l.addi r8,r8,1),
+ OR1K_INST(l.jr r9)
+ )
+
+_T1: OR1K_DELAYED(
+ OR1K_INST(l.addi r8,r8,1),
+ OR1K_INST(l.jal _T2)
+ )
+
+ l.sfeqi r0,0
+ OR1K_DELAYED(
+ OR1K_INST(l.addi r8,r8,1),
+ OR1K_INST(l.bf _T3)
+ )
+
+_T3: l.sfeqi r0,1
+ OR1K_DELAYED(
+ OR1K_INST(l.addi r8,r8,1),
+ OR1K_INST(l.bf _T4)
+ )
+
+ l.addi r8,r8,1
+
+_T4: l.sfeqi r0,0
+ OR1K_DELAYED(
+ OR1K_INST(l.addi r8,r8,1),
+ OR1K_INST(l.bnf _T5)
+ )
+
+ l.addi r8,r8,1
+
+_T5: l.sfeqi r0,1
+ OR1K_DELAYED(
+ OR1K_INST(l.addi r8,r8,1),
+ OR1K_INST(l.bnf _T6)
+ )
+
+ l.addi r8,r8,1
+
+_T6: l.movhi r3,hi(_T7)
+ l.ori r3,r3,lo(_T7)
+ l.mtspr r0,r3,32
+ l.mfspr r5,r0,17
+ l.mtspr r0,r5,64
+ l.rfe
+ l.addi r8,r8,1 // l.rfe should not have a delay slot
+
+ l.addi r8,r8,1
+
+_T7: REPORT_REG_TO_CONSOLE r8 // Should be 0x000000009
+
+ l.lwz r9,0(r31)
+ l.add r8,r9,r8
+ l.sw 0(r31),r8
+
+ l.lwz r9,0(r31)
+ l.movhi r3,0x4c69
+ l.ori r3,r3,0xe5f7
+ l.add r8,r8,r3
+
+ REPORT_REG_TO_CONSOLE r8 // Should be 0xdeaddead
+
+
+ // Test l.movhi, on 32-bit implementations it should not sign-extend anything.
+
+ l.movhi r3, -1
+ REPORT_REG_TO_CONSOLE r3
+
+
+ // Test l.cmov
+
+ LOAD_IMMEDIATE r14, 0x12345678
+ LOAD_IMMEDIATE r15, 0xABCDF0BD
+
+ SET_SPR_SR_FLAGS SPR_SR_F, r6, r7
+ l.cmov r10, r14, r15
+ CLEAR_SPR_SR_FLAGS SPR_SR_F, r6, r7
+ l.cmov r11, r14, r15
+
+ REPORT_REG_TO_CONSOLE r10
+ REPORT_REG_TO_CONSOLE r11
+
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/div.S b/sim/testsuite/sim/or1k/div.S
new file mode 100644
index 0000000..1821e63
--- /dev/null
+++ b/sim/testsuite/sim/or1k/div.S
@@ -0,0 +1,198 @@
+/* Tests the divide instructions.
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x0000000c);\n
+# output: report(0x00000003);\n
+# output: report(0x00000004);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x0000000b);\n
+# output: report(0x00000003);\n
+# output: report(0x00000003);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xfffffff4);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000004);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xfffffff5);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000003);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xfffffff4);\n
+# output: report(0x00000003);\n
+# output: report(0xfffffffc);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xfffffff5);\n
+# output: report(0x00000003);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x0000000c);\n
+# output: report(0xfffffffd);\n
+# output: report(0xfffffffc);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x0000000b);\n
+# output: report(0xfffffffd);\n
+# output: report(0xfffffffd);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x0000000c);\n
+# output: report(0x00000003);\n
+# output: report(0x00000004);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x0000000b);\n
+# output: report(0x00000003);\n
+# output: report(0x00000003);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xfffffff4);\n
+# output: report(0x00000003);\n
+# output: report(0x55555551);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xfffffff5);\n
+# output: report(0x00000003);\n
+# output: report(0x55555551);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // Test l.div
+
+ // Divide two positive numbers and check rounding. Should set no flags.
+ TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000003 // 12 / 3 = 4
+ TEST_INST_I32_I32 l.div, 0x0000000b, 0x00000003 // 11 / 3 = 3
+
+ // Divide two negative numbers and check rounding. Should set no flags.
+ TEST_INST_I32_I32 l.div, 0xfffffff4, 0xfffffffd
+ TEST_INST_I32_I32 l.div, 0xfffffff5, 0xfffffffd
+
+ // Divide a negative number by a positive number and check rounding. Should set no flags.
+ TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000003
+ TEST_INST_I32_I32 l.div, 0xfffffff5, 0x00000003
+
+ // Divide a positive number by a negative number and check rounding. Should set no flags.
+ TEST_INST_I32_I32 l.div, 0x0000000c, 0xfffffffd
+ TEST_INST_I32_I32 l.div, 0x0000000b, 0xfffffffd
+
+ // Divide by zero. Should set the overflow flag.
+ // TODO: temporarily disabled as these tests fail on both or1ksim and or1200
+ // TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000000
+ // TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000000
+
+ // ------ Check that range exceptions are triggered.
+
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // Divide by zero. Should set the overflow flag and trigger an exception.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.div, 0x0000000c, 0x00000000
+ // TEST_INST_I32_I32 l.div, 0xfffffff4, 0x00000000
+
+ CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+
+ // Test l.divu
+
+ // Divide two positive numbers and check rounding. Should set no flags.
+ TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000003
+ TEST_INST_I32_I32 l.divu, 0x0000000b, 0x00000003
+
+ // Divide two numbers that would be negative under 2's complement and
+ // check rounding. Should set no flags.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.divu, 0xfffffff4, 0xfffffffd
+ // TEST_INST_I32_I32 l.divu, 0xfffffff5, 0xfffffffd
+
+ // Divide a number that would be negative under 2's complement by a
+ // number that would be positive under 2's complement and check rounding. Should set no flags.
+ TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000003
+ TEST_INST_I32_I32 l.divu, 0xfffffff5, 0x00000003
+
+ // Divide a number that would be positive under 2's complement by a
+ // number that would be negative under 2's complement and check rounding. Should set no flags.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.divu, 0x0000000c, 0xfffffffd
+ // TEST_INST_I32_I32 l.divu, 0x0000000b, 0xfffffffd
+
+ // Divide by zero. Should set the overflow flag.
+ // TODO: temporarily disabled as these tests fail on both or1ksim and or1200
+ // TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000000
+ // TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000000
+
+ // ------ Check that range exceptions are triggered.
+
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // Divide by zero. Should set the overflow flag and trigger an exception.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.divu, 0x0000000c, 0x00000000
+ // TEST_INST_I32_I32 l.divu, 0xfffffff4, 0x00000000
+
+ CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/ext.S b/sim/testsuite/sim/or1k/ext.S
new file mode 100644
index 0000000..78d9cf2
--- /dev/null
+++ b/sim/testsuite/sim/or1k/ext.S
@@ -0,0 +1,251 @@
+/* Tests the l.ext{b,h}{s,z} instructions
+
+ Copyright (C) 2005 György 'nog' Jeney <nog@sdf.lonestar.org>
+ Contributor György 'nog' Jeney <nog@sdf.lonestar.org>
+ Copyright (C) 2010 Embecosm Limited
+ Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ Copyright (C) 2012 R. Diez
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+# mach: or1k
+# output: report(0x0000007f);\n
+# output: report(0x0000007f);\n
+# output: report(0x00000053);\n
+# output: report(0x00000053);\n
+# output: report(0x0000ff53);\n
+# output: report(0x00000053);\n
+# output: report(0x00001234);\n
+# output: report(0x00000034);\n
+# output: report(0x000000ff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000080);\n
+# output: report(0xffffff80);\n
+# output: report(0x0000ff80);\n
+# output: report(0xffffff80);\n
+# output: report(0x00007f80);\n
+# output: report(0xffffff80);\n
+# output: report(0x00007fff);\n
+# output: report(0xffffffff);\n
+# output: report(0x0000007f);\n
+# output: report(0x0000007f);\n
+# output: report(0x00000053);\n
+# output: report(0x00000053);\n
+# output: report(0x0000ff53);\n
+# output: report(0x00000053);\n
+# output: report(0x00001234);\n
+# output: report(0x00000034);\n
+# output: report(0x000000ff);\n
+# output: report(0x000000ff);\n
+# output: report(0x00000080);\n
+# output: report(0x00000080);\n
+# output: report(0x0000ff80);\n
+# output: report(0x00000080);\n
+# output: report(0x00007f80);\n
+# output: report(0x00000080);\n
+# output: report(0x00007fff);\n
+# output: report(0x000000ff);\n
+# output: report(0x00007fff);\n
+# output: report(0x00007fff);\n
+# output: report(0x00005233);\n
+# output: report(0x00005233);\n
+# output: report(0xffff2f53);\n
+# output: report(0x00002f53);\n
+# output: report(0x12345678);\n
+# output: report(0x00005678);\n
+# output: report(0x0000ffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00008000);\n
+# output: report(0xffff8000);\n
+# output: report(0x0000ff80);\n
+# output: report(0xffffff80);\n
+# output: report(0x80008000);\n
+# output: report(0xffff8000);\n
+# output: report(0x7fffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00007fff);\n
+# output: report(0x00007fff);\n
+# output: report(0x00005233);\n
+# output: report(0x00005233);\n
+# output: report(0xffff2f53);\n
+# output: report(0x00002f53);\n
+# output: report(0x12345678);\n
+# output: report(0x00005678);\n
+# output: report(0x0000ffff);\n
+# output: report(0x0000ffff);\n
+# output: report(0x00008000);\n
+# output: report(0x00008000);\n
+# output: report(0x0000ff80);\n
+# output: report(0x0000ff80);\n
+# output: report(0x80008000);\n
+# output: report(0x00008000);\n
+# output: report(0x7fffffff);\n
+# output: report(0x0000ffff);\n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0x7fff7fff);\n
+# output: report(0x7fff7fff);\n
+# output: report(0xffff7f7f);\n
+# output: report(0xffff7f7f);\n
+# output: report(0xffffff7f);\n
+# output: report(0xffffff7f);\n
+# output: report(0xffff7fff);\n
+# output: report(0xffff7fff);\n
+# output: report(0x7fff7f7f);\n
+# output: report(0x7fff7f7f);\n
+# output: report(0x12345678);\n
+# output: report(0x12345678);\n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0x7fff7fff);\n
+# output: report(0x7fff7fff);\n
+# output: report(0xffff7f7f);\n
+# output: report(0xffff7f7f);\n
+# output: report(0xffffff7f);\n
+# output: report(0xffffff7f);\n
+# output: report(0xffff7fff);\n
+# output: report(0xffff7fff);\n
+# output: report(0x7fff7f7f);\n
+# output: report(0x7fff7f7f);\n
+# output: report(0x12345678);\n
+# output: report(0x12345678);\n
+# output: exit(0)\n
+
+#include "or1k-asm-test-env.h"
+
+.macro CHECK_EXT insn, val, mask, high_mask
+ LOAD_IMMEDIATE r4, \val
+ REPORT_REG_TO_CONSOLE r4
+ \insn r5, r4
+ REPORT_REG_TO_CONSOLE r5
+
+ LOAD_IMMEDIATE r6, \mask
+ l.xori r7, r6, -1
+
+ l.and r8, r4, r6
+ l.and r9, r5, r6
+ l.sfne r8, r9
+ OR1K_DELAYED_NOP(l.bf ext_fail)
+
+ l.and r8, r5, r7
+
+ LOAD_IMMEDIATE r7, \high_mask
+
+ l.sfne r8, r7
+ OR1K_DELAYED_NOP(l.bf ext_fail)
+.endm
+
+
+#define CHECK_HIGH3_CLEAR(insn, val) CHECK_EXT insn, val, 0x000000ff, 0
+#define CHECK_HIGH3_SET(val) CHECK_EXT l.extbs, val, 0x000000ff, 0xffffff00
+#define CHECK_HIGH2_CLEAR(insn, val) CHECK_EXT insn, val, 0x0000ffff, 0
+#define CHECK_HIGH2_SET(val) CHECK_EXT l.exths, val, 0x0000ffff, 0xffff0000
+
+.macro CHECK_MOVE insn, val
+
+ LOAD_IMMEDIATE r4, \val
+ REPORT_REG_TO_CONSOLE r4
+
+ \insn r5, r4
+ REPORT_REG_TO_CONSOLE r5
+
+ l.sfne r5, r4
+ OR1K_DELAYED_NOP(l.bf ext_fail)
+
+.endm
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+ // Test l.extbs
+ CHECK_HIGH3_CLEAR( l.extbs, 0x7f )
+ CHECK_HIGH3_CLEAR( l.extbs, 0x53 )
+ CHECK_HIGH3_CLEAR( l.extbs, 0xff53 )
+ CHECK_HIGH3_CLEAR( l.extbs, 0x1234 )
+
+ CHECK_HIGH3_SET(0xff)
+ CHECK_HIGH3_SET(0x80)
+ CHECK_HIGH3_SET(0xff80)
+ CHECK_HIGH3_SET(0x7f80)
+ CHECK_HIGH3_SET(0x7fff)
+
+ // Test l.extbz
+ CHECK_HIGH3_CLEAR(l.extbz, 0x7f)
+ CHECK_HIGH3_CLEAR(l.extbz, 0x53)
+ CHECK_HIGH3_CLEAR(l.extbz, 0xff53)
+ CHECK_HIGH3_CLEAR(l.extbz, 0x1234)
+
+ CHECK_HIGH3_CLEAR(l.extbz, 0xff)
+ CHECK_HIGH3_CLEAR(l.extbz, 0x80)
+ CHECK_HIGH3_CLEAR(l.extbz, 0xff80)
+ CHECK_HIGH3_CLEAR(l.extbz, 0x7f80)
+ CHECK_HIGH3_CLEAR(l.extbz, 0x7fff)
+
+ // Test l.exths
+ CHECK_HIGH2_CLEAR(l.exths, 0x7fff)
+ CHECK_HIGH2_CLEAR(l.exths, 0x5233)
+ CHECK_HIGH2_CLEAR(l.exths, 0xffff2f53)
+ CHECK_HIGH2_CLEAR(l.exths, 0x12345678)
+
+ CHECK_HIGH2_SET(0xffff)
+ CHECK_HIGH2_SET(0x8000)
+ CHECK_HIGH2_SET(0xff80)
+ CHECK_HIGH2_SET(0x80008000)
+ CHECK_HIGH2_SET(0x7fffffff)
+
+ // Test l.exthz
+ CHECK_HIGH2_CLEAR(l.exthz, 0x7fff)
+ CHECK_HIGH2_CLEAR(l.exthz, 0x5233)
+ CHECK_HIGH2_CLEAR(l.exthz, 0xffff2f53)
+ CHECK_HIGH2_CLEAR(l.exthz, 0x12345678)
+
+ CHECK_HIGH2_CLEAR(l.exthz, 0xffff)
+ CHECK_HIGH2_CLEAR(l.exthz, 0x8000)
+ CHECK_HIGH2_CLEAR(l.exthz, 0xff80)
+ CHECK_HIGH2_CLEAR(l.exthz, 0x80008000)
+ CHECK_HIGH2_CLEAR(l.exthz, 0x7fffffff)
+
+ // Test l.extws
+ CHECK_MOVE l.extws, 0xffffffff
+ CHECK_MOVE l.extws, 0x7fffffff
+ CHECK_MOVE l.extws, 0x7fff7fff
+ CHECK_MOVE l.extws, 0xffff7f7f
+ CHECK_MOVE l.extws, 0xffffff7f
+ CHECK_MOVE l.extws, 0xffff7fff
+ CHECK_MOVE l.extws, 0x7fff7f7f
+ CHECK_MOVE l.extws, 0x12345678
+
+ // Test l.extwz
+ CHECK_MOVE l.extwz, 0xffffffff
+ CHECK_MOVE l.extwz, 0x7fffffff
+ CHECK_MOVE l.extwz, 0x7fff7fff
+ CHECK_MOVE l.extwz, 0xffff7f7f
+ CHECK_MOVE l.extwz, 0xffffff7f
+ CHECK_MOVE l.extwz, 0xffff7fff
+ CHECK_MOVE l.extwz, 0x7fff7f7f
+ CHECK_MOVE l.extwz, 0x12345678
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
+
+ext_fail:
+ EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR
diff --git a/sim/testsuite/sim/or1k/find.S b/sim/testsuite/sim/or1k/find.S
new file mode 100644
index 0000000..6c52721
--- /dev/null
+++ b/sim/testsuite/sim/or1k/find.S
@@ -0,0 +1,119 @@
+/* Tests the find instructions.
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x00000001);\n
+# output: report(0x00000001);\n
+# output: \n
+# output: report(0x80000000);\n
+# output: report(0x00000020);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x00000001);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000002);\n
+# output: \n
+# output: report(0x00018000);\n
+# output: report(0x00000010);\n
+# output: \n
+# output: report(0xc0000000);\n
+# output: report(0x0000001f);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: report(0x00000001);\n
+# output: \n
+# output: report(0x80000000);\n
+# output: report(0x00000020);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x0000001f);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000020);\n
+# output: \n
+# output: report(0x00018000);\n
+# output: report(0x00000011);\n
+# output: \n
+# output: report(0xc0000000);\n
+# output: report(0x00000020);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+.macro TEST_FIND opcode, operand
+
+ LOAD_IMMEDIATE r5, \operand
+
+ REPORT_REG_TO_CONSOLE r5
+
+ \opcode r4, r5
+
+ REPORT_REG_TO_CONSOLE r4
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+.endm
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // Test l.ff1
+
+ TEST_FIND l.ff1, 0x00000001
+ TEST_FIND l.ff1, 0x80000000
+ TEST_FIND l.ff1, 0x55555555
+ TEST_FIND l.ff1, 0xaaaaaaaa
+ TEST_FIND l.ff1, 0x00018000
+ TEST_FIND l.ff1, 0xc0000000
+ TEST_FIND l.ff1, 0x00000000
+
+
+ // Test l.fl1
+
+ TEST_FIND l.fl1, 0x00000001
+ TEST_FIND l.fl1, 0x80000000
+ TEST_FIND l.fl1, 0x55555555
+ TEST_FIND l.fl1, 0xaaaaaaaa
+ TEST_FIND l.fl1, 0x00018000
+ TEST_FIND l.fl1, 0xc0000000
+ TEST_FIND l.fl1, 0x00000000
+
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/flag.S b/sim/testsuite/sim/or1k/flag.S
new file mode 100644
index 0000000..c8edbe7
--- /dev/null
+++ b/sim/testsuite/sim/or1k/flag.S
@@ -0,0 +1,405 @@
+/* Tests the l.sf* instructions
+ *
+ * Copyright (C) Julius Baxter, ORSoC AB, <julius.baxter@orsoc.se>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+#define INT_MAX 2147483647 // 0x7fffffff
+#define INT_MAX_MIN1 2147483646 // 0x7ffffffe
+#define NEG_INT_MAX -2147483648 // 0x80000000
+#define NEG_INT_MAX_PL1 -2147483647 // 0x80000001
+#define MIN1 -1 // 0xffffffff
+
+#define SHRT_MIN (-32768)
+#define SHRT_MAX 32767
+
+#define UINT_MAX 4294967295 // 0xffffffff
+#define UINT_MAX_MIN1 4294967294 // 0xfffffffe
+
+#define USHRT_MAX 65535
+
+
+.macro MOVE_TO_R4_R5_AND_REPORT a, b
+
+ LOAD_IMMEDIATE r4, \a
+ LOAD_IMMEDIATE r5, \b
+
+ // During development, add REPORT_xxx statements here to see the operands.
+
+.endm
+
+.macro MOVE_TO_R4_AND_REPORT_I a, b
+
+ LOAD_IMMEDIATE r4, \a
+
+ // During development, add REPORT_xxx statements here to see the operands.
+
+.endm
+
+
+.macro SHOULD_BE_SET
+ OR1K_DELAYED_NOP(l.bnf failed)
+.endm
+
+.macro SHOULDNT_BE_SET
+ OR1K_DELAYED_NOP(l.bf failed)
+.endm
+
+
+.macro SHOULD_BE_LESS_THAN_SIGNED a, b
+ MOVE_TO_R4_R5_AND_REPORT \a , \b
+
+ l.sfeq r4, r5
+ SHOULDNT_BE_SET
+ l.sfne r4, r5
+ SHOULD_BE_SET
+ l.sfgts r4, r5
+ SHOULDNT_BE_SET
+ l.sfges r4, r5
+ SHOULDNT_BE_SET
+ l.sfles r4, r5
+ SHOULD_BE_SET
+ l.sflts r4, r5
+ SHOULD_BE_SET
+.endm
+
+.macro SHOULD_BE_GREATER_THAN_SIGNED a, b
+ MOVE_TO_R4_R5_AND_REPORT \a , \b
+
+ l.sfeq r4, r5
+ SHOULDNT_BE_SET
+ l.sfne r4, r5
+ SHOULD_BE_SET
+ l.sfgts r4, r5
+ SHOULD_BE_SET
+ l.sfges r4, r5
+ SHOULD_BE_SET
+ l.sfles r4, r5
+ SHOULDNT_BE_SET
+ l.sflts r4, r5
+ SHOULDNT_BE_SET
+.endm
+
+.macro SHOULD_BE_LESS_THAN_UNSIGNED a, b
+ MOVE_TO_R4_R5_AND_REPORT \a , \b
+
+ l.sfeq r4, r5
+ SHOULDNT_BE_SET
+ l.sfne r4, r5
+ SHOULD_BE_SET
+ l.sfgtu r4, r5
+ SHOULDNT_BE_SET
+ l.sfgeu r4, r5
+ SHOULDNT_BE_SET
+ l.sfleu r4, r5
+ SHOULD_BE_SET
+ l.sfltu r4, r5
+ SHOULD_BE_SET
+.endm
+
+.macro SHOULD_BE_GREATER_THAN_UNSIGNED a, b
+ MOVE_TO_R4_R5_AND_REPORT \a , \b
+
+ l.sfeq r4, r5
+ SHOULDNT_BE_SET
+ l.sfne r4, r5
+ SHOULD_BE_SET
+ l.sfgtu r4, r5
+ SHOULD_BE_SET
+ l.sfgeu r4, r5
+ SHOULD_BE_SET
+ l.sfleu r4, r5
+ SHOULDNT_BE_SET
+ l.sfltu r4, r5
+ SHOULDNT_BE_SET
+.endm
+
+
+.macro SHOULD_BE_EQUAL a, b
+ MOVE_TO_R4_R5_AND_REPORT \a , \b
+
+ l.sfeq r4, r5
+ SHOULD_BE_SET
+ l.sfne r4, r5
+ SHOULDNT_BE_SET
+
+ // Signed tests.
+ l.sfgts r4, r5
+ SHOULDNT_BE_SET
+ l.sfges r4, r5
+ SHOULD_BE_SET
+ l.sfles r4, r5
+ SHOULD_BE_SET
+ l.sflts r4, r5
+ SHOULDNT_BE_SET
+
+ // Unsigned tests.
+ l.sfgtu r4, r5
+ SHOULDNT_BE_SET
+ l.sfgeu r4, r5
+ SHOULD_BE_SET
+ l.sfleu r4, r5
+ SHOULD_BE_SET
+ l.sfltu r4, r5
+ SHOULDNT_BE_SET
+
+.endm
+
+.macro SHOULDNT_BE_EQUAL a, b
+ MOVE_TO_R4_R5_AND_REPORT \a , \b
+
+ l.sfeq r4, r5
+ SHOULDNT_BE_SET
+ l.sfne r4, r5
+ SHOULD_BE_SET
+
+.endm
+
+.macro SHOULD_BE_EQUAL_I a, b
+
+ MOVE_TO_R4_AND_REPORT_I \a, \b
+
+ l.sfeqi r4, \b
+ SHOULD_BE_SET
+ l.sfnei r4, \b
+ SHOULDNT_BE_SET
+
+ // Signed tests.
+ l.sfgtsi r4, \b
+ SHOULDNT_BE_SET
+ l.sfgesi r4, \b
+ SHOULD_BE_SET
+ l.sflesi r4, \b
+ SHOULD_BE_SET
+ l.sfltsi r4, \b
+ SHOULDNT_BE_SET
+
+ // Unsigned tests.
+ l.sfgtui r4, \b
+ SHOULDNT_BE_SET
+ l.sfgeui r4, \b
+ SHOULD_BE_SET
+ l.sfleui r4, \b
+ SHOULD_BE_SET
+ l.sfltui r4, \b
+ SHOULDNT_BE_SET
+
+.endm
+
+.macro SHOULDNT_BE_EQUAL_I a, b
+
+ MOVE_TO_R4_AND_REPORT_I \a, \b
+
+ l.sfeqi r4, \b
+ SHOULDNT_BE_SET
+ l.sfnei r4, \b
+ SHOULD_BE_SET
+
+.endm
+
+
+.macro SHOULD_BE_LESS_THAN_SIGNED_I a, b
+
+ MOVE_TO_R4_AND_REPORT_I \a, \b
+
+ l.sfeqi r4, \b
+ SHOULDNT_BE_SET
+ l.sfnei r4, \b
+ SHOULD_BE_SET
+ l.sfgtsi r4, \b
+ SHOULDNT_BE_SET
+ l.sfgesi r4, \b
+ SHOULDNT_BE_SET
+ l.sflesi r4, \b
+ SHOULD_BE_SET
+ l.sfltsi r4, \b
+ SHOULD_BE_SET
+.endm
+
+.macro SHOULD_BE_GREATER_THAN_SIGNED_I a, b
+
+ MOVE_TO_R4_AND_REPORT_I \a, \b
+
+ l.sfeqi r4, \b
+ SHOULDNT_BE_SET
+ l.sfnei r4, \b
+ SHOULD_BE_SET
+ l.sfgtsi r4, \b
+ SHOULD_BE_SET
+ l.sfgesi r4, \b
+ SHOULD_BE_SET
+ l.sflesi r4, \b
+ SHOULDNT_BE_SET
+ l.sfltsi r4, \b
+ SHOULDNT_BE_SET
+.endm
+
+
+.macro SHOULD_BE_LESS_THAN_UNSIGNED_I a, b
+ MOVE_TO_R4_AND_REPORT_I \a, \b
+
+ l.sfeqi r4, \b
+ SHOULDNT_BE_SET
+ l.sfnei r4, \b
+ SHOULD_BE_SET
+ l.sfgtui r4, \b
+ SHOULDNT_BE_SET
+ l.sfgeui r4, \b
+ SHOULDNT_BE_SET
+ l.sfleui r4, \b
+ SHOULD_BE_SET
+ l.sfltui r4, \b
+ SHOULD_BE_SET
+.endm
+
+.macro SHOULD_BE_GREATER_THAN_UNSIGNED_I a, b
+ MOVE_TO_R4_AND_REPORT_I \a, \b
+
+ l.sfeqi r4, \b
+ SHOULDNT_BE_SET
+ l.sfnei r4, \b
+ SHOULD_BE_SET
+ l.sfgtui r4, \b
+ SHOULD_BE_SET
+ l.sfgeui r4, \b
+ SHOULD_BE_SET
+ l.sfleui r4, \b
+ SHOULDNT_BE_SET
+ l.sfltui r4, \b
+ SHOULDNT_BE_SET
+.endm
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // Signed tests
+
+ SHOULD_BE_LESS_THAN_SIGNED 0, 1
+ SHOULD_BE_LESS_THAN_SIGNED MIN1, 0
+ SHOULD_BE_LESS_THAN_SIGNED INT_MAX_MIN1, INT_MAX
+ SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, INT_MAX
+ SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, INT_MAX_MIN1
+ SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX_PL1, INT_MAX
+ SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX_PL1, INT_MAX_MIN1
+ SHOULD_BE_LESS_THAN_SIGNED -7, -6
+ SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, NEG_INT_MAX_PL1
+ SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, MIN1
+ SHOULD_BE_LESS_THAN_SIGNED NEG_INT_MAX, 0
+
+ SHOULD_BE_GREATER_THAN_SIGNED 1, 0
+ SHOULD_BE_GREATER_THAN_SIGNED 0, MIN1
+ SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, INT_MAX_MIN1
+ SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, NEG_INT_MAX
+ SHOULD_BE_GREATER_THAN_SIGNED INT_MAX_MIN1, NEG_INT_MAX
+ SHOULD_BE_GREATER_THAN_SIGNED INT_MAX, NEG_INT_MAX_PL1
+ SHOULD_BE_GREATER_THAN_SIGNED INT_MAX_MIN1, NEG_INT_MAX_PL1
+ SHOULD_BE_GREATER_THAN_SIGNED -6, -7
+ SHOULD_BE_GREATER_THAN_SIGNED NEG_INT_MAX_PL1, NEG_INT_MAX
+ SHOULD_BE_GREATER_THAN_SIGNED MIN1, NEG_INT_MAX
+ SHOULD_BE_GREATER_THAN_SIGNED 0, NEG_INT_MAX
+
+ SHOULD_BE_LESS_THAN_SIGNED 0xFFFF7FFF, 0xFFFF8000 // See the immediate tests below.
+ SHOULD_BE_GREATER_THAN_SIGNED 0xFFFF8001, 0xFFFF8000 // See the immediate tests below.
+
+
+ // Signed tests, immediate
+
+ SHOULD_BE_LESS_THAN_SIGNED_I 0, 1
+ SHOULD_BE_LESS_THAN_SIGNED_I -1, 0
+ SHOULD_BE_LESS_THAN_SIGNED_I -7, -6
+
+ SHOULD_BE_GREATER_THAN_SIGNED_I 0x00008000, 0x7FFF
+ SHOULD_BE_LESS_THAN_SIGNED_I 0xFFFFFFFF, 0x7FFF
+ SHOULD_BE_LESS_THAN_SIGNED_I 0xFFFF7FFF, 0x8000 // 0x8000 gets sign-extended to 0xFFFF8000.
+ SHOULD_BE_GREATER_THAN_SIGNED_I 0xFFFF8001, 0x8000 // 0x8000 gets sign-extended to 0xFFFF8000.
+ SHOULD_BE_GREATER_THAN_SIGNED_I 0x00008000, 0x8000 // 0x8000 gets sign-extended to 0xFFFF8000.
+
+
+ // Unsigned tests
+
+ SHOULD_BE_LESS_THAN_UNSIGNED 0, 1
+ SHOULD_BE_LESS_THAN_UNSIGNED UINT_MAX_MIN1, UINT_MAX
+ SHOULD_BE_GREATER_THAN_UNSIGNED 1, 0
+ SHOULD_BE_GREATER_THAN_UNSIGNED UINT_MAX, UINT_MAX_MIN1
+ SHOULD_BE_GREATER_THAN_UNSIGNED UINT_MAX, 0
+ SHOULD_BE_GREATER_THAN_UNSIGNED 0x80000001, 0x80000000
+ SHOULD_BE_LESS_THAN_UNSIGNED 0x80000000, 0x80000001
+ SHOULD_BE_GREATER_THAN_UNSIGNED 0x80000000, 0x7fffffff
+ SHOULD_BE_LESS_THAN_UNSIGNED 0x7fffffff, 0x80000000
+ SHOULD_BE_GREATER_THAN_UNSIGNED 0x7fffffff, 0x7ffffffe
+ SHOULD_BE_LESS_THAN_UNSIGNED 0x7ffffffe, 0x7fffffff
+ SHOULD_BE_LESS_THAN_UNSIGNED 0x2024fae0, 0xfef03220
+
+
+ // Unsigned tests, immediate
+
+ SHOULD_BE_LESS_THAN_UNSIGNED_I 0, 1
+ SHOULD_BE_GREATER_THAN_UNSIGNED_I 1, 0
+ SHOULD_BE_LESS_THAN_UNSIGNED_I SHRT_MAX - 1, SHRT_MAX
+ SHOULD_BE_GREATER_THAN_UNSIGNED_I SHRT_MAX , SHRT_MAX - 1
+
+ // The sign extension produces unexpected results here.
+ SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFFFFFF - 1, 0xFFFF // 0xFFFF gets sign-extended to 0xFFFFFFFF.
+ SHOULD_BE_LESS_THAN_UNSIGNED_I 0xFFFF7FFF , 0x8000 // 0x8000 gets sign-extended to 0xFFFF8000.
+
+
+ // Equal tests.
+
+ SHOULD_BE_EQUAL 0, 0
+ SHOULD_BE_EQUAL UINT_MAX, UINT_MAX
+ SHOULD_BE_EQUAL MIN1, UINT_MAX
+ SHOULD_BE_EQUAL INT_MAX, INT_MAX
+ SHOULD_BE_EQUAL NEG_INT_MAX, NEG_INT_MAX
+
+
+ // Equal tests, immediate. Test the 16-to-32-bit sign extension.
+
+ SHOULD_BE_EQUAL_I 0, 0
+ SHOULD_BE_EQUAL_I 0x00007FFF, 0x7FFF
+ SHOULD_BE_EQUAL_I 0xFFFF8000, 0x8000
+ SHOULD_BE_EQUAL_I 0xFFFFFFFF, 0xFFFF
+
+
+ // Non-equal tests.
+
+ SHOULDNT_BE_EQUAL 0, 1
+ SHOULDNT_BE_EQUAL UINT_MAX, INT_MAX
+ SHOULDNT_BE_EQUAL UINT_MAX, NEG_INT_MAX
+ SHOULDNT_BE_EQUAL MIN1, NEG_INT_MAX_PL1
+ SHOULDNT_BE_EQUAL INT_MAX, NEG_INT_MAX
+ SHOULDNT_BE_EQUAL NEG_INT_MAX_PL1, UINT_MAX_MIN1
+
+
+ // Non-equal tests, immediate. Test the 16-to-32-bit sign extension.
+
+ SHOULDNT_BE_EQUAL_I 0x00008000, 0x8000
+
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
+
+failed:
+ EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR
diff --git a/sim/testsuite/sim/or1k/jump.S b/sim/testsuite/sim/or1k/jump.S
new file mode 100644
index 0000000..63b1acc
--- /dev/null
+++ b/sim/testsuite/sim/or1k/jump.S
@@ -0,0 +1,121 @@
+/* Tests the jump instructions
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x48000000);\n
+# output: report(0x00000005);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x44000000);\n
+# output: report(0x00000005);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+/* ----------------------------------------------------------------------------
+ * Tests a jump instruction using a register destination.
+ * Checks whether the jump succeeds, or whether an exception is triggered (but not if the right exception was triggered yet).
+ *
+ * We manually construct the opcode, to allow us to force R9 into the
+ * destination field, to test exception handling. Usually the assembler would
+ * prevent this.
+ *
+ * Do not specify R31 as the register to use for the jump, as it's used internally.
+ * ------------------------------------------------------------------------- */
+
+.macro TEST_JUMP opcode_value dest_register_number alignment_offset
+
+ REPORT_IMMEDIATE_TO_CONSOLE \opcode_value
+ REPORT_IMMEDIATE_TO_CONSOLE \dest_register_number
+ REPORT_IMMEDIATE_TO_CONSOLE \alignment_offset
+
+ LOAD_IMMEDIATE r\dest_register_number, 51f + \alignment_offset
+
+ // Clear the last exception address. Not really necessary.
+ MOVE_TO_SPR SPR_EPCR_BASE, ZERO_R0
+
+ // Generate the jump opcode.
+ 50: OR1K_DELAYED_NOP(.word ( \opcode_value | (\dest_register_number << 11) ))
+
+ // If the jump failed, we land here.
+ REPORT_IMMEDIATE_TO_CONSOLE 1
+
+ OR1K_DELAYED_NOP(l.j 52f)
+
+ // If the jump succeeds, we land here.
+ 51: REPORT_IMMEDIATE_TO_CONSOLE 0
+
+ 52:
+
+.endm
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+
+ .section .exception_vectors
+
+ // Alignment exception.
+ .org 0x600
+ // TODO: We need to patch the instruction here before returning, or we need to return
+ // to the next instruction. But beware that the or1200 implementation does not behave like the or1ksim simulator.
+ l.rfe
+
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // Test l.jalr (jump and link register)
+
+ TEST_JUMP 0x48000000, 5, 0
+ // TODO: some tests disabled, further work is needed
+ // TEST_JUMP 0x48000000, 5, 1
+ // TEST_JUMP 0x48000000, 5, 2
+ // TEST_JUMP 0x48000000, 5, 3
+
+ // Test with link register as the destination
+ // TODO: disabled, need to add support for the ILLEGAL INSTRUCTION exception:
+ // TEST_JUMP (0x48000000, 9, 0)
+
+
+ // Test l.jr (jump register)
+
+ TEST_JUMP 0x44000000, 5, 0
+ // TODO: some tests disabled, further work is needed
+ // TEST_JUMP 0x44000000, 5, 1
+ // TEST_JUMP 0x44000000, 5, 2
+ // TEST_JUMP 0x44000000, 5, 3
+
+ // Test with link register as the destination (OK here)
+ // TODO: disabled, need to add support for the ILLEGAL INSTRUCTION exception:
+ // TEST_JUMP 0x44000000, 9, 0
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/load.S b/sim/testsuite/sim/or1k/load.S
new file mode 100644
index 0000000..6818ca7
--- /dev/null
+++ b/sim/testsuite/sim/or1k/load.S
@@ -0,0 +1,373 @@
+/* Tests the load and store instructions.
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0xdeadbeef);\n
+# output: report(0x00000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0x80000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0x80000000);\n
+# output: report(0xffffffff);\n
+# output: report(0xdeadbeef);\n
+# output: report(0x00000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0x80000000);\n
+# output: report(0x000000de);\n
+# output: report(0x000000ad);\n
+# output: report(0x000000be);\n
+# output: report(0x000000ef);\n
+# output: report(0x000000ef);\n
+# output: report(0x000000be);\n
+# output: report(0x000000ad);\n
+# output: report(0x000000de);\n
+# output: report(0xffffffde);\n
+# output: report(0xffffffad);\n
+# output: report(0xffffffbe);\n
+# output: report(0xffffffef);\n
+# output: report(0xffffffef);\n
+# output: report(0xffffffbe);\n
+# output: report(0xffffffad);\n
+# output: report(0xffffffde);\n
+# output: report(0x0000dead);\n
+# output: report(0x0000beef);\n
+# output: report(0x0000beef);\n
+# output: report(0x0000dead);\n
+# output: report(0xffffdead);\n
+# output: report(0xffffbeef);\n
+# output: report(0xffffbeef);\n
+# output: report(0xffffdead);\n
+# output: report(0xa1a2a3a4);\n
+# output: report(0xb4b3b2b1);\n
+# output: report(0x81828384);\n
+# output: report(0x53545152);\n
+# output: report(0xa0b0c0d0);\n
+# output: report(0xa1b1c1d1);\n
+# output: report(0xa3b3c3d3);\n
+# output: report(0xa2b2c2d2);\n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+.macro TEST_LW opcode, label, offset
+
+ LOAD_IMMEDIATE r5, \label
+
+ \opcode r4, \offset(r5)
+
+ REPORT_REG_TO_CONSOLE r4
+
+.endm
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .rodata
+ .balign 4
+
+50: .word 0xdeadbeef
+51: .word 0x00000000
+52: .word 0x7fffffff
+53: .word 0x80000000
+54: .word 0xffffffff
+
+
+ .section .data
+ .balign 4
+
+buffer1: .word 0x00000000
+buffer2: .word 0x00000000
+buffer3: .word 0x00000000
+buffer4: .word 0x00000000
+buffer5:
+
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // Test instruction l.lws
+ /* TODO: The instruction l.lws is not implemeted yet in or1200, search for "l.lws support patch" in the mailing list.
+ Note that this instruction is redundant, as l.lwz does exactly the same.
+
+ // Load with zero offset
+ TEST_LW l.lws 50b, 0
+ TEST_LW l.lws 51b, 0
+ TEST_LW l.lws 52b, 0
+ TEST_LW l.lws 53b, 0
+ TEST_LW l.lws 54b, 0
+
+ // Load with positive offset
+ TEST_LW l.lws 50b, 4
+ TEST_LW l.lws 50b, 8
+ TEST_LW l.lws 50b, 12
+ TEST_LW l.lws 50b, 16
+
+ // Load with negative offset
+ TEST_LW l.lws 54b, -16
+ TEST_LW l.lws 54b, -12
+ TEST_LW l.lws 54b, -8
+ TEST_LW l.lws 54b, -4
+
+ add here test cases to cover unaligned memory accesses with l.lws
+ */
+
+
+ // ---------- Test instruction l.lwz ----------
+ // Same tests as above. The instruction l.lwz does the same as l.lws (it is a redundant instruction).
+
+ // Load with zero offset
+ TEST_LW l.lwz 50b, 0
+ TEST_LW l.lwz 51b, 0
+ TEST_LW l.lwz 52b, 0
+ TEST_LW l.lwz 53b, 0
+ TEST_LW l.lwz 54b, 0
+
+ // Load with positive offset
+ TEST_LW l.lwz 50b, 4
+ TEST_LW l.lwz 50b, 8
+ TEST_LW l.lwz 50b, 12
+ TEST_LW l.lwz 50b, 16
+
+ // Load with negative offset
+ TEST_LW l.lwz 54b, -16
+ TEST_LW l.lwz 54b, -12
+ TEST_LW l.lwz 54b, -8
+ TEST_LW l.lwz 54b, -4
+
+ // TODO: add here test cases to cover unaligned memory accesses with l.lwz
+
+ // ---------- Test instruction l.lbz ----------
+
+ // Read data at label 50, forwards, byte by byte.
+ LOAD_IMMEDIATE r5, 50b
+
+ l.lbz r4, 0(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+ l.lbz r4, 1(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+ l.lbz r4, 2(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+ l.lbz r4, 3(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+
+ // Read data at label 50, backwards, byte by byte.
+ LOAD_IMMEDIATE r31, 51b
+
+ l.lbz r3, -1(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+ l.lbz r3, -2(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+ l.lbz r3, -3(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+ l.lbz r3, -4(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+
+ // ---------- Test instruction l.lbs ----------
+
+ // Read data at label 50, forwards, byte by byte.
+ LOAD_IMMEDIATE r5, 50b
+
+ l.lbs r4, 0(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+ l.lbs r4, 1(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+ l.lbs r4, 2(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+ l.lbs r4, 3(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+
+ // Read data at label 50, backwards, byte by byte.
+ LOAD_IMMEDIATE r31, 51b
+
+ l.lbs r3, -1(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+ l.lbs r3, -2(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+ l.lbs r3, -3(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+ l.lbs r3, -4(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+
+ // ---------- Test instruction l.lhz ----------
+
+ // Read data at label 50, forwards, half-word by half-word.
+ LOAD_IMMEDIATE r5, 50b
+
+ l.lhz r4, 0(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+ l.lhz r4, 2(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+
+ // Read data at label 50, backwards, half-word by half-word.
+ LOAD_IMMEDIATE r31, 51b
+
+ l.lhz r3, -2(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+ l.lhz r3, -4(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+ // TODO: add here test cases to cover unaligned memory accesses with l.lhz
+
+
+ // ---------- Test instruction l.lhs ----------
+
+ // Read data at label 50, forwards, half-word by half-word.
+ LOAD_IMMEDIATE r5, 50b
+
+ l.lhs r4, 0(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+ l.lhs r4, 2(r5)
+ REPORT_REG_TO_CONSOLE r4
+
+
+ // Read data at label 50, backwards, half-word by half-word.
+ LOAD_IMMEDIATE r31, 51b
+
+ l.lhs r3, -2(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+ l.lhs r3, -4(r31)
+ REPORT_REG_TO_CONSOLE r3
+
+ // TODO: add here test cases to cover unaligned memory accesses with l.lhs
+
+
+ // ---------- Test instruction l.sb ----------
+
+ // Write 32-bits forwards, byte-to-byte.
+
+ LOAD_IMMEDIATE r5, buffer1
+
+ LOAD_IMMEDIATE r10, 0xA1
+ LOAD_IMMEDIATE r11, 0xA2
+ LOAD_IMMEDIATE r12, 0xA3
+ LOAD_IMMEDIATE r13, 0xA4
+
+ l.sb 0(r5), r10
+ l.sb 1(r5), r11
+ l.sb 2(r5), r12
+ l.sb 3(r5), r13
+
+ l.lwz r3, 0(r5)
+ REPORT_REG_TO_CONSOLE r3
+
+ // Write 32-bits backwards, byte-to-byte.
+
+ LOAD_IMMEDIATE r6, buffer2
+
+ LOAD_IMMEDIATE r10, 0xB1
+ LOAD_IMMEDIATE r11, 0xB2
+ LOAD_IMMEDIATE r12, 0xB3
+ LOAD_IMMEDIATE r13, 0xB4
+
+ l.sb -1(r6), r10
+ l.sb -2(r6), r11
+ l.sb -3(r6), r12
+ l.sb -4(r6), r13
+
+ l.lwz r3, 0(r5)
+ REPORT_REG_TO_CONSOLE r3
+
+ // TODO: add here test cases to cover unaligned memory accesses with l.sb
+
+
+ // ---------- Test instruction l.sh ----------
+
+ // Write 32-bits forwards, one half-word at a time.
+
+ LOAD_IMMEDIATE r5, buffer1
+
+ LOAD_IMMEDIATE r10, 0x8182
+ LOAD_IMMEDIATE r11, 0x8384
+
+ l.sh 0(r5), r10
+ l.sh 2(r5), r11
+
+ l.lwz r3, 0(r5)
+ REPORT_REG_TO_CONSOLE r3
+
+
+ // Write 32-bits backwards, one half-word at a time.
+
+ LOAD_IMMEDIATE r6, buffer2
+
+ LOAD_IMMEDIATE r10, 0x5152
+ LOAD_IMMEDIATE r11, 0x5354
+
+ l.sh -2(r6), r10
+ l.sh -4(r6), r11
+
+ l.lwz r3, 0(r5)
+ REPORT_REG_TO_CONSOLE r3
+
+ // TODO: add here test cases to cover unaligned memory accesses with l.sh
+
+
+ // ---------- Test instruction l.sw ----------
+
+ LOAD_IMMEDIATE r5, buffer1
+ LOAD_IMMEDIATE r6, buffer5
+
+ LOAD_IMMEDIATE r10, 0xA0B0C0D0
+ LOAD_IMMEDIATE r11, 0xA1B1C1D1
+ LOAD_IMMEDIATE r12, 0xA2B2C2D2
+ LOAD_IMMEDIATE r13, 0xA3B3C3D3
+
+ l.sw 0(r5), r10
+ l.sw 4(r5), r11
+ l.sw -4(r6), r12
+ l.sw -8(r6), r13
+
+ TEST_LW l.lwz buffer1, 0
+ TEST_LW l.lwz buffer2, 0
+ TEST_LW l.lwz buffer3, 0
+ TEST_LW l.lwz buffer4, 0
+
+ // TODO: add here test cases to cover unaligned memory accesses with l.sw
+
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/mac.S b/sim/testsuite/sim/or1k/mac.S
new file mode 100644
index 0000000..08e0ebb
--- /dev/null
+++ b/sim/testsuite/sim/or1k/mac.S
@@ -0,0 +1,785 @@
+/* Tests the MAC instructions.
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0x0000000c);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x40000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000006);\n
+# output: report(0x80000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0x7ffffffe);\n
+# output: report(0x00000000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x7ffffffd);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0x0000000c);\n
+# output: report(0x00000000);\n
+# output: report(0x00000005);\n
+# output: report(0xffffffff);\n
+# output: report(0xfffffffa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0xfffffff9);\n
+# output: report(0xffffffff);\n
+# output: report(0xfffffff9);\n
+# output: report(0xfffffffe);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000006);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0xfffffffe);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0x0000000c);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x40000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000006);\n
+# output: report(0x80000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0x7ffffffe);\n
+# output: report(0x00000000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x7ffffffd);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0x0000000c);\n
+# output: report(0x00000000);\n
+# output: report(0x00000005);\n
+# output: report(0xffffffff);\n
+# output: report(0xfffffffa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0xfffffff9);\n
+# output: report(0xffffffff);\n
+# output: report(0xfffffff9);\n
+# output: report(0xfffffffe);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000006);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0xfffffffe);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x0000000c);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000006);\n
+# output: report(0x7ffffffe);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x7ffffffd);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x0000000c);\n
+# output: report(0x00000005);\n
+# output: report(0xfffffffa);\n
+# output: report(0x00000006);\n
+# output: report(0xffffffff);\n
+# output: report(0xfffffff9);\n
+# output: report(0xfffffff9);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x80000000);\n
+# output: report(0x80000006);\n
+# output: report(0x00000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0xfffffffa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0xfffffffa);\n
+# output: report(0x3fffffff);\n
+# output: report(0xfffffffa);\n
+# output: report(0xffffffff);\n
+# output: report(0xfffffff4);\n
+# output: report(0xfffffffe);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000002);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000004);\n
+# output: report(0x00000000);\n
+# output: report(0x00000004);\n
+# output: report(0x7ffffffe);\n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000001);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000004);\n
+# output: report(0xfffffffe);\n
+# output: report(0x00000004);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0xffffffff);\n
+# output: report(0xfffffff9);\n
+# output: report(0x00000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0x0000000c);\n
+# output: report(0x00000001);\n
+# output: report(0x00000005);\n
+# output: report(0x7fffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000005);\n
+# output: report(0x80000000);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0x80000006);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x7fffffff);\n
+# output: report(0x80000000);\n
+# output: report(0x80000000);\n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+.macro TEST_MACRC mac_hi, mac_lo, op1, op2
+
+ LOAD_IMMEDIATE r2, \mac_hi
+ MOVE_TO_SPR SPR_MACHI, r2
+
+ LOAD_IMMEDIATE r2, \mac_lo
+ MOVE_TO_SPR SPR_MACLO, r2
+
+ LOAD_IMMEDIATE r5, \op1
+ LOAD_IMMEDIATE r6, \op2
+
+ l.mac r5, r6
+ l.macrc r3
+
+ REPORT_REG_TO_CONSOLE r3
+
+.endm
+
+
+.macro TEST_MAC mac_hi, mac_lo, op1, op2
+
+ LOAD_IMMEDIATE r2, \mac_hi
+ MOVE_TO_SPR SPR_MACHI, r2
+
+ LOAD_IMMEDIATE r2, \mac_lo
+ MOVE_TO_SPR SPR_MACLO, r2
+
+ LOAD_IMMEDIATE r5, \op1
+ LOAD_IMMEDIATE r6, \op2
+
+ l.mac r5, r6
+
+ MOVE_FROM_SPR r3, SPR_MACHI
+ REPORT_REG_TO_CONSOLE r3
+
+ MOVE_FROM_SPR r3, SPR_MACLO
+ REPORT_REG_TO_CONSOLE r3
+
+.endm
+
+
+.macro TEST_MACI mac_hi, mac_lo, op1, op2_immediate
+
+ LOAD_IMMEDIATE r2, \mac_hi
+ MOVE_TO_SPR SPR_MACHI, r2
+
+ LOAD_IMMEDIATE r2, \mac_lo
+ MOVE_TO_SPR SPR_MACLO, r2
+
+ LOAD_IMMEDIATE r5, \op1
+
+ l.maci r5, \op2_immediate
+
+ MOVE_FROM_SPR r3, SPR_MACHI
+ REPORT_REG_TO_CONSOLE r3
+
+ MOVE_FROM_SPR r3, SPR_MACLO
+ REPORT_REG_TO_CONSOLE r3
+
+.endm
+
+
+.macro TEST_MSB mac_hi, mac_lo, op1, op2
+
+ LOAD_IMMEDIATE r2, \mac_hi
+ MOVE_TO_SPR SPR_MACHI, r2
+
+ LOAD_IMMEDIATE r2, \mac_lo
+ MOVE_TO_SPR SPR_MACLO, r2
+
+ LOAD_IMMEDIATE r5, \op1
+ LOAD_IMMEDIATE r6, \op2
+
+ l.msb r5, r6
+
+ MOVE_FROM_SPR r3, SPR_MACHI
+ REPORT_REG_TO_CONSOLE r3
+
+ MOVE_FROM_SPR r3, SPR_MACLO
+ REPORT_REG_TO_CONSOLE r3
+
+.endm
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // Test the l.mac instruction.
+ // --------------------------------------------
+
+ // -------- two small positive numbers --------
+
+ // MAC two small positive numbers on a zero total
+ TEST_MAC 0x00000000, 0x00000000, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a small positive total
+ TEST_MAC 0x00000000, 0x00000006, 0x00000002, 0x00000003,
+
+ // MAC two small positive numbers on a moderate positive total
+ TEST_MAC 0x00000000, 0xfffffffa, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a large positive total
+ TEST_MAC 0x3fffffff, 0xfffffffa, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a small negative total
+ TEST_MAC 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a moderate negative total
+ TEST_MAC 0xffffffff, 0x00000000, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a large negative total
+ TEST_MAC 0x80000000, 0x00000000, 0x00000002, 0x00000003
+
+
+ // -------- two moderate positive numbers --------
+
+ // MAC two moderate positive numbers on a zero total
+ TEST_MAC 0x00000000, 0x00000000, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a small positive total
+ TEST_MAC 0x00000000, 0x00000002, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a moderate positive total
+ TEST_MAC 0x00000000, 0x80000002, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a large positive total
+ TEST_MAC 0x7fffffff, 0x80000001, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a small negative total
+ TEST_MAC 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a moderate negative total
+ TEST_MAC 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a large negative total
+ TEST_MAC 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe
+
+
+ // -------- two small negative numbers --------
+
+ // MAC two small negative numbers on a zero total
+ TEST_MAC 0x00000000, 0x00000000, 0xfffffffe, 0xfffffffd
+
+ // MAC two small negative numbers on a small positive total
+ TEST_MAC 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd
+
+ // MAC two small negative numbers on a small negative total
+ TEST_MAC 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd
+
+
+ // -------- one small positive and one small negative --------
+
+ // MAC one small positive and one small negative number on a zero total
+ TEST_MAC 0x00000000, 0x00000000, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a small positive total
+ TEST_MAC 0x00000000, 0x0000000c, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a moderate positive total
+ TEST_MAC 0x00000001, 0x00000005, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a large positive total
+ TEST_MAC 0x7fffffff, 0xffffffff, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a small negative total
+ TEST_MAC 0xffffffff, 0xffffffff, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a moderate negative total
+ TEST_MAC 0xffffffff, 0x00000005, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a large negative total
+ TEST_MAC 0x80000000, 0x00000006, 0x00000002, 0xfffffffd
+
+
+ // -------- one moderate positive and one moderate negative number --------
+
+ // MAC one moderate positive and one moderate negative number on a zero total
+ TEST_MAC 0x00000000, 0x00000000, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a small positive total
+ TEST_MAC 0x00000000, 0x00000006, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a moderate positive total
+ TEST_MAC 0x00000000, 0x80000000, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a large positive total
+ TEST_MAC 0x7fffffff, 0xffffffff, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a small negative total
+ TEST_MAC 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a moderate negative total
+ TEST_MAC 0xffffffff, 0x7fffffff, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a large negative total
+ TEST_MAC 0x80000000, 0x80000000, 0x00008000, 0xffff0000
+
+
+ // Test the l.maci instruction.
+ // --------------------------------------------
+
+ // -------- two small positive numbers --------
+
+ // MAC two small positive numbers on a zero total
+ TEST_MACI 0x00000000, 0x00000000, 0x00000002, 0x0003
+
+ // MAC two small positive numbers on a small positive total
+ TEST_MACI 0x00000000, 0x00000006, 0x00000002, 0x0003
+
+ // MAC two small positive numbers on a moderate positive total
+ TEST_MACI 0x00000000, 0xfffffffa, 0x00000002, 0x0003
+
+ // MAC two small positive numbers on a large positive total
+ TEST_MACI 0x3fffffff, 0xfffffffa, 0x00000002, 0x0003
+
+ // MAC two small positive numbers on a small negative total
+ TEST_MACI 0xffffffff, 0xfffffffa, 0x00000002, 0x0003
+
+ // MAC two small positive numbers on a moderate negative total
+ TEST_MACI 0xffffffff, 0x00000000, 0x00000002, 0x0003
+
+ // MAC two small positive numbers on a large negative total
+ TEST_MACI 0x80000000, 0x00000000, 0x00000002, 0x0003
+
+
+ // -------- two moderate positive numbers --------
+
+ // MAC two moderate positive numbers on a zero total
+ TEST_MACI 0x00000000, 0x00000000, 0x00010002, 0x7fff
+
+ // MAC two moderate positive numbers on a small positive total
+ TEST_MACI 0x00000000, 0x00000002, 0x00010002, 0x7fff
+
+ // MAC two moderate positive numbers on a moderate positive total
+ TEST_MACI 0x00000000, 0x80000002, 0x00010002, 0x7fff
+
+ // MAC two moderate positive numbers on a large positive total
+ TEST_MACI 0x7fffffff, 0x80000001, 0x00010002, 0x7fff
+
+ // MAC two moderate positive numbers on a small negative total
+ TEST_MACI 0xffffffff, 0xffffffff, 0x00010002, 0x7fff
+
+ // MAC two moderate positive numbers on a moderate negative total
+ TEST_MACI 0xffffffff, 0x80000002, 0x00010002, 0x7fff
+
+ // MAC two moderate positive numbers on a large negative total
+ TEST_MACI 0xfffffffe, 0x80000002, 0x00010002, 0x7fff
+
+
+ // -------- two small negative numbers --------
+
+ // MAC two small negative numbers on a zero total
+ TEST_MACI 0x00000000, 0x00000000, 0xfffffffe, 0xfffd
+
+ // MAC two small negative numbers on a small positive total
+ TEST_MACI 0x00000000, 0x00000006, 0xfffffffe, 0xfffd
+
+ // MAC two small negative numbers on a small negative total
+ TEST_MACI 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffd
+
+
+ // -------- one small positive and one small negative --------
+
+ // MAC one small positive and one small negative number on a zero total
+ TEST_MACI 0x00000000, 0x00000000, 0x00000002, 0xfffd
+
+ // MAC one small positive and one small negative number on a small positive total
+ TEST_MACI 0x00000000, 0x0000000c, 0x00000002, 0xfffd
+
+ // MAC one small positive and one small negative number on a moderate positive total
+ TEST_MACI 0x00000001, 0x00000005, 0x00000002, 0xfffd
+
+ // MAC one small positive and one small negative number on a large positive total
+ TEST_MACI 0x7fffffff, 0xffffffff, 0x00000002, 0xfffd
+
+ // MAC one small positive and one small negative number on a small negative total
+ TEST_MACI 0xffffffff, 0xffffffff, 0x00000002, 0xfffd
+
+ // MAC one small positive and one small negative number on a moderate negative total
+ TEST_MACI 0xffffffff, 0x00000005, 0x00000002, 0xfffd
+
+ // MAC one small positive and one small negative number on a large negative total
+ TEST_MACI 0x80000000, 0x00000006, 0x00000002, 0xfffd
+
+
+ // -------- one moderate positive and one moderate negative --------
+
+ // MAC one moderate positive and one moderate negative number on a zero total
+ TEST_MACI 0x00000000, 0x00000000, 0x00010000, 0x8000
+
+ // MAC one moderate positive and one moderate negative number on a small positive total
+ TEST_MACI 0x00000000, 0x00000006, 0x00010000, 0x8000
+
+ // MAC one moderate positive and one moderate negative number on a moderate positive total
+ TEST_MACI 0x00000000, 0x80000000, 0x00010000, 0x8000
+
+ // MAC one moderate positive and one moderate negative number on a large positive total
+ TEST_MACI 0x7fffffff, 0xffffffff, 0x00010000, 0x8000
+
+ // MAC one moderate positive and one moderate negative number on a small negative total
+ TEST_MACI 0xffffffff, 0xffffffff, 0x00010000, 0x8000
+
+ // MAC one moderate positive and one moderate negative number on a moderate negative total
+ TEST_MACI 0xffffffff, 0x7fffffff, 0x00010000, 0x8000
+
+ // MAC one moderate positive and one moderate negative number on a large negative total
+ TEST_MACI 0x80000000, 0x80000000, 0x00010000, 0x8000
+
+
+ // Test the l.macrc instruction.
+ // --------------------------------------------
+ // Note that these tests use the same input data as the ones for l.mac above.
+ // The results are the same, but only the low 32-bits are compared.
+
+ // -------- two small positive numbers --------
+
+ // MAC two small positive numbers on a zero total
+ TEST_MACRC 0x00000000, 0x00000000, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a small positive total
+ TEST_MACRC 0x00000000, 0x00000006, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a moderate positive total
+ TEST_MACRC 0x00000000, 0xfffffffa, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a large positive total
+ TEST_MACRC 0x3fffffff, 0xfffffffa, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a small negative total
+ TEST_MACRC 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a moderate negative total
+ TEST_MACRC 0xffffffff, 0x00000000, 0x00000002, 0x00000003
+
+ // MAC two small positive numbers on a large negative total
+ TEST_MACRC 0x80000000, 0x00000000, 0x00000002, 0x00000003
+
+
+ // -------- two moderate positive numbers --------
+
+ // MAC two moderate positive numbers on a zero total
+ TEST_MACRC 0x00000000, 0x00000000, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a small positive total
+ TEST_MACRC 0x00000000, 0x00000002, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a moderate positive total
+ TEST_MACRC 0x00000000, 0x80000002, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a large positive total
+ TEST_MACRC 0x7fffffff, 0x80000001, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a small negative total
+ TEST_MACRC 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a moderate negative total
+ TEST_MACRC 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe
+
+ // MAC two moderate positive numbers on a large negative total
+ TEST_MACRC 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe
+
+
+ // -------- two small negative numbers --------
+
+ // MAC two small negative numbers on a zero total
+ TEST_MACRC 0x00000000, 0x00000000, 0xfffffffe, 0xfffffffd
+
+ // MAC two small negative numbers on a small positive total
+ TEST_MACRC 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd
+
+ // MAC two small negative numbers on a small negative total
+ TEST_MACRC 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd
+
+
+ // -------- one small positive and one small negative number --------
+
+ // MAC one small positive and one small negative number on a zero total
+ TEST_MACRC 0x00000000, 0x00000000, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a small positive total
+ TEST_MACRC 0x00000000, 0x0000000c, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a moderate positive total
+ TEST_MACRC 0x00000001, 0x00000005, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a large positive total
+ TEST_MACRC 0x7fffffff, 0xffffffff, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a small negative total
+ TEST_MACRC 0xffffffff, 0xffffffff, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a moderate negative total
+ TEST_MACRC 0xffffffff, 0x00000005, 0x00000002, 0xfffffffd
+
+ // MAC one small positive and one small negative number on a large negative total
+ TEST_MACRC 0x80000000, 0x00000006, 0x00000002, 0xfffffffd
+
+
+ // -------- one moderate positive and one moderate negative --------
+
+ // MAC one moderate positive and one moderate negative number on a zero total
+ TEST_MACRC 0x00000000, 0x00000000, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a small positive total
+ TEST_MACRC 0x00000000, 0x00000006, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a moderate positive total
+ TEST_MACRC 0x00000000, 0x80000000, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a large positive total
+ TEST_MACRC 0x7fffffff, 0xffffffff, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a small negative total
+ TEST_MACRC 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a moderate negative total
+ TEST_MACRC 0xffffffff, 0x7fffffff, 0x00008000, 0xffff0000
+
+ // MAC one moderate positive and one moderate negative number on a large negative total
+ TEST_MACRC 0x80000000, 0x80000000, 0x00008000, 0xffff0000
+
+
+ // Test the l.msb instruction.
+ // --------------------------------------------
+
+ // MSB two small positive numbers on a zero total
+ TEST_MSB 0x00000000, 0x00000000, 0x00000002, 0x00000003
+
+ // MSB two small positive numbers on a small positive total
+ TEST_MSB 0x00000000, 0x0000000c, 0x00000002, 0x00000003
+
+ // MSB two small positive numbers on a moderate positive total
+ TEST_MSB 0x00000001, 0x00000000, 0x00000002, 0x00000003
+
+ // MSB two small positive numbers on a large positive total
+ TEST_MSB 0x40000000, 0x00000000, 0x00000002, 0x00000003
+
+ // MSB two small positive numbers on a small negative total
+ TEST_MSB 0xffffffff, 0xfffffffa, 0x00000002, 0x00000003
+
+ // MSB two small positive numbers on a moderate negative total
+ TEST_MSB 0xffffffff, 0x00000005, 0x00000002, 0x00000003
+
+ // MSB two small positive numbers on a large negative total
+ TEST_MSB 0x80000000, 0x00000006, 0x00000002, 0x00000003
+
+
+ // -------- two moderate positive numbers --------
+
+ // MSB two moderate positive numbers on a zero total
+ TEST_MSB 0x00000000, 0x00000000, 0x00008001, 0x0000fffe
+
+ // MSB two moderate positive numbers on a small positive total
+ TEST_MSB 0x00000000, 0x00000002, 0x00008001, 0x0000fffe
+
+ // MSB two moderate positive numbers on a moderate positive total
+ TEST_MSB 0x00000000, 0x80000002, 0x00008001, 0x0000fffe
+
+ // MSB two moderate positive numbers on a large positive total
+ TEST_MSB 0x7fffffff, 0x7ffffffd, 0x00008001, 0x0000fffe
+
+ // MSB two moderate positive numbers on a small negative total
+ TEST_MSB 0xffffffff, 0xffffffff, 0x00008001, 0x0000fffe
+
+ // MSB two moderate positive numbers on a moderate negative total
+ TEST_MSB 0xffffffff, 0x80000002, 0x00008001, 0x0000fffe
+
+ // MSB two moderate positive numbers on a large negative total
+ TEST_MSB 0xfffffffe, 0x80000002, 0x00008001, 0x0000fffe
+
+
+ // -------- two small negative numbers --------
+
+ // MSB two small negative numbers on a zero total
+ TEST_MSB 0x00000000, 0x00000006, 0xfffffffe, 0xfffffffd
+
+ // MSB two small negative numbers on a small positive total
+ TEST_MSB 0x00000000, 0x0000000c, 0xfffffffe, 0xfffffffd
+
+ // MSB two small negative numbers on a small negative total
+ TEST_MSB 0xffffffff, 0xffffffff, 0xfffffffe, 0xfffffffd
+
+
+ // -------- one small positive and one small negative number --------
+
+ // MSB one small positive and one small negative number on a zero total
+ TEST_MSB 0x00000000, 0x00000000, 0x00000002, 0xfffffffd
+
+ // MSB one small positive and one small negative number on a small positive total
+ TEST_MSB 0x00000000, 0x00000006, 0x00000002, 0xfffffffd
+
+ // MSB one small positive and one small negative number on a moderate positive total
+ TEST_MSB 0x00000000, 0xffffffff, 0x00000002, 0xfffffffd
+
+ // MSB one small positive and one small negative number on a large positive total
+ TEST_MSB 0x7fffffff, 0xfffffff9, 0x00000002, 0xfffffffd
+
+ // MSB one small positive and one small negative number on a small negative total
+ TEST_MSB 0xffffffff, 0xfffffff9, 0x00000002, 0xfffffffd
+
+ // MSB one small positive and one small negative number on a moderate negative total
+ TEST_MSB 0xfffffffe, 0xffffffff, 0x00000002, 0xfffffffd
+
+ // MSB one small positive and one small negative number on a large negative total
+ TEST_MSB 0x80000000, 0x00000000, 0x00000002, 0xfffffffd
+
+
+ // -------- one moderate positive and one moderate negative number --------
+
+ // MSB one moderate positive and one moderate negative number on a zero total
+ TEST_MSB 0x00000000, 0x00000000, 0x00008000, 0xffff0000
+
+ // MSB one moderate positive and one moderate negative number on a small positive total
+ TEST_MSB 0x00000000, 0x00000006, 0x00008000, 0xffff0000
+
+ // MSB one moderate positive and one moderate negative number on a moderate positive total
+ TEST_MSB 0x00000000, 0x80000000, 0x00008000, 0xffff0000
+
+ // MSB one moderate positive and one moderate negative number on a large positive total
+ TEST_MSB 0x7fffffff, 0x7fffffff, 0x00008000, 0xffff0000
+
+ // MSB one moderate positive and one moderate negative number on a small negative total
+ TEST_MSB 0xffffffff, 0xffffffff, 0x00008000, 0xffff0000
+
+ // MSB one moderate positive and one moderate negative number on a moderate negative total
+ TEST_MSB 0xfffffffe, 0xffffffff, 0x00008000, 0xffff0000
+
+ // MSB one moderate positive and one moderate negative number on a large negative total
+ TEST_MSB 0x80000000, 0x00000000, 0x00008000, 0xffff0000
+
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/mfspr.S b/sim/testsuite/sim/or1k/mfspr.S
new file mode 100644
index 0000000..7007fb6
--- /dev/null
+++ b/sim/testsuite/sim/or1k/mfspr.S
@@ -0,0 +1,196 @@
+/* Tests instructions l.mfspr and l.mtspr
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x00000000);\n
+# output: report(0x00002801);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00002801);\n
+# output: report(0x00000000);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00002801);\n
+# output: report(0x00002801);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00000801);\n
+# output: report(0x00002000);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00002000);\n
+# output: report(0x00000801);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00002801);\n
+# output: report(0x00000001);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00000800);\n
+# output: report(0x00002801);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: report(0x00002801);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00002801);\n
+# output: report(0x00000000);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00002801);\n
+# output: report(0x00002801);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00000801);\n
+# output: report(0x00002000);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00002000);\n
+# output: report(0x00000801);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00002801);\n
+# output: report(0x00000001);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: report(0x00000800);\n
+# output: report(0x00002801);\n
+# output: report(0xdeadbeef);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-env.h"
+
+#define MACLO_VAL 0xdeadbeef
+
+
+/* ----------------------------------------------------------------------------
+ * A macro to carry out a test of l.mfspr
+ *
+ * MACLO (0x2801) is used as the SPR, since it can be read and cleared using l.macrc
+ * and can be set using l.maci. spr_number and immediate_val_to_or should be chosen
+ * to address this register.
+ *
+ * The value placed in the register is entirely arbitrary - we use 0xdeadbeef.
+ * ------------------------------------------------------------------------- */
+
+.macro TEST_MFSPR spr_number, immediate_val_to_or
+
+ REPORT_IMMEDIATE_TO_CONSOLE \spr_number
+ REPORT_IMMEDIATE_TO_CONSOLE \immediate_val_to_or
+
+ // Write MACLO_VAL to MACLO.
+ l.macrc r2
+ LOAD_IMMEDIATE r2, MACLO_VAL
+ l.maci r2, 1
+
+ LOAD_IMMEDIATE r5, \spr_number
+
+ l.mfspr r4, r5, \immediate_val_to_or
+
+ REPORT_REG_TO_CONSOLE r4
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+.endm
+
+
+/* ----------------------------------------------------------------------------
+ * A macro to carry out a test of l.mtspr
+ *
+ * MACLO (0x2801) is used as the SPR, since it can be read and cleared using l.macrc
+ * and can be set using l.maci. spr_number and immediate_val_to_or should be chosen
+ * to address this register.
+ *
+ * The value placed in the register is entirely arbitrary - we use 0xdeadbeef.
+ * ------------------------------------------------------------------------- */
+
+.macro TEST_MTSPR spr_number, immediate_val_to_or
+
+ REPORT_IMMEDIATE_TO_CONSOLE \spr_number
+ REPORT_IMMEDIATE_TO_CONSOLE \immediate_val_to_or
+
+ // Clear MACLO
+ l.macrc r2
+
+ LOAD_IMMEDIATE r4, MACLO_VAL
+ LOAD_IMMEDIATE r5, \spr_number
+
+ l.mtspr r5, r4, \immediate_val_to_or
+
+ // Retrieve MACLO.
+ l.macrc r4
+ REPORT_REG_TO_CONSOLE r4
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+.endm
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // Test the l.mfspr instruction with a range of operands.
+
+ // Move a test value using zero in the register
+ TEST_MFSPR SPR_VR, SPR_MACLO // 0x0000, 0x2801
+
+ // Move a test value using zero as the constant
+ TEST_MFSPR SPR_MACLO, SPR_VR // 0x2801, 0x0000
+
+ // Move a test value using non-zero in both register and constant.
+ // Some of these values will not give the correct result if OR rather
+ // than ADD is used to determine the SPR address
+ TEST_MFSPR SPR_MACLO, SPR_MACLO // 0x2801, 0x2801
+ TEST_MFSPR SPR_DMMUPR, SPR_ICCR // 0x0801, 0x2000
+ TEST_MFSPR SPR_ICCR, SPR_DMMUPR // 0x2000, 0x0801
+ TEST_MFSPR SPR_MACLO, SPR_UPR // 0x2801, 0x0001
+ TEST_MFSPR SPR_DMMUCR, SPR_MACLO // 0x0800, 0x2801
+
+
+ // Test the l.mtspr instruction with a range of operands.
+
+ // Move a test value using zero in the register
+ TEST_MTSPR SPR_VR, SPR_MACLO // 0x0000, 0x2801
+
+ // Move a test value using zero as the constant
+ TEST_MTSPR SPR_MACLO, SPR_VR // 0x2801, 0x0000
+
+ // Move a test value using non-zero in both register and constant.
+ // Some of these values will not give the correct result if OR rather
+ // than ADD is used to determine the SPR address
+ TEST_MTSPR SPR_MACLO, SPR_MACLO // 0x2801, 0x2801
+ TEST_MTSPR SPR_DMMUPR, SPR_ICCR // 0x0801, 0x2000
+ TEST_MTSPR SPR_ICCR, SPR_DMMUPR // 0x2000, 0x0801
+ TEST_MTSPR SPR_MACLO, SPR_UPR // 0x2801, 0x0001
+ TEST_MTSPR SPR_DMMUCR, SPR_MACLO // 0x0800, 0x2801
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/mul.S b/sim/testsuite/sim/or1k/mul.S
new file mode 100644
index 0000000..97b703e
--- /dev/null
+++ b/sim/testsuite/sim/or1k/mul.S
@@ -0,0 +1,277 @@
+/* Tests the multiply instructions.
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x00000002);\n
+# output: report(0x00000003);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00008001);\n
+# output: report(0x0000fffe);\n
+# output: report(0x7ffffffe);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00008000);\n
+# output: report(0x00010000);\n
+# output: report(0x80000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000002);\n
+# output: report(0x00000003);\n
+# output: report(0x00000006);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // Test l.mul
+
+ // Multiply two small positive numbers. Should set no flags.
+ TEST_INST_I32_I32 l.mul, 0x00000002, 0x00000003
+
+ // Multiply two quite large positive numbers. Should set no flags
+ TEST_INST_I32_I32 l.mul, 0x00008001, 0x0000fffe
+
+ // Multiply two slightly too large positive numbers. Should set the
+ // overflow, but not the carry flag .
+ TEST_INST_I32_I32 l.mul, 0x00008000, 0x00010000
+
+ // Multiply two large positive numbers. Should set both the carry and
+ // overflow flags (even though the result is not a negative number.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0x00010000, 0x00010000
+
+ // Multiply two small negative numbers. Should set the overflow, but not
+ // the carry flag.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0xfffffffe, 0xfffffffd
+
+ // Multiply two quite large negative numbers. Should set the overflow,
+ // but not the carry flag.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0002
+
+ // Multiply two slightly too large negative numbers. Should set both the
+ // overflow, and the carry flags
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0000
+
+ // Multiply two large negative numbers. Should set the
+ // both the carry and overflow flags (even though the result is a
+ // positive number.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0xffff0000, 0xfffeffff
+
+ // Multiply one small negative number and one small positive number.
+ // Should set the overflow, but not the carry flag.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0x00000002, 0xfffffffd
+
+ // Multiply one quite large negative number and one quite large
+ // positive number. Should set the overflow, but not the carry flag.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0xffff8000, 0x00010000
+
+ // Multiply one slightly too large negative number and one slightly
+ // too large positive number. Should set both the carry and overflow flags.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0xffff7fff, 0x00010000
+
+ // Multiply the largest negative number by positive unity. Should set
+ // neither carry, nor overflow flag.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0x80000000, 0x00000001
+
+ // ------ Check that range exceptions are triggered.
+
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // Check that an overflow alone causes a RANGE Exception.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0x00008000, 0x00010000
+
+ // Check that a carry alone does not cause a RANGE Exception.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0x00000002, 0xfffffffd
+
+ // Check that carry and overflow together cause an exception.
+ // TODO: disabled, as it fails against ORPSoC V2's or1200
+ // TEST_INST_I32_I32 l.mul, 0xffff7fff, 0xffff0000
+
+ CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+
+ // Test l.muli
+
+ // Multiply two small positive numbers. Should set no flags.
+ TEST_INST_I32_I16 l.muli, 0x00000002, 0x0003
+
+ /* TODO: carry on here
+ // Multiply two quite large positive numbers. Should set no flags
+ TEST_INST_I32_I16 l.muli, 0x00010002, 0x7fff
+
+ // Multiply two slightly too large positive numbers. Should set the
+ // overflow, but not the carry flag
+ TEST_INST_I32_I16 l.muli, 0x00020000, 0x4000
+
+ // Multiply two large positive numbers. Should set both the carry and
+ // overflow flags (even though the result is not a negative number.
+ TEST_INST_I32_I16 l.muli, 0x00040000, 0x4000
+
+ // Multiply two small negative numbers. Should set the overflow, but not
+ // the carry flag.
+ TEST_INST_I32_I16 l.muli, 0xfffffffe, 0xfffd
+
+ // Multiply two quite large negative numbers. Should set the overflow,
+ // but not the carry flag.
+ TEST_INST_I32_I16 l.muli, 0xfffefffe, 0x8001
+
+ // Multiply two slightly too large negative numbers. Should set both the
+ // overflow, and the carry flags
+ TEST_INST_I32_I16 l.muli, 0xfffe0000, 0xbfff
+
+ // Multiply two large negative numbers. Should set the
+ // both the carry and overflow flags (even though the result is a positive number.
+ TEST_INST_I32_I16 l.muli, 0xfffdfffe, 0x8000
+
+ // Multiply one small negative number and one small positive number.
+ // Should set the overflow, but not the carry flag.
+ TEST_INST_I32_I16 l.muli, 0x00000002, 0xfffd
+
+ // Multiply one quite large negative number and one quite large
+ // positive number. Should set the overflow, but not the carry flag.
+ TEST_INST_I32_I16 l.muli, 0x00010000, 0x8000
+
+ // Multiply one slightly too large negative number and one slightly
+ // too large positive number. Should set both the carry and overflow flags.
+ TEST_INST_I32_I16 l.muli, 0xfffdfffc, 0x4000
+
+ // Multiply the largest negative number by positive unity. Should set
+ // neither carry, nor overflow flag.
+ TEST_INST_I32_I16 l.muli, 0x80000000, 0x0001
+
+ // ------ Check that range exceptions are triggered.
+
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // Check that an overflow alone causes a RANGE Exception.
+ TEST_INST_I32_I16 l.muli, 0x00020000, 0x4000
+
+ // Check that a carry alone does not cause a RANGE Exception.
+ TEST_INST_I32_I16 l.muli, 0xfffffffe, 0xfffd
+
+ // Check that carry and overflow together cause an exception.
+ TEST_INST_I32_I16 l.muli, 0xfffdfffe, 0x8000
+
+ CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+
+ // Test l.mulu
+
+ // Multiply two small positive numbers. Should set no flags.
+ TEST_INST_I32_I32 l.mulu, 0x00000002, 0x00000003
+
+ // Multiply two quite large positive numbers. Should set no flags
+ TEST_INST_I32_I32 l.mulu, 0x00008001, 0x0000fffe
+
+ // Multiply two slightly too large positive numbers. Should set the
+ // overflow, but not the carry flag
+ TEST_INST_I32_I32 l.mulu, 0x00008000, 0x00010000
+
+ // Multiply two large positive numbers. Should set both the carry and
+ // overflow flags (even though the result is not a negative number.
+ TEST_INST_I32_I32 l.mulu, 0x00010000, 0x00010000
+
+ // Multiply two small negative numbers. Should set the overflow, but not
+ // the carry flag.
+ TEST_INST_I32_I32 l.mulu, 0xfffffffe, 0xfffffffd
+
+ // Multiply two quite large negative numbers. Should set the overflow,
+ // but not the carry flag.
+ TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0002
+
+ // Multiply two slightly too large negative numbers. Should set both the
+ // overflow, and the carry flags
+ TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0000
+
+ // Multiply two large negative numbers. Should set the
+ // both the carry and overflow flags (even though the result is a positive number.
+ TEST_INST_I32_I32 l.mulu, 0xffff0000, 0xfffeffff
+
+ // Multiply one small negative number and one small positive number.
+ // Should set the overflow, but not the carry flag.
+ TEST_INST_I32_I32 l.mulu, 0x00000002, 0xfffffffd
+
+ // Multiply one quite large negative number and one quite large
+ // positive number. Should set the overflow, but not the carry flag.
+ TEST_INST_I32_I32 l.mulu, 0xffff8000, 0x00010000
+
+ // Multiply one slightly too large negative number and one slightly
+ // too large positive number. Should set both the carry and overflow flags.
+ TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0x00010000
+
+ // Multiply the largest negative number by positive unity. Should set
+ // neither carry, nor overflow flag.
+ TEST_INST_I32_I32 l.mulu, 0x80000000, 0x00000001
+
+
+ // ------ Check that range exceptions are NEVER triggered.
+
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // Check that what would cause an overflow alone in 2's complement does
+ // not cause a RANGE Exception.
+ TEST_INST_I32_I32 l.mulu, 0x00008000, 0x00010000
+
+ // Check that a carry alone does not cause a RANGE Exception.
+ TEST_INST_I32_I32 l.mulu, 0x00000002, 0xfffffffd
+
+ // Check that what would cause an overflow and carry in 2's complement
+ // does not cause a RANGE Exception.
+ TEST_INST_I32_I32 l.mulu, 0xffff7fff, 0xffff0000
+
+ CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+ */
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/or.S b/sim/testsuite/sim/or1k/or.S
new file mode 100644
index 0000000..5d96baf
--- /dev/null
+++ b/sim/testsuite/sim/or1k/or.S
@@ -0,0 +1,207 @@
+/* Tests instructions l.or, l.ori
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0xaaaaaaaa);\n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x55555555);\n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x55555555);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0xb38f0f83);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0xc4c70f07);\n
+# output: report(0xccf7ff7f);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x38f0f83b);\n
+# output: report(0xbbffffbb);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0x0000ffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x0000aaaa);\n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x00005555);\n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00005555);\n
+# output: report(0xaaaaffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000f83);\n
+# output: report(0x4c70ffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000f07);\n
+# output: report(0x4c70ff7f);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000f83b);\n
+# output: report(0xb38fffbb);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+ // Always set OVE. We should never trigger an exception, even if this bit is set.
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ // Test the l.or instruction with a range of operands.
+
+ TEST_INST_I32_I32 l.or, 0x00000000, 0x00000000
+ TEST_INST_I32_I32 l.or, 0xffffffff, 0xffffffff
+ TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0x00000000
+ TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0xaaaaaaaa
+ TEST_INST_I32_I32 l.or, 0x55555555, 0x00000000
+ TEST_INST_I32_I32 l.or, 0x55555555, 0x55555555
+ TEST_INST_I32_I32 l.or, 0xaaaaaaaa, 0x55555555
+ TEST_INST_I32_I32 l.or, 0x4c70f07c, 0xb38f0f83
+ TEST_INST_I32_I32 l.or, 0x4c70f07c, 0xc4c70f07
+ TEST_INST_I32_I32 l.or, 0xb38f0f83, 0x38f0f83b
+
+ // Test the l.ori instruction with a range of operands.
+ TEST_INST_I32_I16 l.ori, 0x00000000, 0x0000
+ TEST_INST_I32_I16 l.ori, 0xffffffff, 0xffff
+ TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0x0000
+ TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0xaaaa
+ TEST_INST_I32_I16 l.ori, 0x55555555, 0x0000
+ TEST_INST_I32_I16 l.ori, 0x55555555, 0x5555
+ TEST_INST_I32_I16 l.ori, 0xaaaaaaaa, 0x5555
+ TEST_INST_I32_I16 l.ori, 0x4c70f07c, 0x0f83
+ TEST_INST_I32_I16 l.ori, 0x4c70f07c, 0x0f07
+ TEST_INST_I32_I16 l.ori, 0xb38f0f83, 0xf83b
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/or1k-asm-test-env.h b/sim/testsuite/sim/or1k/or1k-asm-test-env.h
new file mode 100644
index 0000000..3cf3585
--- /dev/null
+++ b/sim/testsuite/sim/or1k/or1k-asm-test-env.h
@@ -0,0 +1,61 @@
+
+#ifndef OR1K_ASM_TEST_ENV_H
+#define OR1K_ASM_TEST_ENV_H
+
+#include "or1k-asm.h"
+#include "or1k-asm-test.h"
+#include "spr-defs.h"
+
+
+.macro STANDARD_TEST_HEADER
+
+ // Without the "a" (allocatable) flag, this section gets some default flags,
+ // and then it's discarded by objcopy when flattening to the binary file.
+ // 'x' means executable.
+ .section .exception_vectors, "ax"
+ .org 0x100
+ .global _start
+ _start:
+ // Clear R0 on start-up. There is no guarantee that R0 is hardwired to zero,
+ // and indeed it is not when simulating the or1200 Verilog core.
+ CLEAR_REG r0
+
+ OR1K_DELAYED_NOP(l.j test_startup)
+
+ .section .text
+
+ test_startup:
+
+.endm
+
+
+.macro STANDARD_TEST_BODY
+
+ LOAD_IMMEDIATE STACK_POINTER_R1, stack_begin
+
+ CLEAR_BSS r3, r4
+
+ CALL r3, start_tests
+
+ EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_SUCCESS
+
+ .section .stack
+ .space 4096 // We need more than EXCEPTION_STACK_SKIP_SIZE bytes.
+ stack_begin:
+
+.endm
+
+
+.macro STANDARD_TEST_ENVIRONMENT
+
+ // One of the test cases needs to do some tests before setting up the stack and so on.
+ // That's the reason this macro is split into 2 parts, so that the caller
+ // can inject code between the 2 initialisation phases.
+
+ STANDARD_TEST_HEADER
+ STANDARD_TEST_BODY
+
+.endm
+
+
+#endif // Include this file only once.
diff --git a/sim/testsuite/sim/or1k/or1k-asm-test-helpers.h b/sim/testsuite/sim/or1k/or1k-asm-test-helpers.h
new file mode 100644
index 0000000..7cc918c
--- /dev/null
+++ b/sim/testsuite/sim/or1k/or1k-asm-test-helpers.h
@@ -0,0 +1,134 @@
+
+#ifndef OR1K_ASM_TEST_HELPERS_H
+#define OR1K_ASM_TEST_HELPERS_H
+
+#include "spr-defs.h"
+#include "or1k-asm-test-env.h"
+
+
+.macro REPORT_EXCEPTION reg, instruction_addr
+
+ PUSH r2
+ PUSH r3
+
+ MOVE_REG r2, \reg
+
+ LOAD_IMMEDIATE r3, \instruction_addr
+
+ l.sfeq r2, r3
+
+ OR1K_DELAYED_NOP(l.bnf 55f)
+
+ REPORT_IMMEDIATE_TO_CONSOLE 0x00000001
+ OR1K_DELAYED_NOP(l.j 56f)
+
+ 55:
+ REPORT_IMMEDIATE_TO_CONSOLE 0x00000000
+
+ 56:
+ POP r3
+ POP r2
+
+.endm
+
+
+.macro TEST_INST_FF_I32_I32 flags_to_set, flags_to_clear, opcode, op1, op2
+
+ LOAD_IMMEDIATE r5, \op1
+ LOAD_IMMEDIATE r6, \op2
+
+ REPORT_REG_TO_CONSOLE r5
+ REPORT_REG_TO_CONSOLE r6
+
+ // Clear the last exception address.
+ MOVE_TO_SPR SPR_EPCR_BASE, ZERO_R0
+
+ SET_SPR_SR_FLAGS \flags_to_set , r2, r3
+ CLEAR_SPR_SR_FLAGS \flags_to_clear, r2, r3
+
+ l.nop 0 // TODO: temporary, remove at the end
+ l.nop 0 // TODO: temporary, remove at the end
+
+\@1$: \opcode r4, r5, r6
+
+ l.nop 0 // TODO: temporary, remove at the end
+ l.nop 0 // TODO: temporary, remove at the end
+
+ MOVE_FROM_SPR r2, SPR_SR // Save the flags.
+ MOVE_FROM_SPR r5, SPR_EPCR_BASE // Save the exception address.
+
+ REPORT_REG_TO_CONSOLE r4
+
+ REPORT_BIT_TO_CONSOLE r2, SPR_SR_CY
+ REPORT_BIT_TO_CONSOLE r2, SPR_SR_OV
+
+ REPORT_EXCEPTION r5, \@1$
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+.endm
+
+
+.macro TEST_INST_FF_I32_I16 flags_to_set, flags_to_clear, opcode, op1, op2
+
+ LOAD_IMMEDIATE r5, \op1
+
+ REPORT_REG_TO_CONSOLE r5
+ REPORT_IMMEDIATE_TO_CONSOLE \op2
+
+ SET_SPR_SR_FLAGS \flags_to_set , r2, r3
+ CLEAR_SPR_SR_FLAGS \flags_to_clear, r2, r3
+
+ // Clear the last exception address.
+ MOVE_TO_SPR SPR_EPCR_BASE, ZERO_R0
+
+\@1$: \opcode r4, r5, \op2
+
+ MOVE_FROM_SPR r2, SPR_SR // Save the flags.
+ MOVE_FROM_SPR r5, SPR_EPCR_BASE // Save the exception address.
+
+ REPORT_REG_TO_CONSOLE r4
+
+ REPORT_BIT_TO_CONSOLE r2, SPR_SR_CY
+ REPORT_BIT_TO_CONSOLE r2, SPR_SR_OV
+
+ REPORT_EXCEPTION r5, \@1$
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+.endm
+
+
+.macro TEST_INST_I32_I32 opcode, op1, op2
+
+ TEST_INST_FF_I32_I32 0, 0, \opcode, \op1, \op2
+
+.endm
+
+
+.macro TEST_INST_I32_I16 opcode, op1, op2
+
+ TEST_INST_FF_I32_I16 0, 0, \opcode, \op1, \op2
+
+.endm
+
+
+.macro CHECK_CARRY_AND_OVERFLOW_NOT_SET overwritten_reg1, overwritten_reg2
+
+ MOVE_FROM_SPR \overwritten_reg1, SPR_SR
+
+ LOAD_IMMEDIATE \overwritten_reg2, SPR_SR_CY + SPR_SR_OV
+ l.and \overwritten_reg1, \overwritten_reg1, \overwritten_reg2
+
+ l.sfne \overwritten_reg1, ZERO_R0
+
+ OR1K_DELAYED_NOP(l.bnf \@1$)
+
+ EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE SEC_GENERIC_ERROR
+
+ \@1$:
+
+.endm
+
+
+#endif // Include this file only once.
diff --git a/sim/testsuite/sim/or1k/or1k-asm-test.h b/sim/testsuite/sim/or1k/or1k-asm-test.h
new file mode 100644
index 0000000..14c41fe
--- /dev/null
+++ b/sim/testsuite/sim/or1k/or1k-asm-test.h
@@ -0,0 +1,258 @@
+
+#ifndef OR1K_ASM_TEST_H
+#define OR1K_ASM_TEST_H
+
+#include "spr-defs.h"
+
+
+// ----------- Register definitions -----------
+
+// The "jump and link" instructions store the return address in R9.
+#define LINK_REGISTER_R9 r9
+
+// These register definitions match the ABI.
+#define ZERO_R0 r0
+#define STACK_POINTER_R1 r1
+#define FRAME_POINTER_R2 r2
+#define RETURN_VALUE_R11 r11
+
+
+// ----------- Load/move/clear helpers -----------
+
+.macro LOAD_IMMEDIATE reg, val
+ l.movhi \reg, hi( \val )
+ l.ori \reg, \reg, lo( \val )
+.endm
+
+.macro MOVE_REG dest_reg, src_reg
+ .ifnes "\dest_reg","\src_reg"
+ l.ori \dest_reg, \src_reg, 0
+ .endif
+.endm
+
+.macro CLEAR_REG reg
+ l.movhi \reg, 0
+.endm
+
+
+.macro MOVE_FROM_SPR reg, spr_reg
+ l.mfspr \reg, ZERO_R0, \spr_reg
+.endm
+
+.macro MOVE_TO_SPR spr_reg, reg
+ l.mtspr ZERO_R0, \reg, \spr_reg
+.endm
+
+
+.macro SET_SPR_SR_FLAGS flag_mask, scratch_reg_1, scratch_reg_2
+ // We cannot use PUSH and POP here because some flags like Carry would get overwritten.
+
+ // We could optimise this routine, as instruction l.mtspr already does a logical OR.
+ MOVE_FROM_SPR \scratch_reg_2, SPR_SR
+ LOAD_IMMEDIATE \scratch_reg_1, \flag_mask
+ l.or \scratch_reg_2, \scratch_reg_2, \scratch_reg_1
+ MOVE_TO_SPR SPR_SR, \scratch_reg_2
+
+.endm
+
+.macro CLEAR_SPR_SR_FLAGS flag_mask, scratch_reg_1, scratch_reg_2
+ // We cannot use PUSH and POP here because some flags like Carry would get overwritten.
+
+ MOVE_FROM_SPR \scratch_reg_2, SPR_SR
+ LOAD_IMMEDIATE \scratch_reg_1, ~\flag_mask
+ l.and \scratch_reg_2, \scratch_reg_2, \scratch_reg_1
+ MOVE_TO_SPR SPR_SR, \scratch_reg_2
+
+.endm
+
+
+// ----------- Stack helpers -----------
+
+// This value is defined in the OpenRISC 1000 specification.
+#define EXCEPTION_STACK_SKIP_SIZE 2092
+
+
+// WARNING: Functions without prolog cannot use these PUSH or POP macros.
+// PERFORMANCE WARNING: These PUSH/POP macros are convenient, but can lead to slow code:
+// if you need to PUSH or POP several registers, it's faster to
+// use non-zero offsets when loading/storing and then increment/decrement
+// the stack pointer just once.
+// NOTE: There is a 2092-byte (see EXCEPTION_STACK_SKIP_SIZE) safety zone at the bottom of the stack,
+// check out the OpenRISC specification for more information.
+.macro PUSH reg
+ l.addi STACK_POINTER_R1, STACK_POINTER_R1, -4
+ l.sw 0(STACK_POINTER_R1), \reg
+.endm
+
+// WARNING: see the warnings for PUSH.
+.macro POP reg
+ l.lwz \reg, 0(STACK_POINTER_R1)
+ l.addi STACK_POINTER_R1, STACK_POINTER_R1, 4
+.endm
+
+
+// ----------- l.nop definitions for simulation control and console output -----------
+
+
+// Register definitions for the simulation l.nop codes.
+#define NOP_REPORT_R3 r3
+#define NOP_EXIT_R3 r3
+
+
+// SEC = Simulation Exit Code
+#define SEC_SUCCESS 0
+#define SEC_RETURNED_FROM_MAIN 1
+#define SEC_GENERIC_ERROR 2
+
+// When running under the simulator, this l.nop code terminates the simulation.
+.macro EXIT_SIMULATION_WITH_IMMEDIATE_EXIT_CODE immediate_value
+ LOAD_IMMEDIATE NOP_EXIT_R3, \immediate_value
+ l.nop 1
+.endm
+
+.macro EXIT_SIMULATION_WITH_REG_EXIT_CODE reg
+ MOVE_REG NOP_EXIT_R3, \reg
+ l.nop 1
+.endm
+
+
+// When running under the simulator, this l.nop code prints the value of R3 to the console.
+.macro REPORT_TO_CONSOLE
+ l.nop 2
+.endm
+
+
+// NOTE: The stack must be set up, as this macro uses PUSH and POP.
+.macro REPORT_REG_TO_CONSOLE reg
+
+ .ifeqs "\reg","r3"
+
+ // Nothing more to do here, R3 is the register that gets printed.
+ REPORT_TO_CONSOLE
+
+ .else
+
+ PUSH NOP_REPORT_R3
+
+ MOVE_REG NOP_REPORT_R3, \reg
+ REPORT_TO_CONSOLE
+
+ POP NOP_REPORT_R3
+
+ .endif
+
+.endm
+
+
+// NOTE: The stack must be set up, as this macro uses PUSH and POP.
+.macro REPORT_IMMEDIATE_TO_CONSOLE val
+
+ PUSH NOP_REPORT_R3
+
+ LOAD_IMMEDIATE NOP_REPORT_R3, \val
+ REPORT_TO_CONSOLE
+
+ POP NOP_REPORT_R3
+
+.endm
+
+
+.macro PRINT_NEWLINE_TO_CONSOLE
+
+ PUSH r3
+
+ LOAD_IMMEDIATE r3, 0x0A
+ l.nop 4
+
+ POP r3
+
+.endm
+
+
+// If SR[F] is set, writes 0x00000001 to the console, otherwise it writes 0x00000000.
+
+.macro REPORT_SRF_TO_CONSOLE
+
+ OR1K_DELAYED_NOP(l.bnf \@1$)
+
+ REPORT_IMMEDIATE_TO_CONSOLE 0x00000001
+ OR1K_DELAYED_NOP(l.j \@2$)
+
+\@1$:
+ REPORT_IMMEDIATE_TO_CONSOLE 0x00000000
+
+\@2$:
+
+.endm
+
+
+// If the given register is 0, writes 0x00000000 to the console, otherwise it writes 0x00000001.
+
+.macro REPORT_BOOL_TO_CONSOLE reg
+
+ l.sfne \reg, ZERO_R0
+
+ REPORT_SRF_TO_CONSOLE
+
+.endm
+
+
+// Writes to the console the value of the given register bit.
+
+.macro REPORT_BIT_TO_CONSOLE reg, single_bit_mask
+
+ PUSH r2
+ PUSH r3
+ PUSH r4
+
+ MOVE_REG r2, \reg
+
+ LOAD_IMMEDIATE r4, \single_bit_mask
+ l.and r3, r2, r4
+
+ REPORT_BOOL_TO_CONSOLE r3
+
+ POP r4
+ POP r3
+ POP r2
+
+.endm
+
+
+// ----------- Jump helpers -----------
+
+.macro CALL overwritten_reg, subroutine_name
+ LOAD_IMMEDIATE \overwritten_reg, \subroutine_name
+ OR1K_DELAYED_NOP(l.jalr \overwritten_reg)
+.endm
+
+.macro RETURN_TO_LINK_REGISTER_R9
+ OR1K_DELAYED_NOP(l.jr LINK_REGISTER_R9)
+.endm
+
+
+// ----------- Clear the BSS section on start-up -----------
+
+.macro CLEAR_BSS overwritten_reg1, overwritten_reg2
+
+ LOAD_IMMEDIATE \overwritten_reg1, _bss_begin
+ LOAD_IMMEDIATE \overwritten_reg2, _bss_end
+
+ l.sfgeu \overwritten_reg1, \overwritten_reg2
+ OR1K_DELAYED_NOP(l.bf bss_is_empty)
+
+bss_clear_loop:
+ // Possible optimisation to investigate: move "l.sw 0(\overwritten_reg1), r0" to the jump delay slot
+ // as "l.sw -4(\overwritten_reg1), r0" or similar. But keep in mind that there are plans to remove
+ // the jump delay slot.
+ l.sw 0(\overwritten_reg1), r0
+ l.addi \overwritten_reg1, \overwritten_reg1, 4
+ l.sfgtu \overwritten_reg2, \overwritten_reg1
+ OR1K_DELAYED_NOP(l.bf bss_clear_loop)
+
+bss_is_empty:
+
+.endm
+
+
+#endif // Include this file only once.
diff --git a/sim/testsuite/sim/or1k/or1k-asm.h b/sim/testsuite/sim/or1k/or1k-asm.h
new file mode 100644
index 0000000..c328b20
--- /dev/null
+++ b/sim/testsuite/sim/or1k/or1k-asm.h
@@ -0,0 +1,20 @@
+#ifndef OR1K_ASM_H
+#define OR1K_ASM_H
+
+#define OR1K_INST(...) __VA_ARGS__
+
+#if defined(__OR1K_NODELAY__)
+#define OR1K_DELAYED(a, b) a; b
+#define OR1K_DELAYED_NOP(a) a
+.nodelay
+#elif defined(__OR1K_DELAY__)
+#define OR1K_DELAYED(a, b) b; a
+#define OR1K_DELAYED_NOP(a) a; l.nop
+#elif defined(__OR1K_DELAY_COMPAT__)
+#define OR1K_DELAYED(a, b) a; b; l.nop
+#define OR1K_DELAYED_NOP(a) a; l.nop
+#else
+#error One of __OR1K_NODELAY__, __OR1K_DELAY__, or __OR1K_DELAY_COMPAT__ must be defined
+#endif
+
+#endif
diff --git a/sim/testsuite/sim/or1k/or1k-test.ld b/sim/testsuite/sim/or1k/or1k-test.ld
new file mode 100644
index 0000000..11ed9c9
--- /dev/null
+++ b/sim/testsuite/sim/or1k/or1k-test.ld
@@ -0,0 +1,57 @@
+
+MEMORY
+{
+ /* The exception vectors actually start at 0x100, but if you specify that address here,
+ the "--output-target binary" step will start from address 0 with the contents meant for address 0x100 */
+ exception_vectors : ORIGIN = 0 , LENGTH = 8K
+ ram : ORIGIN = 8K, LENGTH = 2M - 8K
+}
+
+SECTIONS
+{
+ .exception_vectors :
+ {
+ KEEP(*(.exception_vectors))
+ } > exception_vectors
+
+ .text :
+ {
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata.*)
+ } > ram
+
+ .data :
+ {
+ *(.data)
+ *(.data.*)
+ } > ram
+
+
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+
+ /* WARNING about section size alignment:
+ The start-up assembly code can only clear BSS section sizes which are aligned to 4 bytes.
+ However, the size of the BSS section may not be aligned, therefore up to 3 bytes more
+ could be zeroed on start-up. This is normally not an issue, as the start of the next section
+ is usually aligned too, so those extra bytes should be just padding. I did try the following
+ trick to align the BSS section size, to no avail:
+ . = ALIGN(., 4);
+ */
+ } > ram
+
+ _bss_begin = ADDR(.bss);
+ _bss_end = _bss_begin + SIZEOF(.bss);
+
+
+ .stack ALIGN(16) (NOLOAD):
+ {
+ *(.stack)
+ } > ram
+}
+
+ENTRY(_start) /* Otherwise, --gc-sections would throw everything away. */
diff --git a/sim/testsuite/sim/or1k/ror.S b/sim/testsuite/sim/or1k/ror.S
new file mode 100644
index 0000000..f263a8e
--- /dev/null
+++ b/sim/testsuite/sim/or1k/ror.S
@@ -0,0 +1,186 @@
+/* Tests instructions l.ror and l.rori
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0xb38f0f83);\n
+# output: report(0x00000000);\n
+# output: report(0xb38f0f83);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000001);\n
+# output: report(0xd9c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000004);\n
+# output: report(0x3b38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000010);\n
+# output: report(0x0f83b38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000001f);\n
+# output: report(0x671e1f07);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000021);\n
+# output: report(0xd9c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00002224);\n
+# output: report(0x3b38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00f789f0);\n
+# output: report(0x0f83b38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0xffffffff);\n
+# output: report(0x671e1f07);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000000);\n
+# output: report(0xb38f0f83);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000001);\n
+# output: report(0xd9c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000004);\n
+# output: report(0x3b38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000010);\n
+# output: report(0x0f83b38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000001f);\n
+# output: report(0x671e1f07);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000021);\n
+# output: report(0xd9c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000024);\n
+# output: report(0x3b38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000030);\n
+# output: report(0x0f83b38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000003f);\n
+# output: report(0x671e1f07);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-env.h"
+
+
+.macro TEST_ROR op1, op2, res
+
+ // Note that 'res' is not used here. We could stop using the .TestResults file
+ // and use 'res' here instead.
+
+ LOAD_IMMEDIATE r5, \op1
+ LOAD_IMMEDIATE r6, \op2
+
+ REPORT_REG_TO_CONSOLE r5
+ REPORT_REG_TO_CONSOLE r6
+
+ l.ror r4, r5, r6
+
+ REPORT_REG_TO_CONSOLE r4
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+.endm
+
+
+.macro TEST_RORI op1, op2, res
+
+ // Note that 'res' is not used here. We could stop using the .TestResults file
+ // and use 'res' here instead.
+
+ LOAD_IMMEDIATE r5, \op1
+
+ REPORT_REG_TO_CONSOLE r5
+ REPORT_IMMEDIATE_TO_CONSOLE \op2
+
+ l.rori r4, r5, \op2
+
+ REPORT_REG_TO_CONSOLE r4
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+.endm
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // Test the l.ror instruction.
+
+ // Rotate by zero
+ TEST_ROR 0xb38f0f83, 0x00000000, 0xb38f0f83
+
+ // Rotate by amounts in the 1 - 31 range.
+ TEST_ROR 0xb38f0f83, 0x00000001, 0xd9c787c1
+ TEST_ROR 0xb38f0f83, 0x00000004, 0x3b38f0f8
+ TEST_ROR 0xb38f0f83, 0x00000010, 0x0f83b38f
+ TEST_ROR 0xb38f0f83, 0x0000001f, 0x671e1f07
+
+ // Rotate by larger amounts - should be masked.
+ TEST_ROR 0xb38f0f83, 0x00000021, 0xd9c787c1
+ TEST_ROR 0xb38f0f83, 0x00002224, 0x3b38f0f8
+ TEST_ROR 0xb38f0f83, 0x00f789f0, 0x0f83b38f
+ TEST_ROR 0xb38f0f83, 0xffffffff, 0x671e1f07
+
+
+ // Test the l.rori instruction.
+
+ // Rotate by zero */
+ TEST_RORI 0xb38f0f83, 0x00000000, 0xb38f0f83
+
+ // Rotate by amounts in the 1 - 31 range.
+ TEST_RORI 0xb38f0f83, 0x01, 0xd9c787c1
+ TEST_RORI 0xb38f0f83, 0x04, 0x3b38f0f8
+ TEST_RORI 0xb38f0f83, 0x10, 0x0f83b38f
+ TEST_RORI 0xb38f0f83, 0x1f, 0x671e1f07
+
+ // Rotate by larger amounts (32 - 63) - should be masked.
+ TEST_RORI 0xb38f0f83, 0x21, 0xd9c787c1
+ TEST_RORI 0xb38f0f83, 0x24, 0x3b38f0f8
+ TEST_RORI 0xb38f0f83, 0x30, 0x0f83b38f
+ TEST_RORI 0xb38f0f83, 0x3f, 0x671e1f07
+
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/shift.S b/sim/testsuite/sim/or1k/shift.S
new file mode 100644
index 0000000..b4b3ea3
--- /dev/null
+++ b/sim/testsuite/sim/or1k/shift.S
@@ -0,0 +1,572 @@
+/* Tests the shift instructions.
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0xb38f0f83);\n
+# output: report(0x00000000);\n
+# output: report(0xb38f0f83);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000001);\n
+# output: report(0x671e1f06);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000004);\n
+# output: report(0x38f0f830);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000010);\n
+# output: report(0x0f830000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000001f);\n
+# output: report(0x80000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000021);\n
+# output: report(0x671e1f06);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00002224);\n
+# output: report(0x38f0f830);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00f789f0);\n
+# output: report(0x0f830000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0xffffffff);\n
+# output: report(0x80000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000000);\n
+# output: report(0xb38f0f83);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000001);\n
+# output: report(0x671e1f06);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000004);\n
+# output: report(0x38f0f830);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000010);\n
+# output: report(0x0f830000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000001f);\n
+# output: report(0x80000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000021);\n
+# output: report(0x671e1f06);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000024);\n
+# output: report(0x38f0f830);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000030);\n
+# output: report(0x0f830000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000003f);\n
+# output: report(0x80000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000000);\n
+# output: report(0xb38f0f83);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000001);\n
+# output: report(0xd9c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000004);\n
+# output: report(0xfb38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000010);\n
+# output: report(0xffffb38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000001f);\n
+# output: report(0xffffffff);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000001);\n
+# output: report(0x2638783e);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000004);\n
+# output: report(0x04c70f07);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000010);\n
+# output: report(0x00004c70);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x0000001f);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000021);\n
+# output: report(0xd9c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00002224);\n
+# output: report(0xfb38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00f789f0);\n
+# output: report(0xffffb38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000021);\n
+# output: report(0x2638783e);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00002224);\n
+# output: report(0x04c70f07);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00f789f0);\n
+# output: report(0x00004c70);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000000);\n
+# output: report(0xb38f0f83);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000001);\n
+# output: report(0xd9c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000004);\n
+# output: report(0xfb38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000010);\n
+# output: report(0xffffb38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000001f);\n
+# output: report(0xffffffff);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000001);\n
+# output: report(0x2638783e);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000004);\n
+# output: report(0x04c70f07);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000010);\n
+# output: report(0x00004c70);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x0000001f);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000021);\n
+# output: report(0xd9c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000024);\n
+# output: report(0xfb38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000030);\n
+# output: report(0xffffb38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000003f);\n
+# output: report(0xffffffff);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000021);\n
+# output: report(0x2638783e);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000024);\n
+# output: report(0x04c70f07);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000030);\n
+# output: report(0x00004c70);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x0000003f);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000000);\n
+# output: report(0xb38f0f83);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000001);\n
+# output: report(0x59c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000004);\n
+# output: report(0x0b38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000010);\n
+# output: report(0x0000b38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000001f);\n
+# output: report(0x00000001);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000001);\n
+# output: report(0x2638783e);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000004);\n
+# output: report(0x04c70f07);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000010);\n
+# output: report(0x00004c70);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x0000001f);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000021);\n
+# output: report(0x59c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00002224);\n
+# output: report(0x0b38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00f789f0);\n
+# output: report(0x0000b38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000001);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000021);\n
+# output: report(0x2638783e);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00002224);\n
+# output: report(0x04c70f07);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00f789f0);\n
+# output: report(0x00004c70);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000000);\n
+# output: report(0xb38f0f83);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000001);\n
+# output: report(0x59c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000004);\n
+# output: report(0x0b38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000010);\n
+# output: report(0x0000b38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000001f);\n
+# output: report(0x00000001);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000001);\n
+# output: report(0x2638783e);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000004);\n
+# output: report(0x04c70f07);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000010);\n
+# output: report(0x00004c70);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x0000001f);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000021);\n
+# output: report(0x59c787c1);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000024);\n
+# output: report(0x0b38f0f8);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x00000030);\n
+# output: report(0x0000b38f);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000003f);\n
+# output: report(0x00000001);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000021);\n
+# output: report(0x2638783e);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000024);\n
+# output: report(0x04c70f07);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000030);\n
+# output: report(0x00004c70);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x0000003f);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+.macro TEST_SHIFT opcode, op1, op2
+
+ LOAD_IMMEDIATE r5, \op1
+ LOAD_IMMEDIATE r6, \op2
+
+ REPORT_REG_TO_CONSOLE r5
+ REPORT_REG_TO_CONSOLE r6
+
+ \opcode r4, r5, r6
+
+ CHECK_CARRY_AND_OVERFLOW_NOT_SET r2, r3
+
+ REPORT_REG_TO_CONSOLE r4
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+.endm
+
+
+.macro TEST_SHIFT_I opcode, op1, op2
+
+ LOAD_IMMEDIATE r5, \op1
+
+ REPORT_REG_TO_CONSOLE r5
+ REPORT_IMMEDIATE_TO_CONSOLE \op2
+
+ \opcode r4, r5, \op2
+
+ CHECK_CARRY_AND_OVERFLOW_NOT_SET r2, r3
+
+ REPORT_REG_TO_CONSOLE r4
+
+ PRINT_NEWLINE_TO_CONSOLE
+
+.endm
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // Always set OVE. We should never trigger an exception, even if this bit is set.
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+
+ // Test l.sll
+
+ // Shift left by zero.
+ TEST_SHIFT l.sll, 0xb38f0f83, 0x00000000
+
+ // Shift left by amounts in the 1-31 range
+ TEST_SHIFT l.sll, 0xb38f0f83, 0x00000001
+ TEST_SHIFT l.sll, 0xb38f0f83, 0x00000004
+ TEST_SHIFT l.sll, 0xb38f0f83, 0x00000010
+ TEST_SHIFT l.sll, 0xb38f0f83, 0x0000001f
+
+ // Shift left by larger amounts - should be masked.
+ TEST_SHIFT l.sll, 0xb38f0f83, 0x00000021
+ TEST_SHIFT l.sll, 0xb38f0f83, 0x00002224
+ TEST_SHIFT l.sll, 0xb38f0f83, 0x00f789f0
+ TEST_SHIFT l.sll, 0xb38f0f83, 0xffffffff
+
+
+ // Test l.slli
+
+ // Shift left by zero.
+ TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0000
+
+ // Shift left by amounts in the 1-31 range
+ TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0001
+ TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0004
+ TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0010
+ TEST_SHIFT_I l.slli, 0xb38f0f83, 0x001f
+
+ // Shift left by larger amounts - should be masked.
+ TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0021
+ TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0024
+ TEST_SHIFT_I l.slli, 0xb38f0f83, 0x0030
+ TEST_SHIFT_I l.slli, 0xb38f0f83, 0x003f
+
+
+ // Test l.sra
+
+ // Shift right by zero.
+ TEST_SHIFT l.sra, 0xb38f0f83, 0x00000000
+
+ // Shift right by amounts in the 1-31 range
+ TEST_SHIFT l.sra, 0xb38f0f83, 0x00000001
+ TEST_SHIFT l.sra, 0xb38f0f83, 0x00000004
+ TEST_SHIFT l.sra, 0xb38f0f83, 0x00000010
+ TEST_SHIFT l.sra, 0xb38f0f83, 0x0000001f
+
+ TEST_SHIFT l.sra, 0x4c70f07c, 0x00000001
+ TEST_SHIFT l.sra, 0x4c70f07c, 0x00000004
+ TEST_SHIFT l.sra, 0x4c70f07c, 0x00000010
+ TEST_SHIFT l.sra, 0x4c70f07c, 0x0000001f
+
+ // Shift right by larger amounts - should be masked.
+ TEST_SHIFT l.sra, 0xb38f0f83, 0x00000021
+ TEST_SHIFT l.sra, 0xb38f0f83, 0x00002224
+ TEST_SHIFT l.sra, 0xb38f0f83, 0x00f789f0
+ TEST_SHIFT l.sra, 0xb38f0f83, 0xffffffff
+
+ TEST_SHIFT l.sra, 0x4c70f07c, 0x00000021
+ TEST_SHIFT l.sra, 0x4c70f07c, 0x00002224
+ TEST_SHIFT l.sra, 0x4c70f07c, 0x00f789f0
+ TEST_SHIFT l.sra, 0x4c70f07c, 0xffffffff
+
+
+ // Test l.srai
+
+ // Shift right by zero.
+ TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0000
+
+ // Shift right by amounts in the 1-31 range
+ TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0001
+ TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0004
+ TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0010
+ TEST_SHIFT_I l.srai, 0xb38f0f83, 0x001f
+
+ TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0001
+ TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0004
+ TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0010
+ TEST_SHIFT_I l.srai, 0x4c70f07c, 0x001f
+
+ // Shift right by larger amounts - should be masked.
+ TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0021
+ TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0024
+ TEST_SHIFT_I l.srai, 0xb38f0f83, 0x0030
+ TEST_SHIFT_I l.srai, 0xb38f0f83, 0x003f
+
+ TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0021
+ TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0024
+ TEST_SHIFT_I l.srai, 0x4c70f07c, 0x0030
+ TEST_SHIFT_I l.srai, 0x4c70f07c, 0x003f
+
+
+ // Test l.srl
+
+ // Shift right by zero.
+ TEST_SHIFT l.srl, 0xb38f0f83, 0x00000000
+
+ // Shift right by amounts in the 1-31 range
+ TEST_SHIFT l.srl, 0xb38f0f83, 0x00000001
+ TEST_SHIFT l.srl, 0xb38f0f83, 0x00000004
+ TEST_SHIFT l.srl, 0xb38f0f83, 0x00000010
+ TEST_SHIFT l.srl, 0xb38f0f83, 0x0000001f
+
+ TEST_SHIFT l.srl, 0x4c70f07c, 0x00000001
+ TEST_SHIFT l.srl, 0x4c70f07c, 0x00000004
+ TEST_SHIFT l.srl, 0x4c70f07c, 0x00000010
+ TEST_SHIFT l.srl, 0x4c70f07c, 0x0000001f
+
+ // Shift right by larger amounts - should be masked.
+ TEST_SHIFT l.srl, 0xb38f0f83, 0x00000021
+ TEST_SHIFT l.srl, 0xb38f0f83, 0x00002224
+ TEST_SHIFT l.srl, 0xb38f0f83, 0x00f789f0
+ TEST_SHIFT l.srl, 0xb38f0f83, 0xffffffff
+
+ TEST_SHIFT l.srl, 0x4c70f07c, 0x00000021
+ TEST_SHIFT l.srl, 0x4c70f07c, 0x00002224
+ TEST_SHIFT l.srl, 0x4c70f07c, 0x00f789f0
+ TEST_SHIFT l.srl, 0x4c70f07c, 0xffffffff
+
+
+ // Test l.srli
+
+ // Shift right by zero.
+ TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0000
+
+ // Shift right by amounts in the 1-31 range
+ TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0001
+ TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0004
+ TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0010
+ TEST_SHIFT_I l.srli, 0xb38f0f83, 0x001f
+
+ TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0001
+ TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0004
+ TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0010
+ TEST_SHIFT_I l.srli, 0x4c70f07c, 0x001f
+
+ // Shift right by larger amounts - should be masked.
+ TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0021
+ TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0024
+ TEST_SHIFT_I l.srli, 0xb38f0f83, 0x0030
+ TEST_SHIFT_I l.srli, 0xb38f0f83, 0x003f
+
+ TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0021
+ TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0024
+ TEST_SHIFT_I l.srli, 0x4c70f07c, 0x0030
+ TEST_SHIFT_I l.srli, 0x4c70f07c, 0x003f
+
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/spr-defs.h b/sim/testsuite/sim/or1k/spr-defs.h
new file mode 100644
index 0000000..4499a75
--- /dev/null
+++ b/sim/testsuite/sim/or1k/spr-defs.h
@@ -0,0 +1,590 @@
+/* Special Purpose Registers definitions
+
+ Copyright (C) 1999, 2000 Damjan Lampret, lampret@opencores.org
+ Copyright (C) 2008, 2010 Embecosm Limited
+ Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ Copyright (C) 2012, R. Diez
+
+
+ This program is free software; you can redistribute it and/or modify it
+ under the terms of the GNU General Public License as published by the Free
+ Software Foundation; either version 3 of the License, or (at your option)
+ any later version.
+
+ This program is distributed in the hope that it will be useful, but WITHOUT
+ ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ more details.
+
+ You should have received a copy of the GNU General Public License along
+ with this program. If not, see <http://www.gnu.org/licenses/>. */
+
+
+#ifndef SPR_DEFS_H
+#define SPR_DEFS_H
+
+#define MAX_GRPS 32
+#define MAX_SPRS_PER_GRP_BITS 11
+
+/* Base addresses for the groups */
+#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS)
+#define SPRGROUP_FP (11<< MAX_SPRS_PER_GRP_BITS)
+
+/* System control and status group */
+#define SPR_VR (SPRGROUP_SYS + 0) // Value: 0x0000
+#define SPR_UPR (SPRGROUP_SYS + 1) // Value: 0x0001
+#define SPR_CPUCFGR (SPRGROUP_SYS + 2)
+#define SPR_DMMUCFGR (SPRGROUP_SYS + 3)
+#define SPR_IMMUCFGR (SPRGROUP_SYS + 4)
+#define SPR_DCCFGR (SPRGROUP_SYS + 5)
+#define SPR_ICCFGR (SPRGROUP_SYS + 6)
+#define SPR_DCFGR (SPRGROUP_SYS + 7)
+#define SPR_PCCFGR (SPRGROUP_SYS + 8)
+#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */
+#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */
+#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */
+#define SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */
+#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */
+#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */
+#define SPR_EEAR_BASE (SPRGROUP_SYS + 48)
+#define SPR_EEAR_LAST (SPRGROUP_SYS + 63)
+#define SPR_ESR_BASE (SPRGROUP_SYS + 64)
+#define SPR_ESR_LAST (SPRGROUP_SYS + 79)
+#define SPR_GPR_BASE (SPRGROUP_SYS + 1024)
+
+/* Data MMU group */
+#define SPR_DMMUCR (SPRGROUP_DMMU + 0) // Value: 0x0800
+#define SPR_DMMUPR (SPRGROUP_DMMU + 1) // Value: 0x0801
+#define SPR_DTLBEIR (SPRGROUP_DMMU + 2)
+#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100)
+#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100)
+#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100)
+#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100)
+
+/* Instruction MMU group */
+#define SPR_IMMUCR (SPRGROUP_IMMU + 0)
+#define SPR_ITLBEIR (SPRGROUP_IMMU + 2)
+#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100)
+#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100)
+#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100)
+#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100)
+
+/* Data cache group */
+#define SPR_DCCR (SPRGROUP_DC + 0)
+#define SPR_DCBPR (SPRGROUP_DC + 1)
+#define SPR_DCBFR (SPRGROUP_DC + 2)
+#define SPR_DCBIR (SPRGROUP_DC + 3)
+#define SPR_DCBWR (SPRGROUP_DC + 4)
+#define SPR_DCBLR (SPRGROUP_DC + 5)
+#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200)
+#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200)
+
+/* Instruction cache group */
+#define SPR_ICCR (SPRGROUP_IC + 0) // Value: 0x2000
+#define SPR_ICBPR (SPRGROUP_IC + 1)
+#define SPR_ICBIR (SPRGROUP_IC + 2)
+#define SPR_ICBLR (SPRGROUP_IC + 3)
+#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200)
+#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200)
+
+/* MAC group */
+#define SPR_MACLO (SPRGROUP_MAC + 1) // Value: 0x2801
+#define SPR_MACHI (SPRGROUP_MAC + 2)
+
+/* Debug group */
+#define SPR_DVR(N) (SPRGROUP_D + (N))
+#define SPR_DCR(N) (SPRGROUP_D + 8 + (N))
+#define SPR_DMR1 (SPRGROUP_D + 16)
+#define SPR_DMR2 (SPRGROUP_D + 17)
+#define SPR_DWCR0 (SPRGROUP_D + 18)
+#define SPR_DWCR1 (SPRGROUP_D + 19)
+#define SPR_DSR (SPRGROUP_D + 20)
+#define SPR_DRR (SPRGROUP_D + 21)
+
+/* Performance counters group */
+#define SPR_PCCR(N) (SPRGROUP_PC + (N))
+#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N))
+
+/* Power management group */
+#define SPR_PMR (SPRGROUP_PM + 0)
+
+/* PIC group */
+#define SPR_PICMR (SPRGROUP_PIC + 0)
+#define SPR_PICPR (SPRGROUP_PIC + 1)
+#define SPR_PICSR (SPRGROUP_PIC + 2)
+
+/* Tick Timer group */
+#define SPR_TTMR (SPRGROUP_TT + 0)
+#define SPR_TTCR (SPRGROUP_TT + 1)
+
+/*
+ * Bit definitions for the Version Register
+ *
+ */
+#define SPR_VR_VER 0xff000000 /* Processor version */
+#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */
+#define SPR_VR_RES 0x0000ffc0 /* Reserved */
+#define SPR_VR_REV 0x0000003f /* Processor revision */
+
+#define SPR_VR_VER_OFF 24
+#define SPR_VR_CFG_OFF 16
+#define SPR_VR_REV_OFF 0
+
+/*
+ * Bit definitions for the Unit Present Register
+ *
+ */
+#define SPR_UPR_UP 0x00000001 /* UPR present */
+#define SPR_UPR_DCP 0x00000002 /* Data cache present */
+#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */
+#define SPR_UPR_DMP 0x00000008 /* Data MMU present */
+#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */
+#define SPR_UPR_MP 0x00000020 /* MAC present */
+#define SPR_UPR_DUP 0x00000040 /* Debug unit present */
+#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */
+#define SPR_UPR_PMP 0x00000100 /* Power management present */
+#define SPR_UPR_PICP 0x00000200 /* PIC present */
+#define SPR_UPR_TTP 0x00000400 /* Tick timer present */
+#define SPR_UPR_RES 0x00fe0000 /* Reserved */
+#define SPR_UPR_CUP 0xff000000 /* Context units present */
+
+/*
+ * JPB: Bit definitions for the CPU configuration register
+ *
+ */
+#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */
+#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */
+#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */
+#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */
+#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
+#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
+#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
+#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */
+
+/*
+ * JPB: Bit definitions for the Debug configuration register and other
+ * constants.
+ *
+ */
+
+#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */
+#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */
+#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */
+#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */
+#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */
+#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */
+#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */
+#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */
+#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */
+#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */
+
+#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \
+ 2 == n ? SPR_DCFGR_NDP2 : \
+ 3 == n ? SPR_DCFGR_NDP3 : \
+ 4 == n ? SPR_DCFGR_NDP4 : \
+ 5 == n ? SPR_DCFGR_NDP5 : \
+ 6 == n ? SPR_DCFGR_NDP6 : \
+ 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8)
+#define MAX_MATCHPOINTS 8
+#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2)
+
+/*
+ * Bit definitions for the Supervision Register
+ *
+ */
+#define SPR_SR_SM 0x00000001 /* Supervisor Mode */
+#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */
+#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */
+#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */
+#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */
+#define SPR_SR_DME 0x00000020 /* Data MMU Enable */
+#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */
+#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */
+#define SPR_SR_CE 0x00000100 /* CID Enable */
+#define SPR_SR_F 0x00000200 /* Condition Flag */
+#define SPR_SR_CY 0x00000400 /* Carry flag */
+#define SPR_SR_OV 0x00000800 /* Overflow flag */
+#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */
+#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */
+#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */
+#define SPR_SR_FO 0x00008000 /* Fixed one */
+#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */
+#define SPR_SR_RES 0x0ffe0000 /* Reserved */
+#define SPR_SR_CID 0xf0000000 /* Context ID */
+
+/*
+ * Bit definitions for the Data MMU Control Register
+ *
+ */
+#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */
+#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
+#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
+#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
+
+/*
+ * Bit definitions for the Instruction MMU Control Register
+ *
+ */
+#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */
+#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */
+#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */
+#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */
+
+/*
+ * Bit definitions for the Data TLB Match Register
+ *
+ */
+#define SPR_DTLBMR_V 0x00000001 /* Valid */
+#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
+#define SPR_DTLBMR_CID 0x0000003c /* Context ID */
+#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */
+#define SPR_DTLBMR_VPN 0xffffe000 /* Virtual Page Number */
+
+/*
+ * Bit definitions for the Data TLB Translate Register
+ *
+ */
+#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */
+#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */
+#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */
+#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
+#define SPR_DTLBTR_A 0x00000010 /* Accessed */
+#define SPR_DTLBTR_D 0x00000020 /* Dirty */
+#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */
+#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */
+#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */
+#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */
+#define SPR_DTLBTR_PPN 0xffffe000 /* Physical Page Number */
+
+/*
+ * Bit definitions for the Instruction TLB Match Register
+ *
+ */
+#define SPR_ITLBMR_V 0x00000001 /* Valid */
+#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */
+#define SPR_ITLBMR_CID 0x0000003c /* Context ID */
+#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */
+#define SPR_ITLBMR_VPN 0xffffe000 /* Virtual Page Number */
+
+/*
+ * Bit definitions for the Instruction TLB Translate Register
+ *
+ */
+#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */
+#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */
+#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */
+#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */
+#define SPR_ITLBTR_A 0x00000010 /* Accessed */
+#define SPR_ITLBTR_D 0x00000020 /* Dirty */
+#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */
+#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */
+#define SPR_ITLBTR_PPN 0xffffe000 /* Physical Page Number */
+
+/*
+ * Bit definitions for Data Cache Control register
+ *
+ */
+#define SPR_DCCR_EW 0x000000ff /* Enable ways */
+
+/*
+ * Bit definitions for Insn Cache Control register
+ *
+ */
+#define SPR_ICCR_EW 0x000000ff /* Enable ways */
+
+/*
+ * Bit definitions for Data Cache Configuration Register
+ *
+ */
+
+#define SPR_DCCFGR_NCW 0x00000007
+#define SPR_DCCFGR_NCS 0x00000078
+#define SPR_DCCFGR_CBS 0x00000080
+#define SPR_DCCFGR_CWS 0x00000100
+#define SPR_DCCFGR_CCRI 0x00000200
+#define SPR_DCCFGR_CBIRI 0x00000400
+#define SPR_DCCFGR_CBPRI 0x00000800
+#define SPR_DCCFGR_CBLRI 0x00001000
+#define SPR_DCCFGR_CBFRI 0x00002000
+#define SPR_DCCFGR_CBWBRI 0x00004000
+
+#define SPR_DCCFGR_NCW_OFF 0
+#define SPR_DCCFGR_NCS_OFF 3
+#define SPR_DCCFGR_CBS_OFF 7
+
+/*
+ * Bit definitions for Instruction Cache Configuration Register
+ *
+ */
+#define SPR_ICCFGR_NCW 0x00000007
+#define SPR_ICCFGR_NCS 0x00000078
+#define SPR_ICCFGR_CBS 0x00000080
+#define SPR_ICCFGR_CCRI 0x00000200
+#define SPR_ICCFGR_CBIRI 0x00000400
+#define SPR_ICCFGR_CBPRI 0x00000800
+#define SPR_ICCFGR_CBLRI 0x00001000
+
+#define SPR_ICCFGR_NCW_OFF 0
+#define SPR_ICCFGR_NCS_OFF 3
+#define SPR_ICCFGR_CBS_OFF 7
+
+/*
+ * Bit definitions for Data MMU Configuration Register
+ *
+ */
+
+#define SPR_DMMUCFGR_NTW 0x00000003
+#define SPR_DMMUCFGR_NTS 0x0000001C
+#define SPR_DMMUCFGR_NAE 0x000000E0
+#define SPR_DMMUCFGR_CRI 0x00000100
+#define SPR_DMMUCFGR_PRI 0x00000200
+#define SPR_DMMUCFGR_TEIRI 0x00000400
+#define SPR_DMMUCFGR_HTR 0x00000800
+
+#define SPR_DMMUCFGR_NTW_OFF 0
+#define SPR_DMMUCFGR_NTS_OFF 2
+
+/*
+ * Bit definitions for Instruction MMU Configuration Register
+ *
+ */
+
+#define SPR_IMMUCFGR_NTW 0x00000003
+#define SPR_IMMUCFGR_NTS 0x0000001C
+#define SPR_IMMUCFGR_NAE 0x000000E0
+#define SPR_IMMUCFGR_CRI 0x00000100
+#define SPR_IMMUCFGR_PRI 0x00000200
+#define SPR_IMMUCFGR_TEIRI 0x00000400
+#define SPR_IMMUCFGR_HTR 0x00000800
+
+#define SPR_IMMUCFGR_NTW_OFF 0
+#define SPR_IMMUCFGR_NTS_OFF 2
+
+/*
+ * Bit definitions for Debug Control registers
+ *
+ */
+#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */
+#define SPR_DCR_CC 0x0000000e /* Compare condition */
+#define SPR_DCR_SC 0x00000010 /* Signed compare */
+#define SPR_DCR_CT 0x000000e0 /* Compare to */
+
+/* Bit results with SPR_DCR_CC mask */
+#define SPR_DCR_CC_MASKED 0x00000000
+#define SPR_DCR_CC_EQUAL 0x00000002
+#define SPR_DCR_CC_LESS 0x00000004
+#define SPR_DCR_CC_LESSE 0x00000006
+#define SPR_DCR_CC_GREAT 0x00000008
+#define SPR_DCR_CC_GREATE 0x0000000a
+#define SPR_DCR_CC_NEQUAL 0x0000000c
+
+/* Bit results with SPR_DCR_CT mask */
+#define SPR_DCR_CT_DISABLED 0x00000000
+#define SPR_DCR_CT_IFEA 0x00000020
+#define SPR_DCR_CT_LEA 0x00000040
+#define SPR_DCR_CT_SEA 0x00000060
+#define SPR_DCR_CT_LD 0x00000080
+#define SPR_DCR_CT_SD 0x000000a0
+#define SPR_DCR_CT_LSEA 0x000000c0
+#define SPR_DCR_CT_LSD 0x000000e0
+/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */
+
+/*
+ * Bit definitions for Debug Mode 1 register
+ *
+ */
+#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */
+#define SPR_DMR1_CW0_AND 0x00000001
+#define SPR_DMR1_CW0_OR 0x00000002
+#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR)
+#define SPR_DMR1_CW1_AND 0x00000004
+#define SPR_DMR1_CW1_OR 0x00000008
+#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR)
+#define SPR_DMR1_CW2_AND 0x00000010
+#define SPR_DMR1_CW2_OR 0x00000020
+#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR)
+#define SPR_DMR1_CW3_AND 0x00000040
+#define SPR_DMR1_CW3_OR 0x00000080
+#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR)
+#define SPR_DMR1_CW4_AND 0x00000100
+#define SPR_DMR1_CW4_OR 0x00000200
+#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR)
+#define SPR_DMR1_CW5_AND 0x00000400
+#define SPR_DMR1_CW5_OR 0x00000800
+#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR)
+#define SPR_DMR1_CW6_AND 0x00001000
+#define SPR_DMR1_CW6_OR 0x00002000
+#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR)
+#define SPR_DMR1_CW7_AND 0x00004000
+#define SPR_DMR1_CW7_OR 0x00008000
+#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR)
+#define SPR_DMR1_CW8_AND 0x00010000
+#define SPR_DMR1_CW8_OR 0x00020000
+#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR)
+#define SPR_DMR1_CW9_AND 0x00040000
+#define SPR_DMR1_CW9_OR 0x00080000
+#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR)
+#define SPR_DMR1_RES1 0x00300000 /* Reserved */
+#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/
+#define SPR_DMR1_BT 0x00800000 /* Branch trace */
+#define SPR_DMR1_RES2 0xff000000 /* Reserved */
+
+/*
+ * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
+ *
+ */
+#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */
+#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */
+#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */
+#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */
+#define SPR_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */
+#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */
+#define SPR_DMR2_WBS 0xffc00000 /* JPB: Watchpoint status */
+#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */
+
+/*
+ * Bit definitions for Debug watchpoint counter registers
+ *
+ */
+#define SPR_DWCR_COUNT 0x0000ffff /* Count */
+#define SPR_DWCR_MATCH 0xffff0000 /* Match */
+#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */
+
+/*
+ * Bit definitions for Debug stop register
+ *
+ */
+#define SPR_DSR_RSTE 0x00000001 /* Reset exception */
+#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */
+#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */
+#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */
+#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */
+#define SPR_DSR_AE 0x00000020 /* Alignment exception */
+#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */
+#define SPR_DSR_IE 0x00000080 /* Interrupt exception */
+#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */
+#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */
+#define SPR_DSR_RE 0x00000400 /* Range exception */
+#define SPR_DSR_SCE 0x00000800 /* System call exception */
+#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */
+#define SPR_DSR_TE 0x00002000 /* Trap exception */
+
+/*
+ * Bit definitions for Debug reason register
+ *
+ */
+#define SPR_DRR_RSTE 0x00000001 /* Reset exception */
+#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */
+#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */
+#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */
+#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */
+#define SPR_DRR_AE 0x00000020 /* Alignment exception */
+#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */
+#define SPR_DRR_IE 0x00000080 /* Interrupt exception */
+#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */
+#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */
+#define SPR_DRR_RE 0x00000400 /* Range exception */
+#define SPR_DRR_SCE 0x00000800 /* System call exception */
+#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */
+#define SPR_DRR_TE 0x00002000 /* Trap exception */
+
+/*
+ * Bit definitions for Performance counters mode registers
+ *
+ */
+#define SPR_PCMR_CP 0x00000001 /* Counter present */
+#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */
+#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */
+#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */
+#define SPR_PCMR_LA 0x00000010 /* Load access event */
+#define SPR_PCMR_SA 0x00000020 /* Store access event */
+#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/
+#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */
+#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */
+#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */
+#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */
+#define SPR_PCMR_BS 0x00000800 /* Branch stall event */
+#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */
+#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */
+#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */
+#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */
+
+/*
+ * Bit definitions for the Power management register
+ *
+ */
+#define SPR_PMR_SDF 0x0000000f /* Slow down factor */
+#define SPR_PMR_DME 0x00000010 /* Doze mode enable */
+#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */
+#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */
+#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */
+
+/*
+ * Bit definitions for PICMR
+ *
+ */
+#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */
+
+/*
+ * Bit definitions for PICPR
+ *
+ */
+#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */
+
+/*
+ * Bit definitions for PICSR
+ *
+ */
+#define SPR_PICSR_IS 0xffffffff /* Interrupt status */
+
+/*
+ * Bit definitions for Tick Timer Control Register
+ *
+ */
+#define SPR_TTCR_CNT 0xffffffff /* Count, time period */
+#define SPR_TTMR_TP 0x0fffffff /* Time period */
+#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */
+#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */
+#define SPR_TTMR_DI 0x00000000 /* Disabled */
+#define SPR_TTMR_RT 0x40000000 /* Restart tick */
+#define SPR_TTMR_SR 0x80000000 /* Single run */
+#define SPR_TTMR_CR 0xc0000000 /* Continuous run */
+#define SPR_TTMR_M 0xc0000000 /* Tick mode */
+
+/*
+ * Bit definitions for the FP Control Status Register
+ *
+ */
+#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */
+#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */
+#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */
+#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */
+#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */
+#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */
+#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */
+#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */
+#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */
+#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */
+#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */
+#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \
+ SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \
+ SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF)
+
+#define FPCSR_RM_RN (0<<1)
+#define FPCSR_RM_RZ (1<<1)
+#define FPCSR_RM_RIP (2<<1)
+#define FPCSR_RM_RIN (3<<1)
+
+
+#endif // Include this file only once.
+
diff --git a/sim/testsuite/sim/or1k/sub.S b/sim/testsuite/sim/or1k/sub.S
new file mode 100644
index 0000000..0da4cf0
--- /dev/null
+++ b/sim/testsuite/sim/or1k/sub.S
@@ -0,0 +1,176 @@
+/* Tests instruction l.sub
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x00000003);\n
+# output: report(0x00000002);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000001);\n
+# output: report(0x00000002);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000003);\n
+# output: report(0x00000002);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xfffffffd);\n
+# output: report(0xfffffffe);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0xfffffffe);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x7fffffff);\n
+# output: report(0x3fffffff);\n
+# output: report(0x40000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x40000000);\n
+# output: report(0x40000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x3fffffff);\n
+# output: report(0x40000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x40000000);\n
+# output: report(0x3fffffff);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x80000000);\n
+# output: report(0x7fffffff);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x3fffffff);\n
+# output: report(0x40000000);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000001);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+
+ // ----------- Test l.sub -----------
+
+ // Subtract two small positive numbers. Sets the carry, but never the overflow if the result is negative.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x00000003, 0x00000002
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x00000001, 0x00000002
+
+ // Check carry in is ignored.
+ TEST_INST_FF_I32_I32 SPR_SR_CY, SPR_SR_OV, l.sub, 0x00000003, 0x00000002
+
+ // Subtract two small negative numbers. Sets the carry flag if the
+ // result is negative, but never the overflow flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0xfffffffd, 0xfffffffe
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0xffffffff, 0xfffffffe
+
+ // Subtract two quite large positive numbers. Should set neither the
+ // overflow nor the carry flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, 0x3fffffff
+
+ // Subtract two quite large negative numbers. Should set neither the overflow nor the carry flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x40000000, 0x40000000
+
+ // Subtract two large positive numbers with a negative result. Should
+ // set the carry, but not the overflow flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x3fffffff, 0x40000000
+
+ // Subtract two large negative numbers with a positive result. Should
+ // set neither the carry nor the overflow flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x40000000, 0x3fffffff
+
+ // Subtract a large positive from a large negative number. Should set
+ // overflow but not the carry flag.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x80000000, 0x7fffffff
+
+ // Subtract a large negative from a large positive number. Should set
+ // both the overflow and carry flags.
+ // TODO: disabled, as it fails against ORPSoC V2
+ // TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, 0x80000000
+
+
+ // ------ Check that range exceptions are triggered.
+
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+
+ /* TODO: exceptions test disabled until or1200 fix is in place.
+ // Check that an overflow alone causes a RANGE Exception.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x80000000, 0x7fffffff
+ */
+
+ // Check that a carry alone does not cause a RANGE Exception.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x3fffffff, 0x40000000
+
+ /* TODO: exceptions test disabled until or1200 fix is in place.
+ // Check that carry and overflow together cause an exception.
+ TEST_INST_FF_I32_I32 0, SPR_SR_CY | SPR_SR_OV, l.sub, 0x7fffffff, 0x80000000
+ */
+
+ CLEAR_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
diff --git a/sim/testsuite/sim/or1k/xor.S b/sim/testsuite/sim/or1k/xor.S
new file mode 100644
index 0000000..4864615
--- /dev/null
+++ b/sim/testsuite/sim/or1k/xor.S
@@ -0,0 +1,210 @@
+/* Tests instructions l.xor, l.xori
+ *
+ * This is not a comprehensive test of any instruction (yet).
+ * Of course what is really needed is a comprehensive instruction test...
+ *
+ *
+ * Copyright (C) 1999-2006 OpenCores
+ * Contributors various OpenCores participants
+ * Copyright (C) 2010 Embecosm Limited
+ * Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
+ * Copyright (C) 2012 R. Diez
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 3 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+# mach: or1k
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x55555555);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0xb38f0f83);\n
+# output: report(0xffffffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0xc4c70f07);\n
+# output: report(0x88b7ff7b);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x38f0f83b);\n
+# output: report(0x8b7ff7b8);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xffffffff);\n
+# output: report(0x0000ffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x0000aaaa);\n
+# output: report(0x55550000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x55555555);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x55555555);\n
+# output: report(0x00005555);\n
+# output: report(0x55550000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xaaaaaaaa);\n
+# output: report(0x00005555);\n
+# output: report(0xaaaaffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000f83);\n
+# output: report(0x4c70ffff);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0x4c70f07c);\n
+# output: report(0x00000f07);\n
+# output: report(0x4c70ff7b);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: report(0xb38f0f83);\n
+# output: report(0x0000f83b);\n
+# output: report(0x4c70f7b8);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: report(0x00000000);\n
+# output: \n
+# output: exit(0)\n
+
+#include "or1k-asm-test-helpers.h"
+
+
+ STANDARD_TEST_ENVIRONMENT
+
+ .section .text
+start_tests:
+ PUSH LINK_REGISTER_R9
+
+ // Always set OVE. We should never trigger an exception, even if this bit is set.
+ SET_SPR_SR_FLAGS SPR_SR_OVE, r2, r3
+
+
+ // Test the l.xor instruction with a range of operands.
+
+ TEST_INST_I32_I32 l.xor, 0x00000000, 0x00000000
+ TEST_INST_I32_I32 l.xor, 0xffffffff, 0xffffffff
+ TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0x00000000
+ TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0xaaaaaaaa
+ TEST_INST_I32_I32 l.xor, 0x55555555, 0x00000000
+ TEST_INST_I32_I32 l.xor, 0x55555555, 0x55555555
+ TEST_INST_I32_I32 l.xor, 0xaaaaaaaa, 0x55555555
+ TEST_INST_I32_I32 l.xor, 0x4c70f07c, 0xb38f0f83
+ TEST_INST_I32_I32 l.xor, 0x4c70f07c, 0xc4c70f07
+ TEST_INST_I32_I32 l.xor, 0xb38f0f83, 0x38f0f83b
+
+
+ // Test the l.xori instruction with a range of operands.
+
+ TEST_INST_I32_I16 l.xori, 0x00000000, 0x0000
+ TEST_INST_I32_I16 l.xori, 0xffffffff, 0xffff
+ TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0x0000
+ TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0xaaaa
+ TEST_INST_I32_I16 l.xori, 0x55555555, 0x0000
+ TEST_INST_I32_I16 l.xori, 0x55555555, 0x5555
+ TEST_INST_I32_I16 l.xori, 0xaaaaaaaa, 0x5555
+ TEST_INST_I32_I16 l.xori, 0x4c70f07c, 0x0f83
+ TEST_INST_I32_I16 l.xori, 0x4c70f07c, 0x0f07
+ TEST_INST_I32_I16 l.xori, 0xb38f0f83, 0xf83b
+
+ POP LINK_REGISTER_R9
+ RETURN_TO_LINK_REGISTER_R9
--
2.7.4
^ permalink raw reply [flat|nested] 24+ messages in thread* [PATCH 13/18] sim: or1k: Regenerate cgen files
2016-11-23 22:14 [PATCH 00/18] sim: port for OpenRISC Stafford Horne
` (12 preceding siblings ...)
2016-11-23 22:18 ` [PATCH 16/18] sim: or1k: Do trap breakpoint handling Stafford Horne
@ 2016-11-23 22:18 ` Stafford Horne
2016-11-23 22:18 ` [PATCH 15/18] sim: or1k: Implement register store/fetch Stafford Horne
` (3 subsequent siblings)
17 siblings, 0 replies; 24+ messages in thread
From: Stafford Horne @ 2016-11-23 22:18 UTC (permalink / raw)
To: gdb-patches; +Cc: openrisc, Stafford Horne
These files have been regenerated using latest cgen which has been
updated to generate code that is compatible with the current sim
common api.
---
sim/or1k/arch32.c | 2 +-
sim/or1k/arch64.c | 2 +-
sim/or1k/cpu32.c | 32 ++++
sim/or1k/cpu32.h | 40 ++++-
sim/or1k/cpu64.c | 32 ++++
sim/or1k/cpu64.h | 40 ++++-
sim/or1k/cpuall32.h | 4 +-
sim/or1k/cpuall64.h | 4 +-
sim/or1k/decode32.c | 192 ++++++++++++++++++---
sim/or1k/decode32.h | 68 ++++----
sim/or1k/decode64.c | 196 ++++++++++++++++++---
sim/or1k/decode64.h | 77 +++++----
sim/or1k/model32.c | 180 ++++++++++++++++++-
sim/or1k/model64.c | 10 +-
sim/or1k/or1k32-opc.h | 129 --------------
sim/or1k/or1k64-opc.h | 133 ---------------
sim/or1k/sem32-switch.c | 408 +++++++++++++++++++++++++++++--------------
sim/or1k/sem32.c | 418 +++++++++++++++++++++++++++++++--------------
sim/or1k/sem64-switch.c | 436 +++++++++++++++++++++++++++++++---------------
sim/or1k/sem64.c | 446 +++++++++++++++++++++++++++++++++---------------
20 files changed, 1921 insertions(+), 928 deletions(-)
delete mode 100644 sim/or1k/or1k32-opc.h
delete mode 100644 sim/or1k/or1k64-opc.h
diff --git a/sim/or1k/arch32.c b/sim/or1k/arch32.c
index 769f54c..83a9815 100644
--- a/sim/or1k/arch32.c
+++ b/sim/or1k/arch32.c
@@ -25,7 +25,7 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "bfd.h"
-const MACH *sim_machs[] =
+const SIM_MACH *sim_machs[] =
{
#ifdef HAVE_CPU_OR1K32BF
& or32_mach,
diff --git a/sim/or1k/arch64.c b/sim/or1k/arch64.c
index e73f37b..c3f7597 100644
--- a/sim/or1k/arch64.c
+++ b/sim/or1k/arch64.c
@@ -25,7 +25,7 @@ This file is part of the GNU simulators.
#include "sim-main.h"
#include "bfd.h"
-const MACH *sim_machs[] =
+const SIM_MACH *sim_machs[] =
{
#ifdef HAVE_CPU_OR1K64BF
& or64_mach,
diff --git a/sim/or1k/cpu32.c b/sim/or1k/cpu32.c
index 36b4040..14e11ec 100644
--- a/sim/or1k/cpu32.c
+++ b/sim/or1k/cpu32.c
@@ -10140,6 +10140,38 @@ or1k32bf_h_sys_fpcsr_dzf_set (SIM_CPU *current_cpu, USI newval)
SET_H_SYS_FPCSR_DZF (newval);
}
+/* Get the value of h-atomic-reserve. */
+
+BI
+or1k32bf_h_atomic_reserve_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_atomic_reserve);
+}
+
+/* Set a value for h-atomic-reserve. */
+
+void
+or1k32bf_h_atomic_reserve_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_atomic_reserve) = newval;
+}
+
+/* Get the value of h-atomic-address. */
+
+SI
+or1k32bf_h_atomic_address_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_atomic_address);
+}
+
+/* Set a value for h-atomic-address. */
+
+void
+or1k32bf_h_atomic_address_set (SIM_CPU *current_cpu, SI newval)
+{
+ CPU (h_atomic_address) = newval;
+}
+
/* Record trace results for INSN. */
void
diff --git a/sim/or1k/cpu32.h b/sim/or1k/cpu32.h
index a31a935..771fcdc 100644
--- a/sim/or1k/cpu32.h
+++ b/sim/or1k/cpu32.h
@@ -53,6 +53,14 @@ typedef struct {
do { \
SET_H_SPR ((((index)) + (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))), (x));\
;} while (0)
+ /* atomic reserve flag */
+ BI h_atomic_reserve;
+#define GET_H_ATOMIC_RESERVE() CPU (h_atomic_reserve)
+#define SET_H_ATOMIC_RESERVE(x) (CPU (h_atomic_reserve) = (x))
+ /* atomic reserve address */
+ SI h_atomic_address;
+#define GET_H_ATOMIC_ADDRESS() CPU (h_atomic_address)
+#define SET_H_ATOMIC_ADDRESS(x) (CPU (h_atomic_address) = (x))
} hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} OR1K32BF_CPU_DATA;
@@ -4475,6 +4483,10 @@ USI or1k32bf_h_sys_fpcsr_inf_get (SIM_CPU *);
void or1k32bf_h_sys_fpcsr_inf_set (SIM_CPU *, USI);
USI or1k32bf_h_sys_fpcsr_dzf_get (SIM_CPU *);
void or1k32bf_h_sys_fpcsr_dzf_set (SIM_CPU *, USI);
+BI or1k32bf_h_atomic_reserve_get (SIM_CPU *);
+void or1k32bf_h_atomic_reserve_set (SIM_CPU *, BI);
+SI or1k32bf_h_atomic_address_get (SIM_CPU *);
+void or1k32bf_h_atomic_address_set (SIM_CPU *, SI);
/* These must be hand-written. */
extern CPUREG_FETCH_FN or1k32bf_fetch_register;
@@ -4622,6 +4634,17 @@ struct scache {
f_resv_20_5 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+#define EXTRACT_IFMT_L_MSYNC_VARS \
+ UINT f_opcode; \
+ UINT f_op_25_5; \
+ UINT f_resv_20_21; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_MSYNC_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_resv_20_21 = EXTRACT_LSB0_UINT (insn, 32, 20, 21); \
+
#define EXTRACT_IFMT_L_RFE_VARS \
UINT f_opcode; \
UINT f_resv_25_26; \
@@ -4719,7 +4742,7 @@ struct scache {
#define EXTRACT_IFMT_L_SW_VARS \
UINT f_opcode; \
- UINT f_r1; \
+ UINT f_r2; \
UINT f_r3; \
UINT f_imm16_25_5; \
UINT f_imm16_10_11; \
@@ -4728,12 +4751,25 @@ struct scache {
#define EXTRACT_IFMT_L_SW_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
- f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));\
+#define EXTRACT_IFMT_L_SWA_VARS \
+ UINT f_opcode; \
+ UINT f_r2; \
+ UINT f_r3; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_SWA_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
+
#define EXTRACT_IFMT_L_SLL_VARS \
UINT f_opcode; \
UINT f_r1; \
diff --git a/sim/or1k/cpu64.c b/sim/or1k/cpu64.c
index cd25e89..5f5d605 100644
--- a/sim/or1k/cpu64.c
+++ b/sim/or1k/cpu64.c
@@ -10156,6 +10156,38 @@ or1k64bf_h_sys_fpcsr_dzf_set (SIM_CPU *current_cpu, UDI newval)
SET_H_SYS_FPCSR_DZF (newval);
}
+/* Get the value of h-atomic-reserve. */
+
+BI
+or1k64bf_h_atomic_reserve_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_atomic_reserve);
+}
+
+/* Set a value for h-atomic-reserve. */
+
+void
+or1k64bf_h_atomic_reserve_set (SIM_CPU *current_cpu, BI newval)
+{
+ CPU (h_atomic_reserve) = newval;
+}
+
+/* Get the value of h-atomic-address. */
+
+SI
+or1k64bf_h_atomic_address_get (SIM_CPU *current_cpu)
+{
+ return CPU (h_atomic_address);
+}
+
+/* Set a value for h-atomic-address. */
+
+void
+or1k64bf_h_atomic_address_set (SIM_CPU *current_cpu, SI newval)
+{
+ CPU (h_atomic_address) = newval;
+}
+
/* Record trace results for INSN. */
void
diff --git a/sim/or1k/cpu64.h b/sim/or1k/cpu64.h
index 5bfbf9e..d3a93e7 100644
--- a/sim/or1k/cpu64.h
+++ b/sim/or1k/cpu64.h
@@ -53,6 +53,14 @@ typedef struct {
do { \
SET_H_SPR ((((index)) + (ORDI (SLLDI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))), (x));\
;} while (0)
+ /* atomic reserve flag */
+ BI h_atomic_reserve;
+#define GET_H_ATOMIC_RESERVE() CPU (h_atomic_reserve)
+#define SET_H_ATOMIC_RESERVE(x) (CPU (h_atomic_reserve) = (x))
+ /* atomic reserve address */
+ SI h_atomic_address;
+#define GET_H_ATOMIC_ADDRESS() CPU (h_atomic_address)
+#define SET_H_ATOMIC_ADDRESS(x) (CPU (h_atomic_address) = (x))
} hardware;
#define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
} OR1K64BF_CPU_DATA;
@@ -4482,6 +4490,10 @@ UDI or1k64bf_h_sys_fpcsr_inf_get (SIM_CPU *);
void or1k64bf_h_sys_fpcsr_inf_set (SIM_CPU *, UDI);
UDI or1k64bf_h_sys_fpcsr_dzf_get (SIM_CPU *);
void or1k64bf_h_sys_fpcsr_dzf_set (SIM_CPU *, UDI);
+BI or1k64bf_h_atomic_reserve_get (SIM_CPU *);
+void or1k64bf_h_atomic_reserve_set (SIM_CPU *, BI);
+SI or1k64bf_h_atomic_address_get (SIM_CPU *);
+void or1k64bf_h_atomic_address_set (SIM_CPU *, SI);
/* These must be hand-written. */
extern CPUREG_FETCH_FN or1k64bf_fetch_register;
@@ -4621,6 +4633,17 @@ struct scache {
f_resv_20_5 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
+#define EXTRACT_IFMT_L_MSYNC_VARS \
+ UINT f_opcode; \
+ UINT f_op_25_5; \
+ UINT f_resv_20_21; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_MSYNC_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_resv_20_21 = EXTRACT_LSB0_UINT (insn, 32, 20, 21); \
+
#define EXTRACT_IFMT_L_RFE_VARS \
UINT f_opcode; \
UINT f_resv_25_26; \
@@ -4718,7 +4741,7 @@ struct scache {
#define EXTRACT_IFMT_L_SW_VARS \
UINT f_opcode; \
- UINT f_r1; \
+ UINT f_r2; \
UINT f_r3; \
UINT f_imm16_25_5; \
UINT f_imm16_10_11; \
@@ -4727,12 +4750,25 @@ struct scache {
#define EXTRACT_IFMT_L_SW_CODE \
length = 4; \
f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
- f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));\
+#define EXTRACT_IFMT_L_SWA_VARS \
+ UINT f_opcode; \
+ UINT f_r2; \
+ UINT f_r3; \
+ INT f_simm16; \
+ unsigned int length;
+#define EXTRACT_IFMT_L_SWA_CODE \
+ length = 4; \
+ f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
+
#define EXTRACT_IFMT_L_SLL_VARS \
UINT f_opcode; \
UINT f_r1; \
diff --git a/sim/or1k/cpuall32.h b/sim/or1k/cpuall32.h
index 182bc74..7e792fa 100644
--- a/sim/or1k/cpuall32.h
+++ b/sim/or1k/cpuall32.h
@@ -33,8 +33,8 @@ This file is part of the GNU simulators.
#include "decode.h"
#endif
-extern const MACH or32_mach;
-extern const MACH or32nd_mach;
+extern const SIM_MACH or32_mach;
+extern const SIM_MACH or32nd_mach;
#ifndef WANT_CPU
/* The ARGBUF struct. */
diff --git a/sim/or1k/cpuall64.h b/sim/or1k/cpuall64.h
index 8207d8b..7a58a18 100644
--- a/sim/or1k/cpuall64.h
+++ b/sim/or1k/cpuall64.h
@@ -33,8 +33,8 @@ This file is part of the GNU simulators.
#include "decode64.h"
#endif
-extern const MACH or64_mach;
-extern const MACH or64nd_mach;
+extern const SIM_MACH or64_mach;
+extern const SIM_MACH or64nd_mach;
#ifndef WANT_CPU
/* The ARGBUF struct. */
diff --git a/sim/or1k/decode32.c b/sim/or1k/decode32.c
index 04b29f4..890a50b 100644
--- a/sim/or1k/decode32.c
+++ b/sim/or1k/decode32.c
@@ -54,7 +54,10 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_L_BF, OR1K32BF_INSN_L_BF, OR1K32BF_SFMT_L_BNF },
{ OR1K_INSN_L_TRAP, OR1K32BF_INSN_L_TRAP, OR1K32BF_SFMT_L_TRAP },
{ OR1K_INSN_L_SYS, OR1K32BF_INSN_L_SYS, OR1K32BF_SFMT_L_TRAP },
- { OR1K_INSN_L_RFE, OR1K32BF_INSN_L_RFE, OR1K32BF_SFMT_L_RFE },
+ { OR1K_INSN_L_MSYNC, OR1K32BF_INSN_L_MSYNC, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_PSYNC, OR1K32BF_INSN_L_PSYNC, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CSYNC, OR1K32BF_INSN_L_CSYNC, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_RFE, OR1K32BF_INSN_L_RFE, OR1K32BF_SFMT_L_MSYNC },
{ OR1K_INSN_L_NOP_IMM, OR1K32BF_INSN_L_NOP_IMM, OR1K32BF_SFMT_L_NOP_IMM },
{ OR1K_INSN_L_MOVHI, OR1K32BF_INSN_L_MOVHI, OR1K32BF_SFMT_L_MOVHI },
{ OR1K_INSN_L_MACRC, OR1K32BF_INSN_L_MACRC, OR1K32BF_SFMT_L_MACRC },
@@ -62,6 +65,7 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_L_MTSPR, OR1K32BF_INSN_L_MTSPR, OR1K32BF_SFMT_L_MTSPR },
{ OR1K_INSN_L_LWZ, OR1K32BF_INSN_L_LWZ, OR1K32BF_SFMT_L_LWZ },
{ OR1K_INSN_L_LWS, OR1K32BF_INSN_L_LWS, OR1K32BF_SFMT_L_LWS },
+ { OR1K_INSN_L_LWA, OR1K32BF_INSN_L_LWA, OR1K32BF_SFMT_L_LWA },
{ OR1K_INSN_L_LBZ, OR1K32BF_INSN_L_LBZ, OR1K32BF_SFMT_L_LBZ },
{ OR1K_INSN_L_LBS, OR1K32BF_INSN_L_LBS, OR1K32BF_SFMT_L_LBS },
{ OR1K_INSN_L_LHZ, OR1K32BF_INSN_L_LHZ, OR1K32BF_SFMT_L_LHZ },
@@ -69,6 +73,7 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_L_SW, OR1K32BF_INSN_L_SW, OR1K32BF_SFMT_L_SW },
{ OR1K_INSN_L_SB, OR1K32BF_INSN_L_SB, OR1K32BF_SFMT_L_SB },
{ OR1K_INSN_L_SH, OR1K32BF_INSN_L_SH, OR1K32BF_SFMT_L_SH },
+ { OR1K_INSN_L_SWA, OR1K32BF_INSN_L_SWA, OR1K32BF_SFMT_L_SWA },
{ OR1K_INSN_L_SLL, OR1K32BF_INSN_L_SLL, OR1K32BF_SFMT_L_SLL },
{ OR1K_INSN_L_SLLI, OR1K32BF_INSN_L_SLLI, OR1K32BF_SFMT_L_SLLI },
{ OR1K_INSN_L_SRL, OR1K32BF_INSN_L_SRL, OR1K32BF_SFMT_L_SLL },
@@ -125,14 +130,14 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_L_MAC, OR1K32BF_INSN_L_MAC, OR1K32BF_SFMT_L_MAC },
{ OR1K_INSN_L_MSB, OR1K32BF_INSN_L_MSB, OR1K32BF_SFMT_L_MAC },
{ OR1K_INSN_L_MACI, OR1K32BF_INSN_L_MACI, OR1K32BF_SFMT_L_MACI },
- { OR1K_INSN_L_CUST1, OR1K32BF_INSN_L_CUST1, OR1K32BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST2, OR1K32BF_INSN_L_CUST2, OR1K32BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST3, OR1K32BF_INSN_L_CUST3, OR1K32BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST4, OR1K32BF_INSN_L_CUST4, OR1K32BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST5, OR1K32BF_INSN_L_CUST5, OR1K32BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST6, OR1K32BF_INSN_L_CUST6, OR1K32BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST7, OR1K32BF_INSN_L_CUST7, OR1K32BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST8, OR1K32BF_INSN_L_CUST8, OR1K32BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST1, OR1K32BF_INSN_L_CUST1, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST2, OR1K32BF_INSN_L_CUST2, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST3, OR1K32BF_INSN_L_CUST3, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST4, OR1K32BF_INSN_L_CUST4, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST5, OR1K32BF_INSN_L_CUST5, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST6, OR1K32BF_INSN_L_CUST6, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST7, OR1K32BF_INSN_L_CUST7, OR1K32BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST8, OR1K32BF_INSN_L_CUST8, OR1K32BF_SFMT_L_MSYNC },
{ OR1K_INSN_LF_ADD_S, OR1K32BF_INSN_LF_ADD_S, OR1K32BF_SFMT_LF_ADD_S },
{ OR1K_INSN_LF_SUB_S, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_SFMT_LF_ADD_S },
{ OR1K_INSN_LF_MUL_S, OR1K32BF_INSN_LF_MUL_S, OR1K32BF_SFMT_LF_ADD_S },
@@ -147,7 +152,7 @@ static const struct insn_sem or1k32bf_insn_sem[] =
{ OR1K_INSN_LF_LT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_SFMT_LF_EQ_S },
{ OR1K_INSN_LF_LE_S, OR1K32BF_INSN_LF_LE_S, OR1K32BF_SFMT_LF_EQ_S },
{ OR1K_INSN_LF_MADD_S, OR1K32BF_INSN_LF_MADD_S, OR1K32BF_SFMT_LF_MADD_S },
- { OR1K_INSN_LF_CUST1_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_SFMT_L_RFE },
+ { OR1K_INSN_LF_CUST1_S, OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_SFMT_L_MSYNC },
};
static const struct insn_sem or1k32bf_insn_sem_invalid =
@@ -441,7 +446,34 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
if ((entire_insn & 0xfc1f0000) == 0x18000000)
{ itype = OR1K32BF_INSN_L_MOVHI; goto extract_sfmt_l_movhi; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 256 : /* fall through */
+ case 256 :
+ {
+ unsigned int val = (((insn >> 23) & (7 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffff0000) == 0x20000000)
+ { itype = OR1K32BF_INSN_L_SYS; goto extract_sfmt_l_trap; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffff0000) == 0x21000000)
+ { itype = OR1K32BF_INSN_L_TRAP; goto extract_sfmt_l_trap; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffffffff) == 0x22000000)
+ { itype = OR1K32BF_INSN_L_MSYNC; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffffffff) == 0x22800000)
+ { itype = OR1K32BF_INSN_L_PSYNC; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xffffffff) == 0x23000000)
+ { itype = OR1K32BF_INSN_L_CSYNC; goto extract_sfmt_l_msync; }
+ itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
case 257 : /* fall through */
case 258 : /* fall through */
case 259 : /* fall through */
@@ -490,7 +522,7 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
}
case 288 :
if ((entire_insn & 0xffffffff) == 0x24000000)
- { itype = OR1K32BF_INSN_L_RFE; goto extract_sfmt_l_rfe; }
+ { itype = OR1K32BF_INSN_L_RFE; goto extract_sfmt_l_msync; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 544 :
if ((entire_insn & 0xffff07ff) == 0x44000000)
@@ -535,21 +567,53 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
if ((entire_insn & 0xffe00000) == 0x4c000000)
{ itype = OR1K32BF_INSN_L_MACI; goto extract_sfmt_l_maci; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 864 : /* fall through */
+ case 865 : /* fall through */
+ case 866 : /* fall through */
+ case 867 : /* fall through */
+ case 868 : /* fall through */
+ case 869 : /* fall through */
+ case 870 : /* fall through */
+ case 871 : /* fall through */
+ case 872 : /* fall through */
+ case 873 : /* fall through */
+ case 874 : /* fall through */
+ case 875 : /* fall through */
+ case 876 : /* fall through */
+ case 877 : /* fall through */
+ case 878 : /* fall through */
+ case 879 : /* fall through */
+ case 880 : /* fall through */
+ case 881 : /* fall through */
+ case 882 : /* fall through */
+ case 883 : /* fall through */
+ case 884 : /* fall through */
+ case 885 : /* fall through */
+ case 886 : /* fall through */
+ case 887 : /* fall through */
+ case 888 : /* fall through */
+ case 889 : /* fall through */
+ case 890 : /* fall through */
+ case 891 : /* fall through */
+ case 892 : /* fall through */
+ case 893 : /* fall through */
+ case 894 : /* fall through */
+ case 895 : itype = OR1K32BF_INSN_L_LWA; goto extract_sfmt_l_lwa;
case 896 :
if ((entire_insn & 0xffffffff) == 0x70000000)
- { itype = OR1K32BF_INSN_L_CUST1; goto extract_sfmt_l_rfe; }
+ { itype = OR1K32BF_INSN_L_CUST1; goto extract_sfmt_l_msync; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 928 :
if ((entire_insn & 0xffffffff) == 0x74000000)
- { itype = OR1K32BF_INSN_L_CUST2; goto extract_sfmt_l_rfe; }
+ { itype = OR1K32BF_INSN_L_CUST2; goto extract_sfmt_l_msync; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 960 :
if ((entire_insn & 0xffffffff) == 0x78000000)
- { itype = OR1K32BF_INSN_L_CUST3; goto extract_sfmt_l_rfe; }
+ { itype = OR1K32BF_INSN_L_CUST3; goto extract_sfmt_l_msync; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 992 :
if ((entire_insn & 0xffffffff) == 0x7c000000)
- { itype = OR1K32BF_INSN_L_CUST4; goto extract_sfmt_l_rfe; }
+ { itype = OR1K32BF_INSN_L_CUST4; goto extract_sfmt_l_msync; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1056 : /* fall through */
case 1057 : /* fall through */
@@ -1206,8 +1270,40 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1616 :
if ((entire_insn & 0xffe007ff) == 0xc80000d0)
- { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_rfe; }
+ { itype = OR1K32BF_INSN_LF_CUST1_S; goto extract_sfmt_l_msync; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1632 : /* fall through */
+ case 1633 : /* fall through */
+ case 1634 : /* fall through */
+ case 1635 : /* fall through */
+ case 1636 : /* fall through */
+ case 1637 : /* fall through */
+ case 1638 : /* fall through */
+ case 1639 : /* fall through */
+ case 1640 : /* fall through */
+ case 1641 : /* fall through */
+ case 1642 : /* fall through */
+ case 1643 : /* fall through */
+ case 1644 : /* fall through */
+ case 1645 : /* fall through */
+ case 1646 : /* fall through */
+ case 1647 : /* fall through */
+ case 1648 : /* fall through */
+ case 1649 : /* fall through */
+ case 1650 : /* fall through */
+ case 1651 : /* fall through */
+ case 1652 : /* fall through */
+ case 1653 : /* fall through */
+ case 1654 : /* fall through */
+ case 1655 : /* fall through */
+ case 1656 : /* fall through */
+ case 1657 : /* fall through */
+ case 1658 : /* fall through */
+ case 1659 : /* fall through */
+ case 1660 : /* fall through */
+ case 1661 : /* fall through */
+ case 1662 : /* fall through */
+ case 1663 : itype = OR1K32BF_INSN_L_SWA; goto extract_sfmt_l_swa;
case 1696 : /* fall through */
case 1697 : /* fall through */
case 1698 : /* fall through */
@@ -1486,19 +1582,19 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
}
case 1920 :
if ((entire_insn & 0xffffffff) == 0xf0000000)
- { itype = OR1K32BF_INSN_L_CUST5; goto extract_sfmt_l_rfe; }
+ { itype = OR1K32BF_INSN_L_CUST5; goto extract_sfmt_l_msync; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1952 :
if ((entire_insn & 0xffffffff) == 0xf4000000)
- { itype = OR1K32BF_INSN_L_CUST6; goto extract_sfmt_l_rfe; }
+ { itype = OR1K32BF_INSN_L_CUST6; goto extract_sfmt_l_msync; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1984 :
if ((entire_insn & 0xffffffff) == 0xf8000000)
- { itype = OR1K32BF_INSN_L_CUST7; goto extract_sfmt_l_rfe; }
+ { itype = OR1K32BF_INSN_L_CUST7; goto extract_sfmt_l_msync; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2016 :
if ((entire_insn & 0xffffffff) == 0xfc000000)
- { itype = OR1K32BF_INSN_L_CUST8; goto extract_sfmt_l_rfe; }
+ { itype = OR1K32BF_INSN_L_CUST8; goto extract_sfmt_l_msync; }
itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K32BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -1618,14 +1714,14 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
- extract_sfmt_l_rfe:
+ extract_sfmt_l_msync:
{
const IDESC *idesc = &or1k32bf_insn_data[itype];
#define FLD(f) abuf->fields.sfmt_empty.f
/* Record the fields for the semantic handler. */
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_rfe", (char *) 0));
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_msync", (char *) 0));
#undef FLD
return idesc;
@@ -1781,6 +1877,29 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
+ extract_sfmt_l_lwa:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_lwa", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
extract_sfmt_l_lbz:
{
const IDESC *idesc = &or1k32bf_insn_data[itype];
@@ -1954,6 +2073,33 @@ or1k32bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
+ extract_sfmt_l_swa:
+ {
+ const IDESC *idesc = &or1k32bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ UINT f_imm16_25_5;
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_imm16_10_11;
+ INT f_simm16_split;
+
+ f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+ f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11);
+ f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_simm16_split) = f_simm16_split;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_swa", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_simm16_split 0x%x", 'x', f_simm16_split, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
extract_sfmt_l_sll:
{
const IDESC *idesc = &or1k32bf_insn_data[itype];
diff --git a/sim/or1k/decode32.h b/sim/or1k/decode32.h
index a854856..5511bcc 100644
--- a/sim/or1k/decode32.h
+++ b/sim/or1k/decode32.h
@@ -37,46 +37,48 @@ typedef enum or1k32bf_insn_type {
OR1K32BF_INSN_X_INVALID, OR1K32BF_INSN_X_AFTER, OR1K32BF_INSN_X_BEFORE, OR1K32BF_INSN_X_CTI_CHAIN
, OR1K32BF_INSN_X_CHAIN, OR1K32BF_INSN_X_BEGIN, OR1K32BF_INSN_L_J, OR1K32BF_INSN_L_JAL
, OR1K32BF_INSN_L_JR, OR1K32BF_INSN_L_JALR, OR1K32BF_INSN_L_BNF, OR1K32BF_INSN_L_BF
- , OR1K32BF_INSN_L_TRAP, OR1K32BF_INSN_L_SYS, OR1K32BF_INSN_L_RFE, OR1K32BF_INSN_L_NOP_IMM
- , OR1K32BF_INSN_L_MOVHI, OR1K32BF_INSN_L_MACRC, OR1K32BF_INSN_L_MFSPR, OR1K32BF_INSN_L_MTSPR
- , OR1K32BF_INSN_L_LWZ, OR1K32BF_INSN_L_LWS, OR1K32BF_INSN_L_LBZ, OR1K32BF_INSN_L_LBS
+ , OR1K32BF_INSN_L_TRAP, OR1K32BF_INSN_L_SYS, OR1K32BF_INSN_L_MSYNC, OR1K32BF_INSN_L_PSYNC
+ , OR1K32BF_INSN_L_CSYNC, OR1K32BF_INSN_L_RFE, OR1K32BF_INSN_L_NOP_IMM, OR1K32BF_INSN_L_MOVHI
+ , OR1K32BF_INSN_L_MACRC, OR1K32BF_INSN_L_MFSPR, OR1K32BF_INSN_L_MTSPR, OR1K32BF_INSN_L_LWZ
+ , OR1K32BF_INSN_L_LWS, OR1K32BF_INSN_L_LWA, OR1K32BF_INSN_L_LBZ, OR1K32BF_INSN_L_LBS
, OR1K32BF_INSN_L_LHZ, OR1K32BF_INSN_L_LHS, OR1K32BF_INSN_L_SW, OR1K32BF_INSN_L_SB
- , OR1K32BF_INSN_L_SH, OR1K32BF_INSN_L_SLL, OR1K32BF_INSN_L_SLLI, OR1K32BF_INSN_L_SRL
- , OR1K32BF_INSN_L_SRLI, OR1K32BF_INSN_L_SRA, OR1K32BF_INSN_L_SRAI, OR1K32BF_INSN_L_ROR
- , OR1K32BF_INSN_L_RORI, OR1K32BF_INSN_L_AND, OR1K32BF_INSN_L_OR, OR1K32BF_INSN_L_XOR
- , OR1K32BF_INSN_L_ADD, OR1K32BF_INSN_L_SUB, OR1K32BF_INSN_L_ADDC, OR1K32BF_INSN_L_MUL
- , OR1K32BF_INSN_L_MULU, OR1K32BF_INSN_L_DIV, OR1K32BF_INSN_L_DIVU, OR1K32BF_INSN_L_FF1
- , OR1K32BF_INSN_L_FL1, OR1K32BF_INSN_L_ANDI, OR1K32BF_INSN_L_ORI, OR1K32BF_INSN_L_XORI
- , OR1K32BF_INSN_L_ADDI, OR1K32BF_INSN_L_ADDIC, OR1K32BF_INSN_L_MULI, OR1K32BF_INSN_L_EXTHS
- , OR1K32BF_INSN_L_EXTBS, OR1K32BF_INSN_L_EXTHZ, OR1K32BF_INSN_L_EXTBZ, OR1K32BF_INSN_L_EXTWS
- , OR1K32BF_INSN_L_EXTWZ, OR1K32BF_INSN_L_CMOV, OR1K32BF_INSN_L_SFGTS, OR1K32BF_INSN_L_SFGTSI
- , OR1K32BF_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGES, OR1K32BF_INSN_L_SFGESI
- , OR1K32BF_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFLTS, OR1K32BF_INSN_L_SFLTSI
- , OR1K32BF_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLES, OR1K32BF_INSN_L_SFLESI
- , OR1K32BF_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFEQ, OR1K32BF_INSN_L_SFEQI
- , OR1K32BF_INSN_L_SFNE, OR1K32BF_INSN_L_SFNEI, OR1K32BF_INSN_L_MAC, OR1K32BF_INSN_L_MSB
- , OR1K32BF_INSN_L_MACI, OR1K32BF_INSN_L_CUST1, OR1K32BF_INSN_L_CUST2, OR1K32BF_INSN_L_CUST3
- , OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5, OR1K32BF_INSN_L_CUST6, OR1K32BF_INSN_L_CUST7
- , OR1K32BF_INSN_L_CUST8, OR1K32BF_INSN_LF_ADD_S, OR1K32BF_INSN_LF_SUB_S, OR1K32BF_INSN_LF_MUL_S
- , OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_REM_S, OR1K32BF_INSN_LF_ITOF_S, OR1K32BF_INSN_LF_FTOI_S
- , OR1K32BF_INSN_LF_EQ_S, OR1K32BF_INSN_LF_NE_S, OR1K32BF_INSN_LF_GE_S, OR1K32BF_INSN_LF_GT_S
- , OR1K32BF_INSN_LF_LT_S, OR1K32BF_INSN_LF_LE_S, OR1K32BF_INSN_LF_MADD_S, OR1K32BF_INSN_LF_CUST1_S
- , OR1K32BF_INSN__MAX
+ , OR1K32BF_INSN_L_SH, OR1K32BF_INSN_L_SWA, OR1K32BF_INSN_L_SLL, OR1K32BF_INSN_L_SLLI
+ , OR1K32BF_INSN_L_SRL, OR1K32BF_INSN_L_SRLI, OR1K32BF_INSN_L_SRA, OR1K32BF_INSN_L_SRAI
+ , OR1K32BF_INSN_L_ROR, OR1K32BF_INSN_L_RORI, OR1K32BF_INSN_L_AND, OR1K32BF_INSN_L_OR
+ , OR1K32BF_INSN_L_XOR, OR1K32BF_INSN_L_ADD, OR1K32BF_INSN_L_SUB, OR1K32BF_INSN_L_ADDC
+ , OR1K32BF_INSN_L_MUL, OR1K32BF_INSN_L_MULU, OR1K32BF_INSN_L_DIV, OR1K32BF_INSN_L_DIVU
+ , OR1K32BF_INSN_L_FF1, OR1K32BF_INSN_L_FL1, OR1K32BF_INSN_L_ANDI, OR1K32BF_INSN_L_ORI
+ , OR1K32BF_INSN_L_XORI, OR1K32BF_INSN_L_ADDI, OR1K32BF_INSN_L_ADDIC, OR1K32BF_INSN_L_MULI
+ , OR1K32BF_INSN_L_EXTHS, OR1K32BF_INSN_L_EXTBS, OR1K32BF_INSN_L_EXTHZ, OR1K32BF_INSN_L_EXTBZ
+ , OR1K32BF_INSN_L_EXTWS, OR1K32BF_INSN_L_EXTWZ, OR1K32BF_INSN_L_CMOV, OR1K32BF_INSN_L_SFGTS
+ , OR1K32BF_INSN_L_SFGTSI, OR1K32BF_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGES
+ , OR1K32BF_INSN_L_SFGESI, OR1K32BF_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFLTS
+ , OR1K32BF_INSN_L_SFLTSI, OR1K32BF_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLES
+ , OR1K32BF_INSN_L_SFLESI, OR1K32BF_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFEQ
+ , OR1K32BF_INSN_L_SFEQI, OR1K32BF_INSN_L_SFNE, OR1K32BF_INSN_L_SFNEI, OR1K32BF_INSN_L_MAC
+ , OR1K32BF_INSN_L_MSB, OR1K32BF_INSN_L_MACI, OR1K32BF_INSN_L_CUST1, OR1K32BF_INSN_L_CUST2
+ , OR1K32BF_INSN_L_CUST3, OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5, OR1K32BF_INSN_L_CUST6
+ , OR1K32BF_INSN_L_CUST7, OR1K32BF_INSN_L_CUST8, OR1K32BF_INSN_LF_ADD_S, OR1K32BF_INSN_LF_SUB_S
+ , OR1K32BF_INSN_LF_MUL_S, OR1K32BF_INSN_LF_DIV_S, OR1K32BF_INSN_LF_REM_S, OR1K32BF_INSN_LF_ITOF_S
+ , OR1K32BF_INSN_LF_FTOI_S, OR1K32BF_INSN_LF_EQ_S, OR1K32BF_INSN_LF_NE_S, OR1K32BF_INSN_LF_GE_S
+ , OR1K32BF_INSN_LF_GT_S, OR1K32BF_INSN_LF_LT_S, OR1K32BF_INSN_LF_LE_S, OR1K32BF_INSN_LF_MADD_S
+ , OR1K32BF_INSN_LF_CUST1_S, OR1K32BF_INSN__MAX
} OR1K32BF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family or1k32bf. */
typedef enum or1k32bf_sfmt_type {
OR1K32BF_SFMT_EMPTY, OR1K32BF_SFMT_L_J, OR1K32BF_SFMT_L_JAL, OR1K32BF_SFMT_L_JR
- , OR1K32BF_SFMT_L_JALR, OR1K32BF_SFMT_L_BNF, OR1K32BF_SFMT_L_TRAP, OR1K32BF_SFMT_L_RFE
+ , OR1K32BF_SFMT_L_JALR, OR1K32BF_SFMT_L_BNF, OR1K32BF_SFMT_L_TRAP, OR1K32BF_SFMT_L_MSYNC
, OR1K32BF_SFMT_L_NOP_IMM, OR1K32BF_SFMT_L_MOVHI, OR1K32BF_SFMT_L_MACRC, OR1K32BF_SFMT_L_MFSPR
- , OR1K32BF_SFMT_L_MTSPR, OR1K32BF_SFMT_L_LWZ, OR1K32BF_SFMT_L_LWS, OR1K32BF_SFMT_L_LBZ
- , OR1K32BF_SFMT_L_LBS, OR1K32BF_SFMT_L_LHZ, OR1K32BF_SFMT_L_LHS, OR1K32BF_SFMT_L_SW
- , OR1K32BF_SFMT_L_SB, OR1K32BF_SFMT_L_SH, OR1K32BF_SFMT_L_SLL, OR1K32BF_SFMT_L_SLLI
- , OR1K32BF_SFMT_L_AND, OR1K32BF_SFMT_L_ADD, OR1K32BF_SFMT_L_ADDC, OR1K32BF_SFMT_L_DIV
- , OR1K32BF_SFMT_L_FF1, OR1K32BF_SFMT_L_XORI, OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC
- , OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV, OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI
- , OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI, OR1K32BF_SFMT_LF_ADD_S, OR1K32BF_SFMT_LF_ITOF_S
- , OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S, OR1K32BF_SFMT_LF_MADD_S
+ , OR1K32BF_SFMT_L_MTSPR, OR1K32BF_SFMT_L_LWZ, OR1K32BF_SFMT_L_LWS, OR1K32BF_SFMT_L_LWA
+ , OR1K32BF_SFMT_L_LBZ, OR1K32BF_SFMT_L_LBS, OR1K32BF_SFMT_L_LHZ, OR1K32BF_SFMT_L_LHS
+ , OR1K32BF_SFMT_L_SW, OR1K32BF_SFMT_L_SB, OR1K32BF_SFMT_L_SH, OR1K32BF_SFMT_L_SWA
+ , OR1K32BF_SFMT_L_SLL, OR1K32BF_SFMT_L_SLLI, OR1K32BF_SFMT_L_AND, OR1K32BF_SFMT_L_ADD
+ , OR1K32BF_SFMT_L_ADDC, OR1K32BF_SFMT_L_DIV, OR1K32BF_SFMT_L_FF1, OR1K32BF_SFMT_L_XORI
+ , OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC, OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV
+ , OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI, OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI
+ , OR1K32BF_SFMT_LF_ADD_S, OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S
+ , OR1K32BF_SFMT_LF_MADD_S
} OR1K32BF_SFMT_TYPE;
/* Function unit handlers (user written). */
diff --git a/sim/or1k/decode64.c b/sim/or1k/decode64.c
index 752fa13..4065010 100644
--- a/sim/or1k/decode64.c
+++ b/sim/or1k/decode64.c
@@ -54,7 +54,10 @@ static const struct insn_sem or1k64bf_insn_sem[] =
{ OR1K_INSN_L_BF, OR1K64BF_INSN_L_BF, OR1K64BF_SFMT_L_BNF },
{ OR1K_INSN_L_TRAP, OR1K64BF_INSN_L_TRAP, OR1K64BF_SFMT_L_TRAP },
{ OR1K_INSN_L_SYS, OR1K64BF_INSN_L_SYS, OR1K64BF_SFMT_L_TRAP },
- { OR1K_INSN_L_RFE, OR1K64BF_INSN_L_RFE, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_L_MSYNC, OR1K64BF_INSN_L_MSYNC, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_PSYNC, OR1K64BF_INSN_L_PSYNC, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CSYNC, OR1K64BF_INSN_L_CSYNC, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_RFE, OR1K64BF_INSN_L_RFE, OR1K64BF_SFMT_L_MSYNC },
{ OR1K_INSN_L_NOP_IMM, OR1K64BF_INSN_L_NOP_IMM, OR1K64BF_SFMT_L_NOP_IMM },
{ OR1K_INSN_L_MOVHI, OR1K64BF_INSN_L_MOVHI, OR1K64BF_SFMT_L_MOVHI },
{ OR1K_INSN_L_MACRC, OR1K64BF_INSN_L_MACRC, OR1K64BF_SFMT_L_MACRC },
@@ -62,6 +65,7 @@ static const struct insn_sem or1k64bf_insn_sem[] =
{ OR1K_INSN_L_MTSPR, OR1K64BF_INSN_L_MTSPR, OR1K64BF_SFMT_L_MTSPR },
{ OR1K_INSN_L_LWZ, OR1K64BF_INSN_L_LWZ, OR1K64BF_SFMT_L_LWZ },
{ OR1K_INSN_L_LWS, OR1K64BF_INSN_L_LWS, OR1K64BF_SFMT_L_LWS },
+ { OR1K_INSN_L_LWA, OR1K64BF_INSN_L_LWA, OR1K64BF_SFMT_L_LWA },
{ OR1K_INSN_L_LBZ, OR1K64BF_INSN_L_LBZ, OR1K64BF_SFMT_L_LBZ },
{ OR1K_INSN_L_LBS, OR1K64BF_INSN_L_LBS, OR1K64BF_SFMT_L_LBS },
{ OR1K_INSN_L_LHZ, OR1K64BF_INSN_L_LHZ, OR1K64BF_SFMT_L_LHZ },
@@ -69,6 +73,7 @@ static const struct insn_sem or1k64bf_insn_sem[] =
{ OR1K_INSN_L_SW, OR1K64BF_INSN_L_SW, OR1K64BF_SFMT_L_SW },
{ OR1K_INSN_L_SB, OR1K64BF_INSN_L_SB, OR1K64BF_SFMT_L_SB },
{ OR1K_INSN_L_SH, OR1K64BF_INSN_L_SH, OR1K64BF_SFMT_L_SH },
+ { OR1K_INSN_L_SWA, OR1K64BF_INSN_L_SWA, OR1K64BF_SFMT_L_SWA },
{ OR1K_INSN_L_SLL, OR1K64BF_INSN_L_SLL, OR1K64BF_SFMT_L_SLL },
{ OR1K_INSN_L_SLLI, OR1K64BF_INSN_L_SLLI, OR1K64BF_SFMT_L_SLLI },
{ OR1K_INSN_L_SRL, OR1K64BF_INSN_L_SRL, OR1K64BF_SFMT_L_SLL },
@@ -125,14 +130,14 @@ static const struct insn_sem or1k64bf_insn_sem[] =
{ OR1K_INSN_L_MAC, OR1K64BF_INSN_L_MAC, OR1K64BF_SFMT_L_MAC },
{ OR1K_INSN_L_MSB, OR1K64BF_INSN_L_MSB, OR1K64BF_SFMT_L_MAC },
{ OR1K_INSN_L_MACI, OR1K64BF_INSN_L_MACI, OR1K64BF_SFMT_L_MACI },
- { OR1K_INSN_L_CUST1, OR1K64BF_INSN_L_CUST1, OR1K64BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST2, OR1K64BF_INSN_L_CUST2, OR1K64BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST3, OR1K64BF_INSN_L_CUST3, OR1K64BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST4, OR1K64BF_INSN_L_CUST4, OR1K64BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST5, OR1K64BF_INSN_L_CUST5, OR1K64BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST6, OR1K64BF_INSN_L_CUST6, OR1K64BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST7, OR1K64BF_INSN_L_CUST7, OR1K64BF_SFMT_L_RFE },
- { OR1K_INSN_L_CUST8, OR1K64BF_INSN_L_CUST8, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_L_CUST1, OR1K64BF_INSN_L_CUST1, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST2, OR1K64BF_INSN_L_CUST2, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST3, OR1K64BF_INSN_L_CUST3, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST4, OR1K64BF_INSN_L_CUST4, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST5, OR1K64BF_INSN_L_CUST5, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST6, OR1K64BF_INSN_L_CUST6, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST7, OR1K64BF_INSN_L_CUST7, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_L_CUST8, OR1K64BF_INSN_L_CUST8, OR1K64BF_SFMT_L_MSYNC },
{ OR1K_INSN_LF_ADD_S, OR1K64BF_INSN_LF_ADD_S, OR1K64BF_SFMT_LF_ADD_S },
{ OR1K_INSN_LF_ADD_D, OR1K64BF_INSN_LF_ADD_D, OR1K64BF_SFMT_LF_ADD_D },
{ OR1K_INSN_LF_SUB_S, OR1K64BF_INSN_LF_SUB_S, OR1K64BF_SFMT_LF_ADD_S },
@@ -161,8 +166,8 @@ static const struct insn_sem or1k64bf_insn_sem[] =
{ OR1K_INSN_LF_LE_D, OR1K64BF_INSN_LF_LE_D, OR1K64BF_SFMT_LF_EQ_D },
{ OR1K_INSN_LF_MADD_S, OR1K64BF_INSN_LF_MADD_S, OR1K64BF_SFMT_LF_MADD_S },
{ OR1K_INSN_LF_MADD_D, OR1K64BF_INSN_LF_MADD_D, OR1K64BF_SFMT_LF_MADD_D },
- { OR1K_INSN_LF_CUST1_S, OR1K64BF_INSN_LF_CUST1_S, OR1K64BF_SFMT_L_RFE },
- { OR1K_INSN_LF_CUST1_D, OR1K64BF_INSN_LF_CUST1_D, OR1K64BF_SFMT_L_RFE },
+ { OR1K_INSN_LF_CUST1_S, OR1K64BF_INSN_LF_CUST1_S, OR1K64BF_SFMT_L_MSYNC },
+ { OR1K_INSN_LF_CUST1_D, OR1K64BF_INSN_LF_CUST1_D, OR1K64BF_SFMT_L_MSYNC },
};
static const struct insn_sem or1k64bf_insn_sem_invalid =
@@ -456,7 +461,34 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
if ((entire_insn & 0xfc1f0000) == 0x18000000)
{ itype = OR1K64BF_INSN_L_MOVHI; goto extract_sfmt_l_movhi; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
- case 256 : /* fall through */
+ case 256 :
+ {
+ unsigned int val = (((insn >> 23) & (7 << 0)));
+ switch (val)
+ {
+ case 0 :
+ if ((entire_insn & 0xffff0000) == 0x20000000)
+ { itype = OR1K64BF_INSN_L_SYS; goto extract_sfmt_l_trap; }
+ itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 2 :
+ if ((entire_insn & 0xffff0000) == 0x21000000)
+ { itype = OR1K64BF_INSN_L_TRAP; goto extract_sfmt_l_trap; }
+ itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 4 :
+ if ((entire_insn & 0xffffffff) == 0x22000000)
+ { itype = OR1K64BF_INSN_L_MSYNC; goto extract_sfmt_l_msync; }
+ itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 5 :
+ if ((entire_insn & 0xffffffff) == 0x22800000)
+ { itype = OR1K64BF_INSN_L_PSYNC; goto extract_sfmt_l_msync; }
+ itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 6 :
+ if ((entire_insn & 0xffffffff) == 0x23000000)
+ { itype = OR1K64BF_INSN_L_CSYNC; goto extract_sfmt_l_msync; }
+ itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ default : itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ }
+ }
case 257 : /* fall through */
case 258 : /* fall through */
case 259 : /* fall through */
@@ -505,7 +537,7 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
}
case 288 :
if ((entire_insn & 0xffffffff) == 0x24000000)
- { itype = OR1K64BF_INSN_L_RFE; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_L_RFE; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 544 :
if ((entire_insn & 0xffff07ff) == 0x44000000)
@@ -550,21 +582,53 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
if ((entire_insn & 0xffe00000) == 0x4c000000)
{ itype = OR1K64BF_INSN_L_MACI; goto extract_sfmt_l_maci; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 864 : /* fall through */
+ case 865 : /* fall through */
+ case 866 : /* fall through */
+ case 867 : /* fall through */
+ case 868 : /* fall through */
+ case 869 : /* fall through */
+ case 870 : /* fall through */
+ case 871 : /* fall through */
+ case 872 : /* fall through */
+ case 873 : /* fall through */
+ case 874 : /* fall through */
+ case 875 : /* fall through */
+ case 876 : /* fall through */
+ case 877 : /* fall through */
+ case 878 : /* fall through */
+ case 879 : /* fall through */
+ case 880 : /* fall through */
+ case 881 : /* fall through */
+ case 882 : /* fall through */
+ case 883 : /* fall through */
+ case 884 : /* fall through */
+ case 885 : /* fall through */
+ case 886 : /* fall through */
+ case 887 : /* fall through */
+ case 888 : /* fall through */
+ case 889 : /* fall through */
+ case 890 : /* fall through */
+ case 891 : /* fall through */
+ case 892 : /* fall through */
+ case 893 : /* fall through */
+ case 894 : /* fall through */
+ case 895 : itype = OR1K64BF_INSN_L_LWA; goto extract_sfmt_l_lwa;
case 896 :
if ((entire_insn & 0xffffffff) == 0x70000000)
- { itype = OR1K64BF_INSN_L_CUST1; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_L_CUST1; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 928 :
if ((entire_insn & 0xffffffff) == 0x74000000)
- { itype = OR1K64BF_INSN_L_CUST2; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_L_CUST2; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 960 :
if ((entire_insn & 0xffffffff) == 0x78000000)
- { itype = OR1K64BF_INSN_L_CUST3; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_L_CUST3; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 992 :
if ((entire_insn & 0xffffffff) == 0x7c000000)
- { itype = OR1K64BF_INSN_L_CUST4; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_L_CUST4; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1056 : /* fall through */
case 1057 : /* fall through */
@@ -1167,7 +1231,7 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 7 :
if ((entire_insn & 0xffe007ff) == 0xc80000e0)
- { itype = OR1K64BF_INSN_LF_CUST1_D; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_LF_CUST1_D; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -1235,7 +1299,7 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 3 :
if ((entire_insn & 0xffe007ff) == 0xc80000d0)
- { itype = OR1K64BF_INSN_LF_CUST1_S; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_LF_CUST1_S; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -1292,6 +1356,38 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
if ((entire_insn & 0xffe007ff) == 0xc800001d)
{ itype = OR1K64BF_INSN_LF_LE_D; goto extract_sfmt_lf_eq_d; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
+ case 1632 : /* fall through */
+ case 1633 : /* fall through */
+ case 1634 : /* fall through */
+ case 1635 : /* fall through */
+ case 1636 : /* fall through */
+ case 1637 : /* fall through */
+ case 1638 : /* fall through */
+ case 1639 : /* fall through */
+ case 1640 : /* fall through */
+ case 1641 : /* fall through */
+ case 1642 : /* fall through */
+ case 1643 : /* fall through */
+ case 1644 : /* fall through */
+ case 1645 : /* fall through */
+ case 1646 : /* fall through */
+ case 1647 : /* fall through */
+ case 1648 : /* fall through */
+ case 1649 : /* fall through */
+ case 1650 : /* fall through */
+ case 1651 : /* fall through */
+ case 1652 : /* fall through */
+ case 1653 : /* fall through */
+ case 1654 : /* fall through */
+ case 1655 : /* fall through */
+ case 1656 : /* fall through */
+ case 1657 : /* fall through */
+ case 1658 : /* fall through */
+ case 1659 : /* fall through */
+ case 1660 : /* fall through */
+ case 1661 : /* fall through */
+ case 1662 : /* fall through */
+ case 1663 : itype = OR1K64BF_INSN_L_SWA; goto extract_sfmt_l_swa;
case 1696 : /* fall through */
case 1697 : /* fall through */
case 1698 : /* fall through */
@@ -1562,19 +1658,19 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
}
case 1920 :
if ((entire_insn & 0xffffffff) == 0xf0000000)
- { itype = OR1K64BF_INSN_L_CUST5; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_L_CUST5; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1952 :
if ((entire_insn & 0xffffffff) == 0xf4000000)
- { itype = OR1K64BF_INSN_L_CUST6; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_L_CUST6; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 1984 :
if ((entire_insn & 0xffffffff) == 0xf8000000)
- { itype = OR1K64BF_INSN_L_CUST7; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_L_CUST7; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
case 2016 :
if ((entire_insn & 0xffffffff) == 0xfc000000)
- { itype = OR1K64BF_INSN_L_CUST8; goto extract_sfmt_l_rfe; }
+ { itype = OR1K64BF_INSN_L_CUST8; goto extract_sfmt_l_msync; }
itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
default : itype = OR1K64BF_INSN_X_INVALID; goto extract_sfmt_empty;
}
@@ -1694,14 +1790,14 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
- extract_sfmt_l_rfe:
+ extract_sfmt_l_msync:
{
const IDESC *idesc = &or1k64bf_insn_data[itype];
#define FLD(f) abuf->fields.sfmt_empty.f
/* Record the fields for the semantic handler. */
- TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_rfe", (char *) 0));
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_msync", (char *) 0));
#undef FLD
return idesc;
@@ -1857,6 +1953,29 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
+ extract_sfmt_l_lwa:
+ {
+ const IDESC *idesc = &or1k64bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ UINT f_r1;
+ UINT f_r2;
+ INT f_simm16;
+
+ f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_simm16) = f_simm16;
+ FLD (f_r1) = f_r1;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_lwa", "f_r2 0x%x", 'x', f_r2, "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
extract_sfmt_l_lbz:
{
const IDESC *idesc = &or1k64bf_insn_data[itype];
@@ -2030,6 +2149,33 @@ or1k64bf_decode (SIM_CPU *current_cpu, IADDR pc,
return idesc;
}
+ extract_sfmt_l_swa:
+ {
+ const IDESC *idesc = &or1k64bf_insn_data[itype];
+ CGEN_INSN_WORD insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ UINT f_imm16_25_5;
+ UINT f_r2;
+ UINT f_r3;
+ UINT f_imm16_10_11;
+ INT f_simm16_split;
+
+ f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5);
+ f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5);
+ f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5);
+ f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11);
+ f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_r2) = f_r2;
+ FLD (f_r3) = f_r3;
+ FLD (f_simm16_split) = f_simm16_split;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_l_swa", "f_r2 0x%x", 'x', f_r2, "f_r3 0x%x", 'x', f_r3, "f_simm16_split 0x%x", 'x', f_simm16_split, (char *) 0));
+
+#undef FLD
+ return idesc;
+ }
+
extract_sfmt_l_sll:
{
const IDESC *idesc = &or1k64bf_insn_data[itype];
diff --git a/sim/or1k/decode64.h b/sim/or1k/decode64.h
index db5f56f..b43e6ee 100644
--- a/sim/or1k/decode64.h
+++ b/sim/or1k/decode64.h
@@ -37,50 +37,53 @@ typedef enum or1k64bf_insn_type {
OR1K64BF_INSN_X_INVALID, OR1K64BF_INSN_X_AFTER, OR1K64BF_INSN_X_BEFORE, OR1K64BF_INSN_X_CTI_CHAIN
, OR1K64BF_INSN_X_CHAIN, OR1K64BF_INSN_X_BEGIN, OR1K64BF_INSN_L_J, OR1K64BF_INSN_L_JAL
, OR1K64BF_INSN_L_JR, OR1K64BF_INSN_L_JALR, OR1K64BF_INSN_L_BNF, OR1K64BF_INSN_L_BF
- , OR1K64BF_INSN_L_TRAP, OR1K64BF_INSN_L_SYS, OR1K64BF_INSN_L_RFE, OR1K64BF_INSN_L_NOP_IMM
- , OR1K64BF_INSN_L_MOVHI, OR1K64BF_INSN_L_MACRC, OR1K64BF_INSN_L_MFSPR, OR1K64BF_INSN_L_MTSPR
- , OR1K64BF_INSN_L_LWZ, OR1K64BF_INSN_L_LWS, OR1K64BF_INSN_L_LBZ, OR1K64BF_INSN_L_LBS
+ , OR1K64BF_INSN_L_TRAP, OR1K64BF_INSN_L_SYS, OR1K64BF_INSN_L_MSYNC, OR1K64BF_INSN_L_PSYNC
+ , OR1K64BF_INSN_L_CSYNC, OR1K64BF_INSN_L_RFE, OR1K64BF_INSN_L_NOP_IMM, OR1K64BF_INSN_L_MOVHI
+ , OR1K64BF_INSN_L_MACRC, OR1K64BF_INSN_L_MFSPR, OR1K64BF_INSN_L_MTSPR, OR1K64BF_INSN_L_LWZ
+ , OR1K64BF_INSN_L_LWS, OR1K64BF_INSN_L_LWA, OR1K64BF_INSN_L_LBZ, OR1K64BF_INSN_L_LBS
, OR1K64BF_INSN_L_LHZ, OR1K64BF_INSN_L_LHS, OR1K64BF_INSN_L_SW, OR1K64BF_INSN_L_SB
- , OR1K64BF_INSN_L_SH, OR1K64BF_INSN_L_SLL, OR1K64BF_INSN_L_SLLI, OR1K64BF_INSN_L_SRL
- , OR1K64BF_INSN_L_SRLI, OR1K64BF_INSN_L_SRA, OR1K64BF_INSN_L_SRAI, OR1K64BF_INSN_L_ROR
- , OR1K64BF_INSN_L_RORI, OR1K64BF_INSN_L_AND, OR1K64BF_INSN_L_OR, OR1K64BF_INSN_L_XOR
- , OR1K64BF_INSN_L_ADD, OR1K64BF_INSN_L_SUB, OR1K64BF_INSN_L_ADDC, OR1K64BF_INSN_L_MUL
- , OR1K64BF_INSN_L_MULU, OR1K64BF_INSN_L_DIV, OR1K64BF_INSN_L_DIVU, OR1K64BF_INSN_L_FF1
- , OR1K64BF_INSN_L_FL1, OR1K64BF_INSN_L_ANDI, OR1K64BF_INSN_L_ORI, OR1K64BF_INSN_L_XORI
- , OR1K64BF_INSN_L_ADDI, OR1K64BF_INSN_L_ADDIC, OR1K64BF_INSN_L_MULI, OR1K64BF_INSN_L_EXTHS
- , OR1K64BF_INSN_L_EXTBS, OR1K64BF_INSN_L_EXTHZ, OR1K64BF_INSN_L_EXTBZ, OR1K64BF_INSN_L_EXTWS
- , OR1K64BF_INSN_L_EXTWZ, OR1K64BF_INSN_L_CMOV, OR1K64BF_INSN_L_SFGTS, OR1K64BF_INSN_L_SFGTSI
- , OR1K64BF_INSN_L_SFGTU, OR1K64BF_INSN_L_SFGTUI, OR1K64BF_INSN_L_SFGES, OR1K64BF_INSN_L_SFGESI
- , OR1K64BF_INSN_L_SFGEU, OR1K64BF_INSN_L_SFGEUI, OR1K64BF_INSN_L_SFLTS, OR1K64BF_INSN_L_SFLTSI
- , OR1K64BF_INSN_L_SFLTU, OR1K64BF_INSN_L_SFLTUI, OR1K64BF_INSN_L_SFLES, OR1K64BF_INSN_L_SFLESI
- , OR1K64BF_INSN_L_SFLEU, OR1K64BF_INSN_L_SFLEUI, OR1K64BF_INSN_L_SFEQ, OR1K64BF_INSN_L_SFEQI
- , OR1K64BF_INSN_L_SFNE, OR1K64BF_INSN_L_SFNEI, OR1K64BF_INSN_L_MAC, OR1K64BF_INSN_L_MSB
- , OR1K64BF_INSN_L_MACI, OR1K64BF_INSN_L_CUST1, OR1K64BF_INSN_L_CUST2, OR1K64BF_INSN_L_CUST3
- , OR1K64BF_INSN_L_CUST4, OR1K64BF_INSN_L_CUST5, OR1K64BF_INSN_L_CUST6, OR1K64BF_INSN_L_CUST7
- , OR1K64BF_INSN_L_CUST8, OR1K64BF_INSN_LF_ADD_S, OR1K64BF_INSN_LF_ADD_D, OR1K64BF_INSN_LF_SUB_S
- , OR1K64BF_INSN_LF_SUB_D, OR1K64BF_INSN_LF_MUL_S, OR1K64BF_INSN_LF_MUL_D, OR1K64BF_INSN_LF_DIV_S
- , OR1K64BF_INSN_LF_DIV_D, OR1K64BF_INSN_LF_REM_S, OR1K64BF_INSN_LF_REM_D, OR1K64BF_INSN_LF_ITOF_S
- , OR1K64BF_INSN_LF_ITOF_D, OR1K64BF_INSN_LF_FTOI_S, OR1K64BF_INSN_LF_FTOI_D, OR1K64BF_INSN_LF_EQ_S
- , OR1K64BF_INSN_LF_EQ_D, OR1K64BF_INSN_LF_NE_S, OR1K64BF_INSN_LF_NE_D, OR1K64BF_INSN_LF_GE_S
- , OR1K64BF_INSN_LF_GE_D, OR1K64BF_INSN_LF_GT_S, OR1K64BF_INSN_LF_GT_D, OR1K64BF_INSN_LF_LT_S
- , OR1K64BF_INSN_LF_LT_D, OR1K64BF_INSN_LF_LE_S, OR1K64BF_INSN_LF_LE_D, OR1K64BF_INSN_LF_MADD_S
- , OR1K64BF_INSN_LF_MADD_D, OR1K64BF_INSN_LF_CUST1_S, OR1K64BF_INSN_LF_CUST1_D, OR1K64BF_INSN__MAX
+ , OR1K64BF_INSN_L_SH, OR1K64BF_INSN_L_SWA, OR1K64BF_INSN_L_SLL, OR1K64BF_INSN_L_SLLI
+ , OR1K64BF_INSN_L_SRL, OR1K64BF_INSN_L_SRLI, OR1K64BF_INSN_L_SRA, OR1K64BF_INSN_L_SRAI
+ , OR1K64BF_INSN_L_ROR, OR1K64BF_INSN_L_RORI, OR1K64BF_INSN_L_AND, OR1K64BF_INSN_L_OR
+ , OR1K64BF_INSN_L_XOR, OR1K64BF_INSN_L_ADD, OR1K64BF_INSN_L_SUB, OR1K64BF_INSN_L_ADDC
+ , OR1K64BF_INSN_L_MUL, OR1K64BF_INSN_L_MULU, OR1K64BF_INSN_L_DIV, OR1K64BF_INSN_L_DIVU
+ , OR1K64BF_INSN_L_FF1, OR1K64BF_INSN_L_FL1, OR1K64BF_INSN_L_ANDI, OR1K64BF_INSN_L_ORI
+ , OR1K64BF_INSN_L_XORI, OR1K64BF_INSN_L_ADDI, OR1K64BF_INSN_L_ADDIC, OR1K64BF_INSN_L_MULI
+ , OR1K64BF_INSN_L_EXTHS, OR1K64BF_INSN_L_EXTBS, OR1K64BF_INSN_L_EXTHZ, OR1K64BF_INSN_L_EXTBZ
+ , OR1K64BF_INSN_L_EXTWS, OR1K64BF_INSN_L_EXTWZ, OR1K64BF_INSN_L_CMOV, OR1K64BF_INSN_L_SFGTS
+ , OR1K64BF_INSN_L_SFGTSI, OR1K64BF_INSN_L_SFGTU, OR1K64BF_INSN_L_SFGTUI, OR1K64BF_INSN_L_SFGES
+ , OR1K64BF_INSN_L_SFGESI, OR1K64BF_INSN_L_SFGEU, OR1K64BF_INSN_L_SFGEUI, OR1K64BF_INSN_L_SFLTS
+ , OR1K64BF_INSN_L_SFLTSI, OR1K64BF_INSN_L_SFLTU, OR1K64BF_INSN_L_SFLTUI, OR1K64BF_INSN_L_SFLES
+ , OR1K64BF_INSN_L_SFLESI, OR1K64BF_INSN_L_SFLEU, OR1K64BF_INSN_L_SFLEUI, OR1K64BF_INSN_L_SFEQ
+ , OR1K64BF_INSN_L_SFEQI, OR1K64BF_INSN_L_SFNE, OR1K64BF_INSN_L_SFNEI, OR1K64BF_INSN_L_MAC
+ , OR1K64BF_INSN_L_MSB, OR1K64BF_INSN_L_MACI, OR1K64BF_INSN_L_CUST1, OR1K64BF_INSN_L_CUST2
+ , OR1K64BF_INSN_L_CUST3, OR1K64BF_INSN_L_CUST4, OR1K64BF_INSN_L_CUST5, OR1K64BF_INSN_L_CUST6
+ , OR1K64BF_INSN_L_CUST7, OR1K64BF_INSN_L_CUST8, OR1K64BF_INSN_LF_ADD_S, OR1K64BF_INSN_LF_ADD_D
+ , OR1K64BF_INSN_LF_SUB_S, OR1K64BF_INSN_LF_SUB_D, OR1K64BF_INSN_LF_MUL_S, OR1K64BF_INSN_LF_MUL_D
+ , OR1K64BF_INSN_LF_DIV_S, OR1K64BF_INSN_LF_DIV_D, OR1K64BF_INSN_LF_REM_S, OR1K64BF_INSN_LF_REM_D
+ , OR1K64BF_INSN_LF_ITOF_S, OR1K64BF_INSN_LF_ITOF_D, OR1K64BF_INSN_LF_FTOI_S, OR1K64BF_INSN_LF_FTOI_D
+ , OR1K64BF_INSN_LF_EQ_S, OR1K64BF_INSN_LF_EQ_D, OR1K64BF_INSN_LF_NE_S, OR1K64BF_INSN_LF_NE_D
+ , OR1K64BF_INSN_LF_GE_S, OR1K64BF_INSN_LF_GE_D, OR1K64BF_INSN_LF_GT_S, OR1K64BF_INSN_LF_GT_D
+ , OR1K64BF_INSN_LF_LT_S, OR1K64BF_INSN_LF_LT_D, OR1K64BF_INSN_LF_LE_S, OR1K64BF_INSN_LF_LE_D
+ , OR1K64BF_INSN_LF_MADD_S, OR1K64BF_INSN_LF_MADD_D, OR1K64BF_INSN_LF_CUST1_S, OR1K64BF_INSN_LF_CUST1_D
+ , OR1K64BF_INSN__MAX
} OR1K64BF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family or1k64bf. */
typedef enum or1k64bf_sfmt_type {
OR1K64BF_SFMT_EMPTY, OR1K64BF_SFMT_L_J, OR1K64BF_SFMT_L_JAL, OR1K64BF_SFMT_L_JR
- , OR1K64BF_SFMT_L_JALR, OR1K64BF_SFMT_L_BNF, OR1K64BF_SFMT_L_TRAP, OR1K64BF_SFMT_L_RFE
+ , OR1K64BF_SFMT_L_JALR, OR1K64BF_SFMT_L_BNF, OR1K64BF_SFMT_L_TRAP, OR1K64BF_SFMT_L_MSYNC
, OR1K64BF_SFMT_L_NOP_IMM, OR1K64BF_SFMT_L_MOVHI, OR1K64BF_SFMT_L_MACRC, OR1K64BF_SFMT_L_MFSPR
- , OR1K64BF_SFMT_L_MTSPR, OR1K64BF_SFMT_L_LWZ, OR1K64BF_SFMT_L_LWS, OR1K64BF_SFMT_L_LBZ
- , OR1K64BF_SFMT_L_LBS, OR1K64BF_SFMT_L_LHZ, OR1K64BF_SFMT_L_LHS, OR1K64BF_SFMT_L_SW
- , OR1K64BF_SFMT_L_SB, OR1K64BF_SFMT_L_SH, OR1K64BF_SFMT_L_SLL, OR1K64BF_SFMT_L_SLLI
- , OR1K64BF_SFMT_L_AND, OR1K64BF_SFMT_L_ADD, OR1K64BF_SFMT_L_ADDC, OR1K64BF_SFMT_L_DIV
- , OR1K64BF_SFMT_L_FF1, OR1K64BF_SFMT_L_XORI, OR1K64BF_SFMT_L_ADDI, OR1K64BF_SFMT_L_ADDIC
- , OR1K64BF_SFMT_L_EXTHS, OR1K64BF_SFMT_L_CMOV, OR1K64BF_SFMT_L_SFGTS, OR1K64BF_SFMT_L_SFGTSI
- , OR1K64BF_SFMT_L_MAC, OR1K64BF_SFMT_L_MACI, OR1K64BF_SFMT_LF_ADD_S, OR1K64BF_SFMT_LF_ADD_D
- , OR1K64BF_SFMT_LF_ITOF_S, OR1K64BF_SFMT_LF_ITOF_D, OR1K64BF_SFMT_LF_FTOI_S, OR1K64BF_SFMT_LF_FTOI_D
- , OR1K64BF_SFMT_LF_EQ_S, OR1K64BF_SFMT_LF_EQ_D, OR1K64BF_SFMT_LF_MADD_S, OR1K64BF_SFMT_LF_MADD_D
+ , OR1K64BF_SFMT_L_MTSPR, OR1K64BF_SFMT_L_LWZ, OR1K64BF_SFMT_L_LWS, OR1K64BF_SFMT_L_LWA
+ , OR1K64BF_SFMT_L_LBZ, OR1K64BF_SFMT_L_LBS, OR1K64BF_SFMT_L_LHZ, OR1K64BF_SFMT_L_LHS
+ , OR1K64BF_SFMT_L_SW, OR1K64BF_SFMT_L_SB, OR1K64BF_SFMT_L_SH, OR1K64BF_SFMT_L_SWA
+ , OR1K64BF_SFMT_L_SLL, OR1K64BF_SFMT_L_SLLI, OR1K64BF_SFMT_L_AND, OR1K64BF_SFMT_L_ADD
+ , OR1K64BF_SFMT_L_ADDC, OR1K64BF_SFMT_L_DIV, OR1K64BF_SFMT_L_FF1, OR1K64BF_SFMT_L_XORI
+ , OR1K64BF_SFMT_L_ADDI, OR1K64BF_SFMT_L_ADDIC, OR1K64BF_SFMT_L_EXTHS, OR1K64BF_SFMT_L_CMOV
+ , OR1K64BF_SFMT_L_SFGTS, OR1K64BF_SFMT_L_SFGTSI, OR1K64BF_SFMT_L_MAC, OR1K64BF_SFMT_L_MACI
+ , OR1K64BF_SFMT_LF_ADD_S, OR1K64BF_SFMT_LF_ADD_D, OR1K64BF_SFMT_LF_ITOF_S, OR1K64BF_SFMT_LF_ITOF_D
+ , OR1K64BF_SFMT_LF_FTOI_S, OR1K64BF_SFMT_LF_FTOI_D, OR1K64BF_SFMT_LF_EQ_S, OR1K64BF_SFMT_LF_EQ_D
+ , OR1K64BF_SFMT_LF_MADD_S, OR1K64BF_SFMT_LF_MADD_D
} OR1K64BF_SFMT_TYPE;
/* Function unit handlers (user written). */
diff --git a/sim/or1k/model32.c b/sim/or1k/model32.c
index 72c0d61..ec33b24 100644
--- a/sim/or1k/model32.c
+++ b/sim/or1k/model32.c
@@ -163,6 +163,54 @@ model_or1200_l_sys (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_or1200_l_msync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_psync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200_l_csync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_or1200_l_rfe (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
@@ -291,6 +339,22 @@ model_or1200_l_lws (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_or1200_l_lwa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_or1200_l_lbz (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
@@ -403,6 +467,22 @@ model_or1200_l_sh (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_or1200_l_swa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_or1200_l_sll (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
@@ -1795,6 +1875,54 @@ model_or1200nd_l_sys (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_or1200nd_l_msync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_psync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_or1200nd_l_csync (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_or1200nd_l_rfe (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_empty.f
@@ -1923,6 +2051,22 @@ model_or1200nd_l_lws (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_or1200nd_l_lwa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_or1200nd_l_lbz (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_lwz.f
@@ -2035,6 +2179,22 @@ model_or1200nd_l_sh (SIM_CPU *current_cpu, void *sem_arg)
}
static int
+model_or1200nd_l_swa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += or1k32bf_model_or1200nd_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_or1200nd_l_sll (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_l_sll.f
@@ -3318,6 +3478,9 @@ static const INSN_TIMING or1200_timing[] = {
{ OR1K32BF_INSN_L_BF, model_or1200_l_bf, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_TRAP, model_or1200_l_trap, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SYS, model_or1200_l_sys, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MSYNC, model_or1200_l_msync, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_PSYNC, model_or1200_l_psync, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CSYNC, model_or1200_l_csync, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_RFE, model_or1200_l_rfe, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_NOP_IMM, model_or1200_l_nop_imm, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_MOVHI, model_or1200_l_movhi, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
@@ -3326,6 +3489,7 @@ static const INSN_TIMING or1200_timing[] = {
{ OR1K32BF_INSN_L_MTSPR, model_or1200_l_mtspr, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_LWZ, model_or1200_l_lwz, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_LWS, model_or1200_l_lws, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LWA, model_or1200_l_lwa, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_LBZ, model_or1200_l_lbz, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_LBS, model_or1200_l_lbs, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_LHZ, model_or1200_l_lhz, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
@@ -3333,6 +3497,7 @@ static const INSN_TIMING or1200_timing[] = {
{ OR1K32BF_INSN_L_SW, model_or1200_l_sw, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SB, model_or1200_l_sb, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SH, model_or1200_l_sh, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SWA, model_or1200_l_swa, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SLL, model_or1200_l_sll, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SLLI, model_or1200_l_slli, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SRL, model_or1200_l_srl, { { (int) UNIT_OR1200_U_EXEC, 1, 1 } } },
@@ -3431,6 +3596,9 @@ static const INSN_TIMING or1200nd_timing[] = {
{ OR1K32BF_INSN_L_BF, model_or1200nd_l_bf, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_TRAP, model_or1200nd_l_trap, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SYS, model_or1200nd_l_sys, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_MSYNC, model_or1200nd_l_msync, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_PSYNC, model_or1200nd_l_psync, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_CSYNC, model_or1200nd_l_csync, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_RFE, model_or1200nd_l_rfe, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_NOP_IMM, model_or1200nd_l_nop_imm, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_MOVHI, model_or1200nd_l_movhi, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
@@ -3439,6 +3607,7 @@ static const INSN_TIMING or1200nd_timing[] = {
{ OR1K32BF_INSN_L_MTSPR, model_or1200nd_l_mtspr, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_LWZ, model_or1200nd_l_lwz, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_LWS, model_or1200nd_l_lws, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_LWA, model_or1200nd_l_lwa, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_LBZ, model_or1200nd_l_lbz, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_LBS, model_or1200nd_l_lbs, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_LHZ, model_or1200nd_l_lhz, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
@@ -3446,6 +3615,7 @@ static const INSN_TIMING or1200nd_timing[] = {
{ OR1K32BF_INSN_L_SW, model_or1200nd_l_sw, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SB, model_or1200nd_l_sb, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SH, model_or1200nd_l_sh, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
+ { OR1K32BF_INSN_L_SWA, model_or1200nd_l_swa, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SLL, model_or1200nd_l_sll, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SLLI, model_or1200nd_l_slli, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
{ OR1K32BF_INSN_L_SRL, model_or1200nd_l_srl, { { (int) UNIT_OR1200ND_U_EXEC, 1, 1 } } },
@@ -3547,13 +3717,13 @@ or1200nd_model_init (SIM_CPU *cpu)
#define TIMING_DATA(td) 0
#endif
-static const MODEL or32_models[] =
+static const SIM_MODEL or32_models[] =
{
{ "or1200", & or32_mach, MODEL_OR1200, TIMING_DATA (& or1200_timing[0]), or1200_model_init },
{ 0 }
};
-static const MODEL or32nd_models[] =
+static const SIM_MODEL or32nd_models[] =
{
{ "or1200nd", & or32nd_mach, MODEL_OR1200ND, TIMING_DATA (& or1200nd_timing[0]), or1200nd_model_init },
{ 0 }
@@ -3561,7 +3731,7 @@ static const MODEL or32nd_models[] =
/* The properties of this cpu's implementation. */
-static const MACH_IMP_PROPERTIES or1k32bf_imp_properties =
+static const SIM_MACH_IMP_PROPERTIES or1k32bf_imp_properties =
{
sizeof (SIM_CPU),
#if WITH_SCACHE
@@ -3603,7 +3773,7 @@ or32_init_cpu (SIM_CPU *cpu)
#endif
}
-const MACH or32_mach =
+const SIM_MACH or32_mach =
{
"or32", "or1k", MACH_OR32,
32, 32, & or32_models[0], & or1k32bf_imp_properties,
@@ -3629,7 +3799,7 @@ or32nd_init_cpu (SIM_CPU *cpu)
#endif
}
-const MACH or32nd_mach =
+const SIM_MACH or32nd_mach =
{
"or32nd", "or1knd", MACH_OR32ND,
32, 32, & or32nd_models[0], & or1k32bf_imp_properties,
diff --git a/sim/or1k/model64.c b/sim/or1k/model64.c
index 4fa3399..93107d2 100644
--- a/sim/or1k/model64.c
+++ b/sim/or1k/model64.c
@@ -45,19 +45,19 @@ This file is part of the GNU simulators.
#define TIMING_DATA(td) 0
#endif
-static const MODEL or64_models[] =
+static const SIM_MODEL or64_models[] =
{
{ 0 }
};
-static const MODEL or64nd_models[] =
+static const SIM_MODEL or64nd_models[] =
{
{ 0 }
};
/* The properties of this cpu's implementation. */
-static const MACH_IMP_PROPERTIES or1k64bf_imp_properties =
+static const SIM_MACH_IMP_PROPERTIES or1k64bf_imp_properties =
{
sizeof (SIM_CPU),
#if WITH_SCACHE
@@ -99,7 +99,7 @@ or64_init_cpu (SIM_CPU *cpu)
#endif
}
-const MACH or64_mach =
+const SIM_MACH or64_mach =
{
"or64", "or1k64", MACH_OR64,
64, 64, & or64_models[0], & or1k64bf_imp_properties,
@@ -125,7 +125,7 @@ or64nd_init_cpu (SIM_CPU *cpu)
#endif
}
-const MACH or64nd_mach =
+const SIM_MACH or64nd_mach =
{
"or64nd", "or1k64nd", MACH_OR64ND,
64, 64, & or64nd_models[0], & or1k64bf_imp_properties,
diff --git a/sim/or1k/or1k32-opc.h b/sim/or1k/or1k32-opc.h
deleted file mode 100644
index 97aab87..0000000
--- a/sim/or1k/or1k32-opc.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/* Instruction opcode header for or1k.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996-2010 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#ifndef OR1K_OPC_H
-#define OR1K_OPC_H
-
-/* -- opc.h */
-
-#undef CGEN_DIS_HASH_SIZE
-#define CGEN_DIS_HASH_SIZE 256
-#undef CGEN_DIS_HASH
-#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
-
-/* -- */
-/* Enum declaration for or1k instruction types. */
-typedef enum cgen_insn_type {
- OR1K_INSN_INVALID, OR1K_INSN_L_J, OR1K_INSN_L_JAL, OR1K_INSN_L_JR
- , OR1K_INSN_L_JALR, OR1K_INSN_L_BNF, OR1K_INSN_L_BF, OR1K_INSN_L_TRAP
- , OR1K_INSN_L_SYS, OR1K_INSN_L_RFE, OR1K_INSN_L_NOP_IMM, OR1K_INSN_L_NOP
- , OR1K_INSN_L_MOVHI, OR1K_INSN_L_MACRC, OR1K_INSN_L_MFSPR, OR1K_INSN_L_MTSPR
- , OR1K_INSN_L_LWZ, OR1K_INSN_L_LWS, OR1K_INSN_L_LBZ, OR1K_INSN_L_LBS
- , OR1K_INSN_L_LHZ, OR1K_INSN_L_LHS, OR1K_INSN_L_SW, OR1K_INSN_L_SB
- , OR1K_INSN_L_SH, OR1K_INSN_L_SLL, OR1K_INSN_L_SLLI, OR1K_INSN_L_SRL
- , OR1K_INSN_L_SRLI, OR1K_INSN_L_SRA, OR1K_INSN_L_SRAI, OR1K_INSN_L_ROR
- , OR1K_INSN_L_RORI, OR1K_INSN_L_AND, OR1K_INSN_L_OR, OR1K_INSN_L_XOR
- , OR1K_INSN_L_ADD, OR1K_INSN_L_SUB, OR1K_INSN_L_ADDC, OR1K_INSN_L_MUL
- , OR1K_INSN_L_MULU, OR1K_INSN_L_DIV, OR1K_INSN_L_DIVU, OR1K_INSN_L_FF1
- , OR1K_INSN_L_FL1, OR1K_INSN_L_ANDI, OR1K_INSN_L_ORI, OR1K_INSN_L_XORI
- , OR1K_INSN_L_ADDI, OR1K_INSN_L_ADDIC, OR1K_INSN_L_MULI, OR1K_INSN_L_EXTHS
- , OR1K_INSN_L_EXTBS, OR1K_INSN_L_EXTHZ, OR1K_INSN_L_EXTBZ, OR1K_INSN_L_EXTWS
- , OR1K_INSN_L_EXTWZ, OR1K_INSN_L_CMOV, OR1K_INSN_L_SFGTU, OR1K_INSN_L_SFGEU
- , OR1K_INSN_L_SFLTU, OR1K_INSN_L_SFLEU, OR1K_INSN_L_SFGTS, OR1K_INSN_L_SFGES
- , OR1K_INSN_L_SFLTS, OR1K_INSN_L_SFLES, OR1K_INSN_L_SFGTUI, OR1K_INSN_L_SFGEUI
- , OR1K_INSN_L_SFLTUI, OR1K_INSN_L_SFLEUI, OR1K_INSN_L_SFGTSI, OR1K_INSN_L_SFGESI
- , OR1K_INSN_L_SFLTSI, OR1K_INSN_L_SFLESI, OR1K_INSN_L_SFEQ, OR1K_INSN_L_SFEQI
- , OR1K_INSN_L_SFNE, OR1K_INSN_L_SFNEI, OR1K_INSN_L_MAC, OR1K_INSN_L_MSB
- , OR1K_INSN_L_MACI, OR1K_INSN_L_CUST1, OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3
- , OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5, OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7
- , OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S, OR1K_INSN_LF_SUB_S, OR1K_INSN_LF_MUL_S
- , OR1K_INSN_LF_DIV_S, OR1K_INSN_LF_REM_S, OR1K_INSN_LF_ITOF_S, OR1K_INSN_LF_FTOI_S
- , OR1K_INSN_LF_EQ_S, OR1K_INSN_LF_NE_S, OR1K_INSN_LF_GE_S, OR1K_INSN_LF_GT_S
- , OR1K_INSN_LF_LT_S, OR1K_INSN_LF_LE_S, OR1K_INSN_LF_MADD_S, OR1K_INSN_LF_CUST1_S
-} CGEN_INSN_TYPE;
-
-/* Index of `invalid' insn place holder. */
-#define CGEN_INSN_INVALID OR1K_INSN_INVALID
-
-/* Total number of insns in table. */
-#define MAX_INSNS ((int) OR1K_INSN_LF_CUST1_S + 1)
-
-/* This struct records data prior to insertion or after extraction. */
-struct cgen_fields
-{
- int length;
- long f_nil;
- long f_anyof;
- long f_opcode;
- long f_r1;
- long f_r2;
- long f_r3;
- long f_op_25_2;
- long f_op_25_5;
- long f_op_16_1;
- long f_op_7_4;
- long f_op_3_4;
- long f_op_9_2;
- long f_op_9_4;
- long f_op_7_8;
- long f_op_7_2;
- long f_resv_25_26;
- long f_resv_25_10;
- long f_resv_25_5;
- long f_resv_23_8;
- long f_resv_20_5;
- long f_resv_20_4;
- long f_resv_15_8;
- long f_resv_15_6;
- long f_resv_10_11;
- long f_resv_10_7;
- long f_resv_10_3;
- long f_resv_10_1;
- long f_resv_7_4;
- long f_resv_5_2;
- long f_imm16_25_5;
- long f_imm16_10_11;
- long f_disp26;
- long f_uimm16;
- long f_simm16;
- long f_uimm6;
- long f_uimm16_split;
- long f_simm16_split;
-};
-
-#define CGEN_INIT_PARSE(od) \
-{\
-}
-#define CGEN_INIT_INSERT(od) \
-{\
-}
-#define CGEN_INIT_EXTRACT(od) \
-{\
-}
-#define CGEN_INIT_PRINT(od) \
-{\
-}
-
-
-#endif /* OR1K_OPC_H */
diff --git a/sim/or1k/or1k64-opc.h b/sim/or1k/or1k64-opc.h
deleted file mode 100644
index b35a1bf..0000000
--- a/sim/or1k/or1k64-opc.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/* Instruction opcode header for or1k.
-
-THIS FILE IS MACHINE GENERATED WITH CGEN.
-
-Copyright 1996-2010 Free Software Foundation, Inc.
-
-This file is part of the GNU Binutils and/or GDB, the GNU debugger.
-
- This file is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3, or (at your option)
- any later version.
-
- It is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
- License for more details.
-
- You should have received a copy of the GNU General Public License along
- with this program; if not, write to the Free Software Foundation, Inc.,
- 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
-
-*/
-
-#ifndef OR1K_OPC_H
-#define OR1K_OPC_H
-
-/* -- opc.h */
-
-#undef CGEN_DIS_HASH_SIZE
-#define CGEN_DIS_HASH_SIZE 256
-#undef CGEN_DIS_HASH
-#define CGEN_DIS_HASH(buffer, value) (((unsigned char *) (buffer))[0] >> 2)
-
-/* -- */
-/* Enum declaration for or1k instruction types. */
-typedef enum cgen_insn_type {
- OR1K_INSN_INVALID, OR1K_INSN_L_J, OR1K_INSN_L_JAL, OR1K_INSN_L_JR
- , OR1K_INSN_L_JALR, OR1K_INSN_L_BNF, OR1K_INSN_L_BF, OR1K_INSN_L_TRAP
- , OR1K_INSN_L_SYS, OR1K_INSN_L_RFE, OR1K_INSN_L_NOP_IMM, OR1K_INSN_L_NOP
- , OR1K_INSN_L_MOVHI, OR1K_INSN_L_MACRC, OR1K_INSN_L_MFSPR, OR1K_INSN_L_MTSPR
- , OR1K_INSN_L_LWZ, OR1K_INSN_L_LWS, OR1K_INSN_L_LBZ, OR1K_INSN_L_LBS
- , OR1K_INSN_L_LHZ, OR1K_INSN_L_LHS, OR1K_INSN_L_SW, OR1K_INSN_L_SB
- , OR1K_INSN_L_SH, OR1K_INSN_L_SLL, OR1K_INSN_L_SLLI, OR1K_INSN_L_SRL
- , OR1K_INSN_L_SRLI, OR1K_INSN_L_SRA, OR1K_INSN_L_SRAI, OR1K_INSN_L_ROR
- , OR1K_INSN_L_RORI, OR1K_INSN_L_AND, OR1K_INSN_L_OR, OR1K_INSN_L_XOR
- , OR1K_INSN_L_ADD, OR1K_INSN_L_SUB, OR1K_INSN_L_ADDC, OR1K_INSN_L_MUL
- , OR1K_INSN_L_MULU, OR1K_INSN_L_DIV, OR1K_INSN_L_DIVU, OR1K_INSN_L_FF1
- , OR1K_INSN_L_FL1, OR1K_INSN_L_ANDI, OR1K_INSN_L_ORI, OR1K_INSN_L_XORI
- , OR1K_INSN_L_ADDI, OR1K_INSN_L_ADDIC, OR1K_INSN_L_MULI, OR1K_INSN_L_EXTHS
- , OR1K_INSN_L_EXTBS, OR1K_INSN_L_EXTHZ, OR1K_INSN_L_EXTBZ, OR1K_INSN_L_EXTWS
- , OR1K_INSN_L_EXTWZ, OR1K_INSN_L_CMOV, OR1K_INSN_L_SFGTU, OR1K_INSN_L_SFGEU
- , OR1K_INSN_L_SFLTU, OR1K_INSN_L_SFLEU, OR1K_INSN_L_SFGTS, OR1K_INSN_L_SFGES
- , OR1K_INSN_L_SFLTS, OR1K_INSN_L_SFLES, OR1K_INSN_L_SFGTUI, OR1K_INSN_L_SFGEUI
- , OR1K_INSN_L_SFLTUI, OR1K_INSN_L_SFLEUI, OR1K_INSN_L_SFGTSI, OR1K_INSN_L_SFGESI
- , OR1K_INSN_L_SFLTSI, OR1K_INSN_L_SFLESI, OR1K_INSN_L_SFEQ, OR1K_INSN_L_SFEQI
- , OR1K_INSN_L_SFNE, OR1K_INSN_L_SFNEI, OR1K_INSN_L_MAC, OR1K_INSN_L_MSB
- , OR1K_INSN_L_MACI, OR1K_INSN_L_CUST1, OR1K_INSN_L_CUST2, OR1K_INSN_L_CUST3
- , OR1K_INSN_L_CUST4, OR1K_INSN_L_CUST5, OR1K_INSN_L_CUST6, OR1K_INSN_L_CUST7
- , OR1K_INSN_L_CUST8, OR1K_INSN_LF_ADD_S, OR1K_INSN_LF_ADD_D, OR1K_INSN_LF_SUB_S
- , OR1K_INSN_LF_SUB_D, OR1K_INSN_LF_MUL_S, OR1K_INSN_LF_MUL_D, OR1K_INSN_LF_DIV_S
- , OR1K_INSN_LF_DIV_D, OR1K_INSN_LF_REM_S, OR1K_INSN_LF_REM_D, OR1K_INSN_LF_ITOF_S
- , OR1K_INSN_LF_ITOF_D, OR1K_INSN_LF_FTOI_S, OR1K_INSN_LF_FTOI_D, OR1K_INSN_LF_EQ_S
- , OR1K_INSN_LF_EQ_D, OR1K_INSN_LF_NE_S, OR1K_INSN_LF_NE_D, OR1K_INSN_LF_GE_S
- , OR1K_INSN_LF_GE_D, OR1K_INSN_LF_GT_S, OR1K_INSN_LF_GT_D, OR1K_INSN_LF_LT_S
- , OR1K_INSN_LF_LT_D, OR1K_INSN_LF_LE_S, OR1K_INSN_LF_LE_D, OR1K_INSN_LF_MADD_S
- , OR1K_INSN_LF_MADD_D, OR1K_INSN_LF_CUST1_S, OR1K_INSN_LF_CUST1_D
-} CGEN_INSN_TYPE;
-
-/* Index of `invalid' insn place holder. */
-#define CGEN_INSN_INVALID OR1K_INSN_INVALID
-
-/* Total number of insns in table. */
-#define MAX_INSNS ((int) OR1K_INSN_LF_CUST1_D + 1)
-
-/* This struct records data prior to insertion or after extraction. */
-struct cgen_fields
-{
- int length;
- long f_nil;
- long f_anyof;
- long f_opcode;
- long f_r1;
- long f_r2;
- long f_r3;
- long f_op_25_2;
- long f_op_25_5;
- long f_op_16_1;
- long f_op_7_4;
- long f_op_3_4;
- long f_op_9_2;
- long f_op_9_4;
- long f_op_7_8;
- long f_op_7_2;
- long f_resv_25_26;
- long f_resv_25_10;
- long f_resv_25_5;
- long f_resv_23_8;
- long f_resv_20_5;
- long f_resv_20_4;
- long f_resv_15_8;
- long f_resv_15_6;
- long f_resv_10_11;
- long f_resv_10_7;
- long f_resv_10_3;
- long f_resv_10_1;
- long f_resv_7_4;
- long f_resv_5_2;
- long f_imm16_25_5;
- long f_imm16_10_11;
- long f_disp26;
- long f_uimm16;
- long f_simm16;
- long f_uimm6;
- long f_uimm16_split;
- long f_simm16_split;
-};
-
-#define CGEN_INIT_PARSE(od) \
-{\
-}
-#define CGEN_INIT_INSERT(od) \
-{\
-}
-#define CGEN_INIT_EXTRACT(od) \
-{\
-}
-#define CGEN_INIT_PRINT(od) \
-{\
-}
-
-
-#endif /* OR1K_OPC_H */
diff --git a/sim/or1k/sem32-switch.c b/sim/or1k/sem32-switch.c
index 7d3d97f..37c0dc7 100644
--- a/sim/or1k/sem32-switch.c
+++ b/sim/or1k/sem32-switch.c
@@ -46,6 +46,9 @@ This file is part of the GNU simulators.
{ OR1K32BF_INSN_L_BF, && case_sem_INSN_L_BF },
{ OR1K32BF_INSN_L_TRAP, && case_sem_INSN_L_TRAP },
{ OR1K32BF_INSN_L_SYS, && case_sem_INSN_L_SYS },
+ { OR1K32BF_INSN_L_MSYNC, && case_sem_INSN_L_MSYNC },
+ { OR1K32BF_INSN_L_PSYNC, && case_sem_INSN_L_PSYNC },
+ { OR1K32BF_INSN_L_CSYNC, && case_sem_INSN_L_CSYNC },
{ OR1K32BF_INSN_L_RFE, && case_sem_INSN_L_RFE },
{ OR1K32BF_INSN_L_NOP_IMM, && case_sem_INSN_L_NOP_IMM },
{ OR1K32BF_INSN_L_MOVHI, && case_sem_INSN_L_MOVHI },
@@ -54,6 +57,7 @@ This file is part of the GNU simulators.
{ OR1K32BF_INSN_L_MTSPR, && case_sem_INSN_L_MTSPR },
{ OR1K32BF_INSN_L_LWZ, && case_sem_INSN_L_LWZ },
{ OR1K32BF_INSN_L_LWS, && case_sem_INSN_L_LWS },
+ { OR1K32BF_INSN_L_LWA, && case_sem_INSN_L_LWA },
{ OR1K32BF_INSN_L_LBZ, && case_sem_INSN_L_LBZ },
{ OR1K32BF_INSN_L_LBS, && case_sem_INSN_L_LBS },
{ OR1K32BF_INSN_L_LHZ, && case_sem_INSN_L_LHZ },
@@ -61,6 +65,7 @@ This file is part of the GNU simulators.
{ OR1K32BF_INSN_L_SW, && case_sem_INSN_L_SW },
{ OR1K32BF_INSN_L_SB, && case_sem_INSN_L_SB },
{ OR1K32BF_INSN_L_SH, && case_sem_INSN_L_SH },
+ { OR1K32BF_INSN_L_SWA, && case_sem_INSN_L_SWA },
{ OR1K32BF_INSN_L_SLL, && case_sem_INSN_L_SLL },
{ OR1K32BF_INSN_L_SLLI, && case_sem_INSN_L_SLLI },
{ OR1K32BF_INSN_L_SRL, && case_sem_INSN_L_SRL },
@@ -165,8 +170,8 @@ This file is part of the GNU simulators.
special handlers into the instruction "stream". */
#if FAST_P
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
#endif
#undef GET_ATTR
@@ -354,7 +359,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -382,14 +387,14 @@ if (1)
{
USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
SET_H_GPR (((UINT) 9), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
{
{
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -419,7 +424,7 @@ if (1)
{
USI opval = GET_H_GPR (FLD (f_r3));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -447,14 +452,14 @@ if (1)
{
USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
SET_H_GPR (((UINT) 9), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
{
{
USI opval = GET_H_GPR (FLD (f_r3));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -486,7 +491,7 @@ if (NOTSI (GET_H_SYS_SR_F ())) {
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
} else {
@@ -496,7 +501,7 @@ if (GET_H_SYS_CPUCFGR_ND ()) {
USI opval = ADDSI (pc, 4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
@@ -530,7 +535,7 @@ if (GET_H_SYS_SR_F ()) {
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
} else {
@@ -540,7 +545,7 @@ if (GET_H_SYS_CPUCFGR_ND ()) {
USI opval = ADDSI (pc, 4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
@@ -587,6 +592,51 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
}
NEXT (vpc);
+ CASE (sem, INSN_L_MSYNC) : /* l.msync */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_PSYNC) : /* l.psync */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CSYNC) : /* l.csync */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
CASE (sem, INSN_L_RFE) : /* l.rfe */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
@@ -629,7 +679,7 @@ or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
{
USI opval = SLLSI (ZEXTSISI (FLD (f_uimm16)), 16);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -649,17 +699,17 @@ or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
{
USI opval = GET_H_MAC_MACLO ();
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
USI opval = 0;
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
{
USI opval = 0;
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
}
@@ -679,7 +729,7 @@ or1k32bf_nop (current_cpu, ZEXTSISI (FLD (f_uimm16)));
{
USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -713,7 +763,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -732,13 +782,44 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
SI opval = EXTSISI (GETMEMSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
}
NEXT (vpc);
+ CASE (sem, INSN_L_LWA) : /* l.lwa $rD,${simm16}($rA) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+ {
+ SI opval = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4);
+ CPU (h_atomic_address) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
CASE (sem, INSN_L_LBZ) : /* l.lbz $rD,${simm16}($rA) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
@@ -751,7 +832,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = ZEXTQISI (GETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -770,7 +851,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
SI opval = EXTQISI (GETMEMQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -789,7 +870,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = ZEXTHISI (GETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -808,7 +889,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
SI opval = EXTHISI (GETMEMHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -824,12 +905,25 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
{
USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
- SETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+ abuf->written = written;
#undef FLD
}
NEXT (vpc);
@@ -843,12 +937,25 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1);
{
UQI opval = TRUNCSIQI (GET_H_GPR (FLD (f_r3)));
- SETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+ abuf->written = written;
#undef FLD
}
NEXT (vpc);
@@ -862,12 +969,63 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2);
{
UHI opval = TRUNCSIHI (GET_H_GPR (FLD (f_r3)));
- SETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUHI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SWA) : /* l.swa ${simm16-split}($rA),$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_addr;
+ BI tmp_flag;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
+ {
+ USI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+if (GET_H_SYS_SR_F ()) {
+ {
+ USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
+}
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+ abuf->written = written;
#undef FLD
}
NEXT (vpc);
@@ -884,7 +1042,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -903,7 +1061,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -922,7 +1080,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -941,7 +1099,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -960,7 +1118,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = SRASI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -979,7 +1137,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = SRASI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -998,7 +1156,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = RORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1017,7 +1175,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = RORSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1036,7 +1194,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1055,7 +1213,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = ORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1074,7 +1232,7 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
USI opval = XORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1095,17 +1253,17 @@ or1k32bf_mtspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm
{
BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1131,17 +1289,17 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = SUBCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = SUBOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
USI opval = SUBSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1169,17 +1327,17 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
USI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1205,17 +1363,17 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1241,17 +1399,17 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1279,13 +1437,13 @@ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 0;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
} else {
@@ -1293,13 +1451,13 @@ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 1;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
}
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
@@ -1327,13 +1485,13 @@ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 0;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
} else {
@@ -1341,13 +1499,13 @@ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 1;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
}
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
@@ -1371,7 +1529,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = or1k32bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1390,7 +1548,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = or1k32bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1409,7 +1567,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1428,7 +1586,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1447,7 +1605,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = XORSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1468,17 +1626,17 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1506,17 +1664,17 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
SI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1542,17 +1700,17 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
USI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1576,7 +1734,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = EXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1595,7 +1753,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = EXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1614,7 +1772,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = ZEXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1633,7 +1791,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = ZEXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1652,7 +1810,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = EXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1671,7 +1829,7 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
USI opval = ZEXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -1692,14 +1850,14 @@ if (GET_H_SYS_SR_F ()) {
USI opval = GET_H_GPR (FLD (f_r2));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 3);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
} else {
{
USI opval = GET_H_GPR (FLD (f_r3));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 3);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
@@ -1720,7 +1878,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1739,7 +1897,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1758,7 +1916,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1777,7 +1935,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1796,7 +1954,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1815,7 +1973,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1834,7 +1992,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1853,7 +2011,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1872,7 +2030,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1891,7 +2049,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1910,7 +2068,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1929,7 +2087,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1948,7 +2106,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1967,7 +2125,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -1986,7 +2144,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2005,7 +2163,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2024,7 +2182,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = EQSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2043,7 +2201,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = EQSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2062,7 +2220,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = NESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2081,7 +2239,7 @@ if (GET_H_SYS_SR_F ()) {
{
USI opval = NESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2105,12 +2263,12 @@ if (GET_H_SYS_SR_F ()) {
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2135,12 +2293,12 @@ if (GET_H_SYS_SR_F ()) {
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2165,12 +2323,12 @@ if (GET_H_SYS_SR_F ()) {
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2310,7 +2468,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2329,7 +2487,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2348,7 +2506,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2367,7 +2525,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2386,7 +2544,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2405,7 +2563,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCSISI (GET_H_GPR (FLD (f_r2))));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2424,7 +2582,7 @@ if (GET_H_SYS_SR_F ()) {
{
SI opval = EXTSISI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
#undef FLD
@@ -2443,7 +2601,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2462,7 +2620,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2481,7 +2639,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2500,7 +2658,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2519,7 +2677,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2538,7 +2696,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2557,7 +2715,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
diff --git a/sim/or1k/sem32.c b/sim/or1k/sem32.c
index e8cbcc9..61d66cf 100644
--- a/sim/or1k/sem32.c
+++ b/sim/or1k/sem32.c
@@ -37,8 +37,8 @@ This file is part of the GNU simulators.
FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
#if FAST_P
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
#else
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
#endif
@@ -214,7 +214,7 @@ SEM_FN_NAME (or1k32bf,l_j) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -244,14 +244,14 @@ SEM_FN_NAME (or1k32bf,l_jal) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
SET_H_GPR (((UINT) 9), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
{
{
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -283,7 +283,7 @@ SEM_FN_NAME (or1k32bf,l_jr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = GET_H_GPR (FLD (f_r3));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -313,14 +313,14 @@ SEM_FN_NAME (or1k32bf,l_jalr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ADDSI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
SET_H_GPR (((UINT) 9), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
{
{
USI opval = GET_H_GPR (FLD (f_r3));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -354,7 +354,7 @@ if (NOTSI (GET_H_SYS_SR_F ())) {
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
} else {
@@ -364,7 +364,7 @@ if (GET_H_SYS_CPUCFGR_ND ()) {
USI opval = ADDSI (pc, 4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
@@ -400,7 +400,7 @@ if (GET_H_SYS_SR_F ()) {
USI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
} else {
@@ -410,7 +410,7 @@ if (GET_H_SYS_CPUCFGR_ND ()) {
USI opval = ADDSI (pc, 4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval);
}
}
}
@@ -461,6 +461,57 @@ or1k32bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
#undef FLD
}
+/* l-msync: l.msync */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_msync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-psync: l.psync */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_psync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-csync: l.csync */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_csync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
/* l-rfe: l.rfe */
static SEM_PC
@@ -509,7 +560,7 @@ SEM_FN_NAME (or1k32bf,l_movhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = SLLSI (ZEXTSISI (FLD (f_uimm16)), 16);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -531,17 +582,17 @@ SEM_FN_NAME (or1k32bf,l_macrc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = GET_H_MAC_MACLO ();
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
{
USI opval = 0;
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
{
USI opval = 0;
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
}
@@ -563,7 +614,7 @@ SEM_FN_NAME (or1k32bf,l_mfspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = or1k32bf_mfspr (current_cpu, ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -601,7 +652,7 @@ SEM_FN_NAME (or1k32bf,l_lwz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -622,8 +673,41 @@ SEM_FN_NAME (or1k32bf,l_lws) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = EXTSISI (GETMEMSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-lwa: l.lwa $rD,${simm16}($rA) */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_lwa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ USI opval = ZEXTSISI (GETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+ {
+ SI opval = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4);
+ CPU (h_atomic_address) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval);
}
+}
return vpc;
#undef FLD
@@ -643,7 +727,7 @@ SEM_FN_NAME (or1k32bf,l_lbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ZEXTQISI (GETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -664,7 +748,7 @@ SEM_FN_NAME (or1k32bf,l_lbs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = EXTQISI (GETMEMQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -685,7 +769,7 @@ SEM_FN_NAME (or1k32bf,l_lhz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ZEXTHISI (GETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -706,7 +790,7 @@ SEM_FN_NAME (or1k32bf,l_lhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = EXTHISI (GETMEMHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -724,12 +808,25 @@ SEM_FN_NAME (or1k32bf,l_sw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
{
USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
- SETMEMUSI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
}
+}
+}
+ abuf->written = written;
return vpc;
#undef FLD
}
@@ -745,12 +842,25 @@ SEM_FN_NAME (or1k32bf,l_sb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1);
{
UQI opval = TRUNCSIQI (GET_H_GPR (FLD (f_r3)));
- SETMEMUQI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
}
+}
+}
+ abuf->written = written;
return vpc;
#undef FLD
}
@@ -766,12 +876,65 @@ SEM_FN_NAME (or1k32bf,l_sh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2);
{
UHI opval = TRUNCSIHI (GET_H_GPR (FLD (f_r3)));
- SETMEMUHI (current_cpu, pc, or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUHI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* l-swa: l.swa ${simm16-split}($rA),$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k32bf,l_swa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ BI tmp_flag;
+ tmp_addr = or1k32bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
+ {
+ USI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ }
+if (GET_H_SYS_SR_F ()) {
+ {
+ USI opval = TRUNCSISI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+
+ abuf->written = written;
return vpc;
#undef FLD
}
@@ -790,7 +953,7 @@ SEM_FN_NAME (or1k32bf,l_sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -811,7 +974,7 @@ SEM_FN_NAME (or1k32bf,l_slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = SLLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -832,7 +995,7 @@ SEM_FN_NAME (or1k32bf,l_srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -853,7 +1016,7 @@ SEM_FN_NAME (or1k32bf,l_srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = SRLSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -874,7 +1037,7 @@ SEM_FN_NAME (or1k32bf,l_sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = SRASI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -895,7 +1058,7 @@ SEM_FN_NAME (or1k32bf,l_srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = SRASI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -916,7 +1079,7 @@ SEM_FN_NAME (or1k32bf,l_ror) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = RORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -937,7 +1100,7 @@ SEM_FN_NAME (or1k32bf,l_rori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = RORSI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -958,7 +1121,7 @@ SEM_FN_NAME (or1k32bf,l_and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -979,7 +1142,7 @@ SEM_FN_NAME (or1k32bf,l_or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1000,7 +1163,7 @@ SEM_FN_NAME (or1k32bf,l_xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = XORSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1023,17 +1186,17 @@ SEM_FN_NAME (or1k32bf,l_add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1061,17 +1224,17 @@ SEM_FN_NAME (or1k32bf,l_sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = SUBCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = SUBOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
USI opval = SUBSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1101,17 +1264,17 @@ SEM_FN_NAME (or1k32bf,l_addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
USI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1139,17 +1302,17 @@ SEM_FN_NAME (or1k32bf,l_mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1177,17 +1340,17 @@ SEM_FN_NAME (or1k32bf,l_mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
BI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
USI opval = MULSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1217,13 +1380,13 @@ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 0;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
SI opval = DIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
} else {
@@ -1231,13 +1394,13 @@ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 1;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
}
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
@@ -1267,13 +1430,13 @@ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 0;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
USI opval = UDIVSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
} else {
@@ -1281,13 +1444,13 @@ if (NESI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 1;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
}
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
or1k32bf_exception (current_cpu, pc, EXCEPT_RANGE);
@@ -1313,7 +1476,7 @@ SEM_FN_NAME (or1k32bf,l_ff1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = or1k32bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1334,7 +1497,7 @@ SEM_FN_NAME (or1k32bf,l_fl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = or1k32bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1355,7 +1518,7 @@ SEM_FN_NAME (or1k32bf,l_andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ANDSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1376,7 +1539,7 @@ SEM_FN_NAME (or1k32bf,l_ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ORSI (GET_H_GPR (FLD (f_r2)), ZEXTSISI (FLD (f_uimm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1397,7 +1560,7 @@ SEM_FN_NAME (or1k32bf,l_xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = XORSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1420,17 +1583,17 @@ SEM_FN_NAME (or1k32bf,l_addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
USI opval = ADDSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1460,17 +1623,17 @@ SEM_FN_NAME (or1k32bf,l_addic) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = ADDCFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
SI opval = ADDCSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1498,17 +1661,17 @@ SEM_FN_NAME (or1k32bf,l_muli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = MUL2OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
USI opval = MUL1OFSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
USI opval = MULSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1534,7 +1697,7 @@ SEM_FN_NAME (or1k32bf,l_exths) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = EXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1555,7 +1718,7 @@ SEM_FN_NAME (or1k32bf,l_extbs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = EXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1576,7 +1739,7 @@ SEM_FN_NAME (or1k32bf,l_exthz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ZEXTHISI (TRUNCSIHI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1597,7 +1760,7 @@ SEM_FN_NAME (or1k32bf,l_extbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ZEXTQISI (TRUNCSIQI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1618,7 +1781,7 @@ SEM_FN_NAME (or1k32bf,l_extws) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = EXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1639,7 +1802,7 @@ SEM_FN_NAME (or1k32bf,l_extwz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = ZEXTSISI (TRUNCSISI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -1662,14 +1825,14 @@ if (GET_H_SYS_SR_F ()) {
USI opval = GET_H_GPR (FLD (f_r2));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 3);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
} else {
{
USI opval = GET_H_GPR (FLD (f_r3));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 3);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
}
@@ -1692,7 +1855,7 @@ SEM_FN_NAME (or1k32bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = GTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1713,7 +1876,7 @@ SEM_FN_NAME (or1k32bf,l_sfgtsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = GTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1734,7 +1897,7 @@ SEM_FN_NAME (or1k32bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1755,7 +1918,7 @@ SEM_FN_NAME (or1k32bf,l_sfgtui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = GTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1776,7 +1939,7 @@ SEM_FN_NAME (or1k32bf,l_sfges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = GESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1797,7 +1960,7 @@ SEM_FN_NAME (or1k32bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = GESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1818,7 +1981,7 @@ SEM_FN_NAME (or1k32bf,l_sfgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1839,7 +2002,7 @@ SEM_FN_NAME (or1k32bf,l_sfgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = GEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1860,7 +2023,7 @@ SEM_FN_NAME (or1k32bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = LTSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1881,7 +2044,7 @@ SEM_FN_NAME (or1k32bf,l_sfltsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = LTSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1902,7 +2065,7 @@ SEM_FN_NAME (or1k32bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1923,7 +2086,7 @@ SEM_FN_NAME (or1k32bf,l_sfltui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = LTUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1944,7 +2107,7 @@ SEM_FN_NAME (or1k32bf,l_sfles) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = LESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1965,7 +2128,7 @@ SEM_FN_NAME (or1k32bf,l_sflesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = LESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -1986,7 +2149,7 @@ SEM_FN_NAME (or1k32bf,l_sfleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2007,7 +2170,7 @@ SEM_FN_NAME (or1k32bf,l_sfleui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = LEUSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2028,7 +2191,7 @@ SEM_FN_NAME (or1k32bf,l_sfeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = EQSI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2049,7 +2212,7 @@ SEM_FN_NAME (or1k32bf,l_sfeqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = EQSI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2070,7 +2233,7 @@ SEM_FN_NAME (or1k32bf,l_sfne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = NESI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2091,7 +2254,7 @@ SEM_FN_NAME (or1k32bf,l_sfnei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
USI opval = NESI (GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2117,12 +2280,12 @@ SEM_FN_NAME (or1k32bf,l_mac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2149,12 +2312,12 @@ SEM_FN_NAME (or1k32bf,l_msb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2181,12 +2344,12 @@ SEM_FN_NAME (or1k32bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2344,7 +2507,7 @@ SEM_FN_NAME (or1k32bf,lf_add_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2365,7 +2528,7 @@ SEM_FN_NAME (or1k32bf,lf_sub_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2386,7 +2549,7 @@ SEM_FN_NAME (or1k32bf,lf_mul_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2407,7 +2570,7 @@ SEM_FN_NAME (or1k32bf,lf_div_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2428,7 +2591,7 @@ SEM_FN_NAME (or1k32bf,lf_rem_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2449,7 +2612,7 @@ SEM_FN_NAME (or1k32bf,lf_itof_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCSISI (GET_H_GPR (FLD (f_r2))));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2470,7 +2633,7 @@ SEM_FN_NAME (or1k32bf,lf_ftoi_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = EXTSISI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'x', opval);
}
return vpc;
@@ -2491,7 +2654,7 @@ SEM_FN_NAME (or1k32bf,lf_eq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2512,7 +2675,7 @@ SEM_FN_NAME (or1k32bf,lf_ne_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2533,7 +2696,7 @@ SEM_FN_NAME (or1k32bf,lf_ge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2554,7 +2717,7 @@ SEM_FN_NAME (or1k32bf,lf_gt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2575,7 +2738,7 @@ SEM_FN_NAME (or1k32bf,lf_lt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2596,7 +2759,7 @@ SEM_FN_NAME (or1k32bf,lf_le_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2617,7 +2780,7 @@ SEM_FN_NAME (or1k32bf,lf_madd_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2658,6 +2821,9 @@ static const struct sem_fn_desc sem_fns[] = {
{ OR1K32BF_INSN_L_BF, SEM_FN_NAME (or1k32bf,l_bf) },
{ OR1K32BF_INSN_L_TRAP, SEM_FN_NAME (or1k32bf,l_trap) },
{ OR1K32BF_INSN_L_SYS, SEM_FN_NAME (or1k32bf,l_sys) },
+ { OR1K32BF_INSN_L_MSYNC, SEM_FN_NAME (or1k32bf,l_msync) },
+ { OR1K32BF_INSN_L_PSYNC, SEM_FN_NAME (or1k32bf,l_psync) },
+ { OR1K32BF_INSN_L_CSYNC, SEM_FN_NAME (or1k32bf,l_csync) },
{ OR1K32BF_INSN_L_RFE, SEM_FN_NAME (or1k32bf,l_rfe) },
{ OR1K32BF_INSN_L_NOP_IMM, SEM_FN_NAME (or1k32bf,l_nop_imm) },
{ OR1K32BF_INSN_L_MOVHI, SEM_FN_NAME (or1k32bf,l_movhi) },
@@ -2666,6 +2832,7 @@ static const struct sem_fn_desc sem_fns[] = {
{ OR1K32BF_INSN_L_MTSPR, SEM_FN_NAME (or1k32bf,l_mtspr) },
{ OR1K32BF_INSN_L_LWZ, SEM_FN_NAME (or1k32bf,l_lwz) },
{ OR1K32BF_INSN_L_LWS, SEM_FN_NAME (or1k32bf,l_lws) },
+ { OR1K32BF_INSN_L_LWA, SEM_FN_NAME (or1k32bf,l_lwa) },
{ OR1K32BF_INSN_L_LBZ, SEM_FN_NAME (or1k32bf,l_lbz) },
{ OR1K32BF_INSN_L_LBS, SEM_FN_NAME (or1k32bf,l_lbs) },
{ OR1K32BF_INSN_L_LHZ, SEM_FN_NAME (or1k32bf,l_lhz) },
@@ -2673,6 +2840,7 @@ static const struct sem_fn_desc sem_fns[] = {
{ OR1K32BF_INSN_L_SW, SEM_FN_NAME (or1k32bf,l_sw) },
{ OR1K32BF_INSN_L_SB, SEM_FN_NAME (or1k32bf,l_sb) },
{ OR1K32BF_INSN_L_SH, SEM_FN_NAME (or1k32bf,l_sh) },
+ { OR1K32BF_INSN_L_SWA, SEM_FN_NAME (or1k32bf,l_swa) },
{ OR1K32BF_INSN_L_SLL, SEM_FN_NAME (or1k32bf,l_sll) },
{ OR1K32BF_INSN_L_SLLI, SEM_FN_NAME (or1k32bf,l_slli) },
{ OR1K32BF_INSN_L_SRL, SEM_FN_NAME (or1k32bf,l_srl) },
diff --git a/sim/or1k/sem64-switch.c b/sim/or1k/sem64-switch.c
index 9de4e16..1bb27e4 100644
--- a/sim/or1k/sem64-switch.c
+++ b/sim/or1k/sem64-switch.c
@@ -46,6 +46,9 @@ This file is part of the GNU simulators.
{ OR1K64BF_INSN_L_BF, && case_sem_INSN_L_BF },
{ OR1K64BF_INSN_L_TRAP, && case_sem_INSN_L_TRAP },
{ OR1K64BF_INSN_L_SYS, && case_sem_INSN_L_SYS },
+ { OR1K64BF_INSN_L_MSYNC, && case_sem_INSN_L_MSYNC },
+ { OR1K64BF_INSN_L_PSYNC, && case_sem_INSN_L_PSYNC },
+ { OR1K64BF_INSN_L_CSYNC, && case_sem_INSN_L_CSYNC },
{ OR1K64BF_INSN_L_RFE, && case_sem_INSN_L_RFE },
{ OR1K64BF_INSN_L_NOP_IMM, && case_sem_INSN_L_NOP_IMM },
{ OR1K64BF_INSN_L_MOVHI, && case_sem_INSN_L_MOVHI },
@@ -54,6 +57,7 @@ This file is part of the GNU simulators.
{ OR1K64BF_INSN_L_MTSPR, && case_sem_INSN_L_MTSPR },
{ OR1K64BF_INSN_L_LWZ, && case_sem_INSN_L_LWZ },
{ OR1K64BF_INSN_L_LWS, && case_sem_INSN_L_LWS },
+ { OR1K64BF_INSN_L_LWA, && case_sem_INSN_L_LWA },
{ OR1K64BF_INSN_L_LBZ, && case_sem_INSN_L_LBZ },
{ OR1K64BF_INSN_L_LBS, && case_sem_INSN_L_LBS },
{ OR1K64BF_INSN_L_LHZ, && case_sem_INSN_L_LHZ },
@@ -61,6 +65,7 @@ This file is part of the GNU simulators.
{ OR1K64BF_INSN_L_SW, && case_sem_INSN_L_SW },
{ OR1K64BF_INSN_L_SB, && case_sem_INSN_L_SB },
{ OR1K64BF_INSN_L_SH, && case_sem_INSN_L_SH },
+ { OR1K64BF_INSN_L_SWA, && case_sem_INSN_L_SWA },
{ OR1K64BF_INSN_L_SLL, && case_sem_INSN_L_SLL },
{ OR1K64BF_INSN_L_SLLI, && case_sem_INSN_L_SLLI },
{ OR1K64BF_INSN_L_SRL, && case_sem_INSN_L_SRL },
@@ -180,8 +185,8 @@ This file is part of the GNU simulators.
special handlers into the instruction "stream". */
#if FAST_P
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
#endif
#undef GET_ATTR
@@ -369,7 +374,7 @@ SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case)
{
UDI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -397,14 +402,14 @@ if (1)
{
UDI opval = ADDDI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
SET_H_GPR (((UINT) 9), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
{
{
{
UDI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -434,7 +439,7 @@ if (1)
{
UDI opval = GET_H_GPR (FLD (f_r3));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -462,14 +467,14 @@ if (1)
{
UDI opval = ADDDI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
SET_H_GPR (((UINT) 9), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
{
{
{
UDI opval = GET_H_GPR (FLD (f_r3));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -501,7 +506,7 @@ if (NOTDI (GET_H_SYS_SR_F ())) {
UDI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
} else {
@@ -511,7 +516,7 @@ if (GET_H_SYS_CPUCFGR_ND ()) {
UDI opval = ADDDI (pc, 4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
@@ -545,7 +550,7 @@ if (GET_H_SYS_SR_F ()) {
UDI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
} else {
@@ -555,7 +560,7 @@ if (GET_H_SYS_CPUCFGR_ND ()) {
UDI opval = ADDDI (pc, 4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
@@ -602,6 +607,51 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
}
NEXT (vpc);
+ CASE (sem, INSN_L_MSYNC) : /* l.msync */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_PSYNC) : /* l.psync */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_CSYNC) : /* l.csync */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_empty.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+#undef FLD
+}
+ NEXT (vpc);
+
CASE (sem, INSN_L_RFE) : /* l.rfe */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
@@ -644,7 +694,7 @@ or1k64bf_nop (current_cpu, ZEXTSIDI (FLD (f_uimm16)));
{
UDI opval = SLLDI (ZEXTSIDI (FLD (f_uimm16)), 16);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -664,17 +714,17 @@ or1k64bf_nop (current_cpu, ZEXTSIDI (FLD (f_uimm16)));
{
UDI opval = GET_H_MAC_MACLO ();
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
{
UDI opval = 0;
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'D', opval);
}
{
UDI opval = 0;
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'D', opval);
}
}
@@ -694,7 +744,7 @@ or1k64bf_nop (current_cpu, ZEXTSIDI (FLD (f_uimm16)));
{
UDI opval = or1k64bf_mfspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -728,7 +778,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = ZEXTSIDI (GETMEMUSI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -747,13 +797,44 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
}
NEXT (vpc);
+ CASE (sem, INSN_L_LWA) : /* l.lwa $rD,${simm16}($rA) */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ UDI opval = ZEXTSIDI (GETMEMUSI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+ {
+ SI opval = or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4);
+ CPU (h_atomic_address) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval);
+ }
+}
+
+#undef FLD
+}
+ NEXT (vpc);
+
CASE (sem, INSN_L_LBZ) : /* l.lbz $rD,${simm16}($rA) */
{
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
@@ -766,7 +847,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = ZEXTQIDI (GETMEMUQI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -785,7 +866,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
DI opval = EXTQIDI (GETMEMQI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -804,7 +885,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = ZEXTHIDI (GETMEMUHI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -823,7 +904,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
DI opval = EXTHIDI (GETMEMHI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -839,12 +920,25 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
{
USI opval = TRUNCDISI (GET_H_GPR (FLD (f_r3)));
- SETMEMUSI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+ abuf->written = written;
#undef FLD
}
NEXT (vpc);
@@ -858,12 +952,25 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1);
{
UQI opval = TRUNCDIQI (GET_H_GPR (FLD (f_r3)));
- SETMEMUQI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+ abuf->written = written;
#undef FLD
}
NEXT (vpc);
@@ -877,12 +984,63 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
IADDR UNUSED pc = abuf->addr;
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2);
{
UHI opval = TRUNCDIHI (GET_H_GPR (FLD (f_r3)));
- SETMEMUHI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUHI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+#undef FLD
+}
+ NEXT (vpc);
+
+ CASE (sem, INSN_L_SWA) : /* l.swa ${simm16-split}($rA),$rB */
+{
+ SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ SI tmp_addr;
+ BI tmp_flag;
+ tmp_addr = or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
+ {
+ UDI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ }
+if (GET_H_SYS_SR_F ()) {
+ {
+ USI opval = TRUNCDISI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
+}
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+ abuf->written = written;
#undef FLD
}
NEXT (vpc);
@@ -899,7 +1057,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = SLLDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -918,7 +1076,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = SLLDI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -937,7 +1095,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = SRLDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -956,7 +1114,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = SRLDI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -975,7 +1133,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = SRADI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -994,7 +1152,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = SRADI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1013,7 +1171,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = RORDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1032,7 +1190,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = RORDI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1051,7 +1209,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = ANDDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1070,7 +1228,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = ORDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1089,7 +1247,7 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
UDI opval = XORDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1110,17 +1268,17 @@ or1k64bf_mtspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm
{
BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
UDI opval = ADDDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1146,17 +1304,17 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = SUBCFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = SUBOFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
UDI opval = SUBDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1184,17 +1342,17 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
UDI opval = ADDCDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1220,17 +1378,17 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = MUL2OFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
BI opval = MUL1OFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
UDI opval = MULDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1256,17 +1414,17 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
BI opval = MUL1OFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
UDI opval = MULDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1294,13 +1452,13 @@ if (NEDI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 0;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
DI opval = DIVDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
} else {
@@ -1308,13 +1466,13 @@ if (NEDI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 1;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
}
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
@@ -1342,13 +1500,13 @@ if (NEDI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 0;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
UDI opval = UDIVDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
} else {
@@ -1356,13 +1514,13 @@ if (NEDI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 1;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
}
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
@@ -1386,7 +1544,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = or1k64bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1405,7 +1563,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = or1k64bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1424,7 +1582,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = ANDDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1443,7 +1601,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1462,7 +1620,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = XORDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1483,17 +1641,17 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
UDI opval = ADDDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1521,17 +1679,17 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
DI opval = ADDCDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1557,17 +1715,17 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = MUL2OFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'D', opval);
}
{
UDI opval = MUL1OFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'D', opval);
}
{
UDI opval = MULDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1591,7 +1749,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = EXTHIDI (TRUNCDIHI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1610,7 +1768,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = EXTQIDI (TRUNCDIQI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1629,7 +1787,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = ZEXTHIDI (TRUNCDIHI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1648,7 +1806,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = ZEXTQIDI (TRUNCDIQI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1667,7 +1825,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = EXTSIDI (TRUNCDISI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1686,7 +1844,7 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
{
UDI opval = ZEXTSISI (TRUNCDISI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -1707,14 +1865,14 @@ if (GET_H_SYS_SR_F ()) {
UDI opval = GET_H_GPR (FLD (f_r2));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 3);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
} else {
{
UDI opval = GET_H_GPR (FLD (f_r3));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 3);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
@@ -1735,7 +1893,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1754,7 +1912,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1773,7 +1931,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1792,7 +1950,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1811,7 +1969,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1830,7 +1988,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1849,7 +2007,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1868,7 +2026,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1887,7 +2045,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1906,7 +2064,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1925,7 +2083,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1944,7 +2102,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1963,7 +2121,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -1982,7 +2140,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -2001,7 +2159,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -2020,7 +2178,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -2039,7 +2197,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = EQDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -2058,7 +2216,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = EQDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -2077,7 +2235,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = NEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -2096,7 +2254,7 @@ if (GET_H_SYS_SR_F ()) {
{
UDI opval = NEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
#undef FLD
@@ -2120,12 +2278,12 @@ if (GET_H_SYS_SR_F ()) {
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2150,12 +2308,12 @@ if (GET_H_SYS_SR_F ()) {
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2180,12 +2338,12 @@ if (GET_H_SYS_SR_F ()) {
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2325,7 +2483,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2344,7 +2502,7 @@ if (GET_H_SYS_SR_F ()) {
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
#undef FLD
@@ -2363,7 +2521,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2382,7 +2540,7 @@ if (GET_H_SYS_SR_F ()) {
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
#undef FLD
@@ -2401,7 +2559,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2420,7 +2578,7 @@ if (GET_H_SYS_SR_F ()) {
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
#undef FLD
@@ -2439,7 +2597,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2458,7 +2616,7 @@ if (GET_H_SYS_SR_F ()) {
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
#undef FLD
@@ -2477,7 +2635,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2496,7 +2654,7 @@ if (GET_H_SYS_SR_F ()) {
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->moddf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
#undef FLD
@@ -2515,7 +2673,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCDISI (GET_H_GPR (FLD (f_r2))));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2534,7 +2692,7 @@ if (GET_H_SYS_SR_F ()) {
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_GPR (FLD (f_r2)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
#undef FLD
@@ -2553,7 +2711,7 @@ if (GET_H_SYS_SR_F ()) {
{
DI opval = EXTSIDI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -2572,7 +2730,7 @@ if (GET_H_SYS_SR_F ()) {
{
DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FDR (FLD (f_r1)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
#undef FLD
@@ -2591,7 +2749,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2610,7 +2768,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2629,7 +2787,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2648,7 +2806,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2667,7 +2825,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2686,7 +2844,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2705,7 +2863,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2724,7 +2882,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2743,7 +2901,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2762,7 +2920,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2781,7 +2939,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2800,7 +2958,7 @@ if (GET_H_SYS_SR_F ()) {
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
#undef FLD
@@ -2819,7 +2977,7 @@ if (GET_H_SYS_SR_F ()) {
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
#undef FLD
@@ -2838,7 +2996,7 @@ if (GET_H_SYS_SR_F ()) {
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1))), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
#undef FLD
diff --git a/sim/or1k/sem64.c b/sim/or1k/sem64.c
index 08bc8bb..8b6c504 100644
--- a/sim/or1k/sem64.c
+++ b/sim/or1k/sem64.c
@@ -37,8 +37,8 @@ This file is part of the GNU simulators.
FAST_P, when desired, is defined on the command line, -DFAST_P=1. */
#if FAST_P
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_semf_,fn)
-#undef TRACE_RESULT
-#define TRACE_RESULT(cpu, abuf, name, type, val)
+#undef CGEN_TRACE_RESULT
+#define CGEN_TRACE_RESULT(cpu, abuf, name, type, val)
#else
#define SEM_FN_NAME(cpu,fn) XCONCAT3 (cpu,_sem_,fn)
#endif
@@ -214,7 +214,7 @@ SEM_FN_NAME (or1k64bf,l_j) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -244,14 +244,14 @@ SEM_FN_NAME (or1k64bf,l_jal) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ADDDI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
SET_H_GPR (((UINT) 9), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
{
{
{
UDI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -283,7 +283,7 @@ SEM_FN_NAME (or1k64bf,l_jr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = GET_H_GPR (FLD (f_r3));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -313,14 +313,14 @@ SEM_FN_NAME (or1k64bf,l_jalr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ADDDI (pc, ((GET_H_SYS_CPUCFGR_ND ()) ? (4) : (8)));
SET_H_GPR (((UINT) 9), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
{
{
{
UDI opval = GET_H_GPR (FLD (f_r3));
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
if (GET_H_SYS_CPUCFGR_ND ()) {
@@ -354,7 +354,7 @@ if (NOTDI (GET_H_SYS_SR_F ())) {
UDI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
} else {
@@ -364,7 +364,7 @@ if (GET_H_SYS_CPUCFGR_ND ()) {
UDI opval = ADDDI (pc, 4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
@@ -400,7 +400,7 @@ if (GET_H_SYS_SR_F ()) {
UDI opval = FLD (i_disp26);
SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
} else {
@@ -410,7 +410,7 @@ if (GET_H_SYS_CPUCFGR_ND ()) {
UDI opval = ADDDI (pc, 4);
SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc);
written |= (1 << 4);
- TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "pc", 'D', opval);
}
}
}
@@ -461,6 +461,57 @@ or1k64bf_exception (current_cpu, pc, EXCEPT_SYSCALL);
#undef FLD
}
+/* l-msync: l.msync */
+
+static SEM_PC
+SEM_FN_NAME (or1k64bf,l_msync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-psync: l.psync */
+
+static SEM_PC
+SEM_FN_NAME (or1k64bf,l_psync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* l-csync: l.csync */
+
+static SEM_PC
+SEM_FN_NAME (or1k64bf,l_csync) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
/* l-rfe: l.rfe */
static SEM_PC
@@ -509,7 +560,7 @@ SEM_FN_NAME (or1k64bf,l_movhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = SLLDI (ZEXTSIDI (FLD (f_uimm16)), 16);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -531,17 +582,17 @@ SEM_FN_NAME (or1k64bf,l_macrc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = GET_H_MAC_MACLO ();
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
{
UDI opval = 0;
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'D', opval);
}
{
UDI opval = 0;
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'D', opval);
}
}
@@ -563,7 +614,7 @@ SEM_FN_NAME (or1k64bf,l_mfspr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = or1k64bf_mfspr (current_cpu, ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -601,7 +652,7 @@ SEM_FN_NAME (or1k64bf,l_lwz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ZEXTSIDI (GETMEMUSI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -622,8 +673,41 @@ SEM_FN_NAME (or1k64bf,l_lws) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DI opval = EXTSIDI (GETMEMSI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+
+ return vpc;
+#undef FLD
+}
+
+/* l-lwa: l.lwa $rD,${simm16}($rA) */
+
+static SEM_PC
+SEM_FN_NAME (or1k64bf,l_lwa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_lwz.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+{
+ {
+ UDI opval = ZEXTSIDI (GETMEMUSI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4)));
+ SET_H_GPR (FLD (f_r1), opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ }
+ {
+ BI opval = 1;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+ {
+ SI opval = or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 4);
+ CPU (h_atomic_address) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-address", 'x', opval);
}
+}
return vpc;
#undef FLD
@@ -643,7 +727,7 @@ SEM_FN_NAME (or1k64bf,l_lbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ZEXTQIDI (GETMEMUQI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -664,7 +748,7 @@ SEM_FN_NAME (or1k64bf,l_lbs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DI opval = EXTQIDI (GETMEMQI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 1)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -685,7 +769,7 @@ SEM_FN_NAME (or1k64bf,l_lhz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ZEXTHIDI (GETMEMUHI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -706,7 +790,7 @@ SEM_FN_NAME (or1k64bf,l_lhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DI opval = EXTHIDI (GETMEMHI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16)), 2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -724,12 +808,25 @@ SEM_FN_NAME (or1k64bf,l_sw) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
{
USI opval = TRUNCDISI (GET_H_GPR (FLD (f_r3)));
- SETMEMUSI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
}
+}
+}
+ abuf->written = written;
return vpc;
#undef FLD
}
@@ -745,12 +842,25 @@ SEM_FN_NAME (or1k64bf,l_sb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1);
{
UQI opval = TRUNCDIQI (GET_H_GPR (FLD (f_r3)));
- SETMEMUQI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 1), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUQI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
}
+}
+}
+ abuf->written = written;
return vpc;
#undef FLD
}
@@ -766,12 +876,65 @@ SEM_FN_NAME (or1k64bf,l_sh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
IADDR UNUSED pc = abuf->addr;
SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ tmp_addr = or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2);
{
UHI opval = TRUNCDIHI (GET_H_GPR (FLD (f_r3)));
- SETMEMUHI (current_cpu, pc, or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 2), opval);
- TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ SETMEMUHI (current_cpu, pc, tmp_addr, opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
}
+if (EQSI (ANDSI (tmp_addr, 268435452), CPU (h_atomic_address))) {
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ written |= (1 << 4);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* l-swa: l.swa ${simm16-split}($rA),$rB */
+
+static SEM_PC
+SEM_FN_NAME (or1k64bf,l_swa) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_l_sw.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+{
+ SI tmp_addr;
+ BI tmp_flag;
+ tmp_addr = or1k64bf_make_load_store_addr (current_cpu, GET_H_GPR (FLD (f_r2)), EXTSISI (FLD (f_simm16_split)), 4);
+ {
+ UDI opval = ANDBI (CPU (h_atomic_reserve), EQSI (tmp_addr, CPU (h_atomic_address)));
+ SET_H_SYS_SR_F (opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ }
+if (GET_H_SYS_SR_F ()) {
+ {
+ USI opval = TRUNCDISI (GET_H_GPR (FLD (f_r3)));
+ SETMEMUSI (current_cpu, pc, tmp_addr, opval);
+ written |= (1 << 7);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval);
+ }
+}
+ {
+ BI opval = 0;
+ CPU (h_atomic_reserve) = opval;
+ CGEN_TRACE_RESULT (current_cpu, abuf, "atomic-reserve", 'x', opval);
+ }
+}
+
+ abuf->written = written;
return vpc;
#undef FLD
}
@@ -790,7 +953,7 @@ SEM_FN_NAME (or1k64bf,l_sll) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = SLLDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -811,7 +974,7 @@ SEM_FN_NAME (or1k64bf,l_slli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = SLLDI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -832,7 +995,7 @@ SEM_FN_NAME (or1k64bf,l_srl) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = SRLDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -853,7 +1016,7 @@ SEM_FN_NAME (or1k64bf,l_srli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = SRLDI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -874,7 +1037,7 @@ SEM_FN_NAME (or1k64bf,l_sra) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = SRADI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -895,7 +1058,7 @@ SEM_FN_NAME (or1k64bf,l_srai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = SRADI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -916,7 +1079,7 @@ SEM_FN_NAME (or1k64bf,l_ror) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = RORDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -937,7 +1100,7 @@ SEM_FN_NAME (or1k64bf,l_rori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = RORDI (GET_H_GPR (FLD (f_r2)), FLD (f_uimm6));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -958,7 +1121,7 @@ SEM_FN_NAME (or1k64bf,l_and) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ANDDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -979,7 +1142,7 @@ SEM_FN_NAME (or1k64bf,l_or) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ORDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1000,7 +1163,7 @@ SEM_FN_NAME (or1k64bf,l_xor) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = XORDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1023,17 +1186,17 @@ SEM_FN_NAME (or1k64bf,l_add) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
UDI opval = ADDDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1061,17 +1224,17 @@ SEM_FN_NAME (or1k64bf,l_sub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = SUBCFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = SUBOFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
UDI opval = SUBDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1101,17 +1264,17 @@ SEM_FN_NAME (or1k64bf,l_addc) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
UDI opval = ADDCDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)), tmp_tmp_sys_sr_cy);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1139,17 +1302,17 @@ SEM_FN_NAME (or1k64bf,l_mul) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = MUL2OFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
BI opval = MUL1OFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
UDI opval = MULDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1177,17 +1340,17 @@ SEM_FN_NAME (or1k64bf,l_mulu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
BI opval = MUL1OFDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
UDI opval = MULDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1217,13 +1380,13 @@ if (NEDI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 0;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
DI opval = DIVDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
} else {
@@ -1231,13 +1394,13 @@ if (NEDI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 1;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
}
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
@@ -1267,13 +1430,13 @@ if (NEDI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 0;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
UDI opval = UDIVDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 5);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
} else {
@@ -1281,13 +1444,13 @@ if (NEDI (GET_H_GPR (FLD (f_r3)), 0)) {
BI opval = 1;
SET_H_SYS_SR_CY (opval);
written |= (1 << 6);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
}
{
BI opval = 0;
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
if (ANDIF (GET_H_SYS_SR_CY (), GET_H_SYS_SR_OVE ())) {
or1k64bf_exception (current_cpu, pc, EXCEPT_RANGE);
@@ -1313,7 +1476,7 @@ SEM_FN_NAME (or1k64bf,l_ff1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = or1k64bf_ff1 (current_cpu, GET_H_GPR (FLD (f_r2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1334,7 +1497,7 @@ SEM_FN_NAME (or1k64bf,l_fl1) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = or1k64bf_fl1 (current_cpu, GET_H_GPR (FLD (f_r2)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1355,7 +1518,7 @@ SEM_FN_NAME (or1k64bf,l_andi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ANDDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1376,7 +1539,7 @@ SEM_FN_NAME (or1k64bf,l_ori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ORDI (GET_H_GPR (FLD (f_r2)), ZEXTSIDI (FLD (f_uimm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1397,7 +1560,7 @@ SEM_FN_NAME (or1k64bf,l_xori) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = XORDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1420,17 +1583,17 @@ SEM_FN_NAME (or1k64bf,l_addi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), 0);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), 0);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
UDI opval = ADDDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1460,17 +1623,17 @@ SEM_FN_NAME (or1k64bf,l_addic) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = ADDCFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'x', opval);
}
{
BI opval = ADDOFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'x', opval);
}
{
DI opval = ADDCDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)), tmp_tmp_sys_sr_cy);
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1498,17 +1661,17 @@ SEM_FN_NAME (or1k64bf,l_muli) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = MUL2OFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_OV (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-ov", 'D', opval);
}
{
UDI opval = MUL1OFDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_CY (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-cy", 'D', opval);
}
{
UDI opval = MULDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
if (ANDIF (GET_H_SYS_SR_OV (), GET_H_SYS_SR_OVE ())) {
@@ -1534,7 +1697,7 @@ SEM_FN_NAME (or1k64bf,l_exths) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = EXTHIDI (TRUNCDIHI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1555,7 +1718,7 @@ SEM_FN_NAME (or1k64bf,l_extbs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = EXTQIDI (TRUNCDIQI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1576,7 +1739,7 @@ SEM_FN_NAME (or1k64bf,l_exthz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ZEXTHIDI (TRUNCDIHI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1597,7 +1760,7 @@ SEM_FN_NAME (or1k64bf,l_extbz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ZEXTQIDI (TRUNCDIQI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1618,7 +1781,7 @@ SEM_FN_NAME (or1k64bf,l_extws) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = EXTSIDI (TRUNCDISI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1639,7 +1802,7 @@ SEM_FN_NAME (or1k64bf,l_extwz) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = ZEXTSISI (TRUNCDISI (GET_H_GPR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -1662,14 +1825,14 @@ if (GET_H_SYS_SR_F ()) {
UDI opval = GET_H_GPR (FLD (f_r2));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 3);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
} else {
{
UDI opval = GET_H_GPR (FLD (f_r3));
SET_H_GPR (FLD (f_r1), opval);
written |= (1 << 3);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
}
@@ -1692,7 +1855,7 @@ SEM_FN_NAME (or1k64bf,l_sfgts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1713,7 +1876,7 @@ SEM_FN_NAME (or1k64bf,l_sfgtsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = GTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1734,7 +1897,7 @@ SEM_FN_NAME (or1k64bf,l_sfgtu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1755,7 +1918,7 @@ SEM_FN_NAME (or1k64bf,l_sfgtui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = GTUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1776,7 +1939,7 @@ SEM_FN_NAME (or1k64bf,l_sfges) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1797,7 +1960,7 @@ SEM_FN_NAME (or1k64bf,l_sfgesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = GEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1818,7 +1981,7 @@ SEM_FN_NAME (or1k64bf,l_sfgeu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1839,7 +2002,7 @@ SEM_FN_NAME (or1k64bf,l_sfgeui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = GEUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1860,7 +2023,7 @@ SEM_FN_NAME (or1k64bf,l_sflts) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1881,7 +2044,7 @@ SEM_FN_NAME (or1k64bf,l_sfltsi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = LTDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1902,7 +2065,7 @@ SEM_FN_NAME (or1k64bf,l_sfltu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1923,7 +2086,7 @@ SEM_FN_NAME (or1k64bf,l_sfltui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = LTUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1944,7 +2107,7 @@ SEM_FN_NAME (or1k64bf,l_sfles) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1965,7 +2128,7 @@ SEM_FN_NAME (or1k64bf,l_sflesi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = LEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -1986,7 +2149,7 @@ SEM_FN_NAME (or1k64bf,l_sfleu) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -2007,7 +2170,7 @@ SEM_FN_NAME (or1k64bf,l_sfleui) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = LEUDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -2028,7 +2191,7 @@ SEM_FN_NAME (or1k64bf,l_sfeq) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = EQDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -2049,7 +2212,7 @@ SEM_FN_NAME (or1k64bf,l_sfeqi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = EQDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -2070,7 +2233,7 @@ SEM_FN_NAME (or1k64bf,l_sfne) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = NEDI (GET_H_GPR (FLD (f_r2)), GET_H_GPR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -2091,7 +2254,7 @@ SEM_FN_NAME (or1k64bf,l_sfnei) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
UDI opval = NEDI (GET_H_GPR (FLD (f_r2)), EXTSIDI (FLD (f_simm16)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'D', opval);
}
return vpc;
@@ -2117,12 +2280,12 @@ SEM_FN_NAME (or1k64bf,l_mac) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2149,12 +2312,12 @@ SEM_FN_NAME (or1k64bf,l_msb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2181,12 +2344,12 @@ SEM_FN_NAME (or1k64bf,l_maci) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SI opval = SUBWORDDISI (tmp_result, 0);
SET_H_MAC_MACHI (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-machi", 'x', opval);
}
{
SI opval = SUBWORDDISI (tmp_result, 1);
SET_H_MAC_MACLO (opval);
- TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "mac-maclo", 'x', opval);
}
}
@@ -2344,7 +2507,7 @@ SEM_FN_NAME (or1k64bf,lf_add_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2365,7 +2528,7 @@ SEM_FN_NAME (or1k64bf,lf_add_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
return vpc;
@@ -2386,7 +2549,7 @@ SEM_FN_NAME (or1k64bf,lf_sub_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->subsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2407,7 +2570,7 @@ SEM_FN_NAME (or1k64bf,lf_sub_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->subdf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
return vpc;
@@ -2428,7 +2591,7 @@ SEM_FN_NAME (or1k64bf,lf_mul_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2449,7 +2612,7 @@ SEM_FN_NAME (or1k64bf,lf_mul_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
return vpc;
@@ -2470,7 +2633,7 @@ SEM_FN_NAME (or1k64bf,lf_div_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->divsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2491,7 +2654,7 @@ SEM_FN_NAME (or1k64bf,lf_div_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->divdf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
return vpc;
@@ -2512,7 +2675,7 @@ SEM_FN_NAME (or1k64bf,lf_rem_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->remsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2533,7 +2696,7 @@ SEM_FN_NAME (or1k64bf,lf_rem_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->moddf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
return vpc;
@@ -2554,7 +2717,7 @@ SEM_FN_NAME (or1k64bf,lf_itof_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->floatsisf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), TRUNCDISI (GET_H_GPR (FLD (f_r2))));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2575,7 +2738,7 @@ SEM_FN_NAME (or1k64bf,lf_itof_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->floatdidf (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_GPR (FLD (f_r2)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
return vpc;
@@ -2596,7 +2759,7 @@ SEM_FN_NAME (or1k64bf,lf_ftoi_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DI opval = EXTSIDI (CGEN_CPU_FPU (current_cpu)->ops->fixsfsi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FSR (FLD (f_r2))));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -2617,7 +2780,7 @@ SEM_FN_NAME (or1k64bf,lf_ftoi_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DI opval = CGEN_CPU_FPU (current_cpu)->ops->fixdfdi (CGEN_CPU_FPU (current_cpu), (GET_H_SYS_FPCSR_RM () == 0) ? (1) : (GET_H_SYS_FPCSR_RM () == 1) ? (3) : (GET_H_SYS_FPCSR_RM () == 2) ? (4) : (5), GET_H_FDR (FLD (f_r1)));
SET_H_GPR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "gpr", 'D', opval);
}
return vpc;
@@ -2638,7 +2801,7 @@ SEM_FN_NAME (or1k64bf,lf_eq_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2659,7 +2822,7 @@ SEM_FN_NAME (or1k64bf,lf_eq_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->eqdf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2680,7 +2843,7 @@ SEM_FN_NAME (or1k64bf,lf_ne_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->nesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2701,7 +2864,7 @@ SEM_FN_NAME (or1k64bf,lf_ne_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->nedf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2722,7 +2885,7 @@ SEM_FN_NAME (or1k64bf,lf_ge_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2743,7 +2906,7 @@ SEM_FN_NAME (or1k64bf,lf_ge_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gedf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2764,7 +2927,7 @@ SEM_FN_NAME (or1k64bf,lf_gt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2785,7 +2948,7 @@ SEM_FN_NAME (or1k64bf,lf_gt_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->gtdf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2806,7 +2969,7 @@ SEM_FN_NAME (or1k64bf,lf_lt_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2827,7 +2990,7 @@ SEM_FN_NAME (or1k64bf,lf_lt_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->ltdf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2848,7 +3011,7 @@ SEM_FN_NAME (or1k64bf,lf_le_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->lesf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2869,7 +3032,7 @@ SEM_FN_NAME (or1k64bf,lf_le_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
BI opval = CGEN_CPU_FPU (current_cpu)->ops->ledf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1)));
SET_H_SYS_SR_F (opval);
- TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "sys-sr-f", 'x', opval);
}
return vpc;
@@ -2890,7 +3053,7 @@ SEM_FN_NAME (or1k64bf,lf_madd_s) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
SF opval = CGEN_CPU_FPU (current_cpu)->ops->addsf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->mulsf (CGEN_CPU_FPU (current_cpu), GET_H_FSR (FLD (f_r2)), GET_H_FSR (FLD (f_r3))), GET_H_FSR (FLD (f_r1)));
SET_H_FSR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fsr", 'f', opval);
}
return vpc;
@@ -2911,7 +3074,7 @@ SEM_FN_NAME (or1k64bf,lf_madd_d) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
{
DF opval = CGEN_CPU_FPU (current_cpu)->ops->adddf (CGEN_CPU_FPU (current_cpu), CGEN_CPU_FPU (current_cpu)->ops->muldf (CGEN_CPU_FPU (current_cpu), GET_H_FDR (FLD (f_r1)), GET_H_FDR (FLD (f_r1))), GET_H_FDR (FLD (f_r1)));
SET_H_FDR (FLD (f_r1), opval);
- TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
+ CGEN_TRACE_RESULT (current_cpu, abuf, "fdr", 'f', opval);
}
return vpc;
@@ -2969,6 +3132,9 @@ static const struct sem_fn_desc sem_fns[] = {
{ OR1K64BF_INSN_L_BF, SEM_FN_NAME (or1k64bf,l_bf) },
{ OR1K64BF_INSN_L_TRAP, SEM_FN_NAME (or1k64bf,l_trap) },
{ OR1K64BF_INSN_L_SYS, SEM_FN_NAME (or1k64bf,l_sys) },
+ { OR1K64BF_INSN_L_MSYNC, SEM_FN_NAME (or1k64bf,l_msync) },
+ { OR1K64BF_INSN_L_PSYNC, SEM_FN_NAME (or1k64bf,l_psync) },
+ { OR1K64BF_INSN_L_CSYNC, SEM_FN_NAME (or1k64bf,l_csync) },
{ OR1K64BF_INSN_L_RFE, SEM_FN_NAME (or1k64bf,l_rfe) },
{ OR1K64BF_INSN_L_NOP_IMM, SEM_FN_NAME (or1k64bf,l_nop_imm) },
{ OR1K64BF_INSN_L_MOVHI, SEM_FN_NAME (or1k64bf,l_movhi) },
@@ -2977,6 +3143,7 @@ static const struct sem_fn_desc sem_fns[] = {
{ OR1K64BF_INSN_L_MTSPR, SEM_FN_NAME (or1k64bf,l_mtspr) },
{ OR1K64BF_INSN_L_LWZ, SEM_FN_NAME (or1k64bf,l_lwz) },
{ OR1K64BF_INSN_L_LWS, SEM_FN_NAME (or1k64bf,l_lws) },
+ { OR1K64BF_INSN_L_LWA, SEM_FN_NAME (or1k64bf,l_lwa) },
{ OR1K64BF_INSN_L_LBZ, SEM_FN_NAME (or1k64bf,l_lbz) },
{ OR1K64BF_INSN_L_LBS, SEM_FN_NAME (or1k64bf,l_lbs) },
{ OR1K64BF_INSN_L_LHZ, SEM_FN_NAME (or1k64bf,l_lhz) },
@@ -2984,6 +3151,7 @@ static const struct sem_fn_desc sem_fns[] = {
{ OR1K64BF_INSN_L_SW, SEM_FN_NAME (or1k64bf,l_sw) },
{ OR1K64BF_INSN_L_SB, SEM_FN_NAME (or1k64bf,l_sb) },
{ OR1K64BF_INSN_L_SH, SEM_FN_NAME (or1k64bf,l_sh) },
+ { OR1K64BF_INSN_L_SWA, SEM_FN_NAME (or1k64bf,l_swa) },
{ OR1K64BF_INSN_L_SLL, SEM_FN_NAME (or1k64bf,l_sll) },
{ OR1K64BF_INSN_L_SLLI, SEM_FN_NAME (or1k64bf,l_slli) },
{ OR1K64BF_INSN_L_SRL, SEM_FN_NAME (or1k64bf,l_srl) },
--
2.7.4
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