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From: Stafford Horne <shorne@gmail.com>
To: gdb-patches@sourceware.org
Cc: openrisc@lists.librecores.org, Peter Gavin <pgavin@gmail.com>
Subject: [PATCH 07/18] sim: or1k: remove erroneous warning message in sim/or1k/or1k.c
Date: Wed, 23 Nov 2016 22:14:00 -0000	[thread overview]
Message-ID: <1479939272-1754-8-git-send-email-shorne@gmail.com> (raw)
In-Reply-To: <1479939272-1754-1-git-send-email-shorne@gmail.com>

From: Peter Gavin <pgavin@gmail.com>

sim/or1k/ChangeLog:

	* or1k.c (or1k32bf_make_load_store_addr): remove stupid erroneous warning
	message
---
 sim/or1k/ChangeLog | 6 ++++++
 sim/or1k/or1k.c    | 5 -----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/sim/or1k/ChangeLog b/sim/or1k/ChangeLog
index 90dc44a..ccc2c85 100644
--- a/sim/or1k/ChangeLog
+++ b/sim/or1k/ChangeLog
@@ -1,5 +1,11 @@
 2012-06-22  Peter Gavin  <pgavin@gmail.com>
 
+	* or1k.c:
+	(or1k32bf_make_load_store_addr) remove stupid erroneous warning
+	message
+
+2012-06-22  Peter Gavin  <pgavin@gmail.com>
+
 	* configure: regenerated
 
 2012-06-22  Peter Gavin  <pgavin@gmail.com>
diff --git a/sim/or1k/or1k.c b/sim/or1k/or1k.c
index 45147d2..776e720 100644
--- a/sim/or1k/or1k.c
+++ b/sim/or1k/or1k.c
@@ -187,11 +187,6 @@ USI or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset, in
 {
   SIM_DESC sd = CPU_STATE(current_cpu);
 
-  if (!GET_H_SYS_SR_SM ()) {
-    sim_io_eprintf(sd, "WARNING: l.mfspr in user mode\n");
-    return;
-  }
-  
   USI addr = base + offset;
   
   if (GET_H_SYS_SR_LEE ()) {
-- 
2.7.4


  reply	other threads:[~2016-11-23 22:14 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-23 22:14 [PATCH 00/18] sim: port for OpenRISC Stafford Horne
2016-11-23 22:14 ` Stafford Horne [this message]
2016-11-23 22:14 ` [PATCH 05/18] sim: or1k: add NOP_EXIT_SILENT; make simulator print exit code for NOP_EXIT; Stafford Horne
2016-11-23 22:14 ` [PATCH 08/18] sim: or1k: fix fl1 in sim Stafford Horne
2016-11-23 22:14 ` [PATCH 11/18] sim: or1k: fix segfault when run without arguments Stafford Horne
2016-11-23 22:16 ` [PATCH 03/18] sim: cgen: allow suffix on generated arch.[ch] and cpuall.h Stafford Horne
2016-11-23 22:16 ` [PATCH 06/18] sim: or1k: fix branching and exceptions in sim Stafford Horne
2016-11-23 22:16 ` [PATCH 09/18] sim: or1k: regenerate sim files Stafford Horne
2016-11-23 22:16 ` [PATCH 01/18] sim: cgen: add rem (remainder) function (needed for OR1K lf.rem.[sd]) Stafford Horne
2016-11-23 22:16 ` [PATCH 10/18] sim: testsuite: add testsuite for or1k sim Stafford Horne
2016-11-23 22:16 ` [PATCH 12/18] sim: or1k: Get or1k sim building with latest sim common Stafford Horne
2016-11-23 22:16 ` [PATCH 02/18] sim: cgen: add mul-o1flag, mul-o2flag RTL functions to CGEN Stafford Horne
2016-11-23 22:16 ` [PATCH 17/18] sim: or1k: Implement fetch/store for ppc and sr Stafford Horne
2016-11-23 22:18 ` [PATCH 16/18] sim: or1k: Do trap breakpoint handling Stafford Horne
2016-11-23 22:18 ` [PATCH 13/18] sim: or1k: Regenerate cgen files Stafford Horne
2016-11-23 22:18 ` [PATCH 15/18] sim: or1k: Implement register store/fetch Stafford Horne
2016-11-23 22:32 ` [PATCH 18/18] sim: or1k: add additional stubs for linux build Stafford Horne
2016-11-23 23:04 ` [PATCH 00/18] sim: port for OpenRISC Stafford Horne
2016-11-25 16:19 ` Mike Frysinger
2016-11-25 22:46   ` Stafford Horne
2016-12-05  8:41     ` Stafford Horne
2016-12-16 20:34       ` Mike Frysinger
2016-12-17  4:18         ` Stafford Horne
2016-12-18  4:33           ` Mike Frysinger

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