From: Stafford Horne <shorne@gmail.com>
To: gdb-patches@sourceware.org
Cc: openrisc@lists.librecores.org, Stafford Horne <shorne@gmail.com>
Subject: [PATCH 00/18] sim: port for OpenRISC
Date: Wed, 23 Nov 2016 22:14:00 -0000 [thread overview]
Message-ID: <1479939272-1754-1-git-send-email-shorne@gmail.com> (raw)
Hello,
Please find attached the sim patches that allow to get a basic OpenRISC
system running. This was used to verify the OpenRISC gdb port.
The main author is Peter Gavin who should have his FSF copyright in place.
Also some new tests were added specifically for openrisc. Please see the
details of running the testsuite for sim below:
=== sim Summary ===
# of expected passes 17
/home/shorne/work/openrisc/build-gdb/sim/or1k/run 0.5
Thanks,
-Stafford
Peter Gavin (11):
sim: cgen: add rem (remainder) function (needed for OR1K lf.rem.[sd])
sim: cgen: add mul-o1flag, mul-o2flag RTL functions to CGEN
sim: cgen: allow suffix on generated arch.[ch] and cpuall.h
sim: or1k: add or1k target to sim
sim: or1k: add NOP_EXIT_SILENT; make simulator print exit code for
NOP_EXIT;
sim: or1k: fix branching and exceptions in sim
sim: or1k: remove erroneous warning message in sim/or1k/or1k.c
sim: or1k: fix fl1 in sim
sim: or1k: regenerate sim files
sim: testsuite: add testsuite for or1k sim
sim: or1k: fix segfault when run without arguments
Stafford Horne (7):
sim: or1k: Get or1k sim building with latest sim common
sim: or1k: Regenerate cgen files
sim: or1k: Regenerate autotool files
sim: or1k: Implement register store/fetch
sim: or1k: Do trap breakpoint handling
sim: or1k: Implement fetch/store for ppc and sr
sim: or1k: add additional stubs for linux build
next reply other threads:[~2016-11-23 22:14 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-23 22:14 Stafford Horne [this message]
2016-11-23 22:14 ` [PATCH 07/18] sim: or1k: remove erroneous warning message in sim/or1k/or1k.c Stafford Horne
2016-11-23 22:14 ` [PATCH 08/18] sim: or1k: fix fl1 in sim Stafford Horne
2016-11-23 22:14 ` [PATCH 05/18] sim: or1k: add NOP_EXIT_SILENT; make simulator print exit code for NOP_EXIT; Stafford Horne
2016-11-23 22:14 ` [PATCH 11/18] sim: or1k: fix segfault when run without arguments Stafford Horne
2016-11-23 22:16 ` [PATCH 03/18] sim: cgen: allow suffix on generated arch.[ch] and cpuall.h Stafford Horne
2016-11-23 22:16 ` [PATCH 09/18] sim: or1k: regenerate sim files Stafford Horne
2016-11-23 22:16 ` [PATCH 06/18] sim: or1k: fix branching and exceptions in sim Stafford Horne
2016-11-23 22:16 ` [PATCH 01/18] sim: cgen: add rem (remainder) function (needed for OR1K lf.rem.[sd]) Stafford Horne
2016-11-23 22:16 ` [PATCH 10/18] sim: testsuite: add testsuite for or1k sim Stafford Horne
2016-11-23 22:16 ` [PATCH 12/18] sim: or1k: Get or1k sim building with latest sim common Stafford Horne
2016-11-23 22:16 ` [PATCH 02/18] sim: cgen: add mul-o1flag, mul-o2flag RTL functions to CGEN Stafford Horne
2016-11-23 22:16 ` [PATCH 17/18] sim: or1k: Implement fetch/store for ppc and sr Stafford Horne
2016-11-23 22:18 ` [PATCH 16/18] sim: or1k: Do trap breakpoint handling Stafford Horne
2016-11-23 22:18 ` [PATCH 13/18] sim: or1k: Regenerate cgen files Stafford Horne
2016-11-23 22:18 ` [PATCH 15/18] sim: or1k: Implement register store/fetch Stafford Horne
2016-11-23 22:32 ` [PATCH 18/18] sim: or1k: add additional stubs for linux build Stafford Horne
2016-11-23 23:04 ` [PATCH 00/18] sim: port for OpenRISC Stafford Horne
2016-11-25 16:19 ` Mike Frysinger
2016-11-25 22:46 ` Stafford Horne
2016-12-05 8:41 ` Stafford Horne
2016-12-16 20:34 ` Mike Frysinger
2016-12-17 4:18 ` Stafford Horne
2016-12-18 4:33 ` Mike Frysinger
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