From: Stafford Horne <shorne@gmail.com>
To: gdb-patches@sourceware.org
Cc: openrisc@lists.librecores.org, Peter Gavin <pgavin@gmail.com>
Subject: [PATCH 11/18] sim: or1k: fix segfault when run without arguments
Date: Wed, 23 Nov 2016 22:14:00 -0000 [thread overview]
Message-ID: <1479939272-1754-12-git-send-email-shorne@gmail.com> (raw)
In-Reply-To: <1479939272-1754-1-git-send-email-shorne@gmail.com>
From: Peter Gavin <pgavin@gmail.com>
sim/or1k/ChangeLog:
* sim-if.c: (sim_open) push check for delay slot mode further down
in function so other checks happen first. This prevents a
segfault when the simulator is run without arguments.
---
sim/or1k/ChangeLog | 6 ++++++
sim/or1k/sim-if.c | 19 ++++++++++---------
2 files changed, 16 insertions(+), 9 deletions(-)
diff --git a/sim/or1k/ChangeLog b/sim/or1k/ChangeLog
index c1038c3..ff7ca8d 100644
--- a/sim/or1k/ChangeLog
+++ b/sim/or1k/ChangeLog
@@ -1,3 +1,9 @@
+2012-09-06 Peter Gavin <pgavin@gmail.com>
+
+ * sim-if.c: (sim_open) push check for delay slot mode further down
+ in function so other checks happen first. This prevents a
+ segfault when the simulator is run without arguments.
+
2012-06-22 Peter Gavin <pgavin@gmail.com>
* cpu32.c: regenerate
diff --git a/sim/or1k/sim-if.c b/sim/or1k/sim-if.c
index c257ae6..23a8a9e 100644
--- a/sim/or1k/sim-if.c
+++ b/sim/or1k/sim-if.c
@@ -235,14 +235,6 @@ sim_open (kind, callback, abfd, argv)
return 0;
}
- if ((or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) &&
- (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1knd)) {
- sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag set, but loading non-or1knd binary\n");
- } else if (!(or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) &&
- (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1k)) {
- sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag not set, but loading non-or1k binary\n");
- }
-
/* Establish any remaining configuration options. */
if (sim_config (sd) != SIM_RC_OK)
{
@@ -255,7 +247,16 @@ sim_open (kind, callback, abfd, argv)
free_state (sd);
return 0;
}
-
+
+ /* make sure delay slot mode is consistent with the loaded binary */
+ if ((or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) &&
+ (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1knd)) {
+ sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag set, but loading non-or1knd binary\n");
+ } else if (!(or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) &&
+ (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1k)) {
+ sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag not set, but loading non-or1k binary\n");
+ }
+
/* Open a copy of the cpu descriptor table. */
{
CGEN_CPU_DESC cd = or1k_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,
--
2.7.4
next prev parent reply other threads:[~2016-11-23 22:14 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-23 22:14 [PATCH 00/18] sim: port for OpenRISC Stafford Horne
2016-11-23 22:14 ` [PATCH 07/18] sim: or1k: remove erroneous warning message in sim/or1k/or1k.c Stafford Horne
2016-11-23 22:14 ` [PATCH 05/18] sim: or1k: add NOP_EXIT_SILENT; make simulator print exit code for NOP_EXIT; Stafford Horne
2016-11-23 22:14 ` [PATCH 08/18] sim: or1k: fix fl1 in sim Stafford Horne
2016-11-23 22:14 ` Stafford Horne [this message]
2016-11-23 22:16 ` [PATCH 03/18] sim: cgen: allow suffix on generated arch.[ch] and cpuall.h Stafford Horne
2016-11-23 22:16 ` [PATCH 06/18] sim: or1k: fix branching and exceptions in sim Stafford Horne
2016-11-23 22:16 ` [PATCH 09/18] sim: or1k: regenerate sim files Stafford Horne
2016-11-23 22:16 ` [PATCH 01/18] sim: cgen: add rem (remainder) function (needed for OR1K lf.rem.[sd]) Stafford Horne
2016-11-23 22:16 ` [PATCH 10/18] sim: testsuite: add testsuite for or1k sim Stafford Horne
2016-11-23 22:16 ` [PATCH 12/18] sim: or1k: Get or1k sim building with latest sim common Stafford Horne
2016-11-23 22:16 ` [PATCH 02/18] sim: cgen: add mul-o1flag, mul-o2flag RTL functions to CGEN Stafford Horne
2016-11-23 22:16 ` [PATCH 17/18] sim: or1k: Implement fetch/store for ppc and sr Stafford Horne
2016-11-23 22:18 ` [PATCH 16/18] sim: or1k: Do trap breakpoint handling Stafford Horne
2016-11-23 22:18 ` [PATCH 13/18] sim: or1k: Regenerate cgen files Stafford Horne
2016-11-23 22:18 ` [PATCH 15/18] sim: or1k: Implement register store/fetch Stafford Horne
2016-11-23 22:32 ` [PATCH 18/18] sim: or1k: add additional stubs for linux build Stafford Horne
2016-11-23 23:04 ` [PATCH 00/18] sim: port for OpenRISC Stafford Horne
2016-11-25 16:19 ` Mike Frysinger
2016-11-25 22:46 ` Stafford Horne
2016-12-05 8:41 ` Stafford Horne
2016-12-16 20:34 ` Mike Frysinger
2016-12-17 4:18 ` Stafford Horne
2016-12-18 4:33 ` Mike Frysinger
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