From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 74431 invoked by alias); 23 Nov 2016 22:14:58 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 71003 invoked by uid 89); 23 Nov 2016 22:14:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pg0-f65.google.com Received: from mail-pg0-f65.google.com (HELO mail-pg0-f65.google.com) (74.125.83.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Nov 2016 22:14:44 +0000 Received: by mail-pg0-f65.google.com with SMTP id x23so1927196pgx.3 for ; Wed, 23 Nov 2016 14:14:43 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=h8/yQG8j1k1yBOLJXGMs7fsc8M6LxH+VEg56hglu1Ho=; b=h10O3yw2ZD/KPqfu2qNiDYMBzf2ugsXZ9wqiZnrcLiehPVX7rYYTh6LLdT97gY95/Z jxjsAN9RhNyUSeeHiBVQOBrjU1jftMJ+HgxDlsV1GKa29O7CB4mCoyoSl6hlT3/hPmXs hxQ7i1JU/lpRywtN28tZm9qfTEZ9Zh9AfZbYpHy5cSz4xZcmGPyMPXqDoWjjefwFMNzH evT8fKNWRRWyiS8eE9pHdteDnXcxnrdFyjAxXsdUWkhVJ3riBiLBg1s6xXYVDpJufjAb frH8GvfA3fp2UobLbGOSf6LbLqcWSnZ2NfSpRbSt0lWsrNASodb5aYMfjJCrnAV6JMqr l0tQ== X-Gm-Message-State: AKaTC00C7Vbfoj+U+HQz5nn2gb9M3g9SAIUCNO48l6xDK0CJCOSdK2P1osIaPsXXbn8eeQ== X-Received: by 10.84.197.129 with SMTP id n1mr11339090pld.30.1479939282643; Wed, 23 Nov 2016 14:14:42 -0800 (PST) Received: from lianli.shorne-pla.net (z14.124-44-185.ppp.wakwak.ne.jp. [124.44.185.14]) by smtp.gmail.com with ESMTPSA id t20sm54975043pfk.48.2016.11.23.14.14.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Nov 2016 14:14:41 -0800 (PST) Received: from lianli.shorne-pla.net (localhost [127.0.0.1]) by lianli.shorne-pla.net (8.15.2/8.15.2) with ESMTPS id uANMEcuo001960 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 24 Nov 2016 07:14:38 +0900 Received: (from shorne@localhost) by lianli.shorne-pla.net (8.15.2/8.15.2/Submit) id uANMEcUT001959; Thu, 24 Nov 2016 07:14:38 +0900 From: Stafford Horne To: gdb-patches@sourceware.org Cc: openrisc@lists.librecores.org, Peter Gavin Subject: [PATCH 11/18] sim: or1k: fix segfault when run without arguments Date: Wed, 23 Nov 2016 22:14:00 -0000 Message-Id: <1479939272-1754-12-git-send-email-shorne@gmail.com> In-Reply-To: <1479939272-1754-1-git-send-email-shorne@gmail.com> References: <1479939272-1754-1-git-send-email-shorne@gmail.com> X-IsSubscribed: yes X-SW-Source: 2016-11/txt/msg00711.txt.bz2 From: Peter Gavin sim/or1k/ChangeLog: * sim-if.c: (sim_open) push check for delay slot mode further down in function so other checks happen first. This prevents a segfault when the simulator is run without arguments. --- sim/or1k/ChangeLog | 6 ++++++ sim/or1k/sim-if.c | 19 ++++++++++--------- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/sim/or1k/ChangeLog b/sim/or1k/ChangeLog index c1038c3..ff7ca8d 100644 --- a/sim/or1k/ChangeLog +++ b/sim/or1k/ChangeLog @@ -1,3 +1,9 @@ +2012-09-06 Peter Gavin + + * sim-if.c: (sim_open) push check for delay slot mode further down + in function so other checks happen first. This prevents a + segfault when the simulator is run without arguments. + 2012-06-22 Peter Gavin * cpu32.c: regenerate diff --git a/sim/or1k/sim-if.c b/sim/or1k/sim-if.c index c257ae6..23a8a9e 100644 --- a/sim/or1k/sim-if.c +++ b/sim/or1k/sim-if.c @@ -235,14 +235,6 @@ sim_open (kind, callback, abfd, argv) return 0; } - if ((or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) && - (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1knd)) { - sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag set, but loading non-or1knd binary\n"); - } else if (!(or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) && - (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1k)) { - sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag not set, but loading non-or1k binary\n"); - } - /* Establish any remaining configuration options. */ if (sim_config (sd) != SIM_RC_OK) { @@ -255,7 +247,16 @@ sim_open (kind, callback, abfd, argv) free_state (sd); return 0; } - + + /* make sure delay slot mode is consistent with the loaded binary */ + if ((or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) && + (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1knd)) { + sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag set, but loading non-or1knd binary\n"); + } else if (!(or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) && + (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1k)) { + sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag not set, but loading non-or1k binary\n"); + } + /* Open a copy of the cpu descriptor table. */ { CGEN_CPU_DESC cd = or1k_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, -- 2.7.4