From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 74231 invoked by alias); 23 Nov 2016 22:14:58 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 71071 invoked by uid 89); 23 Nov 2016 22:14:48 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=cia, H*RU:209.85.192.196, Hx-spam-relays-external:209.85.192.196, vpc X-HELO: mail-pf0-f196.google.com Received: from mail-pf0-f196.google.com (HELO mail-pf0-f196.google.com) (209.85.192.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Nov 2016 22:14:46 +0000 Received: by mail-pf0-f196.google.com with SMTP id 144so1049432pfv.0 for ; Wed, 23 Nov 2016 14:14:45 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6VMj3muaCEIkLKqUDr9nGEBpIWDPVOpD6Z7FCZiygJU=; b=eHvTDm0l+xO/OHhSQChqx0MHv5Gv3bkliBl3Zqu1D0BA1qCKbvehxVl9qP1VjwYbne DwbLUir/LEw9QjWPF/RyIMg0SoCHYTQIsfDB2oTmR1U/Ez9uvKkI8Pmsp8IeBgOAYObZ o+WlbOeFHuDKWz62mCfiOcG0FYN3+PcTxwvSpQhhI6xS1hAzGcWPWpJCOPWxqwC8INd1 9fC/Vt0FMnWQNHAO6gVCHT5c9FGjg9XWbqqa7ppAihn9gbgvMiPVPCkNF6M9iV5LIwPl BKWxMURSd/M36ZxRrmrr4j1r51PLcE7S1QNoMp7ZjGhNe5Eck+iKMmKFP+65qhKifPnu wINA== X-Gm-Message-State: AKaTC01b7LK9Gpa+5huYgbog/as0/JkFyEMm39v4upKMFMLT4OWoJ5IfiNKjuCJkcLfwYg== X-Received: by 10.98.157.148 with SMTP id a20mr5084154pfk.1.1479939284239; Wed, 23 Nov 2016 14:14:44 -0800 (PST) Received: from lianli.shorne-pla.net (z14.124-44-185.ppp.wakwak.ne.jp. [124.44.185.14]) by smtp.gmail.com with ESMTPSA id o29sm18629523pgn.28.2016.11.23.14.14.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Nov 2016 14:14:42 -0800 (PST) Received: from lianli.shorne-pla.net (localhost [127.0.0.1]) by lianli.shorne-pla.net (8.15.2/8.15.2) with ESMTPS id uANMEduv001980 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 24 Nov 2016 07:14:39 +0900 Received: (from shorne@localhost) by lianli.shorne-pla.net (8.15.2/8.15.2/Submit) id uANMEdGL001979; Thu, 24 Nov 2016 07:14:39 +0900 From: Stafford Horne To: gdb-patches@sourceware.org Cc: openrisc@lists.librecores.org, Stafford Horne Subject: [PATCH 16/18] sim: or1k: Do trap breakpoint handling Date: Wed, 23 Nov 2016 22:18:00 -0000 Message-Id: <1479939272-1754-17-git-send-email-shorne@gmail.com> In-Reply-To: <1479939272-1754-1-git-send-email-shorne@gmail.com> References: <1479939272-1754-1-git-send-email-shorne@gmail.com> X-IsSubscribed: yes X-SW-Source: 2016-11/txt/msg00725.txt.bz2 Breakpoints were not implemented in the sim. This change allows for trap instructions (inserted when gdb sets breakpoints) to transfer control back to GDB allowing breakpoints to work with 'target sim' After implementing this gdb test suite is looking better with: === gdb Summary === # of expected passes 15981 # of unexpected failures 509 # of expected failures 27 # of known failures 47 # of unresolved testcases 34 # of untested testcases 174 # of unsupported tests 309 --- sim/or1k/traps.c | 70 ++++++++++++++++++++++++++++++-------------------------- 1 file changed, 37 insertions(+), 33 deletions(-) diff --git a/sim/or1k/traps.c b/sim/or1k/traps.c index 526f2e7..235d9b5 100644 --- a/sim/or1k/traps.c +++ b/sim/or1k/traps.c @@ -17,48 +17,52 @@ sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc) #ifdef WANT_CPU_OR1K32BF or1k32bf_exception (current_cpu, cia, EXCEPT_ILLEGAL); #endif - + return vpc; } void or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum) { SIM_DESC sd = CPU_STATE(current_cpu); - - SET_H_SYS_ESR0 (GET_H_SYS_SR ()); - - SET_H_SYS_SR_DSX (current_cpu->delay_slot); - - switch (exnum) { - case EXCEPT_RESET: - break; - case EXCEPT_SYSCALL: - SET_H_SYS_EPCR0 (pc + 4 - (current_cpu->delay_slot ? 4 : 0)); - break; + if (exnum == EXCEPT_TRAP) { + /* Trap, used for breakpoints, sends control back to gdb breakpoint handling */ + sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP); + } else { + + /* Calculate the exception program counter */ + switch (exnum) { + case EXCEPT_RESET: + break; + + case EXCEPT_SYSCALL: + SET_H_SYS_EPCR0 (pc + 4 - (current_cpu->delay_slot ? 4 : 0)); + break; + + case EXCEPT_BUSERR: + case EXCEPT_ALIGN: + case EXCEPT_ILLEGAL: + SET_H_SYS_EPCR0 (pc - (current_cpu->delay_slot ? 4 : 0)); + break; + + default: + sim_io_error (sd, "unexpected exception 0x%x raised at PC 0x%08x", exnum, pc); + break; + } - case EXCEPT_BUSERR: - case EXCEPT_ALIGN: - case EXCEPT_RANGE: - case EXCEPT_TRAP: - case EXCEPT_ILLEGAL: - SET_H_SYS_EPCR0 (pc - (current_cpu->delay_slot ? 4 : 0)); - break; + /* Store the curent SR into ESR0 */ + SET_H_SYS_ESR0 (GET_H_SYS_SR ()); - default: - sim_io_error (sd, "unexpected exception 0x%x raised at PC 0x%08x", exnum, pc); - break; - + /* Indicate in SR if the failed instruction is in delay slot or not */ + SET_H_SYS_SR_DSX (current_cpu->delay_slot); + + current_cpu->next_delay_slot = 0; + + /* jump program counter into handler */ + IADDR handler_pc = (GET_H_SYS_SR_EPH() ? 0xf0000000 : 0x00000000) + (exnum << 8); + + sim_engine_restart (sd, current_cpu, NULL, handler_pc); } - - current_cpu->next_delay_slot = 0; - - IADDR handler_pc = (GET_H_SYS_SR_EPH() ? 0xf0000000 : 0x00000000) + (exnum << 8); - - sim_engine_restart (CPU_STATE (current_cpu), - current_cpu, - NULL, - handler_pc); } void or1k32bf_rfe (sim_cpu *current_cpu) @@ -97,8 +101,8 @@ USI or1k32bf_mfspr (sim_cpu *current_cpu, USI addr) case SPR_ADDR(SYS,PPC): case SPR_ADDR(SYS,FPCSR): case SPR_ADDR(SYS,EPCR0): - case SPR_ADDR(MAC,MACHI): case SPR_ADDR(MAC,MACLO): + case SPR_ADDR(MAC,MACHI): break; default: -- 2.7.4