From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 73373 invoked by alias); 23 Nov 2016 22:14:55 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 70689 invoked by uid 89); 23 Nov 2016 22:14:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=952, 927, questioning X-HELO: mail-pg0-f66.google.com Received: from mail-pg0-f66.google.com (HELO mail-pg0-f66.google.com) (74.125.83.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Nov 2016 22:14:44 +0000 Received: by mail-pg0-f66.google.com with SMTP id e9so1925933pgc.1 for ; Wed, 23 Nov 2016 14:14:44 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=6VMgoMTxcVfXkm+2rL22hKEPjLYfZfQQVZd0bWf3JDc=; b=BhEgZM7a8A347cr5aAnnxT++N6UqispTSQWNP7OYOSqsU2yGCtl1WRpmt0ZRIIPkT5 zdnpvLqFuoAKEIifpRipXzLOpsiHKDD2Ap/MaUdmZZhyq6u44J6LEQs0ZFFvD9F6cUJL ZjwG6X9ohVFRS8+zTIwE/mimx2vA71ByVzjxHXRrd2tji0kbY8uivFrx4Lxi7NBHXe7/ ZOJnRXqMMv3VXIVrLd1KGW4C5Z7YMNuDpXEpTyVRea2Wxo2LRjdWsxNgCLLl/5C50t55 CU5O/P2guzThrNmyptghS8VwFEupn5ZPfcesCqviXriuPxjMuXSn759kcJr1COnBBBoj 2d/g== X-Gm-Message-State: AKaTC01CkxTtyl7qmA+omv33guLwHWf73roK5UETmBlxJspu2lCsV2+Y/ItzrMSjUcr30A== X-Received: by 10.84.217.203 with SMTP id d11mr11410928plj.164.1479939283367; Wed, 23 Nov 2016 14:14:43 -0800 (PST) Received: from lianli.shorne-pla.net (z14.124-44-185.ppp.wakwak.ne.jp. [124.44.185.14]) by smtp.gmail.com with ESMTPSA id a1sm37047664pgf.16.2016.11.23.14.14.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Nov 2016 14:14:42 -0800 (PST) Received: from lianli.shorne-pla.net (localhost [127.0.0.1]) by lianli.shorne-pla.net (8.15.2/8.15.2) with ESMTPS id uANMEdVl001976 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 24 Nov 2016 07:14:39 +0900 Received: (from shorne@localhost) by lianli.shorne-pla.net (8.15.2/8.15.2/Submit) id uANMEd8b001975; Thu, 24 Nov 2016 07:14:39 +0900 From: Stafford Horne To: gdb-patches@sourceware.org Cc: openrisc@lists.librecores.org, Stafford Horne Subject: [PATCH 15/18] sim: or1k: Implement register store/fetch Date: Wed, 23 Nov 2016 22:18:00 -0000 Message-Id: <1479939272-1754-16-git-send-email-shorne@gmail.com> In-Reply-To: <1479939272-1754-1-git-send-email-shorne@gmail.com> References: <1479939272-1754-1-git-send-email-shorne@gmail.com> X-IsSubscribed: yes X-SW-Source: 2016-11/txt/msg00727.txt.bz2 There was a comment questioning the use of these. But as soon as I run any basic test gdb complains that these are not implemented. More tests and basic run and execute work now. --- sim/or1k/or1k-sim.h | 2 +- sim/or1k/or1k.c | 31 ++++++++++++++++++++++++++++--- 2 files changed, 29 insertions(+), 4 deletions(-) diff --git a/sim/or1k/or1k-sim.h b/sim/or1k/or1k-sim.h index 9e1754f..7213caa 100644 --- a/sim/or1k/or1k-sim.h +++ b/sim/or1k/or1k-sim.h @@ -4,7 +4,7 @@ #include "symcat.h" /* GDB register numbers. */ -#define PC_REGNUM 16 +#define PC_REGNUM 33 /* Misc. profile data. */ typedef struct { diff --git a/sim/or1k/or1k.c b/sim/or1k/or1k.c index 98225ab..565a018 100644 --- a/sim/or1k/or1k.c +++ b/sim/or1k/or1k.c @@ -9,27 +9,52 @@ #include "sim-main.h" #include "symcat.h" #include "cgen-ops.h" +#include "cgen-mem.h" +#include "cpuall.h" #include -/* not sure what the point of these is */ int XCONCAT2(WANT_CPU,_fetch_register) (sim_cpu *current_cpu, int rn, unsigned char *buf, int len) { - return -1; + if (rn < 32) + SETTWI (buf, XCONCAT2(WANT_CPU,_h_gpr_get) (current_cpu, rn)); + else + switch (rn) + { + case PC_REGNUM : + SETTWI (buf, XCONCAT2(WANT_CPU,_h_pc_get) (current_cpu)); + break; + default : + return 0; + } + return sizeof(WI); /* WI from arch.h */ } int XCONCAT2(WANT_CPU,_store_register) (sim_cpu *current_cpu, int rn, unsigned char *buf, int len) { - return -1; + if (rn < 32) + XCONCAT2(WANT_CPU,_h_gpr_set) (current_cpu, rn, GETTWI (buf)); + else + switch (rn) + { + case PC_REGNUM : + XCONCAT2(WANT_CPU,_h_pc_set) (current_cpu, GETTWI (buf)); + break; + default : + return 0; + } + return sizeof(WI); /* WI from arch.h */ } #ifdef WANT_CPU_OR1K32BF int or1k32bf_model_or1200_u_exec (sim_cpu * UNUSED current_cpu, const IDESC * UNUSED idesc, int unit_num, int referenced) { + return -1; } int or1k32bf_model_or1200nd_u_exec (sim_cpu * UNUSED current_cpu, const IDESC * UNUSED idesc, int unit_num, int referenced) { + return -1; } void or1k32bf_model_insn_before (sim_cpu * UNUSED current_cpu, int UNUSED first_p) -- 2.7.4