From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 92718 invoked by alias); 23 Nov 2016 22:15:51 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 72049 invoked by uid 89); 23 Nov 2016 22:14:51 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.2 spammy=cgen, 936, H*RU:209.85.192.196, Hx-spam-relays-external:209.85.192.196 X-HELO: mail-pf0-f196.google.com Received: from mail-pf0-f196.google.com (HELO mail-pf0-f196.google.com) (209.85.192.196) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Nov 2016 22:14:40 +0000 Received: by mail-pf0-f196.google.com with SMTP id c4so1040639pfb.3 for ; Wed, 23 Nov 2016 14:14:40 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tksfAy9z9E2K8UEvNKI6ANr0n8/ev1hJMM4ahgcb3sE=; b=AAzG3wFUz3kmPLulvpZ3jzzZhwMZ+ZWL29ZzSlaIchxuh6WPBHs7Sbzhr+CcoYhBEG tXnRJ6hARjXb3IYgw8VX9ulflNqOQz6t+2I0IPEmYrAqjnBY3axnbYGj9krH+WgeZtnM n+bcNmbw9UkO+UkbFX9G4IG4ysVIkaE4RlAABxL468/Z6QqlMoitUQVpSeF+NvZnVRIb /Bm5Ff46NMUuB26iCwuvzaq7tyZsq2G+r4IWFL4JfRZ8Obdz1V+j/VdLrEKKjJ8L0mCN UhFShr8yHskyzJa3m+2h2NOd9AqKzHNbjo0koLwmC9Bfe1eUW/LV7DSwjD89vFrbXPMb NNzw== X-Gm-Message-State: AKaTC02xPu5yxtw9g+RgyYzMSiHnq8LlqTP0W918oHT48RW8YlTuV7HufOMJRz3sVArt/g== X-Received: by 10.84.216.10 with SMTP id m10mr11217707pli.131.1479939278567; Wed, 23 Nov 2016 14:14:38 -0800 (PST) Received: from lianli.shorne-pla.net (z14.124-44-185.ppp.wakwak.ne.jp. [124.44.185.14]) by smtp.gmail.com with ESMTPSA id x26sm34435110pge.24.2016.11.23.14.14.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Nov 2016 14:14:38 -0800 (PST) Received: from lianli.shorne-pla.net (localhost [127.0.0.1]) by lianli.shorne-pla.net (8.15.2/8.15.2) with ESMTPS id uANMEaRb001913 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Thu, 24 Nov 2016 07:14:36 +0900 Received: (from shorne@localhost) by lianli.shorne-pla.net (8.15.2/8.15.2/Submit) id uANMEZxJ001912; Thu, 24 Nov 2016 07:14:35 +0900 From: Stafford Horne To: gdb-patches@sourceware.org Cc: openrisc@lists.librecores.org, Peter Gavin Subject: [PATCH 01/18] sim: cgen: add rem (remainder) function (needed for OR1K lf.rem.[sd]) Date: Wed, 23 Nov 2016 22:16:00 -0000 Message-Id: <1479939272-1754-2-git-send-email-shorne@gmail.com> In-Reply-To: <1479939272-1754-1-git-send-email-shorne@gmail.com> References: <1479939272-1754-1-git-send-email-shorne@gmail.com> X-IsSubscribed: yes X-SW-Source: 2016-11/txt/msg00720.txt.bz2 From: Peter Gavin * sim/common/ChangeLog-OR1K: 2012-03-14 Peter Gavin * cgen-accfp.c: add rem (remainder) function (needed for OR1K lf.rem.[sd]) (remsf) new function (remdf) ditto (struct cgen_fp_ops) add fields for rem[sdxt]f functions --- sim/common/cgen-accfp.c | 40 ++++++++++++++++++++++++++++++ sim/common/cgen-fpu.h | 4 +++ sim/common/sim-fpu.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++ sim/common/sim-fpu.h | 3 +++ 4 files changed, 113 insertions(+) diff --git a/sim/common/cgen-accfp.c b/sim/common/cgen-accfp.c index afbca6d..d7124fe 100644 --- a/sim/common/cgen-accfp.c +++ b/sim/common/cgen-accfp.c @@ -93,6 +93,25 @@ divsf (CGEN_FPU* fpu, SF x, SF y) } static SF +remsf (CGEN_FPU* fpu, SF x, SF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned32 res; + sim_fpu_status status; + + sim_fpu_32to (&op1, x); + sim_fpu_32to (&op2, y); + status = sim_fpu_rem (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to32 (&res, &ans); + + return res; +} + +static SF negsf (CGEN_FPU* fpu, SF x) { sim_fpu op1; @@ -452,6 +471,25 @@ divdf (CGEN_FPU* fpu, DF x, DF y) return res; } +static SF +remdf (CGEN_FPU* fpu, DF x, DF y) +{ + sim_fpu op1; + sim_fpu op2; + sim_fpu ans; + unsigned64 res; + sim_fpu_status status; + + sim_fpu_64to (&op1, x); + sim_fpu_64to (&op2, y); + status = sim_fpu_rem (&ans, &op1, &op2); + if (status != 0) + (*fpu->ops->error) (fpu, status); + sim_fpu_to64(&res, &ans); + + return res; +} + static DF negdf (CGEN_FPU* fpu, DF x) { @@ -664,6 +702,7 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error) o->subsf = subsf; o->mulsf = mulsf; o->divsf = divsf; + o->remsf = remsf; o->negsf = negsf; o->abssf = abssf; o->sqrtsf = sqrtsf; @@ -682,6 +721,7 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error) o->subdf = subdf; o->muldf = muldf; o->divdf = divdf; + o->remdf = remdf; o->negdf = negdf; o->absdf = absdf; o->sqrtdf = sqrtdf; diff --git a/sim/common/cgen-fpu.h b/sim/common/cgen-fpu.h index 134b4d0..5f9b55d 100644 --- a/sim/common/cgen-fpu.h +++ b/sim/common/cgen-fpu.h @@ -69,6 +69,7 @@ struct cgen_fp_ops { SF (*subsf) (CGEN_FPU*, SF, SF); SF (*mulsf) (CGEN_FPU*, SF, SF); SF (*divsf) (CGEN_FPU*, SF, SF); + SF (*remsf) (CGEN_FPU*, SF, SF); SF (*negsf) (CGEN_FPU*, SF); SF (*abssf) (CGEN_FPU*, SF); SF (*sqrtsf) (CGEN_FPU*, SF); @@ -93,6 +94,7 @@ struct cgen_fp_ops { DF (*subdf) (CGEN_FPU*, DF, DF); DF (*muldf) (CGEN_FPU*, DF, DF); DF (*divdf) (CGEN_FPU*, DF, DF); + DF (*remdf) (CGEN_FPU*, DF, DF); DF (*negdf) (CGEN_FPU*, DF); DF (*absdf) (CGEN_FPU*, DF); DF (*sqrtdf) (CGEN_FPU*, DF); @@ -142,6 +144,7 @@ struct cgen_fp_ops { XF (*subxf) (CGEN_FPU*, XF, XF); XF (*mulxf) (CGEN_FPU*, XF, XF); XF (*divxf) (CGEN_FPU*, XF, XF); + XF (*remxf) (CGEN_FPU*, XF, XF); XF (*negxf) (CGEN_FPU*, XF); XF (*absxf) (CGEN_FPU*, XF); XF (*sqrtxf) (CGEN_FPU*, XF); @@ -180,6 +183,7 @@ struct cgen_fp_ops { TF (*subtf) (CGEN_FPU*, TF, TF); TF (*multf) (CGEN_FPU*, TF, TF); TF (*divtf) (CGEN_FPU*, TF, TF); + TF (*remtf) (CGEN_FPU*, TF, TF); TF (*negtf) (CGEN_FPU*, TF); TF (*abstf) (CGEN_FPU*, TF); TF (*sqrttf) (CGEN_FPU*, TF); diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c index 801fbd0..d6e92b8 100644 --- a/sim/common/sim-fpu.c +++ b/sim/common/sim-fpu.c @@ -41,6 +41,7 @@ along with this program. If not, see . */ #include "sim-io.h" #include "sim-assert.h" +#include /* for drem, remove when soft-float version is implemented */ /* Debugging support. If digits is -1, then print all digits. */ @@ -1551,6 +1552,71 @@ sim_fpu_div (sim_fpu *f, INLINE_SIM_FPU (int) +sim_fpu_rem (sim_fpu *f, + const sim_fpu *l, + const sim_fpu *r) +{ + if (sim_fpu_is_snan (l)) + { + *f = *l; + f->class = sim_fpu_class_qnan; + return sim_fpu_status_invalid_snan; + } + if (sim_fpu_is_snan (r)) + { + *f = *r; + f->class = sim_fpu_class_qnan; + return sim_fpu_status_invalid_snan; + } + if (sim_fpu_is_qnan (l)) + { + *f = *l; + f->class = sim_fpu_class_qnan; + return 0; + } + if (sim_fpu_is_qnan (r)) + { + *f = *r; + f->class = sim_fpu_class_qnan; + return 0; + } + if (sim_fpu_is_infinity (l)) + { + *f = sim_fpu_qnan; + return sim_fpu_status_invalid_irx; + } + if (sim_fpu_is_zero (r)) + { + *f = sim_fpu_qnan; + return sim_fpu_status_invalid_div0; + } + if (sim_fpu_is_zero (l)) + { + *f = *l; + return 0; + } + if (sim_fpu_is_infinity (r)) + { + *f = *l; + return 0; + } + + { + /* cheat for now */ + /* TODO: don't use hard float */ + + sim_fpu_map lval, rval, fval; + lval.i = pack_fpu(l, 1); + rval.i = pack_fpu(r, 1); + fval.d = drem(lval.d, rval.d); + unpack_fpu(f, fval.i, 1); + return 0; + + } +} + + +INLINE_SIM_FPU (int) sim_fpu_max (sim_fpu *f, const sim_fpu *l, const sim_fpu *r) diff --git a/sim/common/sim-fpu.h b/sim/common/sim-fpu.h index eb00beb..2b1c9fe 100644 --- a/sim/common/sim-fpu.h +++ b/sim/common/sim-fpu.h @@ -151,6 +151,7 @@ typedef enum sim_fpu_status_overflow = 4096, sim_fpu_status_underflow = 8192, sim_fpu_status_denorm = 16384, + sim_fpu_status_invalid_irx = 32768, /* (inf % X) */ } sim_fpu_status; @@ -230,6 +231,8 @@ INLINE_SIM_FPU (int) sim_fpu_mul (sim_fpu *f, const sim_fpu *l, const sim_fpu *r); INLINE_SIM_FPU (int) sim_fpu_div (sim_fpu *f, const sim_fpu *l, const sim_fpu *r); +INLINE_SIM_FPU (int) sim_fpu_rem (sim_fpu *f, + const sim_fpu *l, const sim_fpu *r); INLINE_SIM_FPU (int) sim_fpu_max (sim_fpu *f, const sim_fpu *l, const sim_fpu *r); INLINE_SIM_FPU (int) sim_fpu_min (sim_fpu *f, -- 2.7.4