Re: [PATCH v3 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

Re: [PATCH v3 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

[Aktemur, Baris]

AMD General

Hi Klaus,

This is a reply to

 https://inbox.sourceware.org/gdb-patches/87zffcn798.fsf@redhat.com/

It seems the patch is not merged to upstream master, yet.  I assume it's
simply an oversight.  Could you take a look?

I have one comment below:

> diff --git a/gdb/infrun.c b/gdb/infrun.c
> index 43eca814e29..eb34aed09e0 100644
> --- a/gdb/infrun.c
> +++ b/gdb/infrun.c
> @@ -6138,7 +6138,9 @@ handle_inferior_event (struct execution_control_state *ecs)
>       stack.  */
>    if (ecs->ws.kind () == TARGET_WAITKIND_STOPPED
>        && (ecs->ws.sig () == GDB_SIGNAL_ILL
> -       || ecs->ws.sig () == GDB_SIGNAL_SEGV
> +       || (ecs->ws.sig () == GDB_SIGNAL_SEGV
> +           && !gdbarch_imprecise_pagefault_reporting
> +             (current_inferior ()->arch ()))

In a case like AMD GPUs, the inferior contains a mixture of CPU and GPU threads.
The imprecise reporting property would depend on the kind of the thread.  Therefore,
instead of

  current_inferior ()->arch ()

I'd propose

  target_thread_architecture (ecs->event_thread->ptid)

That should still give the same behavior for Intel's case because by default a
process stratum target returns the inferior's arch.

Best,
-Baris

RE: [PATCH v3 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

[Gerlicher, Klaus]

Hi Baris,

Thanks a lot for noticing this, indeed it's an oversight.

I'll try the target_thread_architecture (ecs->event_thread->ptid) modificiation.

Thanks
Klaus


> -----Original Message-----
> From: Aktemur, Baris <TankutBaris.Aktemur@amd.com>
> Sent: Wednesday, May 13, 2026 10:20 AM
> To: Gerlicher, Klaus <klaus.gerlicher@intel.com>; gdb-
> patches@sourceware.org
> Cc: aburgess@redhat.com
> Subject: Re: [PATCH v3 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on
> user breakpoints
> 
> AMD General
> 
> Hi Klaus,
> 
> This is a reply to
> 
>  https://inbox.sourceware.org/gdb-patches/87zffcn798.fsf@redhat.com/
> 
> It seems the patch is not merged to upstream master, yet.  I assume it's
> simply an oversight.  Could you take a look?
> 
> I have one comment below:
> 
> > diff --git a/gdb/infrun.c b/gdb/infrun.c
> > index 43eca814e29..eb34aed09e0 100644
> > --- a/gdb/infrun.c
> > +++ b/gdb/infrun.c
> > @@ -6138,7 +6138,9 @@ handle_inferior_event (struct
> execution_control_state *ecs)
> >       stack.  */
> >    if (ecs->ws.kind () == TARGET_WAITKIND_STOPPED
> >        && (ecs->ws.sig () == GDB_SIGNAL_ILL
> > -       || ecs->ws.sig () == GDB_SIGNAL_SEGV
> > +       || (ecs->ws.sig () == GDB_SIGNAL_SEGV
> > +           && !gdbarch_imprecise_pagefault_reporting
> > +             (current_inferior ()->arch ()))
> 
> In a case like AMD GPUs, the inferior contains a mixture of CPU and GPU
> threads.
> The imprecise reporting property would depend on the kind of the thread.
> Therefore,
> instead of
> 
>   current_inferior ()->arch ()
> 
> I'd propose
> 
>   target_thread_architecture (ecs->event_thread->ptid)
> 
> That should still give the same behavior for Intel's case because by default a
> process stratum target returns the inferior's arch.
> 
> Best,
> -Baris
> 

Intel Deutschland GmbH
Registered Address: Dornacher Strasse 1, 85622 Feldkirchen, Germany
Tel: +49 89 991 430, www.intel.de
Managing Directors: Harry Demas, Jeffrey Schneiderman, Yin Chong Sorrell
Chairperson of the Supervisory Board: Nicole Lau
Registered Seat: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928

RE: [PATCH v3 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

[Aktemur, Baris]

AMD General

Hi Klaus,

On Tuesday, May 19, 2026 12:30 PM, Gerlicher, Klaus wrote:
> Hi Baris,
>
> Thanks a lot for noticing this, indeed it's an oversight.
>
> I'll try the target_thread_architecture (ecs->event_thread->ptid) modificiation.

Any update on this?

Regards,
-Baris

> Thanks
> Klaus
>
>
> > -----Original Message-----
> > From: Aktemur, Baris <TankutBaris.Aktemur@amd.com>
> > Sent: Wednesday, May 13, 2026 10:20 AM
> > To: Gerlicher, Klaus <klaus.gerlicher@intel.com>; gdb-
> > patches@sourceware.org
> > Cc: aburgess@redhat.com
> > Subject: Re: [PATCH v3 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on
> > user breakpoints
> >
> > AMD General
> >
> > Hi Klaus,
> >
> > This is a reply to
> >
> >  https://inbox.sourceware.org/gdb-patches/87zffcn798.fsf@redhat.com/
> >
> > It seems the patch is not merged to upstream master, yet.  I assume it's
> > simply an oversight.  Could you take a look?
> >
> > I have one comment below:
> >
> > > diff --git a/gdb/infrun.c b/gdb/infrun.c
> > > index 43eca814e29..eb34aed09e0 100644
> > > --- a/gdb/infrun.c
> > > +++ b/gdb/infrun.c
> > > @@ -6138,7 +6138,9 @@ handle_inferior_event (struct
> > execution_control_state *ecs)
> > >       stack.  */
> > >    if (ecs->ws.kind () == TARGET_WAITKIND_STOPPED
> > >        && (ecs->ws.sig () == GDB_SIGNAL_ILL
> > > -       || ecs->ws.sig () == GDB_SIGNAL_SEGV
> > > +       || (ecs->ws.sig () == GDB_SIGNAL_SEGV
> > > +           && !gdbarch_imprecise_pagefault_reporting
> > > +             (current_inferior ()->arch ()))
> >
> > In a case like AMD GPUs, the inferior contains a mixture of CPU and GPU
> > threads.
> > The imprecise reporting property would depend on the kind of the thread.
> > Therefore,
> > instead of
> >
> >   current_inferior ()->arch ()
> >
> > I'd propose
> >
> >   target_thread_architecture (ecs->event_thread->ptid)
> >
> > That should still give the same behavior for Intel's case because by default a
> > process stratum target returns the inferior's arch.
> >
> > Best,
> > -Baris
> >
>
> Intel Deutschland GmbH
> Registered Address: Dornacher Strasse 1, 85622 Feldkirchen, Germany
> Tel: +49 89 991 430, www.intel.de
> Managing Directors: Harry Demas, Jeffrey Schneiderman, Yin Chong Sorrell
> Chairperson of the Supervisory Board: Nicole Lau
> Registered Seat: Munich
> Commercial Register: Amtsgericht Muenchen HRB 186928

[PATCH v4 0/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

[Klaus Gerlicher]

From: "Gerlicher, Klaus" <klaus.gerlicher@intel.com>

Hi Baris, Andrew, all,

thanks for the feedback and approval.

I incorporated your suggestions and added target_thread_architecture() instead of 
current_inferior()->arch() to obtain the architecture for the imprecise_pagefault_reporting
check.

Changes since V3:
- Use target_thread_architecture() instead of current_inferior()->arch()
  to obtain the architecture for the imprecise_pagefault_reporting check.

Thanks
Klaus

Gerlicher, Klaus (1):
  gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

 gdb/gdbarch-gen.c         | 22 ++++++++++++++++++++++
 gdb/gdbarch-gen.h         |  7 +++++++
 gdb/gdbarch_components.py | 12 ++++++++++++
 gdb/infrun.c              |  4 +++-
 4 files changed, 44 insertions(+), 1 deletion(-)

-- 
2.34.1

Intel Deutschland GmbH

Registered Address: Dornacher Strasse 1, 85622 Feldkirchen, Germany
Tel: +49 89 991 430, www.intel.de
Managing Directors: Harry Demas, Jeffrey Schneiderman, Yin Chong Sorrell
Chairperson of the Supervisory Board: Nicole Lau
Registered Seat: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928

[PATCH v4 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

[Klaus Gerlicher]

From: "Gerlicher, Klaus" <klaus.gerlicher@intel.com>

GDB converts signals GDB_SIGNAL_ILL, GDB_SIGNAL_SEGV and GDB_SIGNAL_EMT to
GDB_SIGNAL_TRAP if a breakpoint is inserted at the fault location.  If, due
to imprecise page fault reporting, a breakpoint is at the same address as
the fault address, this signal would always be reported as GDB_SIGNAL_TRAP.

Add a new gdbarch function, imprecise_pagefault_reporting, that allows the
signal conversion from GDB_SIGNAL_SEGV to GDB_SIGNAL_TRAP to be skipped for
an architecture.  The default is false (conversion enabled), preserving
existing behavior.
---
 gdb/gdbarch-gen.c         | 22 ++++++++++++++++++++++
 gdb/gdbarch-gen.h         |  7 +++++++
 gdb/gdbarch_components.py | 12 ++++++++++++
 gdb/infrun.c              |  4 +++-
 4 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/gdb/gdbarch-gen.c b/gdb/gdbarch-gen.c
index f424fa2a86e..d9bb3e7078c 100644
--- a/gdb/gdbarch-gen.c
+++ b/gdb/gdbarch-gen.c
@@ -253,6 +253,7 @@ struct gdbarch
   gdbarch_core_parse_exec_context_ftype *core_parse_exec_context = default_core_parse_exec_context;
   gdbarch_shadow_stack_push_ftype *shadow_stack_push = nullptr;
   gdbarch_get_shadow_stack_pointer_ftype *get_shadow_stack_pointer = default_get_shadow_stack_pointer;
+  gdbarch_imprecise_pagefault_reporting_ftype *imprecise_pagefault_reporting = [] () -> bool {return false;};
 };
 
 /* Create a new ``struct gdbarch'' based on information provided by
@@ -513,6 +514,7 @@ verify_gdbarch (struct gdbarch *gdbarch)
   /* Skip verify of core_parse_exec_context, invalid_p == 0.  */
   /* Skip verify of shadow_stack_push, has predicate.  */
   /* Skip verify of get_shadow_stack_pointer, invalid_p == 0.  */
+  /* Skip verify of imprecise_pagefault_reporting, invalid_p == 0.  */
   if (!log.empty ())
     internal_error (_("verify_gdbarch: the following are invalid ...%s"),
 		    log.c_str ());
@@ -1339,6 +1341,9 @@ gdbarch_dump (struct gdbarch *gdbarch, struct ui_file *file)
   gdb_printf (file,
 	      "gdbarch_dump: get_shadow_stack_pointer = <%s>\n",
 	      host_address_to_string (gdbarch->get_shadow_stack_pointer));
+  gdb_printf (file,
+	      "gdbarch_dump: imprecise_pagefault_reporting = <%s>\n",
+	      host_address_to_string (gdbarch->imprecise_pagefault_reporting));
   if (gdbarch->dump_tdep != nullptr)
     gdbarch->dump_tdep (gdbarch, file);
 }
@@ -5286,3 +5291,20 @@ set_gdbarch_get_shadow_stack_pointer (struct gdbarch *gdbarch,
 {
   gdbarch->get_shadow_stack_pointer = get_shadow_stack_pointer;
 }
+
+bool
+gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch)
+{
+  gdb_assert (gdbarch != NULL);
+  gdb_assert (gdbarch->imprecise_pagefault_reporting != NULL);
+  if (gdbarch_debug >= 2)
+    gdb_printf (gdb_stdlog, "gdbarch_imprecise_pagefault_reporting called\n");
+  return gdbarch->imprecise_pagefault_reporting ();
+}
+
+void
+set_gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch,
+					   gdbarch_imprecise_pagefault_reporting_ftype imprecise_pagefault_reporting)
+{
+  gdbarch->imprecise_pagefault_reporting = imprecise_pagefault_reporting;
+}
diff --git a/gdb/gdbarch-gen.h b/gdb/gdbarch-gen.h
index 678b308fba5..bb95df25eb6 100644
--- a/gdb/gdbarch-gen.h
+++ b/gdb/gdbarch-gen.h
@@ -1752,3 +1752,10 @@ void set_gdbarch_shadow_stack_push (struct gdbarch *gdbarch, gdbarch_shadow_stac
 using gdbarch_get_shadow_stack_pointer_ftype = std::optional<CORE_ADDR> (struct gdbarch *gdbarch, regcache *regcache, bool &shadow_stack_enabled);
 std::optional<CORE_ADDR> gdbarch_get_shadow_stack_pointer (struct gdbarch *gdbarch, regcache *regcache, bool &shadow_stack_enabled);
 void set_gdbarch_get_shadow_stack_pointer (struct gdbarch *gdbarch, gdbarch_get_shadow_stack_pointer_ftype *get_shadow_stack_pointer);
+
+/* Returns true if architecture has imprecise pagefault reporting.  This is
+   used in conversion of SIGSEGV to SIGTRAP for an architecture. */
+
+typedef bool (gdbarch_imprecise_pagefault_reporting_ftype) ();
+extern bool gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch);
+extern void set_gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch, gdbarch_imprecise_pagefault_reporting_ftype *imprecise_pagefault_reporting);
diff --git a/gdb/gdbarch_components.py b/gdb/gdbarch_components.py
index b9304d3036d..d903446435f 100644
--- a/gdb/gdbarch_components.py
+++ b/gdb/gdbarch_components.py
@@ -2781,3 +2781,15 @@ SHADOW_STACK_ENABLED to false.
     predefault="default_get_shadow_stack_pointer",
     invalid=False,
 )
+
+Function(
+    comment="""
+Returns true if architecture has imprecise pagefault reporting.  This is
+used in conversion of SIGSEGV to SIGTRAP for an architecture.
+""",
+    type="bool",
+    name="imprecise_pagefault_reporting",
+    params=[],
+    predefault="[] () -> bool {return false;}",
+    invalid=False
+)
diff --git a/gdb/infrun.c b/gdb/infrun.c
index c0767e7f764..25ed7e7523f 100644
--- a/gdb/infrun.c
+++ b/gdb/infrun.c
@@ -6331,7 +6331,9 @@ handle_inferior_event (struct execution_control_state *ecs)
      stack.  */
   if (ecs->ws.kind () == TARGET_WAITKIND_STOPPED
       && (ecs->ws.sig () == GDB_SIGNAL_ILL
-	  || ecs->ws.sig () == GDB_SIGNAL_SEGV
+	  || (ecs->ws.sig () == GDB_SIGNAL_SEGV
+	      && !gdbarch_imprecise_pagefault_reporting
+		  (target_thread_architecture (ecs->event_thread->ptid)))
 	  || ecs->ws.sig () == GDB_SIGNAL_EMT))
     {
       struct regcache *regcache = get_thread_regcache (ecs->event_thread);
-- 
2.34.1

Intel Deutschland GmbH

Registered Address: Dornacher Strasse 1, 85622 Feldkirchen, Germany
Tel: +49 89 991 430, www.intel.de
Managing Directors: Harry Demas, Jeffrey Schneiderman, Yin Chong Sorrell
Chairperson of the Supervisory Board: Nicole Lau
Registered Seat: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928

RE: [PATCH v4 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

[Aktemur, Baris]

AMD General

Hi Klaus,

On Friday, July 17, 2026 9:45 AM, Klaus Gerlicher wrote:
> GDB converts signals GDB_SIGNAL_ILL, GDB_SIGNAL_SEGV and GDB_SIGNAL_EMT to
> GDB_SIGNAL_TRAP if a breakpoint is inserted at the fault location.  If, due
> to imprecise page fault reporting, a breakpoint is at the same address as
> the fault address, this signal would always be reported as GDB_SIGNAL_TRAP.
>
> Add a new gdbarch function, imprecise_pagefault_reporting, that allows the
> signal conversion from GDB_SIGNAL_SEGV to GDB_SIGNAL_TRAP to be skipped for
> an architecture.  The default is false (conversion enabled), preserving
> existing behavior.

It seems gdbarch.py has been updated since the last time you generated gdbarch files.
Re-generating gives the diff below.  The patch LGTM with that fixed.

Reviewed-By: Tankut Baris Aktemur <TankutBaris.Aktemur@amd.com>

Thank you.
-Baris


diff --git a/gdb/gdbarch-gen.c b/gdb/gdbarch-gen.c
index d9bb3e7078c..0b815296261 100644
--- a/gdb/gdbarch-gen.c
+++ b/gdb/gdbarch-gen.c
@@ -5295,8 +5295,8 @@ set_gdbarch_get_shadow_stack_pointer (struct gdbarch *gdbarch,
 bool
 gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch)
 {
-  gdb_assert (gdbarch != NULL);
-  gdb_assert (gdbarch->imprecise_pagefault_reporting != NULL);
+  gdb_assert (gdbarch != nullptr);
+  gdb_assert (gdbarch->imprecise_pagefault_reporting != nullptr);
   if (gdbarch_debug >= 2)
     gdb_printf (gdb_stdlog, "gdbarch_imprecise_pagefault_reporting called\n");
   return gdbarch->imprecise_pagefault_reporting ();
diff --git a/gdb/gdbarch-gen.h b/gdb/gdbarch-gen.h
index bb95df25eb6..a96692c206c 100644
--- a/gdb/gdbarch-gen.h
+++ b/gdb/gdbarch-gen.h
@@ -1756,6 +1756,6 @@ void set_gdbarch_get_shadow_stack_pointer (struct gdbarch *gdbarch, gdbarch_get_
 /* Returns true if architecture has imprecise pagefault reporting.  This is
    used in conversion of SIGSEGV to SIGTRAP for an architecture. */

-typedef bool (gdbarch_imprecise_pagefault_reporting_ftype) ();
-extern bool gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch);
-extern void set_gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch, gdbarch_imprecise_pagefault_reporting_ftype *imprecise_pagefault_reporting);
+using gdbarch_imprecise_pagefault_reporting_ftype = bool ();
+bool gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch);
+void set_gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch, gdbarch_imprecise_pagefault_reporting_ftype *imprecise_pagefault_reporting);

RE: [PATCH v4 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

[Gerlicher, Klaus]

Thank you, Baris.

 I discovered this too *after* I posted. I'll make sure it's updated once Andrew approves again.

Thanks
Klaus

> -----Original Message-----
> From: Aktemur, Baris <TankutBaris.Aktemur@amd.com>
> Sent: Friday, July 17, 2026 11:17 AM
> To: Gerlicher, Klaus <klaus.gerlicher@intel.com>; gdb-
> patches@sourceware.org
> Cc: aburgess@redhat.com
> Subject: RE: [PATCH v4 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on
> user breakpoints
> 
> AMD General
> 
> Hi Klaus,
> 
> On Friday, July 17, 2026 9:45 AM, Klaus Gerlicher wrote:
> > GDB converts signals GDB_SIGNAL_ILL, GDB_SIGNAL_SEGV and
> GDB_SIGNAL_EMT to
> > GDB_SIGNAL_TRAP if a breakpoint is inserted at the fault location.  If, due
> > to imprecise page fault reporting, a breakpoint is at the same address as
> > the fault address, this signal would always be reported as
> GDB_SIGNAL_TRAP.
> >
> > Add a new gdbarch function, imprecise_pagefault_reporting, that allows the
> > signal conversion from GDB_SIGNAL_SEGV to GDB_SIGNAL_TRAP to be
> skipped for
> > an architecture.  The default is false (conversion enabled), preserving
> > existing behavior.
> 
> It seems gdbarch.py has been updated since the last time you generated
> gdbarch files.
> Re-generating gives the diff below.  The patch LGTM with that fixed.
> 
> Reviewed-By: Tankut Baris Aktemur <TankutBaris.Aktemur@amd.com>
> 
> Thank you.
> -Baris
> 
> 
> diff --git a/gdb/gdbarch-gen.c b/gdb/gdbarch-gen.c
> index d9bb3e7078c..0b815296261 100644
> --- a/gdb/gdbarch-gen.c
> +++ b/gdb/gdbarch-gen.c
> @@ -5295,8 +5295,8 @@ set_gdbarch_get_shadow_stack_pointer (struct
> gdbarch *gdbarch,
>  bool
>  gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch)
>  {
> -  gdb_assert (gdbarch != NULL);
> -  gdb_assert (gdbarch->imprecise_pagefault_reporting != NULL);
> +  gdb_assert (gdbarch != nullptr);
> +  gdb_assert (gdbarch->imprecise_pagefault_reporting != nullptr);
>    if (gdbarch_debug >= 2)
>      gdb_printf (gdb_stdlog, "gdbarch_imprecise_pagefault_reporting
> called\n");
>    return gdbarch->imprecise_pagefault_reporting ();
> diff --git a/gdb/gdbarch-gen.h b/gdb/gdbarch-gen.h
> index bb95df25eb6..a96692c206c 100644
> --- a/gdb/gdbarch-gen.h
> +++ b/gdb/gdbarch-gen.h
> @@ -1756,6 +1756,6 @@ void set_gdbarch_get_shadow_stack_pointer
> (struct gdbarch *gdbarch, gdbarch_get_
>  /* Returns true if architecture has imprecise pagefault reporting.  This is
>     used in conversion of SIGSEGV to SIGTRAP for an architecture. */
> 
> -typedef bool (gdbarch_imprecise_pagefault_reporting_ftype) ();
> -extern bool gdbarch_imprecise_pagefault_reporting (struct gdbarch
> *gdbarch);
> -extern void set_gdbarch_imprecise_pagefault_reporting (struct gdbarch
> *gdbarch, gdbarch_imprecise_pagefault_reporting_ftype
> *imprecise_pagefault_reporting);
> +using gdbarch_imprecise_pagefault_reporting_ftype = bool ();
> +bool gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch);
> +void set_gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch,
> gdbarch_imprecise_pagefault_reporting_ftype
> *imprecise_pagefault_reporting);
> 

Intel Deutschland GmbH

Registered Address: Dornacher Strasse 1, 85622 Feldkirchen, Germany
Tel: +49 89 991 430, www.intel.de
Managing Directors: Harry Demas, Jeffrey Schneiderman, Yin Chong Sorrell
Chairperson of the Supervisory Board: Nicole Lau
Registered Seat: Munich
Commercial Register: Amtsgericht Muenchen HRB 186928

RE: [PATCH v4 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

[Aktemur, Baris]

AMD General

Hi Andrew,

Kindly pinging for a re-approval.

Regards,
-Baris

On Friday, July 17, 2026 3:25 PM, Gerlicher, Klaus wrote:
> Thank you, Baris.
>
>  I discovered this too *after* I posted. I'll make sure it's updated once Andrew
> approves again.
>
> Thanks
> Klaus
>
> > -----Original Message-----
> > From: Aktemur, Baris <TankutBaris.Aktemur@amd.com>
> > Sent: Friday, July 17, 2026 11:17 AM
> > To: Gerlicher, Klaus <klaus.gerlicher@intel.com>; gdb-
> > patches@sourceware.org
> > Cc: aburgess@redhat.com
> > Subject: RE: [PATCH v4 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on
> > user breakpoints
> >
> > AMD General
> >
> > Hi Klaus,
> >
> > On Friday, July 17, 2026 9:45 AM, Klaus Gerlicher wrote:
> > > GDB converts signals GDB_SIGNAL_ILL, GDB_SIGNAL_SEGV and
> > GDB_SIGNAL_EMT to
> > > GDB_SIGNAL_TRAP if a breakpoint is inserted at the fault location.  If, due
> > > to imprecise page fault reporting, a breakpoint is at the same address as
> > > the fault address, this signal would always be reported as
> > GDB_SIGNAL_TRAP.
> > >
> > > Add a new gdbarch function, imprecise_pagefault_reporting, that allows the
> > > signal conversion from GDB_SIGNAL_SEGV to GDB_SIGNAL_TRAP to be
> > skipped for
> > > an architecture.  The default is false (conversion enabled), preserving
> > > existing behavior.
> >
> > It seems gdbarch.py has been updated since the last time you generated
> > gdbarch files.
> > Re-generating gives the diff below.  The patch LGTM with that fixed.
> >
> > Reviewed-By: Tankut Baris Aktemur <TankutBaris.Aktemur@amd.com>
> >
> > Thank you.
> > -Baris
> >
> >
> > diff --git a/gdb/gdbarch-gen.c b/gdb/gdbarch-gen.c
> > index d9bb3e7078c..0b815296261 100644
> > --- a/gdb/gdbarch-gen.c
> > +++ b/gdb/gdbarch-gen.c
> > @@ -5295,8 +5295,8 @@ set_gdbarch_get_shadow_stack_pointer (struct
> > gdbarch *gdbarch,
> >  bool
> >  gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch)
> >  {
> > -  gdb_assert (gdbarch != NULL);
> > -  gdb_assert (gdbarch->imprecise_pagefault_reporting != NULL);
> > +  gdb_assert (gdbarch != nullptr);
> > +  gdb_assert (gdbarch->imprecise_pagefault_reporting != nullptr);
> >    if (gdbarch_debug >= 2)
> >      gdb_printf (gdb_stdlog, "gdbarch_imprecise_pagefault_reporting
> > called\n");
> >    return gdbarch->imprecise_pagefault_reporting ();
> > diff --git a/gdb/gdbarch-gen.h b/gdb/gdbarch-gen.h
> > index bb95df25eb6..a96692c206c 100644
> > --- a/gdb/gdbarch-gen.h
> > +++ b/gdb/gdbarch-gen.h
> > @@ -1756,6 +1756,6 @@ void set_gdbarch_get_shadow_stack_pointer
> > (struct gdbarch *gdbarch, gdbarch_get_
> >  /* Returns true if architecture has imprecise pagefault reporting.  This is
> >     used in conversion of SIGSEGV to SIGTRAP for an architecture. */
> >
> > -typedef bool (gdbarch_imprecise_pagefault_reporting_ftype) ();
> > -extern bool gdbarch_imprecise_pagefault_reporting (struct gdbarch
> > *gdbarch);
> > -extern void set_gdbarch_imprecise_pagefault_reporting (struct gdbarch
> > *gdbarch, gdbarch_imprecise_pagefault_reporting_ftype
> > *imprecise_pagefault_reporting);
> > +using gdbarch_imprecise_pagefault_reporting_ftype = bool ();
> > +bool gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch);
> > +void set_gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch,
> > gdbarch_imprecise_pagefault_reporting_ftype
> > *imprecise_pagefault_reporting);
> >
>
> Intel Deutschland GmbH
>
> Registered Address: Dornacher Strasse 1, 85622 Feldkirchen, Germany
> Tel: +49 89 991 430, www.intel.de
> Managing Directors: Harry Demas, Jeffrey Schneiderman, Yin Chong Sorrell
> Chairperson of the Supervisory Board: Nicole Lau
> Registered Seat: Munich
> Commercial Register: Amtsgericht Muenchen HRB 186928

Re: [PATCH v4 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

[Simon Marchi]

On 7/17/26 3:44 AM, Klaus Gerlicher wrote:
> From: "Gerlicher, Klaus" <klaus.gerlicher@intel.com>
> 
> GDB converts signals GDB_SIGNAL_ILL, GDB_SIGNAL_SEGV and GDB_SIGNAL_EMT to
> GDB_SIGNAL_TRAP if a breakpoint is inserted at the fault location.  If, due
> to imprecise page fault reporting, a breakpoint is at the same address as
> the fault address, this signal would always be reported as GDB_SIGNAL_TRAP.
> 
> Add a new gdbarch function, imprecise_pagefault_reporting, that allows the
> signal conversion from GDB_SIGNAL_SEGV to GDB_SIGNAL_TRAP to be skipped for
> an architecture.  The default is false (conversion enabled), preserving
> existing behavior.

I'm familiar with the similar feature (precise memory location) for the
AMDGPU port, so I had a hunch that it was kind of the same thing, but I
had to go read the thread on v1 where you explained it in more details
to be really sure.  I think that the commit message and perhaps the
gdbarch method documentation should expand a bit on what "imprecise page
fault reporting" is, including giving a brief example.

Here's an example to validate my understanding of it:

  INSN1  <-- generates a SIGSEGV
  INSN2
  INSN3  <-- breakpoint installed here

On such an architecture, if an instruction causes a memory access
violation, it's possible for the backend to report the SIGSEGV a few
instructions later.  Imagine that INSN1 makes an invalid memory access,
and then the backend reports the stop at INSN3, where a breakpoint
happens to be installed.  Then the logic of GDB kicks in where it says:
"oh, there is a breakpoint installed at INSN3, so this SIGSEGV must mean
that we hit the breakpoint, let me convert that to SIGTRAP".  On your
architecture that is not true.  You know that a breakpoint is never
reported by SIGSEGV: if we received a SIGSEGV, it is definitely a
SIGSEGV.  So you want to disable that conversion logic.

Does that sounds right?  If so, feel free to use any of this in your
commit message / doc.  I think that will help people who stumble on that
code in the future.

Instead of being enabled by default, and then having to disable it in
cases like yours, I think it would be nicer if it was disabled by
default, and arches had to opt in to enable it.  For example, if you
know that your arch does report breakpoints as SIGILL (perhaps there is
no dedicated breakpoint instruction so inserting an  illegal instruction
is the only way to reliably make the program stop), then you would
implement the gdbarch method to enable that conversion.  Unfortunately,
that would be a difficult change to do today, because it would require
identifying which of the many old arches that GDB supports would need to
enable that.

> ---
>  gdb/gdbarch-gen.c         | 22 ++++++++++++++++++++++
>  gdb/gdbarch-gen.h         |  7 +++++++
>  gdb/gdbarch_components.py | 12 ++++++++++++

The gdbarch files will need to be regenerated before pushing.

With an improved commit message / documentation, I think that this patch
will be ok to merge.

Simon

RE: [PATCH v3 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints

[Gerlicher, Klaus]

Hi Baris,

Yes, I posted V4 just now.

Thanks
Klaus

> -----Original Message-----
> From: Aktemur, Baris <TankutBaris.Aktemur@amd.com>
> Sent: Tuesday, July 7, 2026 8:36 AM
> To: Gerlicher, Klaus <klaus.gerlicher@intel.com>; gdb-
> patches@sourceware.org
> Cc: aburgess@redhat.com
> Subject: RE: [PATCH v3 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on
> user breakpoints
> 
> AMD General
> 
> Hi Klaus,
> 
> On Tuesday, May 19, 2026 12:30 PM, Gerlicher, Klaus wrote:
> > Hi Baris,
> >
> > Thanks a lot for noticing this, indeed it's an oversight.
> >
> > I'll try the target_thread_architecture (ecs->event_thread->ptid)
> modificiation.
> 
> Any update on this?
> 
> Regards,
> -Baris
> 
> > Thanks
> > Klaus
> >
> >
> > > -----Original Message-----
> > > From: Aktemur, Baris <TankutBaris.Aktemur@amd.com>
> > > Sent: Wednesday, May 13, 2026 10:20 AM
> > > To: Gerlicher, Klaus <klaus.gerlicher@intel.com>; gdb-
> > > patches@sourceware.org
> > > Cc: aburgess@redhat.com
> > > Subject: Re: [PATCH v3 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP
> on
> > > user breakpoints
> > >
> > > AMD General
> > >
> > > Hi Klaus,
> > >
> > > This is a reply to
> > >
> > >  https://inbox.sourceware.org/gdb-patches/87zffcn798.fsf@redhat.com/
> > >
> > > It seems the patch is not merged to upstream master, yet.  I assume it's
> > > simply an oversight.  Could you take a look?
> > >
> > > I have one comment below:
> > >
> > > > diff --git a/gdb/infrun.c b/gdb/infrun.c
> > > > index 43eca814e29..eb34aed09e0 100644
> > > > --- a/gdb/infrun.c
> > > > +++ b/gdb/infrun.c
> > > > @@ -6138,7 +6138,9 @@ handle_inferior_event (struct
> > > execution_control_state *ecs)
> > > >       stack.  */
> > > >    if (ecs->ws.kind () == TARGET_WAITKIND_STOPPED
> > > >        && (ecs->ws.sig () == GDB_SIGNAL_ILL
> > > > -       || ecs->ws.sig () == GDB_SIGNAL_SEGV
> > > > +       || (ecs->ws.sig () == GDB_SIGNAL_SEGV
> > > > +           && !gdbarch_imprecise_pagefault_reporting
> > > > +             (current_inferior ()->arch ()))
> > >
> > > In a case like AMD GPUs, the inferior contains a mixture of CPU and GPU
> > > threads.
> > > The imprecise reporting property would depend on the kind of the thread.
> > > Therefore,
> > > instead of
> > >
> > >   current_inferior ()->arch ()
> > >
> > > I'd propose
> > >
> > >   target_thread_architecture (ecs->event_thread->ptid)
> > >
> > > That should still give the same behavior for Intel's case because by default a
> > > process stratum target returns the inferior's arch.
> > >
> > > Best,
> > > -Baris
> > >
> >
> > Intel Deutschland GmbH
> > Registered Address: Dornacher Strasse 1, 85622 Feldkirchen, Germany
> > Tel: +49 89 991 430, www.intel.de
> > Managing Directors: Harry Demas, Jeffrey Schneiderman, Yin Chong Sorrell
> > Chairperson of the Supervisory Board: Nicole Lau
> > Registered Seat: Munich
> > Commercial Register: Amtsgericht Muenchen HRB 186928