From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from simark.ca by simark.ca with LMTP id icAmIrDdWWr5Hg4AWB0awg (envelope-from ) for ; Fri, 17 Jul 2026 03:45:52 -0400 Authentication-Results: simark.ca; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=UZy8JM06; dkim-atps=neutral Received: by simark.ca (Postfix, from userid 112) id 879401E09E; Fri, 17 Jul 2026 03:45:52 -0400 (EDT) X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-25) on simark.ca X-Spam-Level: X-Spam-Status: No, score=-6.4 required=5.0 tests=ARC_SIGNED,ARC_VALID,BAYES_00, DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham autolearn_force=no version=4.0.1 Received: from vm01.sourceware.org (vm01.sourceware.org [IPv6:2620:52:6:3111::32]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange x25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by simark.ca (Postfix) with ESMTPS id F2E6B1E099 for ; Fri, 17 Jul 2026 03:45:51 -0400 (EDT) Received: from vm01.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E86434BA23CA for ; Fri, 17 Jul 2026 07:45:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E86434BA23CA Authentication-Results: sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=UZy8JM06 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) by sourceware.org (Postfix) with ESMTPS id BDFED4BA2E30 for ; Fri, 17 Jul 2026 07:45:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BDFED4BA2E30 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org BDFED4BA2E30 Authentication-Results: sourceware.org; arc=none smtp.remote-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784274326; cv=none; b=ifS8h5REJLeLbshZHNrNJk9+QSg5kw5E/DrF3CuiedF7zPmQaNg0ubxiSpGyoFjgWsH//QcTTR/XAog4bbuUxrbo5JgsG0prJRRRoGZUmWsMuMHTsQ3WDdpJlhSs9Iu48rIkHSkvFPOMFsKmqwcfV4InKn4uhbPXMK27VKOoxmU= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1784274326; c=relaxed/simple; bh=+faKZynl1LdYRIo2D514yPduzxIHqkTpnCs37yUxs98=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=vIY2iH31bkU6oD3Aq2Q8WQtvMh3WvkdtDOnx7GND5a+zDp9TLuNTXub1ITs/RINfPSX6gLRanzGJ3Xj8QGHjI3MAMzNHo99d3GGYbXWPAhO9xhdYvEVB9vCNPmozvWtPkbJYtd2uSVM4onMPSEPfxQTpp9N3yZtVvAj2n1MAeKA= ARC-Authentication-Results: i=1; sourceware.org; dkim=pass (2048-bit key, unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=UZy8JM06 DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BDFED4BA2E30 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1784274326; x=1815810326; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=+faKZynl1LdYRIo2D514yPduzxIHqkTpnCs37yUxs98=; b=UZy8JM063qXwgsmdKt9d2I3R67Nc1kYHL1P3uTtaz6X+u6DJLDoZk/mc HjNuzq5THyekfsHpXfsfvn3CM2lhTQ0jVBQCSJ9SBylYJnqCYCJezmO9n sOvRTLAXzZCiuDyKnCdwBmf1X69wi4ckcjliUQVq2tiCI7LbeQc61GEft YgcB3+nphdueJaCFqpIyoDLtCfvtlKD8pGCCHl8ooY8SNfORNpWV7kxp2 +xlbPc97sd2bQJY8cpUD+JCBqVv6Rld3IiVImxwD3AUDvCiT5gXxvsMmF q0iPyJwnjWkgWfEgASTNYs/ATzK7jLy5tBC758rSc/grsT51654nwz1ac A==; X-CSE-ConnectionGUID: Trmti5IXQ6KWy0Zoj4R/IQ== X-CSE-MsgGUID: ssJdg+LpR6iub52QwV81Mw== X-IronPort-AV: E=McAfee;i="6800,10657,11848"; a="85035106" X-IronPort-AV: E=Sophos;i="6.25,168,1779174000"; d="scan'208";a="85035106" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2026 00:45:26 -0700 X-CSE-ConnectionGUID: n649FYEsRtaFmZI0Ij1I+w== X-CSE-MsgGUID: vhkuW45oSGSWEdvOh8t2pQ== X-ExtLoop1: 1 Received: from dut1629dg2frd.igk.intel.com (HELO localhost) ([10.211.178.246]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Jul 2026 00:45:24 -0700 From: Klaus Gerlicher To: gdb-patches@sourceware.org Cc: TankutBaris.Aktemur@amd.com, aburgess@redhat.com Subject: [PATCH v4 1/1] gdb: avoid conversion of SIGSEGV to SIGTRAP on user breakpoints Date: Fri, 17 Jul 2026 07:44:53 +0000 Message-Id: <20260717074453.253386-2-klaus.gerlicher@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260717074453.253386-1-klaus.gerlicher@intel.com> References: <20260717074453.253386-1-klaus.gerlicher@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org From: "Gerlicher, Klaus" GDB converts signals GDB_SIGNAL_ILL, GDB_SIGNAL_SEGV and GDB_SIGNAL_EMT to GDB_SIGNAL_TRAP if a breakpoint is inserted at the fault location. If, due to imprecise page fault reporting, a breakpoint is at the same address as the fault address, this signal would always be reported as GDB_SIGNAL_TRAP. Add a new gdbarch function, imprecise_pagefault_reporting, that allows the signal conversion from GDB_SIGNAL_SEGV to GDB_SIGNAL_TRAP to be skipped for an architecture. The default is false (conversion enabled), preserving existing behavior. --- gdb/gdbarch-gen.c | 22 ++++++++++++++++++++++ gdb/gdbarch-gen.h | 7 +++++++ gdb/gdbarch_components.py | 12 ++++++++++++ gdb/infrun.c | 4 +++- 4 files changed, 44 insertions(+), 1 deletion(-) diff --git a/gdb/gdbarch-gen.c b/gdb/gdbarch-gen.c index f424fa2a86e..d9bb3e7078c 100644 --- a/gdb/gdbarch-gen.c +++ b/gdb/gdbarch-gen.c @@ -253,6 +253,7 @@ struct gdbarch gdbarch_core_parse_exec_context_ftype *core_parse_exec_context = default_core_parse_exec_context; gdbarch_shadow_stack_push_ftype *shadow_stack_push = nullptr; gdbarch_get_shadow_stack_pointer_ftype *get_shadow_stack_pointer = default_get_shadow_stack_pointer; + gdbarch_imprecise_pagefault_reporting_ftype *imprecise_pagefault_reporting = [] () -> bool {return false;}; }; /* Create a new ``struct gdbarch'' based on information provided by @@ -513,6 +514,7 @@ verify_gdbarch (struct gdbarch *gdbarch) /* Skip verify of core_parse_exec_context, invalid_p == 0. */ /* Skip verify of shadow_stack_push, has predicate. */ /* Skip verify of get_shadow_stack_pointer, invalid_p == 0. */ + /* Skip verify of imprecise_pagefault_reporting, invalid_p == 0. */ if (!log.empty ()) internal_error (_("verify_gdbarch: the following are invalid ...%s"), log.c_str ()); @@ -1339,6 +1341,9 @@ gdbarch_dump (struct gdbarch *gdbarch, struct ui_file *file) gdb_printf (file, "gdbarch_dump: get_shadow_stack_pointer = <%s>\n", host_address_to_string (gdbarch->get_shadow_stack_pointer)); + gdb_printf (file, + "gdbarch_dump: imprecise_pagefault_reporting = <%s>\n", + host_address_to_string (gdbarch->imprecise_pagefault_reporting)); if (gdbarch->dump_tdep != nullptr) gdbarch->dump_tdep (gdbarch, file); } @@ -5286,3 +5291,20 @@ set_gdbarch_get_shadow_stack_pointer (struct gdbarch *gdbarch, { gdbarch->get_shadow_stack_pointer = get_shadow_stack_pointer; } + +bool +gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch) +{ + gdb_assert (gdbarch != NULL); + gdb_assert (gdbarch->imprecise_pagefault_reporting != NULL); + if (gdbarch_debug >= 2) + gdb_printf (gdb_stdlog, "gdbarch_imprecise_pagefault_reporting called\n"); + return gdbarch->imprecise_pagefault_reporting (); +} + +void +set_gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch, + gdbarch_imprecise_pagefault_reporting_ftype imprecise_pagefault_reporting) +{ + gdbarch->imprecise_pagefault_reporting = imprecise_pagefault_reporting; +} diff --git a/gdb/gdbarch-gen.h b/gdb/gdbarch-gen.h index 678b308fba5..bb95df25eb6 100644 --- a/gdb/gdbarch-gen.h +++ b/gdb/gdbarch-gen.h @@ -1752,3 +1752,10 @@ void set_gdbarch_shadow_stack_push (struct gdbarch *gdbarch, gdbarch_shadow_stac using gdbarch_get_shadow_stack_pointer_ftype = std::optional (struct gdbarch *gdbarch, regcache *regcache, bool &shadow_stack_enabled); std::optional gdbarch_get_shadow_stack_pointer (struct gdbarch *gdbarch, regcache *regcache, bool &shadow_stack_enabled); void set_gdbarch_get_shadow_stack_pointer (struct gdbarch *gdbarch, gdbarch_get_shadow_stack_pointer_ftype *get_shadow_stack_pointer); + +/* Returns true if architecture has imprecise pagefault reporting. This is + used in conversion of SIGSEGV to SIGTRAP for an architecture. */ + +typedef bool (gdbarch_imprecise_pagefault_reporting_ftype) (); +extern bool gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch); +extern void set_gdbarch_imprecise_pagefault_reporting (struct gdbarch *gdbarch, gdbarch_imprecise_pagefault_reporting_ftype *imprecise_pagefault_reporting); diff --git a/gdb/gdbarch_components.py b/gdb/gdbarch_components.py index b9304d3036d..d903446435f 100644 --- a/gdb/gdbarch_components.py +++ b/gdb/gdbarch_components.py @@ -2781,3 +2781,15 @@ SHADOW_STACK_ENABLED to false. predefault="default_get_shadow_stack_pointer", invalid=False, ) + +Function( + comment=""" +Returns true if architecture has imprecise pagefault reporting. This is +used in conversion of SIGSEGV to SIGTRAP for an architecture. +""", + type="bool", + name="imprecise_pagefault_reporting", + params=[], + predefault="[] () -> bool {return false;}", + invalid=False +) diff --git a/gdb/infrun.c b/gdb/infrun.c index c0767e7f764..25ed7e7523f 100644 --- a/gdb/infrun.c +++ b/gdb/infrun.c @@ -6331,7 +6331,9 @@ handle_inferior_event (struct execution_control_state *ecs) stack. */ if (ecs->ws.kind () == TARGET_WAITKIND_STOPPED && (ecs->ws.sig () == GDB_SIGNAL_ILL - || ecs->ws.sig () == GDB_SIGNAL_SEGV + || (ecs->ws.sig () == GDB_SIGNAL_SEGV + && !gdbarch_imprecise_pagefault_reporting + (target_thread_architecture (ecs->event_thread->ptid))) || ecs->ws.sig () == GDB_SIGNAL_EMT)) { struct regcache *regcache = get_thread_regcache (ecs->event_thread); -- 2.34.1 Intel Deutschland GmbH Registered Address: Dornacher Strasse 1, 85622 Feldkirchen, Germany Tel: +49 89 991 430, www.intel.de Managing Directors: Harry Demas, Jeffrey Schneiderman, Yin Chong Sorrell Chairperson of the Supervisory Board: Nicole Lau Registered Seat: Munich Commercial Register: Amtsgericht Muenchen HRB 186928