Re: [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])

Re: [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])

[Doug Evans via gdb-patches]

Stafford Horne writes:
 > From: Peter Gavin <pgavin@gmail.com>
 > 
 > * sim/common/ChangeLog:
 > 
 > 2016-05-21  Peter Gavin  <pgavin@gmail.com>
 > 	    Stafford Horne <shorne@gmail.com>
 > 
 > 	* cgen-accfp.c (remsf, remdf): New function.
 > 	(cgen_init_accurate_fpu): Add remsf and remdf.
 > 	* cgen-fpu.h (cgen_fp_ops): Add remsf, remdf, remxf and remtf.
 > 	* sim-fpu.c (sim_fpu_rem): New function.
 > 	* sim-fpu.h (sim_fpu_status_invalid_irx): New enum.
 > 	(sim_fpu_rem): New function.

LGTM (with the discussed changes to date).

Re: [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])

[Doug Evans via gdb-patches]

Stafford Horne writes:
 > > > +    else if (n.class == sim_fpu_class_number
 > > > +	&& n.normal_exp <= (NR_FRAC_GUARD)) /* If not too large round.  */
 > > 
 > > This line should be aligned with the opening parenthesis (well, one char to the right).
 > 
 > Right, that does move the comment out of the 80 char range, but just the
 > ending '*/'.  I hope thats ok.

A common thing to do is put the comment on the preceding line.

E.g.,

    else if (n.class == sim_fpu_class_number
             /* If not too large round.  */
             && n.normal_exp <= (NR_FRAC_GUARD))

[appropriately tabbed of course]

[PATCH v5 0/6] sim port for OpenRISC

[Stafford Horne]

Hello,

(what I thought would be a few days turned into a month since the comments
on v4)

Please find attached the sim patches that allow to get a basic OpenRISC
system running.  This was used to verify the OpenRISC gdb port.

The main author is Peter Gavin who should have his FSF copyright in place.

Request for comments on:
 - The testcase has a few tests commented out. I do not plan to fix now,
   but hopefully be addressed after upstreaming.

                           # Guide to Code #

As Simon has requested I have tried to comment on the functions in the
simulator implementation.  But I want to provide some general architecture
comments here for reference.  Please let me know if there is a better place
for these kind of docs.

The or1k sim uses the CGEN system to generate most of the simulator code.
There is some documentation for CGEN on sourceware.org here:

  https://sourceware.org/cgen/docs/cgen.html

In the binutils-gdb project there are several files which get combined to
make up the CGEN simulator.  The process for how those are built can be
seen in `or1k/Makefile.in`.  But the main files are:

MAIN
 sim/common/nrun.c - the main() calls sim_open(), sim_resume() and others
 sim/or1k/sim-if.c - implements sim_open() and others used by nrun
                     when envoking sim in gdb, gdb uses sim_open() directly

CGEN input and generated files
 cpu/or1k*.cpu - these define the hardware, model and semantics
 sim/or1k/arch.c - generated defines sim_machs array
 sim/or1k/cpu.c - *generated defines register setters and getters
 sim/or1k/decode.c - generated defines instruction decoder
 sim/or1k/model.c - generated defines instruction cycles
 sim/or1k/sem.c - *generated defines instruction operation semantics
 sim/or1k/sem-switch.c - *generated ditto but as a switch

ENGINE runs decode execute loop
 sim/common/cgen-* - cgen implementation helpers
 sim/common/cgen-run.c - implements sim_resume() which runs the engine
 sim/common/genmloop.sh - helper script to generate mloop.c engine the
                          decode, execute loop
 sim/or1k/mloop.in - openRISC implementation of mloop parts

EXTRAS callbacks from sem* to c code
 sim/or1k/or1k.c - implements some instructions in c (not cgen schema)
 sim/or1k/traps.c - exception handler

For each sim architecture we have choices for how the mloop is implemented.
The OpenRISC engine uses scache pbb (pseudo-basic-block) instruction
extraction with both fast (sem-switch.c based) and full (sem.c based)
implementations.  The fast and full modes are switch via the command line
options to the `run` command, i.e. --trace-insn will run in full mode.

                            # Building #

Simon asked for some details on how we build and test the openrisc sim.
Here are some details:

                            ## TOOLCHAIN ##

This may not be needed as binutils contains most/all of the utilities
required.  But if needed, get this toolchain (this is the newlib binary,
others also available)

  https://github.com/openrisc/or1k-gcc/releases/download/or1k-5.4.0-20170218/or1k-elf-5.4.0-20170218.tar.xz

If you want to build that from scratch look to:

  https://github.com/openrisc/newlib/blob/scripts/build.sh

                              ## GDB ##

In a directory along side binutils-gdb source

  mkdir build-or1k-elf-gdb
  cd build-or1k-elf-gdb

  ../binutils-gdb/configure --target=or1k-elf \
    --prefix=/opt/shorne/software/or1k \
    --disable-itcl \
    --disable-tk \
    --disable-tcl \
    --disable-winsup \
    --disable-gdbtk \
    --disable-libgui \
    --disable-rda \
    --disable-sid \
    --with-sysroot \
    --disable-newlib \
    --disable-libgloss \
    --disable-gas \
    --disable-ld \
    --disable-binutils \
    --disable-gprof \
    --with-system-zlib

  # make gdb, sim
  make

  # test sim
  cd sim
  make check

The sim creates a binary simulator too, you can run binaries such as hello
world with:

  or1k-elf-gcc hello.c
  ./or1k/run --trace-insn ./a.out

                            # Test Results #

Sim dejagnu tests were added specifically for openrisc and used to test
this.  Please see the details of running the testsuite for sim below:

=== sim Summary ===

# of expected passes            18
/home/shorne/work/openrisc/build-gdb/sim/or1k/run 0.5


Thanks,
-Stafford

Changes since v4
 * Added comments to most of the functions
 * Implemented remainder fpu function
 * Actually wire in fpu and error handling logic
 * Added fpu test case

Changes since v3
 * Cleaned up indentation and style of sim testsuite
 * Cleaned up TODOs in testsuite
 * Implemented range exception

Changes since v2
 * Removed 64-bit implementation (reduced files)
 * Removed cgen suffix patch
 * Removed different builds for linux
 * Removed unused macros
 * Fixed gnu style issues pointed out by Mike
 * Fixed copyrights (not Cygnus, added to each file)

Changes since v1
 * Squashed sim patches into single sim patch
 * Put Generated files in separate patch
 * I have my sim/gdb copyright assignment complete


Peter Gavin (3):
  sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])
  sim: cgen: add MUL2OFSI and MUL1OFSI macros (needed for OR1K l.mul[u])
  sim: testsuite: add testsuite for or1k sim

Stafford Horne (3):
  sim: or1k: add or1k target to sim
  sim: or1k: add cgen generated files
  sim: or1k: add autoconf generated files

 sim/common/cgen-accfp.c                        |    40 +
 sim/common/cgen-fpu.h                          |     4 +
 sim/common/cgen-ops.h                          |    18 +
 sim/common/sim-fpu.c                           |    90 +-
 sim/common/sim-fpu.h                           |    13 +-
 sim/configure                                  |     9 +
 sim/configure.tgt                              |     4 +
 sim/or1k/Makefile.in                           |   147 +
 sim/or1k/aclocal.m4                            |   119 +
 sim/or1k/arch.c                                |    38 +
 sim/or1k/arch.h                                |    50 +
 sim/or1k/config.in                             |   248 +
 sim/or1k/configure                             | 16043 +++++++++++++++++++++++
 sim/or1k/configure.ac                          |    17 +
 sim/or1k/cpu.c                                 | 10181 ++++++++++++++
 sim/or1k/cpu.h                                 |  5024 +++++++
 sim/or1k/cpuall.h                              |    66 +
 sim/or1k/decode.c                              |  2559 ++++
 sim/or1k/decode.h                              |    94 +
 sim/or1k/mloop.in                              |   242 +
 sim/or1k/model.c                               |  3809 ++++++
 sim/or1k/or1k-sim.h                            |    95 +
 sim/or1k/or1k.c                                |   355 +
 sim/or1k/sem-switch.c                          |  2748 ++++
 sim/or1k/sem.c                                 |  2953 +++++
 sim/or1k/sim-if.c                              |   281 +
 sim/or1k/sim-main.h                            |    81 +
 sim/or1k/traps.c                               |   299 +
 sim/testsuite/configure                        |     4 +
 sim/testsuite/sim/or1k/add.S                   |   606 +
 sim/testsuite/sim/or1k/alltests.exp            |    34 +
 sim/testsuite/sim/or1k/and.S                   |   198 +
 sim/testsuite/sim/or1k/basic.S                 |   522 +
 sim/testsuite/sim/or1k/div.S                   |   290 +
 sim/testsuite/sim/or1k/ext.S                   |   236 +
 sim/testsuite/sim/or1k/find.S                  |   100 +
 sim/testsuite/sim/or1k/flag.S                  |   378 +
 sim/testsuite/sim/or1k/fpu.S                   |   128 +
 sim/testsuite/sim/or1k/jump.S                  |   104 +
 sim/testsuite/sim/or1k/load.S                  |   358 +
 sim/testsuite/sim/or1k/mac.S                   |   778 ++
 sim/testsuite/sim/or1k/mfspr.S                 |   171 +
 sim/testsuite/sim/or1k/mul.S                   |   573 +
 sim/testsuite/sim/or1k/or.S                    |   199 +
 sim/testsuite/sim/or1k/or1k-asm-test-env.h     |    59 +
 sim/testsuite/sim/or1k/or1k-asm-test-helpers.h |   121 +
 sim/testsuite/sim/or1k/or1k-asm-test.h         |   225 +
 sim/testsuite/sim/or1k/or1k-asm.h              |    37 +
 sim/testsuite/sim/or1k/or1k-test.ld            |    75 +
 sim/testsuite/sim/or1k/ror.S                   |   159 +
 sim/testsuite/sim/or1k/shift.S                 |   541 +
 sim/testsuite/sim/or1k/spr-defs.h              |   120 +
 sim/testsuite/sim/or1k/sub.S                   |   201 +
 sim/testsuite/sim/or1k/xor.S                   |   200 +
 54 files changed, 52037 insertions(+), 7 deletions(-)
 create mode 100644 sim/or1k/Makefile.in
 create mode 100644 sim/or1k/aclocal.m4
 create mode 100644 sim/or1k/arch.c
 create mode 100644 sim/or1k/arch.h
 create mode 100644 sim/or1k/config.in
 create mode 100755 sim/or1k/configure
 create mode 100644 sim/or1k/configure.ac
 create mode 100644 sim/or1k/cpu.c
 create mode 100644 sim/or1k/cpu.h
 create mode 100644 sim/or1k/cpuall.h
 create mode 100644 sim/or1k/decode.c
 create mode 100644 sim/or1k/decode.h
 create mode 100644 sim/or1k/mloop.in
 create mode 100644 sim/or1k/model.c
 create mode 100644 sim/or1k/or1k-sim.h
 create mode 100644 sim/or1k/or1k.c
 create mode 100644 sim/or1k/sem-switch.c
 create mode 100644 sim/or1k/sem.c
 create mode 100644 sim/or1k/sim-if.c
 create mode 100644 sim/or1k/sim-main.h
 create mode 100644 sim/or1k/traps.c
 create mode 100644 sim/testsuite/sim/or1k/add.S
 create mode 100644 sim/testsuite/sim/or1k/alltests.exp
 create mode 100644 sim/testsuite/sim/or1k/and.S
 create mode 100644 sim/testsuite/sim/or1k/basic.S
 create mode 100644 sim/testsuite/sim/or1k/div.S
 create mode 100644 sim/testsuite/sim/or1k/ext.S
 create mode 100644 sim/testsuite/sim/or1k/find.S
 create mode 100644 sim/testsuite/sim/or1k/flag.S
 create mode 100644 sim/testsuite/sim/or1k/fpu.S
 create mode 100644 sim/testsuite/sim/or1k/jump.S
 create mode 100644 sim/testsuite/sim/or1k/load.S
 create mode 100644 sim/testsuite/sim/or1k/mac.S
 create mode 100644 sim/testsuite/sim/or1k/mfspr.S
 create mode 100644 sim/testsuite/sim/or1k/mul.S
 create mode 100644 sim/testsuite/sim/or1k/or.S
 create mode 100644 sim/testsuite/sim/or1k/or1k-asm-test-env.h
 create mode 100644 sim/testsuite/sim/or1k/or1k-asm-test-helpers.h
 create mode 100644 sim/testsuite/sim/or1k/or1k-asm-test.h
 create mode 100644 sim/testsuite/sim/or1k/or1k-asm.h
 create mode 100644 sim/testsuite/sim/or1k/or1k-test.ld
 create mode 100644 sim/testsuite/sim/or1k/ror.S
 create mode 100644 sim/testsuite/sim/or1k/shift.S
 create mode 100644 sim/testsuite/sim/or1k/spr-defs.h
 create mode 100644 sim/testsuite/sim/or1k/sub.S
 create mode 100644 sim/testsuite/sim/or1k/xor.S

-- 
2.13.5

[PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])

[Stafford Horne]

From: Peter Gavin <pgavin@gmail.com>

* sim/common/ChangeLog:

2016-05-21  Peter Gavin  <pgavin@gmail.com>
	    Stafford Horne <shorne@gmail.com>

	* cgen-accfp.c (remsf, remdf): New function.
	(cgen_init_accurate_fpu): Add remsf and remdf.
	* cgen-fpu.h (cgen_fp_ops): Add remsf, remdf, remxf and remtf.
	* sim-fpu.c (sim_fpu_rem): New function.
	* sim-fpu.h (sim_fpu_status_invalid_irx): New enum.
	(sim_fpu_rem): New function.
---
 sim/common/cgen-accfp.c | 40 ++++++++++++++++++++++
 sim/common/cgen-fpu.h   |  4 +++
 sim/common/sim-fpu.c    | 90 +++++++++++++++++++++++++++++++++++++++++++++++--
 sim/common/sim-fpu.h    | 13 ++++---
 4 files changed, 140 insertions(+), 7 deletions(-)

diff --git a/sim/common/cgen-accfp.c b/sim/common/cgen-accfp.c
index afbca6d582..5d600c6e41 100644
--- a/sim/common/cgen-accfp.c
+++ b/sim/common/cgen-accfp.c
@@ -93,6 +93,25 @@ divsf (CGEN_FPU* fpu, SF x, SF y)
 }
 
 static SF
+remsf (CGEN_FPU* fpu, SF x, SF y)
+{
+  sim_fpu op1;
+  sim_fpu op2;
+  sim_fpu ans;
+  unsigned32 res;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&op1, x);
+  sim_fpu_32to (&op2, y);
+  status = sim_fpu_rem (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
+  sim_fpu_to32 (&res, &ans);
+
+  return res;
+}
+
+static SF
 negsf (CGEN_FPU* fpu, SF x)
 {
   sim_fpu op1;
@@ -453,6 +472,25 @@ divdf (CGEN_FPU* fpu, DF x, DF y)
 }
 
 static DF
+remdf (CGEN_FPU* fpu, DF x, DF y)
+{
+  sim_fpu op1;
+  sim_fpu op2;
+  sim_fpu ans;
+  unsigned64 res;
+  sim_fpu_status status;
+
+  sim_fpu_64to (&op1, x);
+  sim_fpu_64to (&op2, y);
+  status = sim_fpu_rem (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
+  sim_fpu_to64(&res, &ans);
+
+  return res;
+}
+
+static DF
 negdf (CGEN_FPU* fpu, DF x)
 {
   sim_fpu op1;
@@ -664,6 +702,7 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
   o->subsf = subsf;
   o->mulsf = mulsf;
   o->divsf = divsf;
+  o->remsf = remsf;
   o->negsf = negsf;
   o->abssf = abssf;
   o->sqrtsf = sqrtsf;
@@ -682,6 +721,7 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
   o->subdf = subdf;
   o->muldf = muldf;
   o->divdf = divdf;
+  o->remdf = remdf;
   o->negdf = negdf;
   o->absdf = absdf;
   o->sqrtdf = sqrtdf;
diff --git a/sim/common/cgen-fpu.h b/sim/common/cgen-fpu.h
index 134b4d031c..5f9b55d32e 100644
--- a/sim/common/cgen-fpu.h
+++ b/sim/common/cgen-fpu.h
@@ -69,6 +69,7 @@ struct cgen_fp_ops {
   SF (*subsf) (CGEN_FPU*, SF, SF);
   SF (*mulsf) (CGEN_FPU*, SF, SF);
   SF (*divsf) (CGEN_FPU*, SF, SF);
+  SF (*remsf) (CGEN_FPU*, SF, SF);
   SF (*negsf) (CGEN_FPU*, SF);
   SF (*abssf) (CGEN_FPU*, SF);
   SF (*sqrtsf) (CGEN_FPU*, SF);
@@ -93,6 +94,7 @@ struct cgen_fp_ops {
   DF (*subdf) (CGEN_FPU*, DF, DF);
   DF (*muldf) (CGEN_FPU*, DF, DF);
   DF (*divdf) (CGEN_FPU*, DF, DF);
+  DF (*remdf) (CGEN_FPU*, DF, DF);
   DF (*negdf) (CGEN_FPU*, DF);
   DF (*absdf) (CGEN_FPU*, DF);
   DF (*sqrtdf) (CGEN_FPU*, DF);
@@ -142,6 +144,7 @@ struct cgen_fp_ops {
   XF (*subxf) (CGEN_FPU*, XF, XF);
   XF (*mulxf) (CGEN_FPU*, XF, XF);
   XF (*divxf) (CGEN_FPU*, XF, XF);
+  XF (*remxf) (CGEN_FPU*, XF, XF);
   XF (*negxf) (CGEN_FPU*, XF);
   XF (*absxf) (CGEN_FPU*, XF);
   XF (*sqrtxf) (CGEN_FPU*, XF);
@@ -180,6 +183,7 @@ struct cgen_fp_ops {
   TF (*subtf) (CGEN_FPU*, TF, TF);
   TF (*multf) (CGEN_FPU*, TF, TF);
   TF (*divtf) (CGEN_FPU*, TF, TF);
+  TF (*remtf) (CGEN_FPU*, TF, TF);
   TF (*negtf) (CGEN_FPU*, TF);
   TF (*abstf) (CGEN_FPU*, TF);
   TF (*sqrttf) (CGEN_FPU*, TF);
diff --git a/sim/common/sim-fpu.c b/sim/common/sim-fpu.c
index 0d4d08ae86..854d19dfd8 100644
--- a/sim/common/sim-fpu.c
+++ b/sim/common/sim-fpu.c
@@ -41,7 +41,6 @@ along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
 #include "sim-io.h"
 #include "sim-assert.h"
 
-
 /* Debugging support.
    If digits is -1, then print all digits.  */
 
@@ -834,6 +833,7 @@ do_normal_round (sim_fpu *f,
   unsigned64 guardmask = LSMASK64 (nr_guards - 1, 0);
   unsigned64 guardmsb = LSBIT64 (nr_guards - 1);
   unsigned64 fraclsb = guardmsb << 1;
+  /* If there are decimal values do the round.  */
   if ((f->fraction & guardmask))
     {
       int status = sim_fpu_status_inexact;
@@ -865,6 +865,7 @@ do_normal_round (sim_fpu *f,
 	case sim_fpu_round_zero:
 	  break;
 	}
+      /* Actually do the rounding by masking out the decimals.  */
       f->fraction &= ~guardmask;
       /* Round if needed, handle resulting overflow.  */
       if ((status & sim_fpu_status_rounded))
@@ -1384,7 +1385,6 @@ sim_fpu_mul (sim_fpu *f,
        up in the high 64 bit word.  In the source the decimal point
        was at NR_FRAC_GUARD. */
     f->normal_exp += NR_FRAC_GUARD + 64 - (NR_FRAC_GUARD * 2);
-
     /* The high word is bounded according to the above.  Consequently
        it has never overflowed into IMPLICIT_2. */
     ASSERT (high < LSBIT64 (((NR_FRAC_GUARD + 1) * 2) - 64));
@@ -1551,6 +1551,89 @@ sim_fpu_div (sim_fpu *f,
 
 
 INLINE_SIM_FPU (int)
+sim_fpu_rem (sim_fpu *f,
+	     const sim_fpu *l,
+	     const sim_fpu *r)
+{
+  if (sim_fpu_is_snan (l))
+    {
+      *f = *l;
+      f->class = sim_fpu_class_qnan;
+      return sim_fpu_status_invalid_snan;
+    }
+  if (sim_fpu_is_snan (r))
+    {
+      *f = *r;
+      f->class = sim_fpu_class_qnan;
+      return sim_fpu_status_invalid_snan;
+    }
+  if (sim_fpu_is_qnan (l))
+    {
+      *f = *l;
+      f->class = sim_fpu_class_qnan;
+      return 0;
+    }
+  if (sim_fpu_is_qnan (r))
+    {
+      *f = *r;
+      f->class = sim_fpu_class_qnan;
+      return 0;
+    }
+  if (sim_fpu_is_infinity (l))
+    {
+      *f = sim_fpu_qnan;
+      return sim_fpu_status_invalid_irx;
+    }
+  if (sim_fpu_is_zero (r))
+    {
+      *f = sim_fpu_qnan;
+      return sim_fpu_status_invalid_div0;
+    }
+  if (sim_fpu_is_zero (l))
+    {
+      *f = *l;
+      return 0;
+    }
+  if (sim_fpu_is_infinity (r))
+    {
+      *f = *l;
+      return 0;
+    }
+  {
+    sim_fpu n, tmp;
+
+    /* Remainder is calculated as l-n*r, where n is l/r rounded to the
+       nearest integer.  The variable n is rounded half even.  */
+
+    sim_fpu_div (&n, l, r);
+    sim_fpu_round_64 (&n, 0, 0);
+
+    if (n.normal_exp < -1) /* If n looks like zero just return l.  */
+      {
+	*f = *l;
+	return 0;
+      }
+    else if (n.class == sim_fpu_class_number
+	&& n.normal_exp <= (NR_FRAC_GUARD)) /* If not too large round.  */
+      do_normal_round (&n, (NR_FRAC_GUARD) - n.normal_exp, sim_fpu_round_near);
+
+    /* Mark 0's as zero so multiply can detect zero.  */
+    if (n.fraction == 0)
+      n.class = sim_fpu_class_zero;
+
+    /* Calculate n*r.  */
+    sim_fpu_mul (&tmp, &n, r);
+    sim_fpu_round_64 (&tmp, 0, 0);
+
+    /* Finally calculate l-n*r.  */
+    sim_fpu_sub (f, l, &tmp);
+
+    return 0;
+  }
+}
+
+
+INLINE_SIM_FPU (int)
 sim_fpu_max (sim_fpu *f,
 	     const sim_fpu *l,
 	     const sim_fpu *r)
@@ -2533,6 +2616,9 @@ sim_fpu_print_status (int status,
 	case sim_fpu_status_invalid_sqrt:
 	  print (arg, "%sSQRT", prefix);
 	  break;
+	case sim_fpu_status_invalid_irx:
+	  print (arg, "%sIRX", prefix);
+	  break;
 	case sim_fpu_status_inexact:
 	  print (arg, "%sX", prefix);
 	  break;
diff --git a/sim/common/sim-fpu.h b/sim/common/sim-fpu.h
index d27d80a513..adf3b1904a 100644
--- a/sim/common/sim-fpu.h
+++ b/sim/common/sim-fpu.h
@@ -146,11 +146,12 @@ typedef enum
   sim_fpu_status_invalid_div0 = 128, /* (X / 0) */
   sim_fpu_status_invalid_cmp = 256, /* compare */
   sim_fpu_status_invalid_sqrt = 512,
-  sim_fpu_status_rounded = 1024,
-  sim_fpu_status_inexact = 2048,
-  sim_fpu_status_overflow = 4096,
-  sim_fpu_status_underflow = 8192,
-  sim_fpu_status_denorm = 16384,
+  sim_fpu_status_invalid_irx = 1024, /* (inf % X) */
+  sim_fpu_status_rounded = 2048,
+  sim_fpu_status_inexact = 4096,
+  sim_fpu_status_overflow = 8192,
+  sim_fpu_status_underflow = 16384,
+  sim_fpu_status_denorm = 32768,
 } sim_fpu_status;
 
 
@@ -230,6 +231,8 @@ INLINE_SIM_FPU (int) sim_fpu_mul (sim_fpu *f,
 				  const sim_fpu *l, const sim_fpu *r);
 INLINE_SIM_FPU (int) sim_fpu_div (sim_fpu *f,
 				  const sim_fpu *l, const sim_fpu *r);
+INLINE_SIM_FPU (int) sim_fpu_rem (sim_fpu *f,
+				  const sim_fpu *l, const sim_fpu *r);
 INLINE_SIM_FPU (int) sim_fpu_max (sim_fpu *f,
 				  const sim_fpu *l, const sim_fpu *r);
 INLINE_SIM_FPU (int) sim_fpu_min (sim_fpu *f,
-- 
2.13.5

Re: [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])

[Simon Marchi]

As far as I can tell, this patch looks good, but I'm more or less clueless about floating point stuff...

I just pointed out nits:

On 2017-10-05 09:49 AM, Stafford Horne wrote:
> From: Peter Gavin <pgavin@gmail.com>
>
> * sim/common/ChangeLog:
>
> 2016-05-21  Peter Gavin  <pgavin@gmail.com>
> 	    Stafford Horne <shorne@gmail.com>
>
> 	* cgen-accfp.c (remsf, remdf): New function.
> 	(cgen_init_accurate_fpu): Add remsf and remdf.
> 	* cgen-fpu.h (cgen_fp_ops): Add remsf, remdf, remxf and remtf.
> 	* sim-fpu.c (sim_fpu_rem): New function.

Mention the change to sim_fpu_print_status.

sim-fpu.c contains other changes (comments added, lines removed).  If you think the changes belong with this patch, mention them here, otherwise submit them as a separate patch.
> @@ -1551,6 +1551,89 @@ sim_fpu_div (sim_fpu *f,
>
>
>  INLINE_SIM_FPU (int)
> +sim_fpu_rem (sim_fpu *f,
> +	     const sim_fpu *l,
> +	     const sim_fpu *r)
> +{
> +  if (sim_fpu_is_snan (l))
> +    {
> +      *f = *l;
> +      f->class = sim_fpu_class_qnan;
> +      return sim_fpu_status_invalid_snan;
> +    }
> +  if (sim_fpu_is_snan (r))
> +    {
> +      *f = *r;
> +      f->class = sim_fpu_class_qnan;
> +      return sim_fpu_status_invalid_snan;
> +    }
> +  if (sim_fpu_is_qnan (l))
> +    {
> +      *f = *l;
> +      f->class = sim_fpu_class_qnan;
> +      return 0;
> +    }
> +  if (sim_fpu_is_qnan (r))
> +    {
> +      *f = *r;
> +      f->class = sim_fpu_class_qnan;
> +      return 0;
> +    }
> +  if (sim_fpu_is_infinity (l))
> +    {
> +      *f = sim_fpu_qnan;
> +      return sim_fpu_status_invalid_irx;
> +    }
> +  if (sim_fpu_is_zero (r))
> +    {
> +      *f = sim_fpu_qnan;
> +      return sim_fpu_status_invalid_div0;
> +    }
> +  if (sim_fpu_is_zero (l))
> +    {
> +      *f = *l;
> +      return 0;
> +    }
> +  if (sim_fpu_is_infinity (r))
> +    {
> +      *f = *l;
> +      return 0;
> +    }
> +  {
> +    sim_fpu n, tmp;
> +
> +    /* Remainder is calculated as l-n*r, where n is l/r rounded to the
> +       nearest integer.  The variable n is rounded half even.  */
> +
> +    sim_fpu_div (&n, l, r);
> +    sim_fpu_round_64 (&n, 0, 0);
> +
> +    if (n.normal_exp < -1) /* If n looks like zero just return l.  */
> +      {
> +	*f = *l;
> +	return 0;
> +      }
> +    else if (n.class == sim_fpu_class_number
> +	&& n.normal_exp <= (NR_FRAC_GUARD)) /* If not too large round.  */

This line should be aligned with the opening parenthesis (well, one char to the right).

> +      do_normal_round (&n, (NR_FRAC_GUARD) - n.normal_exp, sim_fpu_round_near);
> +
> +    /* Mark 0's as zero so multiply can detect zero.  */
> +    if (n.fraction == 0)
> +      n.class = sim_fpu_class_zero;
> +
> +    /* Calculate n*r.  */
> +    sim_fpu_mul (&tmp, &n, r);
> +    sim_fpu_round_64 (&tmp, 0, 0);
> +
> +    /* Finally calculate l-n*r.  */
> +    sim_fpu_sub (f, l, &tmp);
> +
> +    return 0;
> +  }
> +}

Thanks,

Simon

Re: [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])

[Stafford Horne]

On Sat, Oct 07, 2017 at 11:52:30AM -0400, Simon Marchi wrote:
> As far as I can tell, this patch looks good, but I'm more or less clueless about floating point stuff...
> 
> I just pointed out nits:
> 
> On 2017-10-05 09:49 AM, Stafford Horne wrote:
> > From: Peter Gavin <pgavin@gmail.com>
> >
> > * sim/common/ChangeLog:
> >
> > 2016-05-21  Peter Gavin  <pgavin@gmail.com>
> > 	    Stafford Horne <shorne@gmail.com>
> >
> > 	* cgen-accfp.c (remsf, remdf): New function.
> > 	(cgen_init_accurate_fpu): Add remsf and remdf.
> > 	* cgen-fpu.h (cgen_fp_ops): Add remsf, remdf, remxf and remtf.
> > 	* sim-fpu.c (sim_fpu_rem): New function.
> 
> Mention the change to sim_fpu_print_status.

Right, Thank you.

> sim-fpu.c contains other changes (comments added, lines removed).  If you think the changes belong with this patch, mention them here, otherwise submit them as a separate patch.

I just removed them, they are noise.  I saw them when I reviewed the patch
but was not sure if it would be an issue to keep them.

> > @@ -1551,6 +1551,89 @@ sim_fpu_div (sim_fpu *f,
> >
> >
> >  INLINE_SIM_FPU (int)
> > +sim_fpu_rem (sim_fpu *f,
> > +	     const sim_fpu *l,
> > +	     const sim_fpu *r)
> > +{
> > +  if (sim_fpu_is_snan (l))
> > +    {
> > +      *f = *l;
> > +      f->class = sim_fpu_class_qnan;
> > +      return sim_fpu_status_invalid_snan;
> > +    }
> > +  if (sim_fpu_is_snan (r))
> > +    {
> > +      *f = *r;
> > +      f->class = sim_fpu_class_qnan;
> > +      return sim_fpu_status_invalid_snan;
> > +    }
> > +  if (sim_fpu_is_qnan (l))
> > +    {
> > +      *f = *l;
> > +      f->class = sim_fpu_class_qnan;
> > +      return 0;
> > +    }
> > +  if (sim_fpu_is_qnan (r))
> > +    {
> > +      *f = *r;
> > +      f->class = sim_fpu_class_qnan;
> > +      return 0;
> > +    }
> > +  if (sim_fpu_is_infinity (l))
> > +    {
> > +      *f = sim_fpu_qnan;
> > +      return sim_fpu_status_invalid_irx;
> > +    }
> > +  if (sim_fpu_is_zero (r))
> > +    {
> > +      *f = sim_fpu_qnan;
> > +      return sim_fpu_status_invalid_div0;
> > +    }
> > +  if (sim_fpu_is_zero (l))
> > +    {
> > +      *f = *l;
> > +      return 0;
> > +    }
> > +  if (sim_fpu_is_infinity (r))
> > +    {
> > +      *f = *l;
> > +      return 0;
> > +    }
> > +  {
> > +    sim_fpu n, tmp;
> > +
> > +    /* Remainder is calculated as l-n*r, where n is l/r rounded to the
> > +       nearest integer.  The variable n is rounded half even.  */
> > +
> > +    sim_fpu_div (&n, l, r);
> > +    sim_fpu_round_64 (&n, 0, 0);
> > +
> > +    if (n.normal_exp < -1) /* If n looks like zero just return l.  */
> > +      {
> > +	*f = *l;
> > +	return 0;
> > +      }
> > +    else if (n.class == sim_fpu_class_number
> > +	&& n.normal_exp <= (NR_FRAC_GUARD)) /* If not too large round.  */
> 
> This line should be aligned with the opening parenthesis (well, one char to the right).

Right, that does move the comment out of the 80 char range, but just the
ending '*/'.  I hope thats ok.

> > +      do_normal_round (&n, (NR_FRAC_GUARD) - n.normal_exp, sim_fpu_round_near);
> > +
> > +    /* Mark 0's as zero so multiply can detect zero.  */
> > +    if (n.fraction == 0)
> > +      n.class = sim_fpu_class_zero;
> > +
> > +    /* Calculate n*r.  */
> > +    sim_fpu_mul (&tmp, &n, r);
> > +    sim_fpu_round_64 (&tmp, 0, 0);
> > +
> > +    /* Finally calculate l-n*r.  */
> > +    sim_fpu_sub (f, l, &tmp);
> > +
> > +    return 0;
> > +  }
> > +}
> 
> Thanks,
>
> Simon

Thank you,
-Stafford

Re: [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd])

[Simon Marchi]

On 2017-10-08 08:23, Stafford Horne wrote:
>> > +    if (n.normal_exp < -1) /* If n looks like zero just return l.  */
>> > +      {
>> > +	*f = *l;
>> > +	return 0;
>> > +      }
>> > +    else if (n.class == sim_fpu_class_number
>> > +	&& n.normal_exp <= (NR_FRAC_GUARD)) /* If not too large round.  */
>> 
>> This line should be aligned with the opening parenthesis (well, one 
>> char to the right).
> 
> Right, that does move the comment out of the 80 char range, but just 
> the
> ending '*/'.  I hope thats ok.

Hmm, when I try it the trailing */ arrives right before the 80th column.

Simon