From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 117149 invoked by alias); 8 Oct 2017 12:24:05 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sourceware.org Received: (qmail 117111 invoked by uid 89); 8 Oct 2017 12:24:03 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.5 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pf0-f171.google.com Received: from mail-pf0-f171.google.com (HELO mail-pf0-f171.google.com) (209.85.192.171) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 08 Oct 2017 12:24:01 +0000 Received: by mail-pf0-f171.google.com with SMTP id p87so2442766pfj.3 for ; Sun, 08 Oct 2017 05:24:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=bL/jVXR8DnxvQcb+WK6iVPbQ/FD519qpMdO1FykRAFY=; b=DQCVjwne2BZKpJ6KvdP4+7qEHUNQD0KYGf4DBmYgM20w7hQJmLy2YPhAbT4nBQYPGi LKG8XJTxdSR9Lo5lFoFBxyMdfR2W7Hqrq00qXilcrBoNboYp3M8DFh8C4OFjt+F/01Kq M37GBZD2ywsOuBbm723ITDoJiOW62oRzDuS0ZpiFeaex7QKLskAYStZw5ysXmL4kVmvF r0xIatx3hA69wE/vyrR1MTXKFero7ild9McZJVX/6U99hna9W/5f3IrP+TS8qYSLaaLr W+kLnavIk9cBI67vKR/qFs/a0E1/ZuzDLV83oAMbywjG8Efz+/I5nKHhu61kgHrQeEZn 9Zdw== X-Gm-Message-State: AMCzsaXeTkEJ8zWqDgBlPjOHeUAi4lxwTQcuXwOhGOf+6aSvJ+rUHWTc 9KBpjP/l+5hS+r1dJvOSs1h2AOjI X-Google-Smtp-Source: AOwi7QDISuvBB0FteQD+abdcAjpf474+/67yO5AxAcw9l+evoFuQSJ3zbHOFCS6iCsz08SVrUOLcLQ== X-Received: by 10.98.102.82 with SMTP id a79mr7513154pfc.109.1507465439985; Sun, 08 Oct 2017 05:23:59 -0700 (PDT) Received: from localhost (g248.61-45-56.ppp.wakwak.ne.jp. [61.45.56.248]) by smtp.gmail.com with ESMTPSA id m69sm11396027pfk.54.2017.10.08.05.23.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 08 Oct 2017 05:23:59 -0700 (PDT) Date: Sun, 08 Oct 2017 12:24:00 -0000 From: Stafford Horne To: Simon Marchi Cc: GDB patches , Openrisc , Mike Frysinger , Peter Gavin Subject: Re: [PATCH v5 1/6] sim: cgen: add remainder functions (needed for OR1K lf.rem.[sd]) Message-ID: <20171008122357.GA2958@lianli.shorne-pla.net> References: <20171005134912.26799-1-shorne@gmail.com> <20171005134912.26799-2-shorne@gmail.com> <22127605-6ea8-05c4-03a6-cc37478bd459@polymtl.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <22127605-6ea8-05c4-03a6-cc37478bd459@polymtl.ca> User-Agent: Mutt/1.9.1 (2017-09-22) X-IsSubscribed: yes X-SW-Source: 2017-10/txt/msg00159.txt.bz2 On Sat, Oct 07, 2017 at 11:52:30AM -0400, Simon Marchi wrote: > As far as I can tell, this patch looks good, but I'm more or less clueless about floating point stuff... > > I just pointed out nits: > > On 2017-10-05 09:49 AM, Stafford Horne wrote: > > From: Peter Gavin > > > > * sim/common/ChangeLog: > > > > 2016-05-21 Peter Gavin > > Stafford Horne > > > > * cgen-accfp.c (remsf, remdf): New function. > > (cgen_init_accurate_fpu): Add remsf and remdf. > > * cgen-fpu.h (cgen_fp_ops): Add remsf, remdf, remxf and remtf. > > * sim-fpu.c (sim_fpu_rem): New function. > > Mention the change to sim_fpu_print_status. Right, Thank you. > sim-fpu.c contains other changes (comments added, lines removed). If you think the changes belong with this patch, mention them here, otherwise submit them as a separate patch. I just removed them, they are noise. I saw them when I reviewed the patch but was not sure if it would be an issue to keep them. > > @@ -1551,6 +1551,89 @@ sim_fpu_div (sim_fpu *f, > > > > > > INLINE_SIM_FPU (int) > > +sim_fpu_rem (sim_fpu *f, > > + const sim_fpu *l, > > + const sim_fpu *r) > > +{ > > + if (sim_fpu_is_snan (l)) > > + { > > + *f = *l; > > + f->class = sim_fpu_class_qnan; > > + return sim_fpu_status_invalid_snan; > > + } > > + if (sim_fpu_is_snan (r)) > > + { > > + *f = *r; > > + f->class = sim_fpu_class_qnan; > > + return sim_fpu_status_invalid_snan; > > + } > > + if (sim_fpu_is_qnan (l)) > > + { > > + *f = *l; > > + f->class = sim_fpu_class_qnan; > > + return 0; > > + } > > + if (sim_fpu_is_qnan (r)) > > + { > > + *f = *r; > > + f->class = sim_fpu_class_qnan; > > + return 0; > > + } > > + if (sim_fpu_is_infinity (l)) > > + { > > + *f = sim_fpu_qnan; > > + return sim_fpu_status_invalid_irx; > > + } > > + if (sim_fpu_is_zero (r)) > > + { > > + *f = sim_fpu_qnan; > > + return sim_fpu_status_invalid_div0; > > + } > > + if (sim_fpu_is_zero (l)) > > + { > > + *f = *l; > > + return 0; > > + } > > + if (sim_fpu_is_infinity (r)) > > + { > > + *f = *l; > > + return 0; > > + } > > + { > > + sim_fpu n, tmp; > > + > > + /* Remainder is calculated as l-n*r, where n is l/r rounded to the > > + nearest integer. The variable n is rounded half even. */ > > + > > + sim_fpu_div (&n, l, r); > > + sim_fpu_round_64 (&n, 0, 0); > > + > > + if (n.normal_exp < -1) /* If n looks like zero just return l. */ > > + { > > + *f = *l; > > + return 0; > > + } > > + else if (n.class == sim_fpu_class_number > > + && n.normal_exp <= (NR_FRAC_GUARD)) /* If not too large round. */ > > This line should be aligned with the opening parenthesis (well, one char to the right). Right, that does move the comment out of the 80 char range, but just the ending '*/'. I hope thats ok. > > + do_normal_round (&n, (NR_FRAC_GUARD) - n.normal_exp, sim_fpu_round_near); > > + > > + /* Mark 0's as zero so multiply can detect zero. */ > > + if (n.fraction == 0) > > + n.class = sim_fpu_class_zero; > > + > > + /* Calculate n*r. */ > > + sim_fpu_mul (&tmp, &n, r); > > + sim_fpu_round_64 (&tmp, 0, 0); > > + > > + /* Finally calculate l-n*r. */ > > + sim_fpu_sub (f, l, &tmp); > > + > > + return 0; > > + } > > +} > > Thanks, > > Simon Thank you, -Stafford