* Re: [PATCH] AArch64: Allow additional sizes in prologue [not found] <20190805124152.26127-1-alan.hayward@arm.com> @ 2019-08-05 17:43 ` Tom Tromey 2019-08-06 8:58 ` Alan Hayward 0 siblings, 1 reply; 6+ messages in thread From: Tom Tromey @ 2019-08-05 17:43 UTC (permalink / raw) To: Alan Hayward; +Cc: gdb-patches, nd >>>>> "Alan" == Alan Hayward <Alan.Hayward@arm.com> writes: Alan> When saving registers to the stack at the start of a function, not all state Alan> needs to be saved. For example, only the first 64bits of float registers need Alan> saving. However, a program may choose to store extra state if it wishes, Alan> there is nothing preventing it doing so. Alan> The aarch64_analyze_prologue will error if it detects extra state being Alan> stored. Relex this restriction. I don't know anything about AArch64, so I can't really comment on the content of the patch, but I did happen to see a nit: Alan> stack.store (pv_add_constant (regs[rn], Alan> inst.operands[1].addr.offset.imm), Alan> - is64 ? 8 : 4, regs[rt]); Alan> + size, regs[rt]); ...this addition looked mis-indented to me. Tom ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] AArch64: Allow additional sizes in prologue 2019-08-05 17:43 ` [PATCH] AArch64: Allow additional sizes in prologue Tom Tromey @ 2019-08-06 8:58 ` Alan Hayward 2019-08-06 9:56 ` Richard Earnshaw (lists) 2019-08-06 13:52 ` Tom Tromey 0 siblings, 2 replies; 6+ messages in thread From: Alan Hayward @ 2019-08-06 8:58 UTC (permalink / raw) To: Tom Tromey; +Cc: gdb-patches, nd > On 5 Aug 2019, at 18:43, Tom Tromey <tom@tromey.com> wrote: > >>>>>> "Alan" == Alan Hayward <Alan.Hayward@arm.com> writes: > > Alan> When saving registers to the stack at the start of a function, not all state > Alan> needs to be saved. For example, only the first 64bits of float registers need > Alan> saving. However, a program may choose to store extra state if it wishes, > Alan> there is nothing preventing it doing so. > > Alan> The aarch64_analyze_prologue will error if it detects extra state being > Alan> stored. Relex this restriction. > > I don't know anything about AArch64, so I can't really comment on the > content of the patch, but I did happen to see a nit: > > Alan> stack.store (pv_add_constant (regs[rn], > Alan> inst.operands[1].addr.offset.imm), > Alan> - is64 ? 8 : 4, regs[rt]); > Alan> + size, regs[rt]); > > ...this addition looked mis-indented to me. Thanks. I probably missed that because the correct formatting looks horrible: stack.store (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), size, regs[rt]); Instead, I can update it to the following stack.store ( pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), size, regs[rt]); > > Tom ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] AArch64: Allow additional sizes in prologue 2019-08-06 8:58 ` Alan Hayward @ 2019-08-06 9:56 ` Richard Earnshaw (lists) 2019-08-06 12:18 ` Alan Hayward 2019-08-06 13:52 ` Tom Tromey 1 sibling, 1 reply; 6+ messages in thread From: Richard Earnshaw (lists) @ 2019-08-06 9:56 UTC (permalink / raw) To: Alan Hayward, Tom Tromey; +Cc: gdb-patches, nd On 06/08/2019 09:58, Alan Hayward wrote: > > >> On 5 Aug 2019, at 18:43, Tom Tromey <tom@tromey.com> wrote: >> >>>>>>> "Alan" == Alan Hayward <Alan.Hayward@arm.com> writes: >> >> Alan> When saving registers to the stack at the start of a function, not all state >> Alan> needs to be saved. For example, only the first 64bits of float registers need >> Alan> saving. However, a program may choose to store extra state if it wishes, >> Alan> there is nothing preventing it doing so. >> >> Alan> The aarch64_analyze_prologue will error if it detects extra state being >> Alan> stored. Relex this restriction. >> >> I don't know anything about AArch64, so I can't really comment on the >> content of the patch, but I did happen to see a nit: >> >> Alan> stack.store (pv_add_constant (regs[rn], >> Alan> inst.operands[1].addr.offset.imm), >> Alan> - is64 ? 8 : 4, regs[rt]); >> Alan> + size, regs[rt]); >> >> ...this addition looked mis-indented to me. > > Thanks. > I probably missed that because the correct formatting looks horrible: > > stack.store (pv_add_constant (regs[rn], > inst.operands[1].addr.offset.imm), > size, regs[rt]); > > Instead, I can update it to the following > > stack.store ( > pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), > size, regs[rt]); > I think the coding convention in that case is to write: stack.store (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), size, regs[rt]); R. >> >> Tom > ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] AArch64: Allow additional sizes in prologue 2019-08-06 9:56 ` Richard Earnshaw (lists) @ 2019-08-06 12:18 ` Alan Hayward 2019-08-14 15:03 ` Alan Hayward 0 siblings, 1 reply; 6+ messages in thread From: Alan Hayward @ 2019-08-06 12:18 UTC (permalink / raw) To: Richard Earnshaw; +Cc: Tom Tromey, gdb-patches, nd [-- Warning: decoded text below may be mangled, UTF-8 assumed --] [-- Attachment #1: Type: text/plain; charset="us-ascii", Size: 5533 bytes --] > On 6 Aug 2019, at 10:56, Richard Earnshaw (lists) <Richard.Earnshaw@arm.com> wrote: > > On 06/08/2019 09:58, Alan Hayward wrote: >>> On 5 Aug 2019, at 18:43, Tom Tromey <tom@tromey.com> wrote: >>> >>>>>>>> "Alan" == Alan Hayward <Alan.Hayward@arm.com> writes: >>> >>> Alan> When saving registers to the stack at the start of a function, not all state >>> Alan> needs to be saved. For example, only the first 64bits of float registers need >>> Alan> saving. However, a program may choose to store extra state if it wishes, >>> Alan> there is nothing preventing it doing so. >>> >>> Alan> The aarch64_analyze_prologue will error if it detects extra state being >>> Alan> stored. Relex this restriction. >>> >>> I don't know anything about AArch64, so I can't really comment on the >>> content of the patch, but I did happen to see a nit: >>> >>> Alan> stack.store (pv_add_constant (regs[rn], >>> Alan> inst.operands[1].addr.offset.imm), >>> Alan> - is64 ? 8 : 4, regs[rt]); >>> Alan> + size, regs[rt]); >>> >>> ...this addition looked mis-indented to me. >> Thanks. >> I probably missed that because the correct formatting looks horrible: >> stack.store (pv_add_constant (regs[rn], >> inst.operands[1].addr.offset.imm), >> size, regs[rt]); >> Instead, I can update it to the following >> stack.store ( >> pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), >> size, regs[rt]); > > I think the coding convention in that case is to write: > > > stack.store > (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), > size, regs[rt]); > > R. Ok, will use that way. Alan. From gdb-patches-return-157997-listarch-gdb-patches=sources.redhat.com@sourceware.org Tue Aug 06 13:50:35 2019 Return-Path: <gdb-patches-return-157997-listarch-gdb-patches=sources.redhat.com@sourceware.org> Delivered-To: listarch-gdb-patches@sources.redhat.com Received: (qmail 27702 invoked by alias); 6 Aug 2019 13:50:34 -0000 Mailing-List: contact gdb-patches-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: <gdb-patches.sourceware.org> List-Subscribe: <mailto:gdb-patches-subscribe@sourceware.org> List-Archive: <http://sourceware.org/ml/gdb-patches/> List-Post: <mailto:gdb-patches@sourceware.org> List-Help: <mailto:gdb-patches-help@sourceware.org>, <http://sourceware.org/ml/#faqs> Sender: gdb-patches-owner@sourceware.org Delivered-To: mailing list gdb-patches@sourceware.org Received: (qmail 27689 invoked by uid 89); 6 Aug 2019 13:50:34 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-6.9 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS autolearn=ham version=3.3.1 spammy=HX-Languages-Length:629 X-HELO: gateway30.websitewelcome.com Received: from gateway30.websitewelcome.com (HELO gateway30.websitewelcome.com) (192.185.197.25) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 06 Aug 2019 13:50:32 +0000 Received: from cm11.websitewelcome.com (cm11.websitewelcome.com [100.42.49.5]) by gateway30.websitewelcome.com (Postfix) with ESMTP id 0C11036CE3 for <gdb-patches@sourceware.org>; Tue, 6 Aug 2019 08:50:31 -0500 (CDT) Received: from box5379.bluehost.com ([162.241.216.53]) by cmsmtp with SMTP id uzrDhNHs5dnCeuzrDhp9lt; Tue, 06 Aug 2019 08:50:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=tromey.com; sÞfault; h=Content-Type:MIME-Version:Message-ID:In-Reply-To:Date: References:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bhÌ5bIVMIyPWW4OXyvFlyNEoQc3yCNHiWj+I9p1xC+fs=; b=dhFOQ7jaA92KoTi3ABnCgM/qSf NQwKX7b5QqdetvdYB/eE5pgRkF64eIeQfnK7REaULAo/z1pd7e7te0muz+pOTyj4VZ5jBK3mI6hX7 CfqwWcJYEgzFE+ZH+QWVG/rBk; Received: from 97-122-178-82.hlrn.qwest.net ([97.122.178.82]:51666 helo=murgatroyd) by box5379.bluehost.com with esmtpsa (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384:256) (Exim 4.92) (envelope-from <tom@tromey.com>) id 1huzrC-001Rfp-PS; Tue, 06 Aug 2019 08:50:30 -0500 From: Tom Tromey <tom@tromey.com> To: "Christian Biesinger via gdb-patches" <gdb-patches@sourceware.org> Cc: Christian Biesinger <cbiesinger@google.com> Subject: Re: [PATCH] Replace int with enum block_enum where appropriate. References: <20190805185833.236434-1-cbiesinger@google.com> Date: Tue, 06 Aug 2019 13:50:00 -0000 In-Reply-To: <20190805185833.236434-1-cbiesinger@google.com> (Christian Biesinger via gdb-patches's message of "Mon, 5 Aug 2019 13:58:33 -0500") Message-ID: <874l2ubdy2.fsf@tromey.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-SW-Source: 2019-08/txt/msg00134.txt.bz2 Content-length: 573 >>>>> "Christian" == Christian Biesinger via gdb-patches <gdb-patches@sourceware.org> writes: Christian> For better readability and type safety. Christian> gdb/ChangeLog: Christian> 2019-08-05 Christian Biesinger <cbiesinger@google.com> Christian> * symtab.c (symbol_cache_lookup): Change int to enum block_enum. Christian> (error_in_psymtab_expansion): Likewise. Christian> (lookup_symbol_via_quick_fns): Likewise. Christian> (basic_lookup_transparent_type_quick): Likewise. Christian> (basic_lookup_transparent_type_1): Likewise. Thank you. This is ok. Tom ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] AArch64: Allow additional sizes in prologue 2019-08-06 12:18 ` Alan Hayward @ 2019-08-14 15:03 ` Alan Hayward 0 siblings, 0 replies; 6+ messages in thread From: Alan Hayward @ 2019-08-14 15:03 UTC (permalink / raw) To: gdb-patches; +Cc: Tom Tromey, nd, Richard Earnshaw Patch pushed with the formatting fixed. Pasted to end of email for reference. > On 6 Aug 2019, at 13:18, Alan Hayward <Alan.Hayward@arm.com> wrote: > > > >> On 6 Aug 2019, at 10:56, Richard Earnshaw (lists) <Richard.Earnshaw@arm.com> wrote: >> >> On 06/08/2019 09:58, Alan Hayward wrote: >>>> On 5 Aug 2019, at 18:43, Tom Tromey <tom@tromey.com> wrote: >>>> >>>>>>>>> "Alan" == Alan Hayward <Alan.Hayward@arm.com> writes: >>>> >>>> Alan> When saving registers to the stack at the start of a function, not all state >>>> Alan> needs to be saved. For example, only the first 64bits of float registers need >>>> Alan> saving. However, a program may choose to store extra state if it wishes, >>>> Alan> there is nothing preventing it doing so. >>>> >>>> Alan> The aarch64_analyze_prologue will error if it detects extra state being >>>> Alan> stored. Relex this restriction. >>>> >>>> I don't know anything about AArch64, so I can't really comment on the >>>> content of the patch, but I did happen to see a nit: >>>> >>>> Alan> stack.store (pv_add_constant (regs[rn], >>>> Alan> inst.operands[1].addr.offset.imm), >>>> Alan> - is64 ? 8 : 4, regs[rt]); >>>> Alan> + size, regs[rt]); >>>> >>>> ...this addition looked mis-indented to me. >>> Thanks. >>> I probably missed that because the correct formatting looks horrible: >>> stack.store (pv_add_constant (regs[rn], >>> inst.operands[1].addr.offset.imm), >>> size, regs[rt]); >>> Instead, I can update it to the following >>> stack.store ( >>> pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), >>> size, regs[rt]); >> >> I think the coding convention in that case is to write: >> >> >> stack.store >> (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), >> size, regs[rt]); >> >> R. > > Ok, will use that way. > > Alan. diff --git a/gdb/ChangeLog b/gdb/ChangeLog index 15904da82c..6f7474f282 100644 --- a/gdb/ChangeLog +++ b/gdb/ChangeLog @@ -1,3 +1,8 @@ +2019-08-14 Alan Hayward <alan.hayward@arm.com> + + * aarch64-tdep.c (aarch64_analyze_prologue): Allow any valid + register sizes. + 2019-08-14 Tom Tromey <tromey@adacore.com> * darwin-nat.c: Include gdbarch.h. diff --git a/gdb/aarch64-tdep.c b/gdb/aarch64-tdep.c index 9b6324f0fc..5e9f7b8ee0 100644 --- a/gdb/aarch64-tdep.c +++ b/gdb/aarch64-tdep.c @@ -387,17 +387,16 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch, { unsigned rt = inst.operands[0].reg.regno; unsigned rn = inst.operands[1].addr.base_regno; - int is64 - = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); + int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier); gdb_assert (aarch64_num_of_operands (inst.opcode) == 2); gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt); gdb_assert (inst.operands[1].type == AARCH64_OPND_ADDR_SIMM9); gdb_assert (!inst.operands[1].addr.offset.is_reg); - stack.store (pv_add_constant (regs[rn], - inst.operands[1].addr.offset.imm), - is64 ? 8 : 4, regs[rt]); + stack.store + (pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), + size, regs[rt]); } else if ((inst.opcode->iclass == ldstpair_off || (inst.opcode->iclass == ldstpair_indexed @@ -409,6 +408,7 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch, unsigned rt2; unsigned rn = inst.operands[2].addr.base_regno; int32_t imm = inst.operands[2].addr.offset.imm; + int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier); gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt || inst.operands[0].type == AARCH64_OPND_Ft); @@ -430,17 +430,12 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch, rt2 = inst.operands[1].reg.regno; if (inst.operands[0].type == AARCH64_OPND_Ft) { - /* Only bottom 64-bit of each V register (D register) need - to be preserved. */ - gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); rt1 += AARCH64_X_REGISTER_COUNT; rt2 += AARCH64_X_REGISTER_COUNT; } - stack.store (pv_add_constant (regs[rn], imm), 8, - regs[rt1]); - stack.store (pv_add_constant (regs[rn], imm + 8), 8, - regs[rt2]); + stack.store (pv_add_constant (regs[rn], imm), size, regs[rt1]); + stack.store (pv_add_constant (regs[rn], imm + size), size, regs[rt2]); if (inst.operands[2].addr.writeback) regs[rn] = pv_add_constant (regs[rn], imm); @@ -457,21 +452,14 @@ aarch64_analyze_prologue (struct gdbarch *gdbarch, unsigned int rt = inst.operands[0].reg.regno; int32_t imm = inst.operands[1].addr.offset.imm; unsigned int rn = inst.operands[1].addr.base_regno; - bool is64 - = (aarch64_get_qualifier_esize (inst.operands[0].qualifier) == 8); + int size = aarch64_get_qualifier_esize (inst.operands[0].qualifier); gdb_assert (inst.operands[0].type == AARCH64_OPND_Rt || inst.operands[0].type == AARCH64_OPND_Ft); if (inst.operands[0].type == AARCH64_OPND_Ft) - { - /* Only bottom 64-bit of each V register (D register) need - to be preserved. */ - gdb_assert (inst.operands[0].qualifier == AARCH64_OPND_QLF_S_D); - rt += AARCH64_X_REGISTER_COUNT; - } + rt += AARCH64_X_REGISTER_COUNT; - stack.store (pv_add_constant (regs[rn], imm), - is64 ? 8 : 4, regs[rt]); + stack.store (pv_add_constant (regs[rn], imm), size, regs[rt]); if (inst.operands[1].addr.writeback) regs[rn] = pv_add_constant (regs[rn], imm); } diff --git a/gdb/testsuite/ChangeLog b/gdb/testsuite/ChangeLog index e4b9616dde..6c80a69e06 100644 --- a/gdb/testsuite/ChangeLog +++ b/gdb/testsuite/ChangeLog @@ -1,3 +1,8 @@ +2019-08-14 Alan Hayward <alan.hayward@arm.com> + + * gdb.arch/aarch64-prologue.c: New test. + * gdb.arch/aarch64-prologue.exp: New file. + 2019-08-13 Tom de Vries <tdevries@suse.de> * gdb.gdb/selftest.exp (send ^C to child process again): Accept also diff --git a/gdb/testsuite/gdb.arch/aarch64-prologue.c b/gdb/testsuite/gdb.arch/aarch64-prologue.c new file mode 100644 index 0000000000..aa664f704f --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-prologue.c @@ -0,0 +1,83 @@ +/* This testcase is part of GDB, the GNU debugger. + + Copyright 2019 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see <http://www.gnu.org/licenses/>. */ + +#include <stdio.h> + +extern void excessiveprologue (); + +void +innerfunc () +{ + printf ("inner\n"); +} + +/* excessiveprologue saves to the stack in multiple ways. */ + +asm ("\t.section .gnu.sgstubs,\"ax\",%progbits\n" + "\t.global excessiveprologue\n" + "\t.type excessiveprologue, %function\n" + "excessiveprologue:\n" + "\tstp x29, x30, [sp, #-208]!\n" + "\tmov x29, sp\n" + "\tstp w0,w1,[sp,16]\n" + "\tstp x2,x3,[sp,24]\n" + "\tstr w4,[sp,40]\n" + "\tstr x5,[sp,48]\n" + "\tstur w6,[sp,52]\n" + "\tstur x7,[sp,56]\n" + "\tstp s0,s1,[sp,64]\n" + "\tstp d2,d3,[sp,72]\n" + "\tstp q4,q5,[sp,96]\n" + "\tstr b6,[sp,128]\n" + "\tstr h7,[sp,132]\n" + "\tstr s8,[sp,136]\n" + "\tstr d9,[sp,140]\n" + "\tstr q10,[sp,148]\n" + "\tstur b11,[sp,164]\n" + "\tstur h12,[sp,160]\n" + "\tstur s13,[sp,172]\n" + "\tstur d14,[sp,176]\n" + "\tstur q15,[sp,184]\n" + "\tbl innerfunc\n" + "\tldp w0,w1,[sp,16]\n" + "\tldp x2,x3,[sp,24]\n" + "\tldr w4,[sp,40]\n" + "\tldr x5,[sp,48]\n" + "\tldur w6,[sp,52]\n" + "\tldur x7,[sp,56]\n" + "\tldp s0,s1,[sp,64]\n" + "\tldp d2,d3,[sp,72]\n" + "\tldp q4,q5,[sp,96]\n" + "\tldr b6,[sp,128]\n" + "\tldr h7,[sp,132]\n" + "\tldr s8,[sp,136]\n" + "\tldr d9,[sp,140]\n" + "\tldr q10,[sp,148]\n" + "\tldur b11,[sp,164]\n" + "\tldur h12,[sp,160]\n" + "\tldur s13,[sp,172]\n" + "\tldur d14,[sp,176]\n" + "\tldur q15,[sp,184]\n" + "\tldp x29, x30, [sp], #208\n" + "ret\n"); + +int +main (void) +{ + excessiveprologue (); + return 0; +} diff --git a/gdb/testsuite/gdb.arch/aarch64-prologue.exp b/gdb/testsuite/gdb.arch/aarch64-prologue.exp new file mode 100644 index 0000000000..e31261ad25 --- /dev/null +++ b/gdb/testsuite/gdb.arch/aarch64-prologue.exp @@ -0,0 +1,36 @@ +# Copyright 2019 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. + +# This file is part of the gdb testsuite. + +if {![is_aarch64_target]} { + verbose "Skipping ${gdb_test_file_name}." + return 1 +} + +standard_testfile +if { [prepare_for_testing "failed to prepare" $testfile $srcfile {nodebug}]} { + return -1 +} + +if ![runto_main] { + untested "could not run to main" + return -1 +} + +# Ensure gdb can break at excessiveprologue then continue. +gdb_breakpoint "excessiveprologue" +gdb_continue_to_breakpoint "excessiveprologue" +gdb_continue_to_end "excessiveprologue" "continue" 1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] AArch64: Allow additional sizes in prologue 2019-08-06 8:58 ` Alan Hayward 2019-08-06 9:56 ` Richard Earnshaw (lists) @ 2019-08-06 13:52 ` Tom Tromey 1 sibling, 0 replies; 6+ messages in thread From: Tom Tromey @ 2019-08-06 13:52 UTC (permalink / raw) To: Alan Hayward; +Cc: Tom Tromey, gdb-patches, nd >>>>> "Alan" == Alan Hayward <Alan.Hayward@arm.com> writes: Alan> I probably missed that because the correct formatting looks horrible: Alan> stack.store (pv_add_constant (regs[rn], Alan> inst.operands[1].addr.offset.imm), Alan> size, regs[rt]); This is a pretty normal style you'd see in gdb. Alan> Instead, I can update it to the following Alan> stack.store ( Alan> pv_add_constant (regs[rn], inst.operands[1].addr.offset.imm), Alan> size, regs[rt]); gdb doesn't normally use the trailing open paren style like that. Tom ^ permalink raw reply [flat|nested] 6+ messages in thread
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2019-08-05 17:43 ` [PATCH] AArch64: Allow additional sizes in prologue Tom Tromey
2019-08-06 8:58 ` Alan Hayward
2019-08-06 9:56 ` Richard Earnshaw (lists)
2019-08-06 12:18 ` Alan Hayward
2019-08-14 15:03 ` Alan Hayward
2019-08-06 13:52 ` Tom Tromey
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