[PATCH] Set rv64gcv as default to enable vector extension for disassembly

[PATCH] Set rv64gcv as default to enable vector extension for disassembly

[Soham Gargote]

From: GDB Administrator <gdbadmin@sourceware.org>

---
 bfd/version.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/bfd/version.h b/bfd/version.h
index c33770d2738..bdb3f9d0ea0 100644
--- a/bfd/version.h
+++ b/bfd/version.h
@@ -16,7 +16,7 @@
 
    In releases, the date is not included in either version strings or
    sonames.  */
-#define BFD_VERSION_DATE 20250720
+#define BFD_VERSION_DATE 20250721
 #define BFD_VERSION @bfd_version@
 #define BFD_VERSION_STRING  @bfd_version_package@ @bfd_version_string@
 #define REPORT_BUGS_TO @report_bugs_to@
-- 
2.48.1

Re: [PATCH] Set rv64gcv as default to enable vector extension for disassembly

[Andrew Burgess]

Soham Gargote <sgargote@whileone.in> writes:

> From: GDB Administrator <gdbadmin@sourceware.org>
>
> ---
>  bfd/version.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

I suspect you've sent the wrong patch by accident.

Thanks,
Andrew



>
> diff --git a/bfd/version.h b/bfd/version.h
> index c33770d2738..bdb3f9d0ea0 100644
> --- a/bfd/version.h
> +++ b/bfd/version.h
> @@ -16,7 +16,7 @@
>  
>     In releases, the date is not included in either version strings or
>     sonames.  */
> -#define BFD_VERSION_DATE 20250720
> +#define BFD_VERSION_DATE 20250721
>  #define BFD_VERSION @bfd_version@
>  #define BFD_VERSION_STRING  @bfd_version_package@ @bfd_version_string@
>  #define REPORT_BUGS_TO @report_bugs_to@
> -- 
> 2.48.1

[PATCH] Set rv64gcv as default to enable vector extension for disassembly

[Soham Gargote]

Co-Authored-By: Sameer Natu <snatu@whileone.in>

---
 opcodes/riscv-dis.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index f6af9c47a25..a67b51bad74 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1444,7 +1444,7 @@ riscv_init_disasm_info (struct disassemble_info *info)
   pd->riscv_rps_dis.xlen = &pd->xlen;
   pd->riscv_rps_dis.isa_spec = &pd->default_isa_spec;
   pd->riscv_rps_dis.check_unknown_prefixed_ext = false;
-  pd->default_arch = "rv64gc";
+  pd->default_arch = "rv64gcv";
   if (info->section != NULL)
     {
       bfd *abfd = info->section->owner;
-- 
2.48.1

Re: [PATCH] Set rv64gcv as default to enable vector extension for disassembly

[Andrew Burgess]

Hi!

Thanks for working on this.  Patches to the opcodes/ directory need to
be reviewed on the binutils@sourceware.org list (Added to the To: list).

From the GDB side, I have no problems with this change, but I cannot
approve it.

Reviewed-By: Andrew Burgess <aburgess@redhat.com>

Thanks,
Andrew


Soham Gargote <sgargote@whileone.in> writes:

> Co-Authored-By: Sameer Natu <snatu@whileone.in>
>
> ---
>  opcodes/riscv-dis.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index f6af9c47a25..a67b51bad74 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -1444,7 +1444,7 @@ riscv_init_disasm_info (struct disassemble_info *info)
>    pd->riscv_rps_dis.xlen = &pd->xlen;
>    pd->riscv_rps_dis.isa_spec = &pd->default_isa_spec;
>    pd->riscv_rps_dis.check_unknown_prefixed_ext = false;
> -  pd->default_arch = "rv64gc";
> +  pd->default_arch = "rv64gcv";
>    if (info->section != NULL)
>      {
>        bfd *abfd = info->section->owner;
> -- 
> 2.48.1

Re: [PATCH] Set rv64gcv as default to enable vector extension for disassembly

[Andreas Schwab]

Why is that needed?  AFAICT, objdump will happily decode any extension
without that change.

-- 
Andreas Schwab, SUSE Labs, schwab@suse.de
GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE  1748 E4D4 88E3 0EEA B9D7
"And now for something completely different."

Re: [PATCH] Set rv64gcv as default to enable vector extension for disassembly

[Nelson Chu]

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On Wed, Jul 30, 2025 at 9:09 PM Andreas Schwab <schwab@suse.de> wrote:

> Why is that needed?  AFAICT, objdump will happily decode any extension
> without that change.
>

 I guess maybe they are trying to dump an object which writes
vector instructions by .insn directives, so the elf architecture attribute
or mapping symbols won't have v.  I will suggest two solutions here rather
than just modify the default_arch,
1. using -Mmax option
2. Allow to set the default arch from the configure option, like what gas
did before.  Not sure if it is possible to find a way to share the
configure set both for gas and opcode (assembler and dis-assembler).

BTW, force setting default_arch to rv64gc or whatever in dis-assembler
isn't really good, I think that I just forgot to update it before.  So I
sent a patch to let riscv_parse_subset unify the default architecture
both for assembler and dis-assembler from the riscv_all_supported_ext table.
https://sourceware.org/pipermail/binutils/2025-July/143063.html

Nelson

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Re: [PATCH] Set rv64gcv as default to enable vector extension for disassembly

[Charlie Jenkins]

On Thu, Jul 31, 2025 at 10:37:16AM +0800, Nelson Chu wrote:
> On Wed, Jul 30, 2025 at 9:09 PM Andreas Schwab <schwab@suse.de> wrote:
> 
> > Why is that needed?  AFAICT, objdump will happily decode any extension
> > without that change.
> >
> 
>  I guess maybe they are trying to dump an object which writes
> vector instructions by .insn directives, so the elf architecture attribute
> or mapping symbols won't have v.  I will suggest two solutions here rather

The goal here is to be able to use the disassembler from inside of
native riscv gdb to dump any instruction. Currently it seems like gdb
will only dump a subset of all instructions, even with the patch you
sent Nelson. Here is an example program:

$ cat sample.c
// sample.c
volatile int num;
volatile int num2;

int main()
{
        asm("vsetvli t0, a0, e32");
        return num & ~num2; // zbb instruction andn
}
$ gcc -march=rv64gcv_zbb -O2 sample.c -o sample
$ readelf -A sample
Attribute Section: riscv
File Attributes
  Tag_RISCV_stack_align: 16-bytes
  Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
$ objdump -d sample
...
0000000000000570 <main>:
 570:   010572d7                vsetvli t0,a0,e32,m1,tu,mu
 574:   00002517                auipc   a0,0x2
 578:   a9852503                lw      a0,-1384(a0) # 200c <num2>
 57c:   00002797                auipc   a5,0x2
 580:   a947a783                lw      a5,-1388(a5) # 2010 <num>
 584:   40a7f533                andn    a0,a5,a0
 588:   8082                    ret
...
$ gdb sample
(gdb) disassemble main
Dump of assembler code for function main:
   0x0000000000000570 <+0>:     .insn   4, 0x010572d7
   0x0000000000000574 <+4>:     auipc   a0,0x2
   0x0000000000000578 <+8>:     lw      a0,-1384(a0) # 0x200c <num2>
   0x000000000000057c <+12>:    auipc   a5,0x2
   0x0000000000000580 <+16>:    lw      a5,-1388(a5) # 0x2010 <num>
   0x0000000000000584 <+20>:    .insn   4, 0x40a7f533
   0x0000000000000588 <+24>:    .insn   2, 0x8082

The disassembled instructions are lacking, even though the attributes
contains the extensions. I had previously thought that this had to do
with the decode() function in gdb/riscv-tdep.c but that seems to only
handle gdb-specific decoding and not this disassembling. 

What is the way to have the disassembler dump all of the instructions of
supported extensions on native riscv gdb?

- Charlie

> than just modify the default_arch,
> 1. using -Mmax option
> 2. Allow to set the default arch from the configure option, like what gas
> did before.  Not sure if it is possible to find a way to share the
> configure set both for gas and opcode (assembler and dis-assembler).
> 
> BTW, force setting default_arch to rv64gc or whatever in dis-assembler
> isn't really good, I think that I just forgot to update it before.  So I
> sent a patch to let riscv_parse_subset unify the default architecture
> both for assembler and dis-assembler from the riscv_all_supported_ext table.
> https://sourceware.org/pipermail/binutils/2025-July/143063.html
> 
> Nelson

Re: [PATCH] Set rv64gcv as default to enable vector extension for disassembly

[Jan Beulich]

On 31.07.2025 09:21, Charlie Jenkins wrote:
> On Thu, Jul 31, 2025 at 10:37:16AM +0800, Nelson Chu wrote:
>> On Wed, Jul 30, 2025 at 9:09 PM Andreas Schwab <schwab@suse.de> wrote:
>>
>>> Why is that needed?  AFAICT, objdump will happily decode any extension
>>> without that change.
>>>
>>
>>  I guess maybe they are trying to dump an object which writes
>> vector instructions by .insn directives, so the elf architecture attribute
>> or mapping symbols won't have v.  I will suggest two solutions here rather
> 
> The goal here is to be able to use the disassembler from inside of
> native riscv gdb to dump any instruction.

Yet you won't achieve that by enabling just V.

> Currently it seems like gdb
> will only dump a subset of all instructions, even with the patch you
> sent Nelson. Here is an example program:
> 
> $ cat sample.c
> // sample.c
> volatile int num;
> volatile int num2;
> 
> int main()
> {
>         asm("vsetvli t0, a0, e32");
>         return num & ~num2; // zbb instruction andn
> }
> $ gcc -march=rv64gcv_zbb -O2 sample.c -o sample
> $ readelf -A sample
> Attribute Section: riscv
> File Attributes
>   Tag_RISCV_stack_align: 16-bytes
>   Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
> $ objdump -d sample
> ...
> 0000000000000570 <main>:
>  570:   010572d7                vsetvli t0,a0,e32,m1,tu,mu
>  574:   00002517                auipc   a0,0x2
>  578:   a9852503                lw      a0,-1384(a0) # 200c <num2>
>  57c:   00002797                auipc   a5,0x2
>  580:   a947a783                lw      a5,-1388(a5) # 2010 <num>
>  584:   40a7f533                andn    a0,a5,a0
>  588:   8082                    ret
> ...
> $ gdb sample
> (gdb) disassemble main
> Dump of assembler code for function main:
>    0x0000000000000570 <+0>:     .insn   4, 0x010572d7
>    0x0000000000000574 <+4>:     auipc   a0,0x2
>    0x0000000000000578 <+8>:     lw      a0,-1384(a0) # 0x200c <num2>
>    0x000000000000057c <+12>:    auipc   a5,0x2
>    0x0000000000000580 <+16>:    lw      a5,-1388(a5) # 0x2010 <num>
>    0x0000000000000584 <+20>:    .insn   4, 0x40a7f533
>    0x0000000000000588 <+24>:    .insn   2, 0x8082
> 
> The disassembled instructions are lacking, even though the attributes
> contains the extensions. I had previously thought that this had to do
> with the decode() function in gdb/riscv-tdep.c but that seems to only
> handle gdb-specific decoding and not this disassembling. 
> 
> What is the way to have the disassembler dump all of the instructions of
> supported extensions on native riscv gdb?

Iirc there is a way to achieve ...

>> than just modify the default_arch,
>> 1. using -Mmax option

... the effect of this (objdump) option also in gdb, presumably via
some "set" command. Whether it makes sense to make this (and not
GCV) the default in gdb I don't know. The problem is that there are
conflicting extensions. It may be better to set the default based on
(target) host capabilities.

Jan

Re: [PATCH] Set rv64gcv as default to enable vector extension for disassembly

[Nelson Chu]

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On Thu, Jul 31, 2025 at 3:21 PM Charlie Jenkins <charlie@rivosinc.com>
wrote:

> On Thu, Jul 31, 2025 at 10:37:16AM +0800, Nelson Chu wrote:
> > On Wed, Jul 30, 2025 at 9:09 PM Andreas Schwab <schwab@suse.de> wrote:
> >
> > > Why is that needed?  AFAICT, objdump will happily decode any extension
> > > without that change.
> > >
> >
> >  I guess maybe they are trying to dump an object which writes
> > vector instructions by .insn directives, so the elf architecture
> attribute
> > or mapping symbols won't have v.  I will suggest two solutions here
> rather
>
> The goal here is to be able to use the disassembler from inside of
> native riscv gdb to dump any instruction. Currently it seems like gdb
> will only dump a subset of all instructions, even with the patch you
> sent Nelson. Here is an example program:
>

My patch isn't used to resolve your problem, it just lets assembler and
dis-assembler have the same default arch, so people can just update
riscv_all_supported_ext.  It's probably convenient to be maintained.

Nelson

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