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AJvYcCWrOpYMKtamXLNsqsM+qG/Rrc9bvPBUpan2E3FzWBI/MWzRWZCzP2jfNYwpuiv/CmOOCD4HBUr6vKhI9A==@sourceware.org X-Gm-Message-State: AOJu0Ywx+r7SbSC7ejEg6vesNYU1Iy0o7tGSEzYEWXa6/a+n6eMEsWrC zs4uNwVhG7gvNV++78mJko5Yi5njvg3Dd6dge7oOLeyCf2GgCSvQoKvl2zWWt5V6oPReX0uSMzF 60Jp3oDUZqdS5fm/hLY5c5ZJyz2xWpY4/D/fF/WuFFV61jqMD0IAF+NVK6w== X-Gm-Gg: ASbGncsrB2sOP6R/fnsCJYMMrU2VEHoHDUBd/Lkcy0SCBUPJS6YLCfuTyZ8ni+t+JlU z/G5rMEdyO5z1dhQNeKNTdo7jnvcQUXAO3YATkSg6UkGDytFbSeLW9OArm8rgUpIkyR3zwyReLU v7a93yzk/Udqo7tj94ALqVE8OO5r2Bnh2kGbPsOQklxgCYpgyQxh0TUviZP7vRB7CSQ45W547Tu Qte0bU= X-Google-Smtp-Source: AGHT+IGfBp3GVepsJ0EMJfWkLDQt+twfRygLVRv0jZ2NoTkXqglPrVPk6AWjhzybORv5ebiE4a9e5yfQwsaOTyEq9Gc= X-Received: by 2002:a17:90b:1fcf:b0:31c:15d9:8aa with SMTP id 98e67ed59e1d1-31f5de558a4mr6979817a91.34.1753929448008; Wed, 30 Jul 2025 19:37:28 -0700 (PDT) MIME-Version: 1.0 References: <20250723104034.2324-2-sgargote@whileone.in> <87a54ldftg.fsf@redhat.com> In-Reply-To: From: Nelson Chu Date: Thu, 31 Jul 2025 10:37:16 +0800 X-Gm-Features: Ac12FXz6unwYwEyLn7zexuXiztCtGtE_Ur1zZc1ix5K4RUAZPcu0XH7L9YuMwBI Message-ID: Subject: Re: [PATCH] Set rv64gcv as default to enable vector extension for disassembly To: Andreas Schwab Cc: Andrew Burgess , Soham Gargote , gdb-patches@sourceware.org, binutils@sourceware.org, Sameer Natu Content-Type: multipart/alternative; boundary="000000000000b5c560063b3085ec" X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org --000000000000b5c560063b3085ec Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, Jul 30, 2025 at 9:09=E2=80=AFPM Andreas Schwab wro= te: > Why is that needed? AFAICT, objdump will happily decode any extension > without that change. > I guess maybe they are trying to dump an object which writes vector instructions by .insn directives, so the elf architecture attribute or mapping symbols won't have v. I will suggest two solutions here rather than just modify the default_arch, 1. using -Mmax option 2. Allow to set the default arch from the configure option, like what gas did before. Not sure if it is possible to find a way to share the configure set both for gas and opcode (assembler and dis-assembler). BTW, force setting default_arch to rv64gc or whatever in dis-assembler isn't really good, I think that I just forgot to update it before. So I sent a patch to let riscv_parse_subset unify the default architecture both for assembler and dis-assembler from the riscv_all_supported_ext table= . https://sourceware.org/pipermail/binutils/2025-July/143063.html Nelson --000000000000b5c560063b3085ec Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Wed, Jul 30, 2025 at 9:09=E2=80=AFPM A= ndreas Schwab <schwab@suse.de> = wrote:
Why is that needed?=C2=A0 AFAICT, objdu= mp will happily decode any extension
without that change.

=C2=A0I guess mayb= e they are trying to dump an object which writes vector=C2=A0instructions b= y .insn directives, so the elf architecture attribute or mapping symbols wo= n't have v.=C2=A0 I will suggest two solutions here rather than just mo= dify the=C2=A0default_arch,
1. using -Mmax option
2. Al= low to set the default arch from the configure option, like what gas did be= fore.=C2=A0 Not sure if it is possible to find a way to share the configure= =C2=A0set both for gas and opcode (assembler and dis-assembler).
=
BTW, force setting default_arch to rv64gc or whatever in dis= -assembler isn't really good, I think that I just forgot to update it b= efore.=C2=A0 So I sent a patch to let riscv_parse_subset unify the default = architecture both=C2=A0for assembler and dis-assembler from the riscv_all_s= upported_ext table.

Nelson
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