From: Soham Gargote <sgargote@whileone.in>
To: gdb-patches@sourceware.org
Cc: Soham Gargote <sgargote@whileone.in>, Sameer Natu <snatu@whileone.in>
Subject: [PATCH] Set rv64gcv as default to enable vector extension for disassembly
Date: Wed, 23 Jul 2025 10:40:34 +0000 [thread overview]
Message-ID: <20250723104034.2324-2-sgargote@whileone.in> (raw)
Co-Authored-By: Sameer Natu <snatu@whileone.in>
---
opcodes/riscv-dis.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index f6af9c47a25..a67b51bad74 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -1444,7 +1444,7 @@ riscv_init_disasm_info (struct disassemble_info *info)
pd->riscv_rps_dis.xlen = &pd->xlen;
pd->riscv_rps_dis.isa_spec = &pd->default_isa_spec;
pd->riscv_rps_dis.check_unknown_prefixed_ext = false;
- pd->default_arch = "rv64gc";
+ pd->default_arch = "rv64gcv";
if (info->section != NULL)
{
bfd *abfd = info->section->owner;
--
2.48.1
next reply other threads:[~2025-07-23 10:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-23 10:40 Soham Gargote [this message]
2025-07-30 12:27 ` Andrew Burgess
2025-07-30 13:07 ` Andreas Schwab
2025-07-31 2:37 ` Nelson Chu
2025-07-31 7:21 ` Charlie Jenkins
2025-07-31 7:33 ` Jan Beulich
2025-07-31 10:32 ` Nelson Chu
-- strict thread matches above, loose matches on Subject: below --
2025-07-22 10:34 Soham Gargote
2025-07-22 19:42 ` Andrew Burgess
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