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Thu, 31 Jul 2025 00:21:04 -0700 (PDT) Date: Thu, 31 Jul 2025 00:21:02 -0700 From: Charlie Jenkins To: Nelson Chu Cc: Andreas Schwab , Andrew Burgess , Soham Gargote , gdb-patches@sourceware.org, binutils@sourceware.org, Sameer Natu Subject: Re: [PATCH] Set rv64gcv as default to enable vector extension for disassembly Message-ID: References: <20250723104034.2324-2-sgargote@whileone.in> <87a54ldftg.fsf@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-BeenThere: gdb-patches@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gdb-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gdb-patches-bounces~public-inbox=simark.ca@sourceware.org On Thu, Jul 31, 2025 at 10:37:16AM +0800, Nelson Chu wrote: > On Wed, Jul 30, 2025 at 9:09 PM Andreas Schwab wrote: > > > Why is that needed? AFAICT, objdump will happily decode any extension > > without that change. > > > > I guess maybe they are trying to dump an object which writes > vector instructions by .insn directives, so the elf architecture attribute > or mapping symbols won't have v. I will suggest two solutions here rather The goal here is to be able to use the disassembler from inside of native riscv gdb to dump any instruction. Currently it seems like gdb will only dump a subset of all instructions, even with the patch you sent Nelson. Here is an example program: $ cat sample.c // sample.c volatile int num; volatile int num2; int main() { asm("vsetvli t0, a0, e32"); return num & ~num2; // zbb instruction andn } $ gcc -march=rv64gcv_zbb -O2 sample.c -o sample $ readelf -A sample Attribute Section: riscv File Attributes Tag_RISCV_stack_align: 16-bytes Tag_RISCV_arch: "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zmmul1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" $ objdump -d sample ... 0000000000000570
: 570: 010572d7 vsetvli t0,a0,e32,m1,tu,mu 574: 00002517 auipc a0,0x2 578: a9852503 lw a0,-1384(a0) # 200c 57c: 00002797 auipc a5,0x2 580: a947a783 lw a5,-1388(a5) # 2010 584: 40a7f533 andn a0,a5,a0 588: 8082 ret ... $ gdb sample (gdb) disassemble main Dump of assembler code for function main: 0x0000000000000570 <+0>: .insn 4, 0x010572d7 0x0000000000000574 <+4>: auipc a0,0x2 0x0000000000000578 <+8>: lw a0,-1384(a0) # 0x200c 0x000000000000057c <+12>: auipc a5,0x2 0x0000000000000580 <+16>: lw a5,-1388(a5) # 0x2010 0x0000000000000584 <+20>: .insn 4, 0x40a7f533 0x0000000000000588 <+24>: .insn 2, 0x8082 The disassembled instructions are lacking, even though the attributes contains the extensions. I had previously thought that this had to do with the decode() function in gdb/riscv-tdep.c but that seems to only handle gdb-specific decoding and not this disassembling. What is the way to have the disassembler dump all of the instructions of supported extensions on native riscv gdb? - Charlie > than just modify the default_arch, > 1. using -Mmax option > 2. Allow to set the default arch from the configure option, like what gas > did before. Not sure if it is possible to find a way to share the > configure set both for gas and opcode (assembler and dis-assembler). > > BTW, force setting default_arch to rv64gc or whatever in dis-assembler > isn't really good, I think that I just forgot to update it before. So I > sent a patch to let riscv_parse_subset unify the default architecture > both for assembler and dis-assembler from the riscv_all_supported_ext table. > https://sourceware.org/pipermail/binutils/2025-July/143063.html > > Nelson