* sim/mips patch: add support for more NEC VR targets
@ 2002-10-04 9:44 Richard Sandiford
[not found] ` <mailpost.1033749908.1650@news-sj1-1>
0 siblings, 1 reply; 22+ messages in thread
From: Richard Sandiford @ 2002-10-04 9:44 UTC (permalink / raw)
To: gdb-patches
Hi,
The patch below adds vr4120, vr5400 and vr5500 support to
the MIPS simulator. It also handles the mips64vr(el)-elf
configuration (which is already recognised by config.sub).
The new configuration builds a multi-arch simulator that
handles each of the following targets:
- vr4100 (also vr4111 and vr4181)
- vr4120 (also vr4130 and vr4181A)
- vr5000 (standard MIPS IV)
- vr5400
- vr5500
Notes:
- This initial submission doesn't include support for
the vr5400 multimedia extensions.
- gen-engine.c adds the global prefix to the beginning of
ENGINE_ISSUE_(PREFIX|POSTFIX)_HOOK. It seems MIPS is the
only back-end to define these macros, and it never adds a
prefix. The patch adjusts igen accordingly.
- The existing vr5000 model selects three-address mult
and dmult instructions, but those instructions aren't
listed in NEC's documentation. There's a three-address
vr5400 mult instruction, but it has a different opcode.
The vr5000 model only seems to exist for these instructions,
it would otherwise be a standard mipsIV target. Would it
be OK to submit a follow-on patch to remove it?
- The uses of vr4100 in mips.igen seem to be redundant
with mipsIII. OK to remove them as well?
The suggested follow-on patches would clean things up
a bit, but aren't needed for this patch to work, so
I thought I'd better keep them separate.
Attribution (hope I've got everyone!):
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Richard Sandiford <rsandifo@redhat.com>
I'm planning to submit more 4120 patches to FSF GCC soon. In the
meantime, the patch was tested against the NEC GNUPro version.
Please commit if OK.
Richard
igen/
* gen-engine.c (print_engine_issue_prefix_hook): Don't add the
global prefix to ENGINE_ISSUE_PREFIX_HOOK.
(print_engine_issue_postfix_hook): Likewise ENGINE_ISSUE_POSTFIX_HOOK.
mips/
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_MULTI_ALL, SIM_MULTI_CONFIGS): New.
(BUILT_SRC_FROM_MULTI): New. Depend on tmp-multi.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New dependencies.
(tmp-multi): Combine them.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
* sim-main.h: Include bfd.h.
* mips.igen (vr4120, vr5400, vr5500): New models.
(check_mf_cycles): Don't enforce mflo and mfhi separation
in vr5500 code.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
* vr_run.c: New file.
Index: igen/gen-engine.c
===================================================================
RCS file: /cvs/src/src/sim/igen/gen-engine.c,v
retrieving revision 1.2
diff -c -d -p -r1.2 gen-engine.c
*** igen/gen-engine.c 3 Jun 2002 16:04:31 -0000 1.2
--- igen/gen-engine.c 4 Oct 2002 16:26:27 -0000
*************** print_engine_issue_prefix_hook (lf *file
*** 41,50 ****
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (%sENGINE_ISSUE_PREFIX_HOOK)\n",
! options.module.global.prefix.l);
! lf_printf (file, "%sENGINE_ISSUE_PREFIX_HOOK();\n",
! options.module.global.prefix.l);
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
--- 41,48 ----
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (ENGINE_ISSUE_PREFIX_HOOK)\n");
! lf_printf (file, "ENGINE_ISSUE_PREFIX_HOOK();\n");
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
*************** print_engine_issue_postfix_hook (lf *fil
*** 55,64 ****
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (%sENGINE_ISSUE_POSTFIX_HOOK)\n",
! options.module.global.prefix.l);
! lf_printf (file, "%sENGINE_ISSUE_POSTFIX_HOOK();\n",
! options.module.global.prefix.l);
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
--- 53,60 ----
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (ENGINE_ISSUE_POSTFIX_HOOK)\n");
! lf_printf (file, "ENGINE_ISSUE_POSTFIX_HOOK();\n");
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
Index: mips/configure.in
===================================================================
RCS file: /cvs/src/src/sim/mips/configure.in,v
retrieving revision 1.4
diff -c -d -p -r1.4 configure.in
*** mips/configure.in 14 Jun 2002 18:49:09 -0000 1.4
--- mips/configure.in 4 Oct 2002 16:26:27 -0000
*************** SIM_AC_OPTION_WARNINGS
*** 18,23 ****
--- 18,24 ----
# in question.
#
case "${target}" in
+ mips64vr*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
mips*tx39*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
mipsisa32*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mipsisa64*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
*************** case "${target}" in
*** 117,122 ****
--- 118,135 ----
sim_igen_filter="32,64,f"
sim_m16_filter="16"
;;
+ mips64vr-*-* | mips64vrel-*-*)
+ sim_gen=MULTI
+ sim_multi_arch_configs="\
+ vr4100:mipsIII,mips16,vr4100:32,64 \
+ vr4120:mipsIII,mips16,vr4120:32,64 \
+ vr5000:mipsIV:32,64,f \
+ vr5400:mipsIV,vr5400:32,64,f \
+ vr5500:mipsIV,vr5500:32,64,f"
+ sim_multi_obj=vr_run.o
+ sim_multi_machine="-M mipsIII,mipsIV,mips16,vr4100,vr4120,vr5400,vr5500"
+ sim_multi_filter="16,32,64,f"
+ ;;
mips64*-*-*) sim_igen_filter="32,64,f"
sim_gen=IGEN
;;
*************** case "${target}" in
*** 146,156 ****
--- 159,216 ----
sim_igen_filter="32,f"
;;
esac
+
+ # Handle $sim_multi_arch_configs. Each space-separated entry has
+ # the form NAME:MACHINE:FILTER, where NAME is a C-compatible name
+ # for the configuration, MACHINE is a -M argument and FILTER is a
+ # -F argument.
+ #
+ # Each entry will have a separate simulation engine whose prefix is
+ # m32<NAME>. If the machine list includes "mips16", there will also
+ # be a mips16 engine, prefix m16<NAME>. The mips16 engine will be
+ # generated using the same machine list as the 32-bit version,
+ # but the filter will be "16" instead of FILTER.
+ #
+ # If a configuration uses MULTI, it should set $sim_multi_machine
+ # to a list of every machine used in the configuration and
+ # $sim_multi_filter to a list of every filter (including "16"
+ # if there are mips16 configurations). The configuration can
+ # add extra object files to the executable using $sim_multi_obj.
+ if test ${sim_gen} = MULTI; then
+ for c in ${sim_multi_arch_configs}; do
+ name=`echo $c | sed 's/:.*//'`
+ case $c in
+ *:*mips16*:*)
+ ws="m16 m32"
+ sim_multi_src="${sim_multi_src} m16${name}_run.c"
+ sim_multi_obj="${sim_multi_obj} m16${name}_run.o"
+ ;;
+ *)
+ ws=m32 ;;
+ esac
+ for w in ${ws}; do
+ for base in engine icache idecode model semantics support; do
+ sim_multi_src="${sim_multi_src} ${w}${name}_${base}.c"
+ sim_multi_src="${sim_multi_src} ${w}${name}_${base}.h"
+ sim_multi_obj="${sim_multi_obj} ${w}${name}_${base}.o"
+ done
+ sim_multi_configs="${sim_multi_configs} ${w}${c}"
+ done
+ done
+ else
+ # For clean-extra
+ sim_multi_src=doesnt-exist.c
+ fi
sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}"
+ sim_multi_flags="-F ${sim_multi_filter} ${sim_multi_machine}"
AC_SUBST(sim_igen_flags)
AC_SUBST(sim_m16_flags)
AC_SUBST(sim_gen)
+ AC_SUBST(sim_multi_flags)
+ AC_SUBST(sim_multi_configs)
+ AC_SUBST(sim_multi_src)
+ AC_SUBST(sim_multi_obj)
#
Index: mips/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mips/Makefile.in,v
retrieving revision 1.7
diff -c -d -p -r1.7 Makefile.in
*** mips/Makefile.in 14 Jun 2002 18:49:09 -0000 1.7
--- mips/Makefile.in 4 Oct 2002 16:26:27 -0000
*************** SIM_M16_OBJ = \
*** 33,38 ****
--- 33,39 ----
itable.o \
m16run.o \
+ SIM_MULTI_OBJ = itable.o @sim_multi_obj@
MIPS_EXTRA_OBJS = @mips_extra_objs@
MIPS_EXTRA_LIBS = @mips_extra_libs@
*************** BUILT_SRC_FROM_GEN = \
*** 98,103 ****
--- 99,105 ----
SIM_IGEN_ALL = tmp-igen
SIM_M16_ALL = tmp-m16
+ SIM_MULTI_ALL = tmp-multi
$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
*************** tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen
*** 291,300 ****
--- 293,389 ----
touch tmp-m16
+ BUILT_SRC_FROM_MULTI = @sim_multi_src@
+ SIM_MULTI_CONFIGS = @sim_multi_configs@
+
+ $(BUILT_SRC_FROM_MULTI): tmp-multi
+ tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi targ-vals.h
+ tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+ for t in $(SIM_MULTI_CONFIGS); do \
+ p=`echo $${t} | sed -e 's/:.*//'` ; \
+ m=`echo $${t} | sed -e 's/[^:]*:\(.*\):.*/\1/'` ; \
+ f=`echo $${t} | sed -e 's/.*://'` ; \
+ case $${p} in \
+ m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
+ *) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
+ esac; \
+ ../igen/igen \
+ $(IGEN_TRACE) \
+ $${e} \
+ -I $(srcdir) \
+ -Werror \
+ -Wnodiscard \
+ -N 0 \
+ -M $${m} \
+ -G gen-direct-access \
+ -G gen-zero-r0 \
+ -i $(IGEN_INSN) \
+ -P $${p}_ \
+ -x \
+ -n $${p}_icache.h -hc tmp-icache.h \
+ -n $${p}_icache.c -c tmp-icache.c \
+ -n $${p}_semantics.h -hs tmp-semantics.h \
+ -n $${p}_semantics.c -s tmp-semantics.c \
+ -n $${p}_idecode.h -hd tmp-idecode.h \
+ -n $${p}_idecode.c -d tmp-idecode.c \
+ -n $${p}_model.h -hm tmp-model.h \
+ -n $${p}_model.c -m tmp-model.c \
+ -n $${p}_support.h -hf tmp-support.h \
+ -n $${p}_support.c -f tmp-support.c \
+ -n $${p}_engine.h -he tmp-engine.h \
+ -n $${p}_engine.c -e tmp-engine.c \
+ ; \
+ $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
+ $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
+ $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
+ $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
+ $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
+ $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
+ $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
+ $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
+ $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
+ $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
+ $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
+ $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
+ done
+ touch tmp-mach-multi
+ tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+ ../igen/igen \
+ $(IGEN_TRACE) \
+ -I $(srcdir) \
+ -Werror \
+ -Wnodiscard \
+ -Wnowidth \
+ -N 0 \
+ @sim_multi_flags@ \
+ -G gen-direct-access \
+ -G gen-zero-r0 \
+ -i $(IGEN_INSN) \
+ -n itable.h -ht tmp-itable.h \
+ -n itable.c -t tmp-itable.c \
+ #
+ $(srcdir)/../../move-if-change tmp-itable.h itable.h
+ $(srcdir)/../../move-if-change tmp-itable.c itable.c
+ touch tmp-itable-multi
+ tmp-run-multi: $(srcdir)/m16run.c
+ for t in $(SIM_MULTI_CONFIGS); do \
+ case $${t} in \
+ *:*mips16*:*) \
+ m=`echo $${t} | sed 's/m16\([^:]*\):.*/\1/'`; \
+ sed < $(srcdir)/m16run.c > tmp-run \
+ -e "s/^sim_/m16$${m}_/" \
+ -e "s/m16_/m16$${m}_/" \
+ -e "s/m32_/m32$${m}_/" ; \
+ $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
+ esac \
+ done
+ touch tmp-run-multi
+
clean-extra:
rm -f $(BUILT_SRC_FROM_GEN)
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f $(BUILT_SRC_FROM_M16)
+ rm -f $(BUILT_SRC_FROM_MULTI)
rm -f tmp-*
rm -f m16*.o m32*.o itable*.o
Index: mips/sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.h,v
retrieving revision 1.23
diff -c -d -p -r1.23 sim-main.h
*** mips/sim-main.h 14 Jun 2002 18:49:09 -0000 1.23
--- mips/sim-main.h 4 Oct 2002 16:26:27 -0000
*************** mips_core_signal ((SD), (CPU), (CIA), (M
*** 41,47 ****
typedef address_word sim_cia;
#include "sim-base.h"
!
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
--- 41,47 ----
typedef address_word sim_cia;
#include "sim-base.h"
! #include "bfd.h"
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
Index: mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.49
diff -c -d -p -r1.49 mips.igen
*** mips/mips.igen 31 Jul 2002 05:44:54 -0000 1.49
--- mips/mips.igen 4 Oct 2002 16:26:27 -0000
***************
*** 55,61 ****
--- 55,64 ----
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
+ :model:::vr4120:mips4120:
:model:::vr5000:mips5000:
+ :model:::vr5400:mips5400:
+ :model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
***************
*** 229,234 ****
--- 232,240 ----
:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
{
+ /* There are no timing requirements in vr5500 code. */
+ if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_mips5500)
+ return 1;
if (history->mf.timestamp + 3 > time)
{
sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
***************
*** 1010,1015 ****
--- 1016,1022 ----
"clo r<RD>, r<RS>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
***************
*** 1034,1039 ****
--- 1041,1047 ----
"clz r<RD>, r<RS>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
***************
*** 1143,1148 ****
--- 1151,1157 ----
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
+ *vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
***************
*** 1166,1171 ****
--- 1175,1181 ----
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
+ *vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
***************
*** 2189,2194 ****
--- 2199,2205 ----
"madd r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 2208,2213 ****
--- 2219,2225 ----
"maddu r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 2312,2317 ****
--- 2324,2330 ----
"msub r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 2331,2336 ****
--- 2344,2350 ----
"msubu r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 2388,2393 ****
--- 2402,2408 ----
"mul r<RD>, r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 prod;
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Index: mips/vr.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/vr.igen,v
retrieving revision 1.1.1.1
diff -c -d -p -r1.1.1.1 vr.igen
*** mips/vr.igen 16 Apr 1999 01:35:07 -0000 1.1.1.1
--- mips/vr.igen 4 Oct 2002 16:26:27 -0000
***************
*** 3,78 ****
// NEC specific instructions
//
! // Integer Instructions
! // --------------------
! //
! // MulAcc is the Multiply Accumulator.
! // This register is mapped on the the HI and LO registers.
! // Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
! // Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
! :function:::unsigned64:MulAcc:
! *vr4100:
{
! unsigned64 result = U8_4 (HI, LO);
! return result;
}
! :function:::void:SET_MulAcc:unsigned64 value
! *vr4100:
{
! /* 64 bit specific */
! *AL4_8 (&HI) = VH4_8 (value);
! *AL4_8 (&LO) = VL4_8 (value);
}
! :function:::signed64:SignedMultiply:signed32 l, signed32 r
! *vr4100:
{
! signed64 result = (signed64) l * (signed64) r;
return result;
}
! :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
! *vr4100:
{
! unsigned64 result = (unsigned64) l * (unsigned64) r;
return result;
}
! :function:::unsigned64:Low32Bits:unsigned64 value
*vr4100:
{
! unsigned64 result = (signed64) (signed32) VL4_8 (value);
! return result;
}
! :function:::unsigned64:High32Bits:unsigned64 value
*vr4100:
{
! unsigned64 result = (signed64) (signed32) VH4_8 (value);
! return result;
}
! // Multiply, Accumulate
! 000000,5.RS,5.RT,00000,00000,101000::64::MAC
! "mac r<RS>, r<RT>"
! *vr4100:
{
! SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
}
! // D-Multiply, Accumulate
! 000000,5.RS,5.RT,00000,00000,101001::64::DMAC
! "dmac r<RS>, r<RT>"
! *vr4100:
{
! LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
}
--- 3,323 ----
// NEC specific instructions
//
! :%s::::MFHI:int hi
! {
! return hi ? "hi" : "";
! }
+ :%s::::SAT:int s
+ {
+ return s ? "s" : "";
+ }
! :%s::::UNS:int u
{
! return u ? "u" : "";
}
! // Simulate the various kinds of multiply and multiply-accumulate instructions.
! // Perform an operation of the form:
! //
! // LHS (+/-) GPR[RS] * GPR[RT]
! //
! // and store it in the 64-bit accumulator. Optionally copy either LO or
! // HI into a general purpose register.
! //
! // - RD is the destination register of the LO or HI move
! // - RS are RT are the multiplication source registers
! // - ACCUMULATE_P is true if LHS should be the value of the 64-bit accumulator,
! // false if it should be 0.
! // - STORE_HI_P is true if HI should be stored in RD, false if LO should be.
! // - UNSIGNED_P is true if the operation should be unsigned.
! // - SATURATE_P is true if the result should be saturated to a 32-bit value.
! // - SUBTRACT_P is true if the right hand side should be subtraced from LHS,
! // false if it should be added.
! // - SHORT_P is true if RS and RT must be 16-bit numbers.
! // - DOUBLE_P is true if the 64-bit accumulator is in LO, false it is a
! // concatenation of the low 32 bits of HI and LO.
! :function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p
{
! unsigned64 lhs, x, y, xcut, ycut, product, result;
!
! check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
!
! lhs = (!accumulate_p ? 0 : double_p ? LO : U8_4 (HI, LO));
! x = GPR[rs];
! y = GPR[rt];
!
! /* Work out the canonical form of X and Y from their significant bits. */
! if (!short_p)
! {
! /* Normal sign-extension rule for 32-bit operands. */
! xcut = EXTEND32 (x);
! ycut = EXTEND32 (y);
! }
! else if (unsigned_p)
! {
! /* Operands must be zero-extended 16-bit numbers. */
! xcut = x & 0xffff;
! ycut = y & 0xffff;
! }
! else
! {
! /* Likewise but sign-extended. */
! xcut = EXTEND16 (x);
! ycut = EXTEND16 (y);
! }
! if (x != xcut || y != ycut)
! sim_engine_abort (SD, CPU, CIA,
! "invalid multiplication operand at 0x%08lx\n",
! (long) CIA);
!
! TRACE_ALU_INPUT2 (x, y);
! product = (unsigned_p ? x * y : EXTEND32 (x) * EXTEND32 (y));
! result = (subtract_p ? lhs - product : lhs + product);
! if (saturate_p)
! {
! /* Saturate the result to 32 bits. An unsigned, unsaturated
! result is zero-extended to 64 bits, but unsigned overflow
! causes all 64 bits to be set. */
! if (!unsigned_p && (unsigned64) EXTEND32 (result) != result)
! result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff);
! else if (unsigned_p && (result >> 32) != 0)
! result = (unsigned64) 0 - 1;
! }
! TRACE_ALU_RESULT (result);
!
! if (double_p)
! LO = result;
! else
! {
! LO = EXTEND32 (result);
! HI = EXTEND32 (VH4_8 (result));
! }
! if (rd != 0)
! GPR[rd] = store_hi_p ? HI : LO;
}
! // 32-bit rotate right of X by Y bits.
! :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
! *vr5400:
! *vr5500:
{
! unsigned64 result;
!
! y &= 31;
! TRACE_ALU_INPUT2 (x, y);
! result = EXTEND32 (ROTR32 (x, y));
! TRACE_ALU_RESULT (result);
return result;
}
! // Likewise 64-bit
! :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
! *vr5400:
! *vr5500:
{
! unsigned64 result;
!
! y &= 63;
! TRACE_ALU_INPUT2 (x, y);
! result = ROTR64 (x, y);
! TRACE_ALU_RESULT (result);
return result;
}
!
! // VR4100 instructions.
!
! 000000,5.RS,5.RT,00000,00000,101000::32::MADD16
! "madd16 r<RS>, r<RT>"
*vr4100:
{
! do_vr_mul_op (SD_, 0, RS, RT,
! 1 /* accumulate */,
! 0 /* store in LO */,
! 0 /* signed arithmetic */,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 1 /* short */,
! 0 /* single */);
}
! 000000,5.RS,5.RT,00000,00000,101001::64::DMADD16
! "dmadd16 r<RS>, r<RT>"
*vr4100:
{
! do_vr_mul_op (SD_, 0, RS, RT,
! 1 /* accumulate */,
! 0 /* store in LO */,
! 0 /* signed arithmetic */,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 1 /* short */,
! 1 /* double */);
}
! // VR4120 and VR4130 instructions.
!
! 000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101001::64::DMACC
! "dmacc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
! *vr4120:
{
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS, SAT,
! 0 /* don't subtract */,
! SAT /* short */,
! 1 /* double */);
! }
!
! 000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101000::32::MACC_4120
! "macc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
! *vr4120:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS, SAT,
! 0 /* don't subtract */,
! SAT /* short */,
! 0 /* single */);
}
! // VR5400 and VR5500 instructions.
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,001,01100,1.UNS::32::MUL
! "mul%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
{
! do_vr_mul_op (SD_, RD, RS, RT,
! 0 /* don't accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,011,01100,1.UNS::32::MULS
! "muls%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 0 /* don't accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 1 /* subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,101,01100,1.UNS::32::MACC_5xxx
! "macc%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,111,01100,1.UNS::32::MSAC
! "msac%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 1 /* subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
! "ror r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
! }
!
! 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
! "rorv r<RD>, r<RT>, r<RS>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
! "dror r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
! "dror32 r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
! }
!
! 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
! "drorv r<RD>, r<RT>, r<RS>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
! }
!
! 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1
! "luxc1 f<FD>, r<INDEX>(r<BASE>)"
! *vr5500:
! {
! check_fpu (SD_);
! COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD,
! (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0));
! }
!
! 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64::SUXC1
! "suxc1 f<FS>, r<INDEX>(r<BASE>)"
! *vr5500:
! {
! check_fpu (SD_);
! do_store (SD_, AccessLength_DOUBLEWORD,
! (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0,
! COP_SD (1, FS));
}
+ 010000,1,19.*,100000:COP0:32::WAIT
+ "wait"
+ *vr5500:
+
+ 011100,00000,5.RT,5.DR,00000,111101:SPECIAL:64::MFDR
+ "mfdr r<RT>, r<DR>"
+ *vr5400:
+ *vr5500:
+ 011100,00100,5.RT,5.DR,00000,111101:SPECIAL:64::MTDR
+ "mtdr r<RT>, r<DR>"
+ *vr5400:
+ *vr5500:
+ 011100,00000,00000,00000,00000,111110:SPECIAL:64::DRET
+ "dret"
+ *vr5400:
+ *vr5500:
*** /dev/null Tue Nov 14 21:44:43 2000
--- mips/vr_run.c Fri Oct 4 17:25:19 2002
***************
*** 0 ****
--- 1,74 ----
+ /* Main entry point for the mips64vr simulator.
+ Copyright (C) 2002 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ */
+
+ #include "sim-main.h"
+ #include "m16vr4100_engine.h"
+ #include "m16vr4120_engine.h"
+ #include "m32vr5000_engine.h"
+ #include "m32vr5400_engine.h"
+ #include "m32vr5500_engine.h"
+ #include "bfd.h"
+
+ #define SD sd
+ #define CPU cpu
+
+ void
+ sim_engine_run (SIM_DESC sd,
+ int next_cpu_nr,
+ int nr_cpus,
+ int signal) /* ignore */
+ {
+ int mach, i;
+
+ if (STATE_ARCHITECTURE (sd) == NULL)
+ mach = 0;
+ else
+ mach = STATE_ARCHITECTURE (sd)->mach;
+
+ switch (mach)
+ {
+ case bfd_mach_mips4100:
+ case bfd_mach_mips4111:
+ m16vr4100_engine_run (sd, next_cpu_nr, nr_cpus, signal);
+ break;
+
+ case bfd_mach_mips4120:
+ m16vr4120_engine_run (sd, next_cpu_nr, nr_cpus, signal);
+ break;
+
+ default:
+ case bfd_mach_mips4000:
+ case bfd_mach_mips4300:
+ case bfd_mach_mips5000:
+ case bfd_mach_mips8000:
+ /* A standard MIPS IV target. ??? The vr4300 is really
+ a MIPS III target, but FPR<->GPR moves do not have
+ a delay slot. */
+ m32vr5000_engine_run (sd, next_cpu_nr, nr_cpus, signal);
+ break;
+
+ case bfd_mach_mips5400:
+ m32vr5400_engine_run (sd, next_cpu_nr, nr_cpus, signal);
+ break;
+
+ case bfd_mach_mips5500:
+ m32vr5500_engine_run (sd, next_cpu_nr, nr_cpus, signal);
+ break;
+ }
+ }
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
[not found] ` <mailpost.1033749908.1650@news-sj1-1>
@ 2002-10-04 10:54 ` cgd
2002-10-09 7:14 ` Richard Sandiford
2002-11-06 16:46 ` Andrew Cagney
0 siblings, 2 replies; 22+ messages in thread
From: cgd @ 2002-10-04 10:54 UTC (permalink / raw)
To: rsandifo; +Cc: gdb-patches
At Fri, 4 Oct 2002 16:45:09 +0000 (UTC), "Richard Sandiford" wrote:
> The patch below adds vr4120, vr5400 and vr5500 support to
> the MIPS simulator. It also handles the mips64vr(el)-elf
> configuration (which is already recognised by config.sub).
Excellent!
I have a few questions/issues, but other than that this should be OK.
> - gen-engine.c adds the global prefix to the beginning of
> ENGINE_ISSUE_(PREFIX|POSTFIX)_HOOK. It seems MIPS is the
> only back-end to define these macros, and it never adds a
> prefix. The patch adjusts igen accordingly.
Hmm. I don't know igen so well. Andrew? What are your thoughts
here?
> - The existing vr5000 model selects three-address mult
> and dmult instructions, but those instructions aren't
> listed in NEC's documentation. There's a three-address
> vr5400 mult instruction, but it has a different opcode.
>
> The vr5000 model only seems to exist for these instructions,
> it would otherwise be a standard mipsIV target. Would it
> be OK to submit a follow-on patch to remove it?
Well, there are a couple of other differences w.r.t: BC0T, DMFC0,
DMTC0, COPz... But I don't know whether they're relevant.
As far as I'm concerned, if there is no difference, it should probably
be removed. Andrew?
> - The uses of vr4100 in mips.igen seem to be redundant
> with mipsIII. OK to remove them as well?
I'm assuming this is a historical thing.
In the old world order, every processor type had its own model.
In the new world order, which you seem to be adapting nicely to,
processors which are "ISA + extensions" use multiple models.
Looking at your multi-arch code, you seem to be handling this in the
new correct manner.
I am concerned w/ one thing here, though:
vr4100 selects a bunch of different cop1 instructions than mipsIII
does, e.g. CFC1a vs. CFC1b.
(the former, used by MIPS3, does cp1 delay slot handling. The latter,
used by vr4100, does not.)
I don't know which is correct for vr4100.
> I'm planning to submit more 4120 patches to FSF GCC soon. In the
> meantime, the patch was tested against the NEC GNUPro version.
> Please commit if OK.
I assume that means that this was tested in the current gdb+sim
sources, against that version of GNUpro.
There are a couple of specific things that would be nice if you could
arrange in follow-on patches, in addition to what you describe above:
* it would be good if things like vr_run.c could be automatically
generated. It should be easy to do this with a little more info in
sim_multi_arch_configs and a little bit of awk. 8-) (I suppose if
you don't want to tackle that, it would be OK... but could I sign
you up to help test the changes later if you don't do it?)
> ***************
> *** 229,234 ****
> --- 232,240 ----
>
> :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
> {
> + /* There are no timing requirements in vr5500 code. */
> + if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_mips5500)
> + return 1;
> if (history->mf.timestamp + 3 > time)
> {
This is the first case of code like this in the MIPS sim, but it seems
like the right thing.
> ***************
> *** 1010,1015 ****
> --- 1016,1022 ----
> "clo r<RD>, r<RS>"
> *mips32:
> *mips64:
> + *vr5500:
(and the related instructions)
You might check that the 5500 actually uses the same encodings here,
and what it says about unpredicable operation if RT != RD. (this is
coded based on the MIPS32/MIPS64 specs, which accomodate an older
implementation which used the other reg. than mips32/mips64 did.)
Probably right to simulate them w/ the same restrictions, unless
vr5500 does something very different.
There is an annoying interaction between multi-arching a sim and using
STATE_ARCHITECTURE (SD)->mach: e.g. if you have the thing above where
you check bfd_mach_mips5500, if mips5500 is the 'default' for your sim
(i.e., catches unknown machine types), that check will fail.
Really, we need to be sure to check and, if necessary, set 'mach' to a
default value when it is set.
Other than mentioned above (I don't see any real objections 8-), your
patch is OK by me. Andrew might have some comments, and I don't know
that I really have the authority to OK changes to the igen bit.
chris
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-10-04 10:54 ` cgd
@ 2002-10-09 7:14 ` Richard Sandiford
2002-10-22 15:27 ` cgd
2002-11-06 16:46 ` Andrew Cagney
1 sibling, 1 reply; 22+ messages in thread
From: Richard Sandiford @ 2002-10-09 7:14 UTC (permalink / raw)
To: cgd; +Cc: gdb-patches
Thanks for the review.
cgd@broadcom.com writes:
> > - The existing vr5000 model selects three-address mult
> > and dmult instructions, but those instructions aren't
> > listed in NEC's documentation. There's a three-address
> > vr5400 mult instruction, but it has a different opcode.
> >
> > The vr5000 model only seems to exist for these instructions,
> > it would otherwise be a standard mipsIV target. Would it
> > be OK to submit a follow-on patch to remove it?
>
> Well, there are a couple of other differences w.r.t: BC0T, DMFC0,
> DMTC0, COPz... But I don't know whether they're relevant.
Good catch. I checked that vr5000 implied mipsIV, but not the
other way around (duh!).
Anyway, the processor doesn't have bc0f, bc0t, or a coprocessor 2,
so raising a reserved instruction exception is the right thing to do.
But I guess that's true of many targets, and AFAICT the exception
is raised regardless of whether a target is listed under BC0F, BC0T
or COPz. So I think it's safe to "add" vr5000 here.
According to the manual, dmtc0 and dmfc0 are supported. I can't check
on real hardware at the moment, but I've no reason to doubt them.
So it seems removing vr5000 would actually be a bug fix ;)
> > - The uses of vr4100 in mips.igen seem to be redundant
> > with mipsIII. OK to remove them as well?
>
> I am concerned w/ one thing here, though:
>
> vr4100 selects a bunch of different cop1 instructions than mipsIII
> does, e.g. CFC1a vs. CFC1b.
Yeah. I don't understand why, really, since the vr41xx processors don't
have an FPU. Maybe the target environment was assumed to provide an
emulator or something? But key instructions (like bc1f and bc1t ;-)
are missing, so very little FP code is going to work.
> > I'm planning to submit more 4120 patches to FSF GCC soon. In the
> > meantime, the patch was tested against the NEC GNUPro version.
Wasn't very clear, but...
> I assume that means that this was tested in the current gdb+sim
> sources, against that version of GNUpro.
...yes, that's right.
> There are a couple of specific things that would be nice if you could
> arrange in follow-on patches, in addition to what you describe above:
>
> * it would be good if things like vr_run.c could be automatically
> generated.
OK. Guilt at my earlier lameness forced me to give this a go.
New version attached. Not pretty (and I didn't use awk ;-) but
it should reduce the amount of cut&paste if other targets use
MULTI. I've also removed the need to define sim_multi_filter
and sim_multi_machine, since igen can cope with the same machine
& filter being given twice.
> > ***************
> > *** 1010,1015 ****
> > --- 1016,1022 ----
> > "clo r<RD>, r<RS>"
> > *mips32:
> > *mips64:
> > + *vr5500:
>
> (and the related instructions)
>
> You might check that the 5500 actually uses the same encodings here,
> and what it says about unpredicable operation if RT != RD. (this is
> coded based on the MIPS32/MIPS64 specs, which accomodate an older
> implementation which used the other reg. than mips32/mips64 did.)
Just to confirm it and the other insns do have the same encoding.
As for RT & RD, the preliminary data sheet just says "Specify the
same register as general-purpose register rd for general-purpose
register rt." So I think it's fair for the simulator to complain
if they're different.
> There is an annoying interaction between multi-arching a sim and using
> STATE_ARCHITECTURE (SD)->mach: e.g. if you have the thing above where
> you check bfd_mach_mips5500, if mips5500 is the 'default' for your sim
> (i.e., catches unknown machine types), that check will fail.
>
> Really, we need to be sure to check and, if necessary, set 'mach' to a
> default value when it is set.
Where do you think this should happen? In sim_engine_run()?
Anyway, patch with new configuration attached. Tested in
the same way as before.
igen/
* gen-engine.c (print_engine_issue_prefix_hook): Don't add the
global prefix to ENGINE_ISSUE_PREFIX_HOOK.
(print_engine_issue_postfix_hook): Likewise ENGINE_ISSUE_POSTFIX_HOOK.
mips/
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_MULTI_ALL, SIM_MULTI_CONFIGS): New.
(BUILT_SRC_FROM_MULTI): New. Depend on tmp-multi.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New dependencies.
(tmp-multi): Combine them.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
* sim-main.h: Include bfd.h.
* mips.igen (vr4120, vr5400, vr5500): New models.
(check_mf_cycles): Don't enforce mflo and mfhi separation
in vr5500 code.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
* multi_run.c: New file.
Index: igen/gen-engine.c
===================================================================
RCS file: /cvs/src/src/sim/igen/gen-engine.c,v
retrieving revision 1.2
diff -c -d -p -r1.2 gen-engine.c
*** igen/gen-engine.c 3 Jun 2002 16:04:31 -0000 1.2
--- igen/gen-engine.c 9 Oct 2002 09:14:27 -0000
*************** print_engine_issue_prefix_hook (lf *file
*** 41,50 ****
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (%sENGINE_ISSUE_PREFIX_HOOK)\n",
! options.module.global.prefix.l);
! lf_printf (file, "%sENGINE_ISSUE_PREFIX_HOOK();\n",
! options.module.global.prefix.l);
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
--- 41,48 ----
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (ENGINE_ISSUE_PREFIX_HOOK)\n");
! lf_printf (file, "ENGINE_ISSUE_PREFIX_HOOK();\n");
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
*************** print_engine_issue_postfix_hook (lf *fil
*** 55,64 ****
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (%sENGINE_ISSUE_POSTFIX_HOOK)\n",
! options.module.global.prefix.l);
! lf_printf (file, "%sENGINE_ISSUE_POSTFIX_HOOK();\n",
! options.module.global.prefix.l);
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
--- 53,60 ----
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (ENGINE_ISSUE_POSTFIX_HOOK)\n");
! lf_printf (file, "ENGINE_ISSUE_POSTFIX_HOOK();\n");
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
Index: mips/configure.in
===================================================================
RCS file: /cvs/src/src/sim/mips/configure.in,v
retrieving revision 1.4
diff -c -d -p -r1.4 configure.in
*** mips/configure.in 14 Jun 2002 18:49:09 -0000 1.4
--- mips/configure.in 9 Oct 2002 09:14:27 -0000
*************** SIM_AC_OPTION_WARNINGS
*** 18,23 ****
--- 18,24 ----
# in question.
#
case "${target}" in
+ mips64vr*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
mips*tx39*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
mipsisa32*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mipsisa64*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
*************** case "${target}" in
*** 117,122 ****
--- 118,132 ----
sim_igen_filter="32,64,f"
sim_m16_filter="16"
;;
+ mips64vr-*-* | mips64vrel-*-*)
+ sim_gen=MULTI
+ sim_multi_arch_configs="\
+ vr4100:mipsIII,mips16,vr4100:32,64@4100,4111 \
+ vr4120:mipsIII,mips16,vr4120:32,64@4120 \
+ vr5000:mipsIV:32,64,f@4300,5000,default \
+ vr5400:mipsIV,vr5400:32,64,f@5400 \
+ vr5500:mipsIV,vr5500:32,64,f@5500"
+ ;;
mips64*-*-*) sim_igen_filter="32,64,f"
sim_gen=IGEN
;;
*************** case "${target}" in
*** 146,156 ****
--- 156,239 ----
sim_igen_filter="32,f"
;;
esac
+
+ # The MULTI generator can combine several simulation engines into
+ # one executable. A configuration which uses the MULTI should
+ # set ${sim_multi_arch_configs} to the list of engines to build.
+ # Each space-separated entry has the form NAME:MACHINE:FILTER@ARCHS,
+ # where:
+ #
+ # - NAME is a C-compatible prefix for the engine,
+ # - MACHINE is a -M argument,
+ # - FILTER is a -F argument, and
+ # - ARCHS is a comma-separated list of bfd machines that the
+ # simulator can run.
+ #
+ # Each entry will have a separate simulation engine whose prefix is
+ # m32<NAME>. If the machine list includes "mips16", there will also
+ # be a mips16 engine, prefix m16<NAME>. The mips16 engine will be
+ # generated using the same machine list as the 32-bit version,
+ # but the filter will be "16" instead of FILTER.
+ #
+ # The simulator compares the bfd mach against ARCHS to decide
+ # which engine to use. Entries in ARCHS can be a bfd_mach_mips*
+ # value with "bfd_mach_mips" removed, or the special string
+ # "default" to indicate that a particular engine should be
+ # the default.
+ if test ${sim_gen} = MULTI; then
+ rm -f multi-include.h multi-switch.c
+ sim_multi_flags=
+ sim_multi_obj=multi_run.o
+ for fc in ${sim_multi_arch_configs}; do
+ c=`echo ${fc} | sed 's/@.*//'`
+ archs=`echo ${fc} | sed 's/.*@//'`
+ name=`echo ${c} | sed 's/:.*//'`
+ m=`echo ${c} | sed 's/.*:\(.*\):.*/\1/'`
+ f=`echo ${c} | sed 's/.*://'`
+ sim_multi_flags="${sim_multi_flags} -F ${f} -M ${m}"
+ case $c in
+ *:*mips16*:*)
+ ws="m32 m16"
+ sim_multi_src="${sim_multi_src} m16${name}_run.c"
+ sim_multi_obj="${sim_multi_obj} m16${name}_run.o"
+ sim_multi_flags="${sim_multi_flags} -F 16"
+ ;;
+ *)
+ ws=m32
+ ;;
+ esac
+ for w in ${ws}; do
+ for base in engine icache idecode model semantics support; do
+ sim_multi_src="${sim_multi_src} ${w}${name}_${base}.c"
+ sim_multi_src="${sim_multi_src} ${w}${name}_${base}.h"
+ sim_multi_obj="${sim_multi_obj} ${w}${name}_${base}.o"
+ done
+ sim_multi_configs="${sim_multi_configs} ${w}${c}"
+ done
+ echo "#include \"${w}${name}_engine.h\"" >> multi-include.h
+ for a in `echo $archs | sed 's/,/ /g'`; do
+ case $a in
+ default) echo "default:" >> multi-switch.c ;;
+ *) echo "case bfd_mach_mips$a:" >> multi-switch.c ;;
+ esac
+ done
+ echo " ${w}${name}_engine_run (sd, next_cpu_nr, nr_cpus, signal);" \
+ >> multi-switch.c
+ echo " break;" >> multi-switch.c
+ done
+ else
+ # For clean-extra
+ sim_multi_src=doesnt-exist.c
+ fi
sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}"
AC_SUBST(sim_igen_flags)
AC_SUBST(sim_m16_flags)
AC_SUBST(sim_gen)
+ AC_SUBST(sim_multi_flags)
+ AC_SUBST(sim_multi_configs)
+ AC_SUBST(sim_multi_src)
+ AC_SUBST(sim_multi_obj)
#
Index: mips/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mips/Makefile.in,v
retrieving revision 1.7
diff -c -d -p -r1.7 Makefile.in
*** mips/Makefile.in 14 Jun 2002 18:49:09 -0000 1.7
--- mips/Makefile.in 9 Oct 2002 09:14:27 -0000
*************** SIM_M16_OBJ = \
*** 33,38 ****
--- 33,39 ----
itable.o \
m16run.o \
+ SIM_MULTI_OBJ = itable.o @sim_multi_obj@
MIPS_EXTRA_OBJS = @mips_extra_objs@
MIPS_EXTRA_LIBS = @mips_extra_libs@
*************** BUILT_SRC_FROM_GEN = \
*** 98,103 ****
--- 99,105 ----
SIM_IGEN_ALL = tmp-igen
SIM_M16_ALL = tmp-m16
+ SIM_MULTI_ALL = tmp-multi
$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
*************** tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen
*** 291,300 ****
--- 293,389 ----
touch tmp-m16
+ BUILT_SRC_FROM_MULTI = @sim_multi_src@
+ SIM_MULTI_CONFIGS = @sim_multi_configs@
+
+ $(BUILT_SRC_FROM_MULTI): tmp-multi
+ tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi targ-vals.h
+ tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+ for t in $(SIM_MULTI_CONFIGS); do \
+ p=`echo $${t} | sed -e 's/:.*//'` ; \
+ m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
+ f=`echo $${t} | sed -e 's/.*://'` ; \
+ case $${p} in \
+ m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
+ *) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
+ esac; \
+ ../igen/igen \
+ $(IGEN_TRACE) \
+ $${e} \
+ -I $(srcdir) \
+ -Werror \
+ -Wnodiscard \
+ -N 0 \
+ -M $${m} \
+ -G gen-direct-access \
+ -G gen-zero-r0 \
+ -i $(IGEN_INSN) \
+ -P $${p}_ \
+ -x \
+ -n $${p}_icache.h -hc tmp-icache.h \
+ -n $${p}_icache.c -c tmp-icache.c \
+ -n $${p}_semantics.h -hs tmp-semantics.h \
+ -n $${p}_semantics.c -s tmp-semantics.c \
+ -n $${p}_idecode.h -hd tmp-idecode.h \
+ -n $${p}_idecode.c -d tmp-idecode.c \
+ -n $${p}_model.h -hm tmp-model.h \
+ -n $${p}_model.c -m tmp-model.c \
+ -n $${p}_support.h -hf tmp-support.h \
+ -n $${p}_support.c -f tmp-support.c \
+ -n $${p}_engine.h -he tmp-engine.h \
+ -n $${p}_engine.c -e tmp-engine.c \
+ ; \
+ $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
+ $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
+ $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
+ $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
+ $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
+ $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
+ $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
+ $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
+ $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
+ $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
+ $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
+ $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
+ done
+ touch tmp-mach-multi
+ tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+ ../igen/igen \
+ $(IGEN_TRACE) \
+ -I $(srcdir) \
+ -Werror \
+ -Wnodiscard \
+ -Wnowidth \
+ -N 0 \
+ @sim_multi_flags@ \
+ -G gen-direct-access \
+ -G gen-zero-r0 \
+ -i $(IGEN_INSN) \
+ -n itable.h -ht tmp-itable.h \
+ -n itable.c -t tmp-itable.c \
+ #
+ $(srcdir)/../../move-if-change tmp-itable.h itable.h
+ $(srcdir)/../../move-if-change tmp-itable.c itable.c
+ touch tmp-itable-multi
+ tmp-run-multi: $(srcdir)/m16run.c
+ for t in $(SIM_MULTI_CONFIGS); do \
+ case $${t} in \
+ *:*mips16*:*) \
+ m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
+ sed < $(srcdir)/m16run.c > tmp-run \
+ -e "s/^sim_/m16$${m}_/" \
+ -e "s/m16_/m16$${m}_/" \
+ -e "s/m32_/m32$${m}_/" ; \
+ $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
+ esac \
+ done
+ touch tmp-run-multi
+
clean-extra:
rm -f $(BUILT_SRC_FROM_GEN)
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f $(BUILT_SRC_FROM_M16)
+ rm -f $(BUILT_SRC_FROM_MULTI)
rm -f tmp-*
rm -f m16*.o m32*.o itable*.o
Index: mips/sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.h,v
retrieving revision 1.23
diff -c -d -p -r1.23 sim-main.h
*** mips/sim-main.h 14 Jun 2002 18:49:09 -0000 1.23
--- mips/sim-main.h 9 Oct 2002 09:14:27 -0000
*************** mips_core_signal ((SD), (CPU), (CIA), (M
*** 41,47 ****
typedef address_word sim_cia;
#include "sim-base.h"
!
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
--- 41,47 ----
typedef address_word sim_cia;
#include "sim-base.h"
! #include "bfd.h"
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
Index: mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.49
diff -c -d -p -r1.49 mips.igen
*** mips/mips.igen 31 Jul 2002 05:44:54 -0000 1.49
--- mips/mips.igen 9 Oct 2002 09:14:27 -0000
***************
*** 55,61 ****
--- 55,64 ----
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
+ :model:::vr4120:mips4120:
:model:::vr5000:mips5000:
+ :model:::vr5400:mips5400:
+ :model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
***************
*** 229,234 ****
--- 232,240 ----
:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
{
+ /* There are no timing requirements in vr5500 code. */
+ if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_mips5500)
+ return 1;
if (history->mf.timestamp + 3 > time)
{
sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
***************
*** 1010,1015 ****
--- 1016,1022 ----
"clo r<RD>, r<RS>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
***************
*** 1034,1039 ****
--- 1041,1047 ----
"clz r<RD>, r<RS>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
***************
*** 1143,1148 ****
--- 1151,1157 ----
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
+ *vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
***************
*** 1166,1171 ****
--- 1175,1181 ----
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
+ *vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
***************
*** 2189,2194 ****
--- 2199,2205 ----
"madd r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 2208,2213 ****
--- 2219,2225 ----
"maddu r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 2312,2317 ****
--- 2324,2330 ----
"msub r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 2331,2336 ****
--- 2344,2350 ----
"msubu r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
***************
*** 2388,2393 ****
--- 2402,2408 ----
"mul r<RD>, r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 prod;
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Index: mips/vr.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/vr.igen,v
retrieving revision 1.1.1.1
diff -c -d -p -r1.1.1.1 vr.igen
*** mips/vr.igen 16 Apr 1999 01:35:07 -0000 1.1.1.1
--- mips/vr.igen 9 Oct 2002 09:14:27 -0000
***************
*** 3,78 ****
// NEC specific instructions
//
! // Integer Instructions
! // --------------------
! //
! // MulAcc is the Multiply Accumulator.
! // This register is mapped on the the HI and LO registers.
! // Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
! // Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
! :function:::unsigned64:MulAcc:
! *vr4100:
{
! unsigned64 result = U8_4 (HI, LO);
! return result;
}
! :function:::void:SET_MulAcc:unsigned64 value
! *vr4100:
{
! /* 64 bit specific */
! *AL4_8 (&HI) = VH4_8 (value);
! *AL4_8 (&LO) = VL4_8 (value);
}
! :function:::signed64:SignedMultiply:signed32 l, signed32 r
! *vr4100:
{
! signed64 result = (signed64) l * (signed64) r;
return result;
}
! :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
! *vr4100:
{
! unsigned64 result = (unsigned64) l * (unsigned64) r;
return result;
}
! :function:::unsigned64:Low32Bits:unsigned64 value
*vr4100:
{
! unsigned64 result = (signed64) (signed32) VL4_8 (value);
! return result;
}
! :function:::unsigned64:High32Bits:unsigned64 value
*vr4100:
{
! unsigned64 result = (signed64) (signed32) VH4_8 (value);
! return result;
}
! // Multiply, Accumulate
! 000000,5.RS,5.RT,00000,00000,101000::64::MAC
! "mac r<RS>, r<RT>"
! *vr4100:
{
! SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
}
! // D-Multiply, Accumulate
! 000000,5.RS,5.RT,00000,00000,101001::64::DMAC
! "dmac r<RS>, r<RT>"
! *vr4100:
{
! LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
}
--- 3,323 ----
// NEC specific instructions
//
! :%s::::MFHI:int hi
! {
! return hi ? "hi" : "";
! }
+ :%s::::SAT:int s
+ {
+ return s ? "s" : "";
+ }
! :%s::::UNS:int u
{
! return u ? "u" : "";
}
! // Simulate the various kinds of multiply and multiply-accumulate instructions.
! // Perform an operation of the form:
! //
! // LHS (+/-) GPR[RS] * GPR[RT]
! //
! // and store it in the 64-bit accumulator. Optionally copy either LO or
! // HI into a general purpose register.
! //
! // - RD is the destination register of the LO or HI move
! // - RS are RT are the multiplication source registers
! // - ACCUMULATE_P is true if LHS should be the value of the 64-bit accumulator,
! // false if it should be 0.
! // - STORE_HI_P is true if HI should be stored in RD, false if LO should be.
! // - UNSIGNED_P is true if the operation should be unsigned.
! // - SATURATE_P is true if the result should be saturated to a 32-bit value.
! // - SUBTRACT_P is true if the right hand side should be subtraced from LHS,
! // false if it should be added.
! // - SHORT_P is true if RS and RT must be 16-bit numbers.
! // - DOUBLE_P is true if the 64-bit accumulator is in LO, false it is a
! // concatenation of the low 32 bits of HI and LO.
! :function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p
{
! unsigned64 lhs, x, y, xcut, ycut, product, result;
!
! check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
!
! lhs = (!accumulate_p ? 0 : double_p ? LO : U8_4 (HI, LO));
! x = GPR[rs];
! y = GPR[rt];
!
! /* Work out the canonical form of X and Y from their significant bits. */
! if (!short_p)
! {
! /* Normal sign-extension rule for 32-bit operands. */
! xcut = EXTEND32 (x);
! ycut = EXTEND32 (y);
! }
! else if (unsigned_p)
! {
! /* Operands must be zero-extended 16-bit numbers. */
! xcut = x & 0xffff;
! ycut = y & 0xffff;
! }
! else
! {
! /* Likewise but sign-extended. */
! xcut = EXTEND16 (x);
! ycut = EXTEND16 (y);
! }
! if (x != xcut || y != ycut)
! sim_engine_abort (SD, CPU, CIA,
! "invalid multiplication operand at 0x%08lx\n",
! (long) CIA);
!
! TRACE_ALU_INPUT2 (x, y);
! product = (unsigned_p ? x * y : EXTEND32 (x) * EXTEND32 (y));
! result = (subtract_p ? lhs - product : lhs + product);
! if (saturate_p)
! {
! /* Saturate the result to 32 bits. An unsigned, unsaturated
! result is zero-extended to 64 bits, but unsigned overflow
! causes all 64 bits to be set. */
! if (!unsigned_p && (unsigned64) EXTEND32 (result) != result)
! result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff);
! else if (unsigned_p && (result >> 32) != 0)
! result = (unsigned64) 0 - 1;
! }
! TRACE_ALU_RESULT (result);
!
! if (double_p)
! LO = result;
! else
! {
! LO = EXTEND32 (result);
! HI = EXTEND32 (VH4_8 (result));
! }
! if (rd != 0)
! GPR[rd] = store_hi_p ? HI : LO;
}
! // 32-bit rotate right of X by Y bits.
! :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
! *vr5400:
! *vr5500:
{
! unsigned64 result;
!
! y &= 31;
! TRACE_ALU_INPUT2 (x, y);
! result = EXTEND32 (ROTR32 (x, y));
! TRACE_ALU_RESULT (result);
return result;
}
! // Likewise 64-bit
! :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
! *vr5400:
! *vr5500:
{
! unsigned64 result;
!
! y &= 63;
! TRACE_ALU_INPUT2 (x, y);
! result = ROTR64 (x, y);
! TRACE_ALU_RESULT (result);
return result;
}
!
! // VR4100 instructions.
!
! 000000,5.RS,5.RT,00000,00000,101000::32::MADD16
! "madd16 r<RS>, r<RT>"
*vr4100:
{
! do_vr_mul_op (SD_, 0, RS, RT,
! 1 /* accumulate */,
! 0 /* store in LO */,
! 0 /* signed arithmetic */,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 1 /* short */,
! 0 /* single */);
}
! 000000,5.RS,5.RT,00000,00000,101001::64::DMADD16
! "dmadd16 r<RS>, r<RT>"
*vr4100:
{
! do_vr_mul_op (SD_, 0, RS, RT,
! 1 /* accumulate */,
! 0 /* store in LO */,
! 0 /* signed arithmetic */,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 1 /* short */,
! 1 /* double */);
}
! // VR4120 and VR4130 instructions.
!
! 000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101001::64::DMACC
! "dmacc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
! *vr4120:
{
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS, SAT,
! 0 /* don't subtract */,
! SAT /* short */,
! 1 /* double */);
! }
!
! 000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101000::32::MACC_4120
! "macc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
! *vr4120:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS, SAT,
! 0 /* don't subtract */,
! SAT /* short */,
! 0 /* single */);
}
! // VR5400 and VR5500 instructions.
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,001,01100,1.UNS::32::MUL
! "mul%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
{
! do_vr_mul_op (SD_, RD, RS, RT,
! 0 /* don't accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,011,01100,1.UNS::32::MULS
! "muls%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 0 /* don't accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 1 /* subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,101,01100,1.UNS::32::MACC_5xxx
! "macc%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,111,01100,1.UNS::32::MSAC
! "msac%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 1 /* subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
! "ror r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
! }
!
! 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
! "rorv r<RD>, r<RT>, r<RS>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
! "dror r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
! "dror32 r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
! }
!
! 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
! "drorv r<RD>, r<RT>, r<RS>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
! }
!
! 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1
! "luxc1 f<FD>, r<INDEX>(r<BASE>)"
! *vr5500:
! {
! check_fpu (SD_);
! COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD,
! (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0));
! }
!
! 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64::SUXC1
! "suxc1 f<FS>, r<INDEX>(r<BASE>)"
! *vr5500:
! {
! check_fpu (SD_);
! do_store (SD_, AccessLength_DOUBLEWORD,
! (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0,
! COP_SD (1, FS));
}
+ 010000,1,19.*,100000:COP0:32::WAIT
+ "wait"
+ *vr5500:
+
+ 011100,00000,5.RT,5.DR,00000,111101:SPECIAL:64::MFDR
+ "mfdr r<RT>, r<DR>"
+ *vr5400:
+ *vr5500:
+ 011100,00100,5.RT,5.DR,00000,111101:SPECIAL:64::MTDR
+ "mtdr r<RT>, r<DR>"
+ *vr5400:
+ *vr5500:
+ 011100,00000,00000,00000,00000,111110:SPECIAL:64::DRET
+ "dret"
+ *vr5400:
+ *vr5500:
*** /dev/null Tue Nov 14 21:44:43 2000
--- mips/multi_run.c Tue Oct 8 14:43:29 2002
***************
*** 0 ****
--- 1,43 ----
+ /* Main entry point for MULTI simulators.
+ Copyright (C) 2002 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ */
+
+ #include "sim-main.h"
+ #include "multi-include.h"
+
+ #define SD sd
+ #define CPU cpu
+
+ void
+ sim_engine_run (SIM_DESC sd,
+ int next_cpu_nr,
+ int nr_cpus,
+ int signal) /* ignore */
+ {
+ int mach, i;
+
+ if (STATE_ARCHITECTURE (sd) == NULL)
+ mach = 0;
+ else
+ mach = STATE_ARCHITECTURE (sd)->mach;
+
+ switch (mach)
+ {
+ #include "multi-switch.c"
+ }
+ }
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-10-09 7:14 ` Richard Sandiford
@ 2002-10-22 15:27 ` cgd
2002-11-05 8:20 ` Richard Sandiford
0 siblings, 1 reply; 22+ messages in thread
From: cgd @ 2002-10-22 15:27 UTC (permalink / raw)
To: Richard Sandiford; +Cc: gdb-patches
At 09 Oct 2002 15:14:43 +0100, Richard Sandiford wrote:
> Thanks for the review.
That's what I'm here for. 8-) (Sorry for taking so long to get to
this, but, as i mentioned in private mail before I left, I was out of
the office. 8-)
> Good catch. I checked that vr5000 implied mipsIV, but not the
> other way around (duh!).
(I dunno whether you were using the horrible compare_igen_models
script or not, but it does both ways for you and is ... much easier
than hand inspection. 8-)
> Yeah. I don't understand why, really, since the vr41xx processors don't
> have an FPU. Maybe the target environment was assumed to provide an
> emulator or something? But key instructions (like bc1f and bc1t ;-)
> are missing, so very little FP code is going to work.
I don't know, the code predates my time here. 8-)
FWIW, my personal preference is to have a simulator which is good
enough to act like real hardware, then, if necessary and appropriate
(i.e., trying to simulate a firmware or other SW environment which has
an emulator) do actual emulation.
(One implication of this is that a 'good' emulation for a particular
processor might well trap on certain FP cases unimplemented in HW.)
There are both plusses and minuses to this approach, of course.
> > There are a couple of specific things that would be nice if you could
> > arrange in follow-on patches, in addition to what you describe above:
> >
> > * it would be good if things like vr_run.c could be automatically
> > generated.
>
> OK. Guilt at my earlier lameness forced me to give this a go.
> New version attached. Not pretty (and I didn't use awk ;-) but
> it should reduce the amount of cut&paste if other targets use
> MULTI. I've also removed the need to define sim_multi_filter
> and sim_multi_machine, since igen can cope with the same machine
> & filter being given twice.
Heh. (no awk?! what will we do?!)
> > There is an annoying interaction between multi-arching a sim and using
> > STATE_ARCHITECTURE (SD)->mach: e.g. if you have the thing above where
> > you check bfd_mach_mips5500, if mips5500 is the 'default' for your sim
> > (i.e., catches unknown machine types), that check will fail.
> >
> > Really, we need to be sure to check and, if necessary, set 'mach' to a
> > default value when it is set.
>
> Where do you think this should happen? In sim_engine_run()?
To be honest, I'm not really sure. However, I do believe that that is
too late. 8-)
(The problem is that simulator machine state initialization has
happened by the time you invoke sim_engine_run(), and that may have to
differe depending on the type of machine you're simulating.)
Ideally what you want is a replacement for
STATE_ARCHITECTURE (sd) ? STATE_ARCHITECTURE (sd)->mach : 0
that does the correct default handling, but is very very fast. Alas,
I don't know that that's possible. 8-)
Probably the right thing is to just turn it into a function call if
doing MULTI, else have it #defined to the correct specific value if
not MULTI (i.e., a single-arch sim).
People running the GCC test suite in a MULTI sim don't care if they're
getting 200k insns/sec or 1m insns/sec... 8-)
On the other hand, people who want a really fast sim will build one
that targets a single CPU, which will get the #define which also
allows additional optimizations (code to be elided). (Having been in
the position of booting firmware under a sim, then booting OSes under
said firmware, I can say that I like the fastest sim possible
sometimes. 8-)
Thoughts?
> + # The MULTI generator can combine several simulation engines into
> + # one executable. A configuration which uses the MULTI should
> + # set ${sim_multi_arch_configs} to the list of engines to build.
> + # Each space-separated entry has the form NAME:MACHINE:FILTER@ARCHS,
> + # where:
> + #
> + # - NAME is a C-compatible prefix for the engine,
> + # - MACHINE is a -M argument,
> + # - FILTER is a -F argument, and
> + # - ARCHS is a comma-separated list of bfd machines that the
> + # simulator can run.
> + #
> + # Each entry will have a separate simulation engine whose prefix is
> + # m32<NAME>. If the machine list includes "mips16", there will also
> + # be a mips16 engine, prefix m16<NAME>. The mips16 engine will be
> + # generated using the same machine list as the 32-bit version,
> + # but the filter will be "16" instead of FILTER.
> + #
> + # The simulator compares the bfd mach against ARCHS to decide
> + # which engine to use. Entries in ARCHS can be a bfd_mach_mips*
> + # value with "bfd_mach_mips" removed, or the special string
> + # "default" to indicate that a particular engine should be
> + # the default.
I believe there _must_ be one default entry, and this should be
checked for in the code too. What do you think?
Why use "@" rather than another :... makes the seds slightly easier,
that it?
Suggest either:
* archs have only bfd_mach_ prepended i.e., mips4111, mips_sb1, etc.
The current method is ... not so pretty for archs whose bfd define
isn't a number. This makes the specifictions a bit longer, but IMO
that's not biggie.
* more special casing, e.g.:
[0-9]* add bfd_mach_mips
[a-z]* add bfd_mach_mips_
8-) This could get out of hand, though.
(personally, my feeling is that adding even more defines of the form
bfd_mach_mipsNNNN is ... not the right thing. It should be
bfd_mach_mips_vendnum
^^^^^^^ vendor letter/number combo, e.g. sb1, vrNNNN
^^^^ ARCHITECTURE!!!
or whatever... but that's water under the bridge.)
> + if test ${sim_gen} = MULTI; then
> + rm -f multi-include.h multi-switch.c
> + sim_multi_flags=
> + sim_multi_obj=multi_run.o
> + for fc in ${sim_multi_arch_configs}; do
> + c=`echo ${fc} | sed 's/@.*//'`
> + archs=`echo ${fc} | sed 's/.*@//'`
> + name=`echo ${c} | sed 's/:.*//'`
> + m=`echo ${c} | sed 's/.*:\(.*\):.*/\1/'`
> + f=`echo ${c} | sed 's/.*://'`
> + sim_multi_flags="${sim_multi_flags} -F ${f} -M ${m}"
> + case $c in
> + *:*mips16*:*)
> + ws="m32 m16"
> + sim_multi_src="${sim_multi_src} m16${name}_run.c"
> + sim_multi_obj="${sim_multi_obj} m16${name}_run.o"
> + sim_multi_flags="${sim_multi_flags} -F 16"
> + ;;
> + *)
> + ws=m32
> + ;;
> + esac
> + for w in ${ws}; do
> + for base in engine icache idecode model semantics support; do
> + sim_multi_src="${sim_multi_src} ${w}${name}_${base}.c"
> + sim_multi_src="${sim_multi_src} ${w}${name}_${base}.h"
> + sim_multi_obj="${sim_multi_obj} ${w}${name}_${base}.o"
> + done
> + sim_multi_configs="${sim_multi_configs} ${w}${c}"
> + done
> + echo "#include \"${w}${name}_engine.h\"" >> multi-include.h
> + for a in `echo $archs | sed 's/,/ /g'`; do
> + case $a in
> + default) echo "default:" >> multi-switch.c ;;
> + *) echo "case bfd_mach_mips$a:" >> multi-switch.c ;;
> + esac
> + done
> + echo " ${w}${name}_engine_run (sd, next_cpu_nr, nr_cpus, signal);" \
> + >> multi-switch.c
> + echo " break;" >> multi-switch.c
> + done
> + else
> + # For clean-extra
> + sim_multi_src=doesnt-exist.c
> + fi
> sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
> sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}"
> AC_SUBST(sim_igen_flags)
> AC_SUBST(sim_m16_flags)
> AC_SUBST(sim_gen)
> + AC_SUBST(sim_multi_flags)
> + AC_SUBST(sim_multi_configs)
> + AC_SUBST(sim_multi_src)
> + AC_SUBST(sim_multi_obj)
err, shouldn't multi-switch.c be cleaned somehow (during distclean, i
guess, since it's config-generated).
Also, shouldn't multi-run.o depend on multi-switch.c so that the right
thing happens after re-config?
(obviously, if there's a fn to pick the right machine type, the case
statement in the engine generated above doesn't need to include the
default, that fn does.)
chris
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-10-22 15:27 ` cgd
@ 2002-11-05 8:20 ` Richard Sandiford
2002-11-06 10:44 ` cgd
2002-11-06 14:46 ` cgd
0 siblings, 2 replies; 22+ messages in thread
From: Richard Sandiford @ 2002-11-05 8:20 UTC (permalink / raw)
To: cgd; +Cc: gdb-patches
cgd@broadcom.com writes:
> Ideally what you want is a replacement for
>
> STATE_ARCHITECTURE (sd) ? STATE_ARCHITECTURE (sd)->mach : 0
>
> that does the correct default handling, but is very very fast. Alas,
> I don't know that that's possible. 8-)
>
> Probably the right thing is to just turn it into a function call if
> doing MULTI, else have it #defined to the correct specific value if
> not MULTI (i.e., a single-arch sim).
>
> People running the GCC test suite in a MULTI sim don't care if they're
> getting 200k insns/sec or 1m insns/sec... 8-)
OK, I've replaced the use of STATE_ARCHITECTURE with a macro
MIPS_BFD_MACH. It will be a constant for most configurations,
but the MULTI version checks STATE_ARCHITECTURE instead.
At the moment, the macro is zero for all non-MULTI targets.
It would be trivial to set it to something else in configure,
but no target needs to do that yet, and I'd rather not add
dead code.
> I believe there _must_ be one default entry, and this should be
> checked for in the code too. What do you think?
OK, I've done that. The default is now under the control of
a separate variable to make it easier to check.
> Why use "@" rather than another :... makes the seds slightly easier,
> that it?
Main reason was to separate the bit that got passed to "make" from
the rest. I don't think it helped much though. I agree it'd more
consistent to use ':'s all the way, so... fixed.
> Suggest either:
>
> * archs have only bfd_mach_ prepended i.e., mips4111, mips_sb1, etc.
OK, changed like that.
> err, shouldn't multi-switch.c be cleaned somehow (during distclean, i
> guess, since it's config-generated).
Fixed.
> Also, shouldn't multi-run.o depend on multi-switch.c so that the right
> thing happens after re-config?
Also fixed.
So, changes in this version:
- use more igen-like syntax for ${sim_multi_configs} (no '@'s)
- set the default using a separate variable, ${sim_multi_default}
- check that both the above vars are defined
- check that ${sim_multi_configs} mentions ${sim_multi_default}
- clean up the shell code a bit (better names, more comments ;)
- remove the generated files in distclean
- add a make dependency for multi-run.o
- add MIPS_BFD_MACH
- use it in check_mf_cycles() and multi-run.c
Tested in the same way as before. Also:
- built a mips64-elf simulator, just in case
- tried triggering the two new error messages
- did a make distclean
Please install if OK.
Richard
common/
* Make-common.in (SIM_EXTRA_DISTCLEAN): New macro.
(distclean): Depend on it.
igen/
* gen-engine.c (print_engine_issue_prefix_hook): Don't add the
global prefix to ENGINE_ISSUE_PREFIX_HOOK.
(print_engine_issue_postfix_hook): Likewise ENGINE_ISSUE_POSTFIX_HOOK.
mips/
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_CONFIGS): New variables.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New dependencies.
(tmp-multi): Combine them.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_BFD_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(check_mf_cycles): Don't enforce mflo and mfhi separation
in vr5500 code.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
* multi-run.c: New file.
Index: common/Make-common.in
===================================================================
RCS file: /cvs/src/src/sim/common/Make-common.in,v
retrieving revision 1.9
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.9 Make-common.in
*** common/Make-common.in 29 Aug 2002 19:27:52 -0000 1.9
--- common/Make-common.in 5 Nov 2002 16:14:27 -0000
*************** # Dependency of `install' to install any
*** 134,139 ****
--- 134,141 ----
SIM_EXTRA_INSTALL =
# Dependency of `clean' to clean any extra files.
SIM_EXTRA_CLEAN =
+ # Likewise `distclean'
+ SIM_EXTRA_DISTCLEAN =
# Every time a new general purpose source file was added every target's
# Makefile.in needed to be updated to include the file in SIM_OBJS.
*************** clean: $(SIM_EXTRA_CLEAN)
*** 622,628 ****
fi
rm -f tmp-mloop.hin tmp-mloop.h tmp-mloop.cin tmp-mloop.c
! distclean mostlyclean maintainer-clean realclean: clean
rm -f TAGS
rm -f Makefile config.cache config.log config.status .gdbinit
rm -f tconfig.h config.h stamp-h
--- 624,630 ----
fi
rm -f tmp-mloop.hin tmp-mloop.h tmp-mloop.cin tmp-mloop.c
! distclean mostlyclean maintainer-clean realclean: clean $(SIM_EXTRA_DISTCLEAN)
rm -f TAGS
rm -f Makefile config.cache config.log config.status .gdbinit
rm -f tconfig.h config.h stamp-h
Index: igen/gen-engine.c
===================================================================
RCS file: /cvs/src/src/sim/igen/gen-engine.c,v
retrieving revision 1.2
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.2 gen-engine.c
*** igen/gen-engine.c 3 Jun 2002 16:04:31 -0000 1.2
--- igen/gen-engine.c 5 Nov 2002 16:14:27 -0000
*************** print_engine_issue_prefix_hook (lf *file
*** 41,50 ****
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (%sENGINE_ISSUE_PREFIX_HOOK)\n",
! options.module.global.prefix.l);
! lf_printf (file, "%sENGINE_ISSUE_PREFIX_HOOK();\n",
! options.module.global.prefix.l);
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
--- 41,48 ----
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (ENGINE_ISSUE_PREFIX_HOOK)\n");
! lf_printf (file, "ENGINE_ISSUE_PREFIX_HOOK();\n");
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
*************** print_engine_issue_postfix_hook (lf *fil
*** 55,64 ****
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (%sENGINE_ISSUE_POSTFIX_HOOK)\n",
! options.module.global.prefix.l);
! lf_printf (file, "%sENGINE_ISSUE_POSTFIX_HOOK();\n",
! options.module.global.prefix.l);
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
--- 53,60 ----
{
lf_printf (file, "\n");
lf_indent_suppress (file);
! lf_printf (file, "#if defined (ENGINE_ISSUE_POSTFIX_HOOK)\n");
! lf_printf (file, "ENGINE_ISSUE_POSTFIX_HOOK();\n");
lf_indent_suppress (file);
lf_printf (file, "#endif\n");
lf_printf (file, "\n");
Index: mips/configure.in
===================================================================
RCS file: /cvs/src/src/sim/mips/configure.in,v
retrieving revision 1.4
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.4 configure.in
*** mips/configure.in 14 Jun 2002 18:49:09 -0000 1.4
--- mips/configure.in 5 Nov 2002 16:14:27 -0000
*************** # the value of {STATE,CPU}_ARCHITECTURE
*** 18,23 ****
--- 18,24 ----
# in question.
#
case "${target}" in
+ mips64vr*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
mips*tx39*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
mipsisa32*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mipsisa64*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
*************** case "${target}" in
*** 117,122 ****
--- 118,133 ----
sim_igen_filter="32,64,f"
sim_m16_filter="16"
;;
+ mips64vr-*-* | mips64vrel-*-*)
+ sim_gen=MULTI
+ sim_multi_configs="\
+ vr4100:mipsIII,mips16,vr4100:32,64:mips4100,mips4111\
+ vr4120:mipsIII,mips16,vr4120:32,64:mips4120\
+ vr5000:mipsIV:32,64,f:mips4300,mips5000\
+ vr5400:mipsIV,vr5400:32,64,f:mips5400\
+ vr5500:mipsIV,vr5500:32,64,f:mips5500"
+ sim_multi_default=mips5000
+ ;;
mips64*-*-*) sim_igen_filter="32,64,f"
sim_gen=IGEN
;;
*************** case "${target}" in
*** 146,156 ****
--- 157,290 ----
sim_igen_filter="32,f"
;;
esac
+
+ # The MULTI generator can combine several simulation engines into one.
+ # executable. A configuration which uses the MULTI should set two
+ # variables: ${sim_multi_configs} and ${sim_multi_default}.
+ #
+ # ${sim_multi_configs} is the list of engines to build. Each
+ # space-separated entry has the form NAME:MACHINE:FILTER:BFDMACHS,
+ # where:
+ #
+ # - NAME is a C-compatible prefix for the engine,
+ # - MACHINE is a -M argument,
+ # - FILTER is a -F argument, and
+ # - BFDMACHS is a comma-separated list of bfd machines that the
+ # simulator can run.
+ #
+ # Each entry will have a separate simulation engine whose prefix is
+ # m32<NAME>. If the machine list includes "mips16", there will also
+ # be a mips16 engine, prefix m16<NAME>. The mips16 engine will be
+ # generated using the same machine list as the 32-bit version,
+ # but the filter will be "16" instead of FILTER.
+ #
+ # The simulator compares the bfd mach against BFDMACHS to decide
+ # which engine to use. Entries in BFDMACHS should be bfd_mach
+ # values with "bfd_mach_" removed. ${sim_multi_default} says
+ # which entry should be the default.
+ if test ${sim_gen} = MULTI; then
+
+ # Simple sanity check.
+ if test -z "${sim_multi_configs}" || test -z "${sim_multi_default}"; then
+ AC_MSG_ERROR(Error in configure.in: MULTI simulator not set up correctly)
+ fi
+
+ # Start in a known state.
+ rm -f multi-include.h multi-switch.c
+ sim_multi_flags=
+ sim_multi_src=
+ sim_multi_obj=multi-run.o
+ sim_multi_igen_configs=
+ sim_seen_default=no
+
+ for fc in ${sim_multi_configs}; do
+
+ # Split up the entry. ${c} contains the first three elements.
+ # Note: outer sqaure brackets are m4 quotes.
+ c=`echo ${fc} | sed ['s/:[^:]*$//']`
+ bfdmachs=`echo ${fc} | sed 's/.*://'`
+ name=`echo ${c} | sed 's/:.*//'`
+ machine=`echo ${c} | sed 's/.*:\(.*\):.*/\1/'`
+ filter=`echo ${c} | sed 's/.*://'`
+
+ # Build the following lists:
+ #
+ # sim_multi_flags: all -M and -F flags used by the simulator
+ # sim_multi_src: all makefile-generated source files
+ # sim_multi_obj: the objects for ${sim_multi_src}
+ # sim_multi_igen_configs: igen configuration strings.
+ #
+ # Each entry in ${sim_multi_igen_configs} is a prefix (m32
+ # or m16) followed by the NAME, MACHINE and FILTER part of
+ # the ${sim_multi_configs} entry.
+ sim_multi_flags="${sim_multi_flags} -F ${filter} -M ${machine}"
+
+ # Check whether mips16 handling is needed.
+ case ${c} in
+ *:*mips16*:*)
+ # Run igen twice, once for normal mode and once for mips16.
+ ws="m32 m16"
+
+ # The top-level function for the mips16 simulator is
+ # in a file m16${name}_run.c, generated by the
+ # tmp-run-multi Makefile rule.
+ sim_multi_src="${sim_multi_src} m16${name}_run.c"
+ sim_multi_obj="${sim_multi_obj} m16${name}_run.o"
+ sim_multi_flags="${sim_multi_flags} -F 16"
+ ;;
+ *)
+ ws=m32
+ ;;
+ esac
+
+ # Now add the list of igen-generated files to ${sim_multi_src}
+ # and ${sim_multi_obj}.
+ for w in ${ws}; do
+ for base in engine icache idecode model semantics support; do
+ sim_multi_src="${sim_multi_src} ${w}${name}_${base}.c"
+ sim_multi_src="${sim_multi_src} ${w}${name}_${base}.h"
+ sim_multi_obj="${sim_multi_obj} ${w}${name}_${base}.o"
+ done
+ sim_multi_igen_configs="${sim_multi_igen_configs} ${w}${c}"
+ done
+
+ # Add an include for the engine.h file. This file declares the
+ # top-level foo_engine_run() function.
+ echo "#include \"${w}${name}_engine.h\"" >> multi-include.h
+
+ # Add case statements for this engine.
+ for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
+ echo "case bfd_mach_${mach}:" >> multi-switch.c
+ if test ${mach} = ${sim_multi_default}; then
+ echo "default:" >> multi-switch.c
+ sim_seen_default=yes
+ fi
+ done
+ echo " ${w}${name}_engine_run (sd, next_cpu_nr, nr_cpus, signal);" \
+ >> multi-switch.c
+ echo " break;" >> multi-switch.c
+ done
+
+ # Check whether we added a 'default:' label.
+ if test ${sim_seen_default} = no; then
+ AC_MSG_ERROR(Error in configure.in: \${sim_multi_configs} doesn't have an entry for \${sim_multi_default})
+ fi
+
+ # Used to define MIPS_BFD_MACH.
+ SIM_SUBTARGET="$SIM_SUBTARGET -DMULTI_DEFAULT_BFD_MACH=bfd_mach_${sim_multi_default}"
+ else
+ # For clean-extra
+ sim_multi_src=doesnt-exist.c
+ fi
sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}"
AC_SUBST(sim_igen_flags)
AC_SUBST(sim_m16_flags)
AC_SUBST(sim_gen)
+ AC_SUBST(sim_multi_flags)
+ AC_SUBST(sim_multi_igen_configs)
+ AC_SUBST(sim_multi_src)
+ AC_SUBST(sim_multi_obj)
#
Index: mips/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mips/Makefile.in,v
retrieving revision 1.7
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.7 Makefile.in
*** mips/Makefile.in 14 Jun 2002 18:49:09 -0000 1.7
--- mips/Makefile.in 5 Nov 2002 16:14:27 -0000
*************** SIM_M16_OBJ = \
*** 33,38 ****
--- 33,39 ----
itable.o \
m16run.o \
+ SIM_MULTI_OBJ = itable.o @sim_multi_obj@
MIPS_EXTRA_OBJS = @mips_extra_objs@
MIPS_EXTRA_LIBS = @mips_extra_libs@
*************** SIM_SUBTARGET=@SIM_SUBTARGET@
*** 57,62 ****
--- 58,64 ----
SIM_EXTRA_CFLAGS = $(SIM_SUBTARGET)
SIM_EXTRA_CLEAN = clean-extra
+ SIM_EXTRA_DISTCLEAN = distclean-extra
SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
*************** cp1.o: $(srcdir)/cp1.c config.h sim-main
*** 74,79 ****
--- 76,83 ----
mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
+ multi-run.o: multi-include.h multi-switch.c tmp-mach-multi
+
../igen/igen:
cd ../igen && $(MAKE)
*************** BUILT_SRC_FROM_GEN = \
*** 98,103 ****
--- 102,108 ----
SIM_IGEN_ALL = tmp-igen
SIM_M16_ALL = tmp-m16
+ SIM_MULTI_ALL = tmp-multi
$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
*************** tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen
*** 291,300 ****
--- 296,394 ----
touch tmp-m16
+ BUILT_SRC_FROM_MULTI = @sim_multi_src@
+ SIM_MULTI_IGEN_CONFIGS = @sim_multi_igen_configs@
+
+ $(BUILT_SRC_FROM_MULTI): tmp-multi
+ tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi targ-vals.h
+ tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+ for t in $(SIM_MULTI_IGEN_CONFIGS); do \
+ p=`echo $${t} | sed -e 's/:.*//'` ; \
+ m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
+ f=`echo $${t} | sed -e 's/.*://'` ; \
+ case $${p} in \
+ m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
+ *) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
+ esac; \
+ ../igen/igen \
+ $(IGEN_TRACE) \
+ $${e} \
+ -I $(srcdir) \
+ -Werror \
+ -Wnodiscard \
+ -N 0 \
+ -M $${m} \
+ -G gen-direct-access \
+ -G gen-zero-r0 \
+ -i $(IGEN_INSN) \
+ -P $${p}_ \
+ -x \
+ -n $${p}_icache.h -hc tmp-icache.h \
+ -n $${p}_icache.c -c tmp-icache.c \
+ -n $${p}_semantics.h -hs tmp-semantics.h \
+ -n $${p}_semantics.c -s tmp-semantics.c \
+ -n $${p}_idecode.h -hd tmp-idecode.h \
+ -n $${p}_idecode.c -d tmp-idecode.c \
+ -n $${p}_model.h -hm tmp-model.h \
+ -n $${p}_model.c -m tmp-model.c \
+ -n $${p}_support.h -hf tmp-support.h \
+ -n $${p}_support.c -f tmp-support.c \
+ -n $${p}_engine.h -he tmp-engine.h \
+ -n $${p}_engine.c -e tmp-engine.c \
+ ; \
+ $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
+ $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
+ $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
+ $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
+ $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
+ $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
+ $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
+ $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
+ $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
+ $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
+ $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
+ $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
+ done
+ touch tmp-mach-multi
+ tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+ ../igen/igen \
+ $(IGEN_TRACE) \
+ -I $(srcdir) \
+ -Werror \
+ -Wnodiscard \
+ -Wnowidth \
+ -N 0 \
+ @sim_multi_flags@ \
+ -G gen-direct-access \
+ -G gen-zero-r0 \
+ -i $(IGEN_INSN) \
+ -n itable.h -ht tmp-itable.h \
+ -n itable.c -t tmp-itable.c \
+ #
+ $(srcdir)/../../move-if-change tmp-itable.h itable.h
+ $(srcdir)/../../move-if-change tmp-itable.c itable.c
+ touch tmp-itable-multi
+ tmp-run-multi: $(srcdir)/m16run.c
+ for t in $(SIM_MULTI_IGEN_CONFIGS); do \
+ case $${t} in \
+ *:*mips16*:*) \
+ m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
+ sed < $(srcdir)/m16run.c > tmp-run \
+ -e "s/^sim_/m16$${m}_/" \
+ -e "s/m16_/m16$${m}_/" \
+ -e "s/m32_/m32$${m}_/" ; \
+ $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
+ esac \
+ done
+ touch tmp-run-multi
+
clean-extra:
rm -f $(BUILT_SRC_FROM_GEN)
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f $(BUILT_SRC_FROM_M16)
+ rm -f $(BUILT_SRC_FROM_MULTI)
rm -f tmp-*
rm -f m16*.o m32*.o itable*.o
+ distclean-extra:
+ rm -f multi-include.h multi-switch.c
Index: mips/sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.h,v
retrieving revision 1.23
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.23 sim-main.h
*** mips/sim-main.h 14 Jun 2002 18:49:09 -0000 1.23
--- mips/sim-main.h 5 Nov 2002 16:14:27 -0000
*************** #include "sim-basics.h"
*** 41,47 ****
typedef address_word sim_cia;
#include "sim-base.h"
!
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
--- 41,47 ----
typedef address_word sim_cia;
#include "sim-base.h"
! #include "bfd.h"
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
*************** void mips_cpu_exception_trigger(SIM_DESC
*** 950,955 ****
--- 950,965 ----
void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
+ #ifdef MULTI_DEFAULT_BFD_MACH
+ #define MIPS_BFD_MACH(SD) \
+ (STATE_ARCHITECTURE (SD)->mach != 0 \
+ ? STATE_ARCHITECTURE (SD)->mach \
+ : MULTI_DEFAULT_BFD_MACH)
+ #endif
+
+ #ifndef MIPS_BFD_MACH
+ #define MIPS_BFD_MACH(SD) 0
+ #endif
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
#include "sim-main.c"
Index: mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.49
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.49 mips.igen
*** mips/mips.igen 31 Jul 2002 05:44:54 -0000 1.49
--- mips/mips.igen 5 Nov 2002 16:14:27 -0000
***************
*** 55,61 ****
--- 55,64 ----
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
+ :model:::vr4120:mips4120:
:model:::vr5000:mips5000:
+ :model:::vr5400:mips5400:
+ :model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
*************** #endif
*** 229,234 ****
--- 232,240 ----
:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
{
+ /* There are no timing requirements in vr5500 code. */
+ if (MIPS_BFD_MACH (SD) == bfd_mach_mips5500)
+ return 1;
if (history->mf.timestamp + 3 > time)
{
sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
*************** 011100,5.RS,5.RT,5.RD,00000,100001:SPECI
*** 1010,1015 ****
--- 1016,1022 ----
"clo r<RD>, r<RS>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
*************** 011100,5.RS,5.RT,5.RD,00000,100000:SPECI
*** 1034,1039 ****
--- 1041,1047 ----
"clz r<RD>, r<RS>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
*************** 000000,5.RS,5.RT,5.RD,00000,101101:SPECI
*** 1143,1148 ****
--- 1151,1157 ----
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
+ *vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
*************** 011100,5.RS,5.RT,5.RD,00000,100101:SPECI
*** 1166,1171 ****
--- 1175,1181 ----
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
+ *vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
*************** 011100,5.RS,5.RT,00000,00000,000000:SPEC
*** 2189,2194 ****
--- 2199,2205 ----
"madd r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
*************** 011100,5.RS,5.RT,00000,00000,000001:SPEC
*** 2208,2213 ****
--- 2219,2225 ----
"maddu r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
*************** 011100,5.RS,5.RT,00000,00000,000100:SPEC
*** 2312,2317 ****
--- 2324,2330 ----
"msub r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
*************** 011100,5.RS,5.RT,00000,00000,000101:SPEC
*** 2331,2336 ****
--- 2344,2350 ----
"msubu r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
*************** 011100,5.RS,5.RT,5.RD,00000,000010:SPECI
*** 2388,2393 ****
--- 2402,2408 ----
"mul r<RD>, r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 prod;
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Index: mips/vr.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/vr.igen,v
retrieving revision 1.1.1.1
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.1.1.1 vr.igen
*** mips/vr.igen 16 Apr 1999 01:35:07 -0000 1.1.1.1
--- mips/vr.igen 5 Nov 2002 16:14:27 -0000
***************
*** 3,78 ****
// NEC specific instructions
//
! // Integer Instructions
! // --------------------
! //
! // MulAcc is the Multiply Accumulator.
! // This register is mapped on the the HI and LO registers.
! // Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
! // Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
! :function:::unsigned64:MulAcc:
! *vr4100:
{
! unsigned64 result = U8_4 (HI, LO);
! return result;
}
! :function:::void:SET_MulAcc:unsigned64 value
! *vr4100:
{
! /* 64 bit specific */
! *AL4_8 (&HI) = VH4_8 (value);
! *AL4_8 (&LO) = VL4_8 (value);
}
! :function:::signed64:SignedMultiply:signed32 l, signed32 r
! *vr4100:
{
! signed64 result = (signed64) l * (signed64) r;
return result;
}
! :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
! *vr4100:
{
! unsigned64 result = (unsigned64) l * (unsigned64) r;
return result;
}
! :function:::unsigned64:Low32Bits:unsigned64 value
*vr4100:
{
! unsigned64 result = (signed64) (signed32) VL4_8 (value);
! return result;
}
! :function:::unsigned64:High32Bits:unsigned64 value
*vr4100:
{
! unsigned64 result = (signed64) (signed32) VH4_8 (value);
! return result;
}
! // Multiply, Accumulate
! 000000,5.RS,5.RT,00000,00000,101000::64::MAC
! "mac r<RS>, r<RT>"
! *vr4100:
{
! SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
}
! // D-Multiply, Accumulate
! 000000,5.RS,5.RT,00000,00000,101001::64::DMAC
! "dmac r<RS>, r<RT>"
! *vr4100:
{
! LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
}
--- 3,323 ----
// NEC specific instructions
//
! :%s::::MFHI:int hi
! {
! return hi ? "hi" : "";
! }
+ :%s::::SAT:int s
+ {
+ return s ? "s" : "";
+ }
! :%s::::UNS:int u
{
! return u ? "u" : "";
}
! // Simulate the various kinds of multiply and multiply-accumulate instructions.
! // Perform an operation of the form:
! //
! // LHS (+/-) GPR[RS] * GPR[RT]
! //
! // and store it in the 64-bit accumulator. Optionally copy either LO or
! // HI into a general purpose register.
! //
! // - RD is the destination register of the LO or HI move
! // - RS are RT are the multiplication source registers
! // - ACCUMULATE_P is true if LHS should be the value of the 64-bit accumulator,
! // false if it should be 0.
! // - STORE_HI_P is true if HI should be stored in RD, false if LO should be.
! // - UNSIGNED_P is true if the operation should be unsigned.
! // - SATURATE_P is true if the result should be saturated to a 32-bit value.
! // - SUBTRACT_P is true if the right hand side should be subtraced from LHS,
! // false if it should be added.
! // - SHORT_P is true if RS and RT must be 16-bit numbers.
! // - DOUBLE_P is true if the 64-bit accumulator is in LO, false it is a
! // concatenation of the low 32 bits of HI and LO.
! :function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p
{
! unsigned64 lhs, x, y, xcut, ycut, product, result;
!
! check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
!
! lhs = (!accumulate_p ? 0 : double_p ? LO : U8_4 (HI, LO));
! x = GPR[rs];
! y = GPR[rt];
!
! /* Work out the canonical form of X and Y from their significant bits. */
! if (!short_p)
! {
! /* Normal sign-extension rule for 32-bit operands. */
! xcut = EXTEND32 (x);
! ycut = EXTEND32 (y);
! }
! else if (unsigned_p)
! {
! /* Operands must be zero-extended 16-bit numbers. */
! xcut = x & 0xffff;
! ycut = y & 0xffff;
! }
! else
! {
! /* Likewise but sign-extended. */
! xcut = EXTEND16 (x);
! ycut = EXTEND16 (y);
! }
! if (x != xcut || y != ycut)
! sim_engine_abort (SD, CPU, CIA,
! "invalid multiplication operand at 0x%08lx\n",
! (long) CIA);
!
! TRACE_ALU_INPUT2 (x, y);
! product = (unsigned_p ? x * y : EXTEND32 (x) * EXTEND32 (y));
! result = (subtract_p ? lhs - product : lhs + product);
! if (saturate_p)
! {
! /* Saturate the result to 32 bits. An unsigned, unsaturated
! result is zero-extended to 64 bits, but unsigned overflow
! causes all 64 bits to be set. */
! if (!unsigned_p && (unsigned64) EXTEND32 (result) != result)
! result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff);
! else if (unsigned_p && (result >> 32) != 0)
! result = (unsigned64) 0 - 1;
! }
! TRACE_ALU_RESULT (result);
!
! if (double_p)
! LO = result;
! else
! {
! LO = EXTEND32 (result);
! HI = EXTEND32 (VH4_8 (result));
! }
! if (rd != 0)
! GPR[rd] = store_hi_p ? HI : LO;
}
! // 32-bit rotate right of X by Y bits.
! :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
! *vr5400:
! *vr5500:
{
! unsigned64 result;
!
! y &= 31;
! TRACE_ALU_INPUT2 (x, y);
! result = EXTEND32 (ROTR32 (x, y));
! TRACE_ALU_RESULT (result);
return result;
}
! // Likewise 64-bit
! :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
! *vr5400:
! *vr5500:
{
! unsigned64 result;
!
! y &= 63;
! TRACE_ALU_INPUT2 (x, y);
! result = ROTR64 (x, y);
! TRACE_ALU_RESULT (result);
return result;
}
!
! // VR4100 instructions.
!
! 000000,5.RS,5.RT,00000,00000,101000::32::MADD16
! "madd16 r<RS>, r<RT>"
*vr4100:
{
! do_vr_mul_op (SD_, 0, RS, RT,
! 1 /* accumulate */,
! 0 /* store in LO */,
! 0 /* signed arithmetic */,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 1 /* short */,
! 0 /* single */);
}
! 000000,5.RS,5.RT,00000,00000,101001::64::DMADD16
! "dmadd16 r<RS>, r<RT>"
*vr4100:
{
! do_vr_mul_op (SD_, 0, RS, RT,
! 1 /* accumulate */,
! 0 /* store in LO */,
! 0 /* signed arithmetic */,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 1 /* short */,
! 1 /* double */);
}
! // VR4120 and VR4130 instructions.
!
! 000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101001::64::DMACC
! "dmacc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
! *vr4120:
{
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS, SAT,
! 0 /* don't subtract */,
! SAT /* short */,
! 1 /* double */);
! }
!
! 000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101000::32::MACC_4120
! "macc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
! *vr4120:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS, SAT,
! 0 /* don't subtract */,
! SAT /* short */,
! 0 /* single */);
}
! // VR5400 and VR5500 instructions.
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,001,01100,1.UNS::32::MUL
! "mul%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
{
! do_vr_mul_op (SD_, RD, RS, RT,
! 0 /* don't accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,011,01100,1.UNS::32::MULS
! "muls%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 0 /* don't accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 1 /* subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,101,01100,1.UNS::32::MACC_5xxx
! "macc%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,111,01100,1.UNS::32::MSAC
! "msac%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 1 /* subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
! "ror r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
! }
!
! 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
! "rorv r<RD>, r<RT>, r<RS>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
! "dror r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
! "dror32 r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
! }
!
! 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
! "drorv r<RD>, r<RT>, r<RS>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
! }
!
! 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1
! "luxc1 f<FD>, r<INDEX>(r<BASE>)"
! *vr5500:
! {
! check_fpu (SD_);
! COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD,
! (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0));
! }
!
! 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64::SUXC1
! "suxc1 f<FS>, r<INDEX>(r<BASE>)"
! *vr5500:
! {
! check_fpu (SD_);
! do_store (SD_, AccessLength_DOUBLEWORD,
! (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0,
! COP_SD (1, FS));
}
+ 010000,1,19.*,100000:COP0:32::WAIT
+ "wait"
+ *vr5500:
+
+ 011100,00000,5.RT,5.DR,00000,111101:SPECIAL:64::MFDR
+ "mfdr r<RT>, r<DR>"
+ *vr5400:
+ *vr5500:
+ 011100,00100,5.RT,5.DR,00000,111101:SPECIAL:64::MTDR
+ "mtdr r<RT>, r<DR>"
+ *vr5400:
+ *vr5500:
+ 011100,00000,00000,00000,00000,111110:SPECIAL:64::DRET
+ "dret"
+ *vr5400:
+ *vr5500:
*** /dev/null Tue Nov 14 21:44:43 2000
--- mips/multi-run.c Tue Nov 5 12:24:49 2002
***************
*** 0 ****
--- 1,36 ----
+ /* Main entry point for MULTI simulators.
+ Copyright (C) 2002 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ */
+
+ #include "sim-main.h"
+ #include "multi-include.h"
+
+ #define SD sd
+ #define CPU cpu
+
+ void
+ sim_engine_run (SIM_DESC sd,
+ int next_cpu_nr,
+ int nr_cpus,
+ int signal) /* ignore */
+ {
+ switch (MIPS_BFD_MACH (sd))
+ {
+ #include "multi-switch.c"
+ }
+ }
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-11-05 8:20 ` Richard Sandiford
@ 2002-11-06 10:44 ` cgd
2002-11-06 14:46 ` cgd
1 sibling, 0 replies; 22+ messages in thread
From: cgd @ 2002-11-06 10:44 UTC (permalink / raw)
To: Richard Sandiford; +Cc: gdb-patches
At 05 Nov 2002 16:20:00 +0000, Richard Sandiford wrote:
> [ ... ]
> Please install if OK.
> [ ... ]
>
> common/
> * Make-common.in (SIM_EXTRA_DISTCLEAN): New macro.
> (distclean): Depend on it.
>
> igen/
> * gen-engine.c (print_engine_issue_prefix_hook): Don't add the
> global prefix to ENGINE_ISSUE_PREFIX_HOOK.
> (print_engine_issue_postfix_hook): Likewise ENGINE_ISSUE_POSTFIX_HOOK.
I've installed both of these (the former seeming obvious enough and
the latter not getting any comment from others after repeated tries
8-).
I'm still chewing on:
> mips/
> * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
> (mips64vr-*-*, mips64vrel-*-*): New configurations.
> Add a new simulator generator, MULTI.
> * configure: Regenerate.
> * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
> (multi-run.o): New dependency.
> (SIM_MULTI_ALL, SIM_MULTI_CONFIGS): New variables.
> (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
> (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New dependencies.
> (tmp-multi): Combine them.
> (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
> (distclean-extra): New rule.
> * sim-main.h: Include bfd.h.
> (MIPS_BFD_MACH): New macro.
> * mips.igen (vr4120, vr5400, vr5500): New models.
> (check_mf_cycles): Don't enforce mflo and mfhi separation
> in vr5500 code.
> (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
> * vr.igen: Replace with new version.
> * multi-run.c: New file.
I'm thinking that MIPS_BFD_MACH isn't quite right as-is, but it's
probably easier for me to fix it than to describe in vague terms what
I think it should be and then have you try to implement it. 8-)
However, before I decide, I need to fiddle with it a little bit more.
cgd
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-11-05 8:20 ` Richard Sandiford
2002-11-06 10:44 ` cgd
@ 2002-11-06 14:46 ` cgd
2002-11-06 15:08 ` cgd
2002-11-26 4:44 ` Richard Sandiford
1 sibling, 2 replies; 22+ messages in thread
From: cgd @ 2002-11-06 14:46 UTC (permalink / raw)
To: Richard Sandiford; +Cc: gdb-patches
At 05 Nov 2002 16:20:00 +0000, Richard Sandiford wrote:
> mips/
> * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
> (mips64vr-*-*, mips64vrel-*-*): New configurations.
> Add a new simulator generator, MULTI.
> * configure: Regenerate.
> * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
> (multi-run.o): New dependency.
> (SIM_MULTI_ALL, SIM_MULTI_CONFIGS): New variables.
> (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
> (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New dependencies.
> (tmp-multi): Combine them.
> (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
> (distclean-extra): New rule.
> * sim-main.h: Include bfd.h.
> (MIPS_BFD_MACH): New macro.
> * mips.igen (vr4120, vr5400, vr5500): New models.
> (check_mf_cycles): Don't enforce mflo and mfhi separation
> in vr5500 code.
> (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
> * vr.igen: Replace with new version.
> * multi-run.c: New file.
My patch, below, drops down on top of yours, with the following
effect:
* no new multi-run.c src.
* multi-run.c generated in its entirety by configure.in, to provide
functions: sim_engine_run, and mips_mach_multi.
* s/MIPS_BFD_MACH/MIPS_MACH/
* MIPS_MACH either defined to a hard-coded value from configure.in, or
if MULTI to mips_mach_multi() which returns a supported machine
type (either the currently selected one).
The generation of multi-run.c is kinda gross, but i didn't feel like
breaking it out into its own script. For true Rightness, it probably
should be. 8-S
I've not really tested it by running stuff thru the sim, but it does
seem to compile.
chris
==
diff -Nupr -x CVS -x configure mips.rsandifo/Makefile.in mips/Makefile.in
--- mips.rsandifo/Makefile.in Wed Nov 6 11:39:48 2002
+++ mips/Makefile.in Wed Nov 6 14:04:39 2002
@@ -76,7 +76,7 @@ cp1.o: $(srcdir)/cp1.c config.h sim-main
mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
-multi-run.o: multi-include.h multi-switch.c tmp-mach-multi
+multi-run.o: multi-include.h tmp-mach-multi
../igen/igen:
cd ../igen && $(MAKE)
@@ -391,4 +391,4 @@ clean-extra:
rm -f m16*.o m32*.o itable*.o
distclean-extra:
- rm -f multi-include.h multi-switch.c
+ rm -f multi-include.h multi-run.c
diff -Nupr -x CVS -x configure mips.rsandifo/configure.in mips/configure.in
--- mips.rsandifo/configure.in Wed Nov 6 11:39:48 2002
+++ mips/configure.in Wed Nov 6 14:09:07 2002
@@ -101,6 +101,8 @@ sim_igen_machine="-M mipsIV"
sim_m16_machine="-M mips16"
sim_igen_filter="32,64,f"
sim_m16_filter="16"
+sim_mach_default="mips8000"
+
case "${target}" in
mips*tx39*) sim_gen=IGEN
sim_igen_filter="32,f"
@@ -108,15 +110,18 @@ case "${target}" in
;;
mips64vr43*-*-*) sim_gen=IGEN
sim_igen_machine="-M mipsIV"
+ sim_mach_default="mips8000"
;;
mips64vr5*-*-*) sim_gen=IGEN
sim_igen_machine="-M vr5000"
+ sim_mach_default="mips5000"
;;
mips64vr41*) sim_gen=M16
sim_igen_machine="-M vr4100"
sim_m16_machine="-M vr4100"
sim_igen_filter="32,64,f"
sim_m16_filter="16"
+ sim_mach_default="mips4100"
;;
mips64vr-*-* | mips64vrel-*-*)
sim_gen=MULTI
@@ -138,20 +143,24 @@ case "${target}" in
mipsisa32*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips32"
sim_igen_filter="32,f"
+ sim_mach_default="mipsisa32"
;;
mipsisa64sb1*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64,sb1"
sim_igen_filter="32,64,f"
+ sim_mach_default="mips_sb1"
;;
mipsisa64*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64,mips3d"
sim_igen_filter="32,64,f"
+ sim_mach_default="mipsisa64"
;;
mips*lsi*) sim_gen=M16
sim_igen_machine="-M mipsIII,mips16"
sim_m16_machine="-M mips16,mipsIII"
sim_igen_filter="32,f"
sim_m16_filter="16"
+ sim_mach_default="mips4000"
;;
mips*-*-*) sim_gen=IGEN
sim_igen_filter="32,f"
@@ -190,13 +199,58 @@ if test ${sim_gen} = MULTI; then
fi
# Start in a known state.
- rm -f multi-include.h multi-switch.c
+ rm -f multi-include.h multi-run.c
sim_multi_flags=
sim_multi_src=
sim_multi_obj=multi-run.o
sim_multi_igen_configs=
sim_seen_default=no
+ cat << __EOF__ > multi-run.c
+/* Main entry point for MULTI simulators.
+ Copyright (C) 2002 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ --
+
+ This file was generated by sim/mips/configure. */
+
+#include "sim-main.h"
+#include "multi-include.h"
+
+#define SD sd
+#define CPU cpu
+
+void
+sim_engine_run (SIM_DESC sd,
+ int next_cpu_nr,
+ int nr_cpus,
+ int signal) /* ignore */
+{
+ int mach;
+
+ if (STATE_ARCHITECTURE (sd) == NULL)
+ mach = bfd_mach_${sim_multi_default};
+ else
+ mach = STATE_ARCHITECTURE (SD)->mach;
+
+ switch (mach)
+ {
+__EOF__
+
for fc in ${sim_multi_configs}; do
# Split up the entry. ${c} contains the first three elements.
@@ -252,17 +306,17 @@ if test ${sim_gen} = MULTI; then
# top-level foo_engine_run() function.
echo "#include \"${w}${name}_engine.h\"" >> multi-include.h
- # Add case statements for this engine.
+ # Add case statements for this engine to sim_engine_run().
for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
- echo "case bfd_mach_${mach}:" >> multi-switch.c
+ echo " case bfd_mach_${mach}:" >> multi-run.c
if test ${mach} = ${sim_multi_default}; then
- echo "default:" >> multi-switch.c
+ echo " default:" >> multi-run.c
sim_seen_default=yes
fi
done
- echo " ${w}${name}_engine_run (sd, next_cpu_nr, nr_cpus, signal);" \
- >> multi-switch.c
- echo " break;" >> multi-switch.c
+ echo " ${w}${name}_engine_run (sd, next_cpu_nr, nr_cpus, signal);" \
+ >> multi-run.c
+ echo " break;" >> multi-run.c
done
# Check whether we added a 'default:' label.
@@ -270,11 +324,50 @@ if test ${sim_gen} = MULTI; then
AC_MSG_ERROR(Error in configure.in: \${sim_multi_configs} doesn't have an entry for \${sim_multi_default})
fi
- # Used to define MIPS_BFD_MACH.
- SIM_SUBTARGET="$SIM_SUBTARGET -DMULTI_DEFAULT_BFD_MACH=bfd_mach_${sim_multi_default}"
+ cat << __EOF__ >> multi-run.c
+ }
+}
+
+int
+mips_mach_multi (SIM_DESC sd)
+{
+ if (STATE_ARCHITECTURE (sd) == NULL)
+ return bfd_mach_${sim_multi_default};
+
+ switch (STATE_ARCHITECTURE (SD)->mach)
+ {
+__EOF__
+
+ # Add case statements for this engine to mips_mach_multi().
+ for fc in ${sim_multi_configs}; do
+
+ # Split up the entry. ${c} contains the first three elements.
+ # Note: outer sqaure brackets are m4 quotes.
+ c=`echo ${fc} | sed ['s/:[^:]*$//']`
+ bfdmachs=`echo ${fc} | sed 's/.*://'`
+
+ for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
+ echo " case bfd_mach_${mach}:" >> multi-run.c
+ done
+ done
+
+ cat << __EOF__ >> multi-run.c
+ return (STATE_ARCHITECTURE (SD)->mach);
+ default:
+ return bfd_mach_${sim_multi_default};
+ }
+}
+__EOF__
+
+ SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_MULTI"
else
# For clean-extra
sim_multi_src=doesnt-exist.c
+
+ if test x"${sim_mach_default}" = x""; then
+ AC_MSG_ERROR(Error in configure.in: \${sim_mach_default} not defined)
+ fi
+ SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_DEFAULT=bfd_mach_${sim_mach_default}"
fi
sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}"
diff -Nupr -x CVS -x configure mips.rsandifo/mips.igen mips/mips.igen
--- mips.rsandifo/mips.igen Wed Nov 6 11:39:48 2002
+++ mips/mips.igen Wed Nov 6 14:10:02 2002
@@ -233,7 +233,7 @@
:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
{
/* There are no timing requirements in vr5500 code. */
- if (MIPS_BFD_MACH (SD) == bfd_mach_mips5500)
+ if (MIPS_MACH (SD) == bfd_mach_mips5500)
return 1;
if (history->mf.timestamp + 3 > time)
{
diff -Nupr -x CVS -x configure mips.rsandifo/multi-run.c mips/multi-run.c
--- mips.rsandifo/multi-run.c Wed Nov 6 11:39:48 2002
+++ mips/multi-run.c Wed Dec 31 16:00:00 1969
@@ -1,36 +0,0 @@
-/* Main entry point for MULTI simulators.
- Copyright (C) 2002 Free Software Foundation, Inc.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-
- */
-
-#include "sim-main.h"
-#include "multi-include.h"
-
-#define SD sd
-#define CPU cpu
-
-void
-sim_engine_run (SIM_DESC sd,
- int next_cpu_nr,
- int nr_cpus,
- int signal) /* ignore */
-{
- switch (MIPS_BFD_MACH (sd))
- {
-#include "multi-switch.c"
- }
-}
diff -Nupr -x CVS -x configure mips.rsandifo/sim-main.h mips/sim-main.h
--- mips.rsandifo/sim-main.h Wed Nov 6 11:39:48 2002
+++ mips/sim-main.h Wed Nov 6 14:08:48 2002
@@ -950,15 +950,11 @@ void mips_cpu_exception_trigger(SIM_DESC
void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
-#ifdef MULTI_DEFAULT_BFD_MACH
-#define MIPS_BFD_MACH(SD) \
- (STATE_ARCHITECTURE (SD)->mach != 0 \
- ? STATE_ARCHITECTURE (SD)->mach \
- : MULTI_DEFAULT_BFD_MACH)
-#endif
-
-#ifndef MIPS_BFD_MACH
-#define MIPS_BFD_MACH(SD) 0
+#ifdef MIPS_MACH_MULTI
+extern int mips_mach_multi(SIM_DESC sd);
+#define MIPS_MACH(SD) mips_mach_multi(SD)
+#else
+#define MIPS_MACH(SD) MIPS_MACH_DEFAULT
#endif
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-11-06 14:46 ` cgd
@ 2002-11-06 15:08 ` cgd
2002-11-26 4:44 ` Richard Sandiford
1 sibling, 0 replies; 22+ messages in thread
From: cgd @ 2002-11-06 15:08 UTC (permalink / raw)
To: Richard Sandiford; +Cc: gdb-patches
At 06 Nov 2002 14:46:18 -0800, Chris G. Demetriou wrote:
> [ ... ]
Forgot to mention:
looks like there's at least one 'clean'ing issue left in your patch:
after make and then clean in mips64vr-elf build, two files:
m16m32vr4100_run.c
m16m32vr4120_run.c
are left around.
didn't really look into it.
thanks,
chris
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-10-04 10:54 ` cgd
2002-10-09 7:14 ` Richard Sandiford
@ 2002-11-06 16:46 ` Andrew Cagney
2002-11-06 17:28 ` cgd
1 sibling, 1 reply; 22+ messages in thread
From: Andrew Cagney @ 2002-11-06 16:46 UTC (permalink / raw)
To: cgd, rsandifo; +Cc: gdb-patches
[See reall comment at the bottom.]
>> - gen-engine.c adds the global prefix to the beginning of
>> ENGINE_ISSUE_(PREFIX|POSTFIX)_HOOK. It seems MIPS is the
>> only back-end to define these macros, and it never adds a
>> prefix. The patch adjusts igen accordingly.
>
>
> Hmm. I don't know igen so well. Andrew? What are your thoughts
> here?
[I suspect its already been committed]
So, how did it ever build?
Anyway, when someone finds that a prefix is needed, it can be re-visited
with, probably an extra option or.
>> - The existing vr5000 model selects three-address mult
>> and dmult instructions, but those instructions aren't
>> listed in NEC's documentation. There's a three-address
>> vr5400 mult instruction, but it has a different opcode.
>>
>> The vr5000 model only seems to exist for these instructions,
>> it would otherwise be a standard mipsIV target. Would it
>> be OK to submit a follow-on patch to remove it?
>
>
> Well, there are a couple of other differences w.r.t: BC0T, DMFC0,
> DMTC0, COPz... But I don't know whether they're relevant.
>
> As far as I'm concerned, if there is no difference, it should probably
> be removed. Andrew?
Here, I've no idea.
>> - The uses of vr4100 in mips.igen seem to be redundant
>> with mipsIII. OK to remove them as well?
>
>
> I'm assuming this is a historical thing.
>
> In the old world order, every processor type had its own model.
> In the new world order, which you seem to be adapting nicely to,
> processors which are "ISA + extensions" use multiple models.
The real world order is: ISA YYY implements MIPS XXX, BUT with a few
tiny exceptions .... You end up having to check that every single
*&@^#$(*&@#$ instruction matches the generic ISA. Sigh.
:-)
>> ***************
>> *** 229,234 ****
>> --- 232,240 ----
>>
>> :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
>> {
>> + /* There are no timing requirements in vr5500 code. */
>> + if (STATE_ARCHITECTURE (SD)->mach == bfd_mach_mips5500)
>> + return 1;
>> if (history->mf.timestamp + 3 > time)
>> {
>
>
> This is the first case of code like this in the MIPS sim, but it seems
> like the right thing.
Specify two functions. One for the mips5500 and one for the rest. That
way, there isn't any reason for adding TATE_ARCHITECTURE (SD)->mach ==
bfd_mach_mips5500.
It will also solve the default machine problem.
Andrew
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-11-06 16:46 ` Andrew Cagney
@ 2002-11-06 17:28 ` cgd
2002-11-06 17:40 ` Andrew Cagney
0 siblings, 1 reply; 22+ messages in thread
From: cgd @ 2002-11-06 17:28 UTC (permalink / raw)
To: Andrew Cagney; +Cc: rsandifo, gdb-patches
At Wed, 06 Nov 2002 19:46:07 -0500, Andrew Cagney wrote:
> >> - gen-engine.c adds the global prefix to the beginning of
> >> ENGINE_ISSUE_(PREFIX|POSTFIX)_HOOK. It seems MIPS is the
> >> only back-end to define these macros, and it never adds a
> >> prefix. The patch adjusts igen accordingly.
> >
> >
> > Hmm. I don't know igen so well. Andrew? What are your thoughts
> > here?
>
> [I suspect its already been committed]
> So, how did it ever build?
Err, well, build is no problem: the code in question did #if
defined(%sENGINE_ISSUE_PREFIX_HOOK)... so it won't get in there.
> Specify two functions. One for the mips5500 and one for the rest. That
> way, there isn't any reason for adding TATE_ARCHITECTURE (SD)->mach ==
> bfd_mach_mips5500.
>
> It will also solve the default machine problem.
well:
(1) w/ separate fn, you'd need to tag _all_ of the 5500 machine insns
w/ mips5500. (as opposed to ISA + a few mips5500 extensions.)
(2) it doesn't actually solve the default machine problem, since you
need to e.g. pick the right machine (possibly picking default) in
sim_engine_run, and you need to pick the right machine (again
possibly picking default) if doing e.g. MD cp0 register handling.
(I've got a lot of code yet to be submitted that does the latter.)
chris
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-11-06 17:28 ` cgd
@ 2002-11-06 17:40 ` Andrew Cagney
2002-11-07 11:08 ` cgd
0 siblings, 1 reply; 22+ messages in thread
From: Andrew Cagney @ 2002-11-06 17:40 UTC (permalink / raw)
To: cgd; +Cc: rsandifo, gdb-patches
> At Wed, 06 Nov 2002 19:46:07 -0500, Andrew Cagney wrote:
>
>> >> - gen-engine.c adds the global prefix to the beginning of
>> >> ENGINE_ISSUE_(PREFIX|POSTFIX)_HOOK. It seems MIPS is the
>> >> only back-end to define these macros, and it never adds a
>> >> prefix. The patch adjusts igen accordingly.
>
>> >
>> >
>> > Hmm. I don't know igen so well. Andrew? What are your thoughts
>> > here?
>
>>
>> [I suspect its already been committed]
>> So, how did it ever build?
>
>
> Err, well, build is no problem: the code in question did #if
> defined(%sENGINE_ISSUE_PREFIX_HOOK)... so it won't get in there.
>
>
>
>> Specify two functions. One for the mips5500 and one for the rest. That
>> way, there isn't any reason for adding TATE_ARCHITECTURE (SD)->mach ==
>> bfd_mach_mips5500.
>>
>> It will also solve the default machine problem.
>
>
> well:
>
> (1) w/ separate fn, you'd need to tag _all_ of the 5500 machine insns
> w/ mips5500. (as opposed to ISA + a few mips5500 extensions.)
Er, all the instructions that belonged to the MIPS 5500 should be taged
with 5500 anyway. As I noted:
> The real world order is: ISA YYY implements MIPS XXX, BUT with a few tiny exceptions .... You end up having to check that every single *&@^#$(*&@#$ instruction matches the generic ISA. Sigh.
Andrew
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-11-06 17:40 ` Andrew Cagney
@ 2002-11-07 11:08 ` cgd
0 siblings, 0 replies; 22+ messages in thread
From: cgd @ 2002-11-07 11:08 UTC (permalink / raw)
To: Andrew Cagney; +Cc: rsandifo, gdb-patches
At Wed, 06 Nov 2002 20:40:45 -0500, Andrew Cagney wrote:
> > well:
> >
> > (1) w/ separate fn, you'd need to tag _all_ of the 5500 machine insns
> > w/ mips5500. (as opposed to ISA + a few mips5500 extensions.)
>
> Er, all the instructions that belonged to the MIPS 5500 should be taged
> with 5500 anyway. As I noted:
>
> > The real world order is: ISA YYY implements MIPS XXX, BUT with a few tiny exceptions .... You end up having to check that every single *&@^#$(*&@#$ instruction matches the generic ISA. Sigh.
So, i'd like to explore this a bit more. I'll state up front I don't
agree, so you know where i'm going before you're hip-deep in spew. 8-)
I hope this clears up where i'm trying to take things. I think you
knew when you signed me on as co-maintainer that I was likely to have
strong opinions. 8-)
My belief is the that following things, at least, should be considered
when trying to figure out how to support a new ISA, in no particular
order:
* clarity of code.
E.g., if it's MIPS32 with a few small deviations or
something, IMO it's _much_ clearer to code that using mips32
and then test for the machine to handle the diffferences,
than it is to scatter machine_name tags all over and make
people use compare_igen_models to tell the difference.
Obviously, there's a tradeoff: if there are enough if()
checks, then the code quality suffers.
* performance.
Being able to tune a simulator so that it performs well is
important to me, and to serious simulator users.
Like i've said before, we've simulated ... a whole heck of a
lot of instructions (i believe probably "trillions") using a
sim-based simulator, and we prefer that things run as fast
as possible. 8-)
Because there's a desire to support multi-machine
simulators, there's a tradeoff here, too.
To my mind, people who want multi-machine simulators are
willing to sacrifice some performance to do it (but do not
want to lose horribly, either). A few scattered run-time
checks will not significantly harm performance (and heck,
they've already bought a runtime check in sim_engine_run at
minimum).
On the other hand, the ability to provide multiple machine
support should minimally impact single machine support.
Once consequence of that is, when building a single machine
sim, as many run-time tests as possible should be able to be
removed at compile time (e.g. due to constant comparison
results).
* correctness.
By this i mean "matches the actual hardware," and not
"produces computationally-correct results given what the
author of the code was trying to simulatr." The latter is
not something which is negotiable. 8-)
Obviously, the simulator has to be "as close as necessary"
for the author's and the community's use.
There are differing degrees as to what's required there.
For instace, our internal simulator has a full and complete
cp0 implementation, good enough to run OSes and other "hard"
tests of the MIPS architecture.
Many people don't need that, or in fact don't even _want_
it.
For instance, our CP1 simulation actually does trap on the
same inputs that our real FPU does (denorms for certain ops,
or whatever -- i forget) and it's important to us that it
does (when running in "raw hardware" mode). That's
desirable in certain circumstances, but not in many
(e.g. running the GCC testsuite on simulated firmware),
since it'll cause some tests to fail that would normally
pass after OS or firmware fixups.
So, anyway, to get on to the specifics of how to add new machines,
with the choices being:
* leave 'shared' instructions tagged w/ the base ISA type
implemented by the machine (with additional tags for ASEs,
etc.) and use run-time tests to differentiate as necessary
in 'common' instructions
* tag each instruction as being specific to that machine,
differentiating by providing different functions or by
instructions.
* In the case of MIPS32/MIPS64 implementations, i strongly believe
that the former ("the new world order" as i see it) is the right
thing.
there are three basic types of deviations which require
conditionalization:
* cp0 stuff.
IMO, this pretty much _has_ to be done by checking the
machine type in C code.
If you try to do it in igen code, you need IGEN
functions per machine type, then they need to call out
to per-machine-type functions in .c files. It
unnecessarily blows up the size of the code.
This is especially true for MIPS32/MIPS64 CP0, which
_should_ be CP0 as specified, with possibly a tiny bit
of deviation per machine either for allowed customizations
(e.g. VA size, subsetting, etc.) or for defects.
Trying to do M32/M64 CP0 on a per-machine basis would
just be crazy.
* added instructions
There are easily enough handled as "ASE"-ish
additional machine type specifiers.
* bugs.
This should, IMO, be handled on a case-by-case basis.
If a machine has a few of them, they should probably
be handled with if()s on the machine type.
If it's got a _lot_, they should probably be handled
by not using the generic mips32/mips64 instructions,
and littering the new machine's name all over as need
be.
* Pre-MIPS32/MIPS64 is a bit trickier, because in addition to the
above cases where people are implementing on top of a standard ISA,
you run into stuff like:
* vastly diverent CP0 implementations.
* instructions _removed_ from a base ISA (e.g. no ll/sc), or
instructions with same encoding but different behaviour.
* divergent requirements re: hazards (i.e., load to use,
LO/HI, etc.) that it's desirable to have the simulator warn
about (so as to be sure the compiler is avoiding them
adequately).
I believe both should be evaluated on a case-by-case basis, the latter
obviously moreso than the former. (Odds are, if a MIPS CPU has _that_
many bugs, it's not gonna pass conformance testing or ship in any
significant volume. IMO, variations among pre-MIPS32/MIPS64 chips are
likely to be greater than post-, but thankfully going forward we
should see fewer of them being added to the simulator!)
anyway, that having been said, I think i should now state my opinion
re: evaluating this particular case, i.e. Richard's patch to add
vr5500 support (in particular the conditional in check_mf_cycles) as
modified by my subsequent patch:
* the check in check_mf_cycles will evaluate to a constant
true/false if not a multi-machine simulator,
* the vr5500 run-time conditionals are not many in number (uh,
1 8-), and therefore aren't intrusive in that manner (i.e.,
they don't make the code harder to read),
* based on the above 2 points, that runtime check will not
hurt code performance in the case where we care most about
performance (single-machine), and since it's just one check
shouldn't hurt much at all even if multi-machine.
You've suggested the alternative of changing check_mf_cycles to be a
machine-dependent function. I do believe (as you've stated) that
_that_ would require adding vr5500 tags scattered on every instruction
used by the vr5500, i.e., every mipsIV instruction, with the _only_
difference between vr5500 and mipsIV (over the set of insn/fns used by
mipsIV) being check_mf_cycles.
IMO, that would:
* have no significant performance benefit, but
* make the patch to add the vr5500 support harder to
understand (i.e. cluttered with Lots of lines of diffs to
just add vr5500 tags), and finally and most importantly:
* hurt the maintainability of the code.
Instead of vr5500 differences being clearly marked as with
Richard's code, one would _have_ to use
e.g. compare_igen_models to tell the difference, and even
that would say only that each had different check_mf_cycles
fns (i.e., not make the difference clear).
(I also think that doing it the way you suggest would set the wrong
precedent for future additions, which if MIPS32/MIPS64 based really
almost certainly should be done w/ conditional checks.)
In other words, IMO, doing it the way Richard has done it is basically
all gain, no pain, and that compared to that tagging every mipsIV insn
w/ vr5500 is much pain, no gain. 8-)
chris
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-11-06 14:46 ` cgd
2002-11-06 15:08 ` cgd
@ 2002-11-26 4:44 ` Richard Sandiford
[not found] ` <mailpost.1038314670.25092@news-sj1-1>
` (2 more replies)
1 sibling, 3 replies; 22+ messages in thread
From: Richard Sandiford @ 2002-11-26 4:44 UTC (permalink / raw)
To: cgd; +Cc: gdb-patches
cgd@broadcom.com writes:
> My patch, below, drops down on top of yours, with the following
> effect:
>
> * no new multi-run.c src.
>
> * multi-run.c generated in its entirety by configure.in, to provide
> functions: sim_engine_run, and mips_mach_multi.
>
> * s/MIPS_BFD_MACH/MIPS_MACH/
>
> * MIPS_MACH either defined to a hard-coded value from configure.in, or
> if MULTI to mips_mach_multi() which returns a supported machine
> type (either the currently selected one).
I tried it, worked fine.
There doesn't seem to have been objection to your last mail, so I
thought I'd have another stab at getting the stuff accepeted.
Combined diff below.
Richard
Chris Demetriou <cgd@broadcom.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Richard Sandiford <rsandifo@redhat.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(check_mf_cycles): Don't enforce mflo and mfhi separation
in vr5500 code.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
Index: mips/configure.in
===================================================================
RCS file: /cvs/src/src/sim/mips/configure.in,v
retrieving revision 1.4
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.4 configure.in
*** mips/configure.in 14 Jun 2002 18:49:09 -0000 1.4
--- mips/configure.in 26 Nov 2002 12:29:37 -0000
*************** # the value of {STATE,CPU}_ARCHITECTURE
*** 18,23 ****
--- 18,24 ----
# in question.
#
case "${target}" in
+ mips64vr*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
mips*tx39*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
mipsisa32*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mipsisa64*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
*************** sim_igen_machine="-M mipsIV"
*** 100,105 ****
--- 101,108 ----
sim_m16_machine="-M mips16"
sim_igen_filter="32,64,f"
sim_m16_filter="16"
+ sim_mach_default="mips8000"
+
case "${target}" in
mips*tx39*) sim_gen=IGEN
sim_igen_filter="32,f"
*************** case "${target}" in
*** 107,122 ****
--- 110,138 ----
;;
mips64vr43*-*-*) sim_gen=IGEN
sim_igen_machine="-M mipsIV"
+ sim_mach_default="mips8000"
;;
mips64vr5*-*-*) sim_gen=IGEN
sim_igen_machine="-M vr5000"
+ sim_mach_default="mips5000"
;;
mips64vr41*) sim_gen=M16
sim_igen_machine="-M vr4100"
sim_m16_machine="-M vr4100"
sim_igen_filter="32,64,f"
sim_m16_filter="16"
+ sim_mach_default="mips4100"
;;
+ mips64vr-*-* | mips64vrel-*-*)
+ sim_gen=MULTI
+ sim_multi_configs="\
+ vr4100:mipsIII,mips16,vr4100:32,64:mips4100,mips4111\
+ vr4120:mipsIII,mips16,vr4120:32,64:mips4120\
+ vr5000:mipsIV:32,64,f:mips4300,mips5000\
+ vr5400:mipsIV,vr5400:32,64,f:mips5400\
+ vr5500:mipsIV,vr5500:32,64,f:mips5500"
+ sim_multi_default=mips5000
+ ;;
mips64*-*-*) sim_igen_filter="32,64,f"
sim_gen=IGEN
;;
*************** case "${target}" in
*** 127,156 ****
--- 143,383 ----
mipsisa32*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips32"
sim_igen_filter="32,f"
+ sim_mach_default="mipsisa32"
;;
mipsisa64sb1*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64,sb1"
sim_igen_filter="32,64,f"
+ sim_mach_default="mips_sb1"
;;
mipsisa64*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64,mips3d"
sim_igen_filter="32,64,f"
+ sim_mach_default="mipsisa64"
;;
mips*lsi*) sim_gen=M16
sim_igen_machine="-M mipsIII,mips16"
sim_m16_machine="-M mips16,mipsIII"
sim_igen_filter="32,f"
sim_m16_filter="16"
+ sim_mach_default="mips4000"
;;
mips*-*-*) sim_gen=IGEN
sim_igen_filter="32,f"
;;
esac
+
+ # The MULTI generator can combine several simulation engines into one.
+ # executable. A configuration which uses the MULTI should set two
+ # variables: ${sim_multi_configs} and ${sim_multi_default}.
+ #
+ # ${sim_multi_configs} is the list of engines to build. Each
+ # space-separated entry has the form NAME:MACHINE:FILTER:BFDMACHS,
+ # where:
+ #
+ # - NAME is a C-compatible prefix for the engine,
+ # - MACHINE is a -M argument,
+ # - FILTER is a -F argument, and
+ # - BFDMACHS is a comma-separated list of bfd machines that the
+ # simulator can run.
+ #
+ # Each entry will have a separate simulation engine whose prefix is
+ # m32<NAME>. If the machine list includes "mips16", there will also
+ # be a mips16 engine, prefix m16<NAME>. The mips16 engine will be
+ # generated using the same machine list as the 32-bit version,
+ # but the filter will be "16" instead of FILTER.
+ #
+ # The simulator compares the bfd mach against BFDMACHS to decide
+ # which engine to use. Entries in BFDMACHS should be bfd_mach
+ # values with "bfd_mach_" removed. ${sim_multi_default} says
+ # which entry should be the default.
+ if test ${sim_gen} = MULTI; then
+
+ # Simple sanity check.
+ if test -z "${sim_multi_configs}" || test -z "${sim_multi_default}"; then
+ AC_MSG_ERROR(Error in configure.in: MULTI simulator not set up correctly)
+ fi
+
+ # Start in a known state.
+ rm -f multi-include.h multi-run.c
+ sim_multi_flags=
+ sim_multi_src=
+ sim_multi_obj=multi-run.o
+ sim_multi_igen_configs=
+ sim_seen_default=no
+
+ cat << __EOF__ > multi-run.c
+ /* Main entry point for MULTI simulators.
+ Copyright (C) 2002 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ --
+
+ This file was generated by sim/mips/configure. */
+
+ #include "sim-main.h"
+ #include "multi-include.h"
+
+ #define SD sd
+ #define CPU cpu
+
+ void
+ sim_engine_run (SIM_DESC sd,
+ int next_cpu_nr,
+ int nr_cpus,
+ int signal) /* ignore */
+ {
+ int mach;
+
+ if (STATE_ARCHITECTURE (sd) == NULL)
+ mach = bfd_mach_${sim_multi_default};
+ else
+ mach = STATE_ARCHITECTURE (SD)->mach;
+
+ switch (mach)
+ {
+ __EOF__
+
+ for fc in ${sim_multi_configs}; do
+
+ # Split up the entry. ${c} contains the first three elements.
+ # Note: outer sqaure brackets are m4 quotes.
+ c=`echo ${fc} | sed ['s/:[^:]*$//']`
+ bfdmachs=`echo ${fc} | sed 's/.*://'`
+ name=`echo ${c} | sed 's/:.*//'`
+ machine=`echo ${c} | sed 's/.*:\(.*\):.*/\1/'`
+ filter=`echo ${c} | sed 's/.*://'`
+
+ # Build the following lists:
+ #
+ # sim_multi_flags: all -M and -F flags used by the simulator
+ # sim_multi_src: all makefile-generated source files
+ # sim_multi_obj: the objects for ${sim_multi_src}
+ # sim_multi_igen_configs: igen configuration strings.
+ #
+ # Each entry in ${sim_multi_igen_configs} is a prefix (m32
+ # or m16) followed by the NAME, MACHINE and FILTER part of
+ # the ${sim_multi_configs} entry.
+ sim_multi_flags="${sim_multi_flags} -F ${filter} -M ${machine}"
+
+ # Check whether mips16 handling is needed.
+ case ${c} in
+ *:*mips16*:*)
+ # Run igen twice, once for normal mode and once for mips16.
+ ws="m32 m16"
+
+ # The top-level function for the mips16 simulator is
+ # in a file m16${name}_run.c, generated by the
+ # tmp-run-multi Makefile rule.
+ sim_multi_src="${sim_multi_src} m16${name}_run.c"
+ sim_multi_obj="${sim_multi_obj} m16${name}_run.o"
+ sim_multi_flags="${sim_multi_flags} -F 16"
+ ;;
+ *)
+ ws=m32
+ ;;
+ esac
+
+ # Now add the list of igen-generated files to ${sim_multi_src}
+ # and ${sim_multi_obj}.
+ for w in ${ws}; do
+ for base in engine icache idecode model semantics support; do
+ sim_multi_src="${sim_multi_src} ${w}${name}_${base}.c"
+ sim_multi_src="${sim_multi_src} ${w}${name}_${base}.h"
+ sim_multi_obj="${sim_multi_obj} ${w}${name}_${base}.o"
+ done
+ sim_multi_igen_configs="${sim_multi_igen_configs} ${w}${c}"
+ done
+
+ # Add an include for the engine.h file. This file declares the
+ # top-level foo_engine_run() function.
+ echo "#include \"${w}${name}_engine.h\"" >> multi-include.h
+
+ # Add case statements for this engine to sim_engine_run().
+ for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
+ echo " case bfd_mach_${mach}:" >> multi-run.c
+ if test ${mach} = ${sim_multi_default}; then
+ echo " default:" >> multi-run.c
+ sim_seen_default=yes
+ fi
+ done
+ echo " ${w}${name}_engine_run (sd, next_cpu_nr, nr_cpus, signal);" \
+ >> multi-run.c
+ echo " break;" >> multi-run.c
+ done
+
+ # Check whether we added a 'default:' label.
+ if test ${sim_seen_default} = no; then
+ AC_MSG_ERROR(Error in configure.in: \${sim_multi_configs} doesn't have an entry for \${sim_multi_default})
+ fi
+
+ cat << __EOF__ >> multi-run.c
+ }
+ }
+
+ int
+ mips_mach_multi (SIM_DESC sd)
+ {
+ if (STATE_ARCHITECTURE (sd) == NULL)
+ return bfd_mach_${sim_multi_default};
+
+ switch (STATE_ARCHITECTURE (SD)->mach)
+ {
+ __EOF__
+
+ # Add case statements for this engine to mips_mach_multi().
+ for fc in ${sim_multi_configs}; do
+
+ # Split up the entry. ${c} contains the first three elements.
+ # Note: outer sqaure brackets are m4 quotes.
+ c=`echo ${fc} | sed ['s/:[^:]*$//']`
+ bfdmachs=`echo ${fc} | sed 's/.*://'`
+
+ for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
+ echo " case bfd_mach_${mach}:" >> multi-run.c
+ done
+ done
+
+ cat << __EOF__ >> multi-run.c
+ return (STATE_ARCHITECTURE (SD)->mach);
+ default:
+ return bfd_mach_${sim_multi_default};
+ }
+ }
+ __EOF__
+
+ SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_MULTI"
+ else
+ # For clean-extra
+ sim_multi_src=doesnt-exist.c
+
+ if test x"${sim_mach_default}" = x""; then
+ AC_MSG_ERROR(Error in configure.in: \${sim_mach_default} not defined)
+ fi
+ SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_DEFAULT=bfd_mach_${sim_mach_default}"
+ fi
sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}"
AC_SUBST(sim_igen_flags)
AC_SUBST(sim_m16_flags)
AC_SUBST(sim_gen)
+ AC_SUBST(sim_multi_flags)
+ AC_SUBST(sim_multi_igen_configs)
+ AC_SUBST(sim_multi_src)
+ AC_SUBST(sim_multi_obj)
#
Index: mips/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mips/Makefile.in,v
retrieving revision 1.7
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.7 Makefile.in
*** mips/Makefile.in 14 Jun 2002 18:49:09 -0000 1.7
--- mips/Makefile.in 26 Nov 2002 12:29:37 -0000
*************** SIM_M16_OBJ = \
*** 33,38 ****
--- 33,39 ----
itable.o \
m16run.o \
+ SIM_MULTI_OBJ = itable.o @sim_multi_obj@
MIPS_EXTRA_OBJS = @mips_extra_objs@
MIPS_EXTRA_LIBS = @mips_extra_libs@
*************** SIM_SUBTARGET=@SIM_SUBTARGET@
*** 57,62 ****
--- 58,64 ----
SIM_EXTRA_CFLAGS = $(SIM_SUBTARGET)
SIM_EXTRA_CLEAN = clean-extra
+ SIM_EXTRA_DISTCLEAN = distclean-extra
SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
*************** cp1.o: $(srcdir)/cp1.c config.h sim-main
*** 74,79 ****
--- 76,83 ----
mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
+ multi-run.o: multi-include.h tmp-mach-multi
+
../igen/igen:
cd ../igen && $(MAKE)
*************** BUILT_SRC_FROM_GEN = \
*** 98,103 ****
--- 102,108 ----
SIM_IGEN_ALL = tmp-igen
SIM_M16_ALL = tmp-m16
+ SIM_MULTI_ALL = tmp-multi
$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
*************** tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen
*** 291,300 ****
--- 296,394 ----
touch tmp-m16
+ BUILT_SRC_FROM_MULTI = @sim_multi_src@
+ SIM_MULTI_IGEN_CONFIGS = @sim_multi_igen_configs@
+
+ $(BUILT_SRC_FROM_MULTI): tmp-multi
+ tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi targ-vals.h
+ tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+ for t in $(SIM_MULTI_IGEN_CONFIGS); do \
+ p=`echo $${t} | sed -e 's/:.*//'` ; \
+ m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
+ f=`echo $${t} | sed -e 's/.*://'` ; \
+ case $${p} in \
+ m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
+ *) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
+ esac; \
+ ../igen/igen \
+ $(IGEN_TRACE) \
+ $${e} \
+ -I $(srcdir) \
+ -Werror \
+ -Wnodiscard \
+ -N 0 \
+ -M $${m} \
+ -G gen-direct-access \
+ -G gen-zero-r0 \
+ -i $(IGEN_INSN) \
+ -P $${p}_ \
+ -x \
+ -n $${p}_icache.h -hc tmp-icache.h \
+ -n $${p}_icache.c -c tmp-icache.c \
+ -n $${p}_semantics.h -hs tmp-semantics.h \
+ -n $${p}_semantics.c -s tmp-semantics.c \
+ -n $${p}_idecode.h -hd tmp-idecode.h \
+ -n $${p}_idecode.c -d tmp-idecode.c \
+ -n $${p}_model.h -hm tmp-model.h \
+ -n $${p}_model.c -m tmp-model.c \
+ -n $${p}_support.h -hf tmp-support.h \
+ -n $${p}_support.c -f tmp-support.c \
+ -n $${p}_engine.h -he tmp-engine.h \
+ -n $${p}_engine.c -e tmp-engine.c \
+ ; \
+ $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
+ $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
+ $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
+ $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
+ $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
+ $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
+ $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
+ $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
+ $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
+ $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
+ $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
+ $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
+ done
+ touch tmp-mach-multi
+ tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+ ../igen/igen \
+ $(IGEN_TRACE) \
+ -I $(srcdir) \
+ -Werror \
+ -Wnodiscard \
+ -Wnowidth \
+ -N 0 \
+ @sim_multi_flags@ \
+ -G gen-direct-access \
+ -G gen-zero-r0 \
+ -i $(IGEN_INSN) \
+ -n itable.h -ht tmp-itable.h \
+ -n itable.c -t tmp-itable.c \
+ #
+ $(srcdir)/../../move-if-change tmp-itable.h itable.h
+ $(srcdir)/../../move-if-change tmp-itable.c itable.c
+ touch tmp-itable-multi
+ tmp-run-multi: $(srcdir)/m16run.c
+ for t in $(SIM_MULTI_IGEN_CONFIGS); do \
+ case $${t} in \
+ *:*mips16*:*) \
+ m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
+ sed < $(srcdir)/m16run.c > tmp-run \
+ -e "s/^sim_/m16$${m}_/" \
+ -e "s/m16_/m16$${m}_/" \
+ -e "s/m32_/m32$${m}_/" ; \
+ $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
+ esac \
+ done
+ touch tmp-run-multi
+
clean-extra:
rm -f $(BUILT_SRC_FROM_GEN)
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f $(BUILT_SRC_FROM_M16)
+ rm -f $(BUILT_SRC_FROM_MULTI)
rm -f tmp-*
rm -f m16*.o m32*.o itable*.o
+ distclean-extra:
+ rm -f multi-include.h multi-run.c
Index: mips/sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.h,v
retrieving revision 1.23
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.23 sim-main.h
*** mips/sim-main.h 14 Jun 2002 18:49:09 -0000 1.23
--- mips/sim-main.h 26 Nov 2002 12:29:37 -0000
*************** #include "sim-basics.h"
*** 41,47 ****
typedef address_word sim_cia;
#include "sim-base.h"
!
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
--- 41,47 ----
typedef address_word sim_cia;
#include "sim-base.h"
! #include "bfd.h"
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
*************** void mips_cpu_exception_trigger(SIM_DESC
*** 950,955 ****
--- 950,961 ----
void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
+ #ifdef MIPS_MACH_MULTI
+ extern int mips_mach_multi(SIM_DESC sd);
+ #define MIPS_MACH(SD) mips_mach_multi(SD)
+ #else
+ #define MIPS_MACH(SD) MIPS_MACH_DEFAULT
+ #endif
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
#include "sim-main.c"
Index: mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.49
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.49 mips.igen
*** mips/mips.igen 31 Jul 2002 05:44:54 -0000 1.49
--- mips/mips.igen 26 Nov 2002 12:29:37 -0000
***************
*** 55,61 ****
--- 55,64 ----
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
+ :model:::vr4120:mips4120:
:model:::vr5000:mips5000:
+ :model:::vr5400:mips5400:
+ :model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
*************** #endif
*** 229,234 ****
--- 232,240 ----
:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
{
+ /* There are no timing requirements in vr5500 code. */
+ if (MIPS_MACH (SD) == bfd_mach_mips5500)
+ return 1;
if (history->mf.timestamp + 3 > time)
{
sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
*************** 011100,5.RS,5.RT,5.RD,00000,100001:SPECI
*** 1010,1015 ****
--- 1016,1022 ----
"clo r<RD>, r<RS>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
*************** 011100,5.RS,5.RT,5.RD,00000,100000:SPECI
*** 1034,1039 ****
--- 1041,1047 ----
"clz r<RD>, r<RS>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
*************** 000000,5.RS,5.RT,5.RD,00000,101101:SPECI
*** 1143,1148 ****
--- 1151,1157 ----
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
+ *vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
*************** 011100,5.RS,5.RT,5.RD,00000,100101:SPECI
*** 1166,1171 ****
--- 1175,1181 ----
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
+ *vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
*************** 011100,5.RS,5.RT,00000,00000,000000:SPEC
*** 2189,2194 ****
--- 2199,2205 ----
"madd r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
*************** 011100,5.RS,5.RT,00000,00000,000001:SPEC
*** 2208,2213 ****
--- 2219,2225 ----
"maddu r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
*************** 011100,5.RS,5.RT,00000,00000,000100:SPEC
*** 2312,2317 ****
--- 2324,2330 ----
"msub r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
*************** 011100,5.RS,5.RT,00000,00000,000101:SPEC
*** 2331,2336 ****
--- 2344,2350 ----
"msubu r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
*************** 011100,5.RS,5.RT,5.RD,00000,000010:SPECI
*** 2388,2393 ****
--- 2402,2408 ----
"mul r<RD>, r<RS>, r<RT>"
*mips32:
*mips64:
+ *vr5500:
{
signed64 prod;
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Index: mips/vr.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/vr.igen,v
retrieving revision 1.1.1.1
diff -c -d -p -F^[(a-zA-Z0-9_^#] -r1.1.1.1 vr.igen
*** mips/vr.igen 16 Apr 1999 01:35:07 -0000 1.1.1.1
--- mips/vr.igen 26 Nov 2002 12:29:37 -0000
***************
*** 3,78 ****
// NEC specific instructions
//
! // Integer Instructions
! // --------------------
! //
! // MulAcc is the Multiply Accumulator.
! // This register is mapped on the the HI and LO registers.
! // Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
! // Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
! :function:::unsigned64:MulAcc:
! *vr4100:
{
! unsigned64 result = U8_4 (HI, LO);
! return result;
}
! :function:::void:SET_MulAcc:unsigned64 value
! *vr4100:
{
! /* 64 bit specific */
! *AL4_8 (&HI) = VH4_8 (value);
! *AL4_8 (&LO) = VL4_8 (value);
}
! :function:::signed64:SignedMultiply:signed32 l, signed32 r
! *vr4100:
{
! signed64 result = (signed64) l * (signed64) r;
return result;
}
! :function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
! *vr4100:
{
! unsigned64 result = (unsigned64) l * (unsigned64) r;
return result;
}
! :function:::unsigned64:Low32Bits:unsigned64 value
*vr4100:
{
! unsigned64 result = (signed64) (signed32) VL4_8 (value);
! return result;
}
! :function:::unsigned64:High32Bits:unsigned64 value
*vr4100:
{
! unsigned64 result = (signed64) (signed32) VH4_8 (value);
! return result;
}
! // Multiply, Accumulate
! 000000,5.RS,5.RT,00000,00000,101000::64::MAC
! "mac r<RS>, r<RT>"
! *vr4100:
{
! SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
}
! // D-Multiply, Accumulate
! 000000,5.RS,5.RT,00000,00000,101001::64::DMAC
! "dmac r<RS>, r<RT>"
! *vr4100:
{
! LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
}
--- 3,323 ----
// NEC specific instructions
//
! :%s::::MFHI:int hi
! {
! return hi ? "hi" : "";
! }
+ :%s::::SAT:int s
+ {
+ return s ? "s" : "";
+ }
! :%s::::UNS:int u
{
! return u ? "u" : "";
}
! // Simulate the various kinds of multiply and multiply-accumulate instructions.
! // Perform an operation of the form:
! //
! // LHS (+/-) GPR[RS] * GPR[RT]
! //
! // and store it in the 64-bit accumulator. Optionally copy either LO or
! // HI into a general purpose register.
! //
! // - RD is the destination register of the LO or HI move
! // - RS are RT are the multiplication source registers
! // - ACCUMULATE_P is true if LHS should be the value of the 64-bit accumulator,
! // false if it should be 0.
! // - STORE_HI_P is true if HI should be stored in RD, false if LO should be.
! // - UNSIGNED_P is true if the operation should be unsigned.
! // - SATURATE_P is true if the result should be saturated to a 32-bit value.
! // - SUBTRACT_P is true if the right hand side should be subtraced from LHS,
! // false if it should be added.
! // - SHORT_P is true if RS and RT must be 16-bit numbers.
! // - DOUBLE_P is true if the 64-bit accumulator is in LO, false it is a
! // concatenation of the low 32 bits of HI and LO.
! :function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p
{
! unsigned64 lhs, x, y, xcut, ycut, product, result;
!
! check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
!
! lhs = (!accumulate_p ? 0 : double_p ? LO : U8_4 (HI, LO));
! x = GPR[rs];
! y = GPR[rt];
!
! /* Work out the canonical form of X and Y from their significant bits. */
! if (!short_p)
! {
! /* Normal sign-extension rule for 32-bit operands. */
! xcut = EXTEND32 (x);
! ycut = EXTEND32 (y);
! }
! else if (unsigned_p)
! {
! /* Operands must be zero-extended 16-bit numbers. */
! xcut = x & 0xffff;
! ycut = y & 0xffff;
! }
! else
! {
! /* Likewise but sign-extended. */
! xcut = EXTEND16 (x);
! ycut = EXTEND16 (y);
! }
! if (x != xcut || y != ycut)
! sim_engine_abort (SD, CPU, CIA,
! "invalid multiplication operand at 0x%08lx\n",
! (long) CIA);
!
! TRACE_ALU_INPUT2 (x, y);
! product = (unsigned_p ? x * y : EXTEND32 (x) * EXTEND32 (y));
! result = (subtract_p ? lhs - product : lhs + product);
! if (saturate_p)
! {
! /* Saturate the result to 32 bits. An unsigned, unsaturated
! result is zero-extended to 64 bits, but unsigned overflow
! causes all 64 bits to be set. */
! if (!unsigned_p && (unsigned64) EXTEND32 (result) != result)
! result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff);
! else if (unsigned_p && (result >> 32) != 0)
! result = (unsigned64) 0 - 1;
! }
! TRACE_ALU_RESULT (result);
!
! if (double_p)
! LO = result;
! else
! {
! LO = EXTEND32 (result);
! HI = EXTEND32 (VH4_8 (result));
! }
! if (rd != 0)
! GPR[rd] = store_hi_p ? HI : LO;
}
! // 32-bit rotate right of X by Y bits.
! :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
! *vr5400:
! *vr5500:
{
! unsigned64 result;
!
! y &= 31;
! TRACE_ALU_INPUT2 (x, y);
! result = EXTEND32 (ROTR32 (x, y));
! TRACE_ALU_RESULT (result);
return result;
}
! // Likewise 64-bit
! :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
! *vr5400:
! *vr5500:
{
! unsigned64 result;
!
! y &= 63;
! TRACE_ALU_INPUT2 (x, y);
! result = ROTR64 (x, y);
! TRACE_ALU_RESULT (result);
return result;
}
!
! // VR4100 instructions.
!
! 000000,5.RS,5.RT,00000,00000,101000::32::MADD16
! "madd16 r<RS>, r<RT>"
*vr4100:
{
! do_vr_mul_op (SD_, 0, RS, RT,
! 1 /* accumulate */,
! 0 /* store in LO */,
! 0 /* signed arithmetic */,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 1 /* short */,
! 0 /* single */);
}
! 000000,5.RS,5.RT,00000,00000,101001::64::DMADD16
! "dmadd16 r<RS>, r<RT>"
*vr4100:
{
! do_vr_mul_op (SD_, 0, RS, RT,
! 1 /* accumulate */,
! 0 /* store in LO */,
! 0 /* signed arithmetic */,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 1 /* short */,
! 1 /* double */);
}
! // VR4120 and VR4130 instructions.
!
! 000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101001::64::DMACC
! "dmacc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
! *vr4120:
{
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS, SAT,
! 0 /* don't subtract */,
! SAT /* short */,
! 1 /* double */);
! }
!
! 000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101000::32::MACC_4120
! "macc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
! *vr4120:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS, SAT,
! 0 /* don't subtract */,
! SAT /* short */,
! 0 /* single */);
}
! // VR5400 and VR5500 instructions.
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,001,01100,1.UNS::32::MUL
! "mul%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
{
! do_vr_mul_op (SD_, RD, RS, RT,
! 0 /* don't accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,011,01100,1.UNS::32::MULS
! "muls%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 0 /* don't accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 1 /* subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,101,01100,1.UNS::32::MACC_5xxx
! "macc%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 0 /* don't subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,5.RS,5.RT,5.RD,0,1.MFHI,111,01100,1.UNS::32::MSAC
! "msac%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
! *vr5400:
! *vr5500:
! {
! do_vr_mul_op (SD_, RD, RS, RT,
! 1 /* accumulate */,
! MFHI, UNS,
! 0 /* don't saturate */,
! 1 /* subtract */,
! 0 /* not short */,
! 0 /* single */);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
! "ror r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
! }
!
! 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
! "rorv r<RD>, r<RT>, r<RS>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
! "dror r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
! }
!
! 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
! "dror32 r<RD>, r<RT>, <SHIFT>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
! }
!
! 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
! "drorv r<RD>, r<RT>, r<RS>"
! *vr5400:
! *vr5500:
! {
! GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
! }
!
! 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1
! "luxc1 f<FD>, r<INDEX>(r<BASE>)"
! *vr5500:
! {
! check_fpu (SD_);
! COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD,
! (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0));
! }
!
! 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64::SUXC1
! "suxc1 f<FS>, r<INDEX>(r<BASE>)"
! *vr5500:
! {
! check_fpu (SD_);
! do_store (SD_, AccessLength_DOUBLEWORD,
! (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0,
! COP_SD (1, FS));
}
+ 010000,1,19.*,100000:COP0:32::WAIT
+ "wait"
+ *vr5500:
+
+ 011100,00000,5.RT,5.DR,00000,111101:SPECIAL:64::MFDR
+ "mfdr r<RT>, r<DR>"
+ *vr5400:
+ *vr5500:
+ 011100,00100,5.RT,5.DR,00000,111101:SPECIAL:64::MTDR
+ "mtdr r<RT>, r<DR>"
+ *vr5400:
+ *vr5500:
+ 011100,00000,00000,00000,00000,111110:SPECIAL:64::DRET
+ "dret"
+ *vr5400:
+ *vr5500:
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
[not found] ` <mailpost.1038314670.25092@news-sj1-1>
@ 2002-11-26 12:49 ` cgd
0 siblings, 0 replies; 22+ messages in thread
From: cgd @ 2002-11-26 12:49 UTC (permalink / raw)
To: rsandifo; +Cc: gdb-patches
At Tue, 26 Nov 2002 12:44:30 +0000 (UTC), "Richard Sandiford" wrote:
> cgd@broadcom.com writes:
> > My patch, below, drops down on top of yours, with the following
> > effect:
> >
> > * no new multi-run.c src.
> >
> > * multi-run.c generated in its entirety by configure.in, to provide
> > functions: sim_engine_run, and mips_mach_multi.
> >
> > * s/MIPS_BFD_MACH/MIPS_MACH/
> >
> > * MIPS_MACH either defined to a hard-coded value from configure.in, or
> > if MULTI to mips_mach_multi() which returns a supported machine
> > type (either the currently selected one).
>
> I tried it, worked fine.
>
> There doesn't seem to have been objection to your last mail, so I
> thought I'd have another stab at getting the stuff accepeted.
> Combined diff below.
Thanks.
This probably still has the issue that there are one or two files that
don't get cleaned out properly, but IMO that can be fixed after
checkin.
I'll check it in tomorrow unless somebody (Andrew 8-) screams "no" or
earlier if he states no-objection. 8-)
chris
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-11-26 4:44 ` Richard Sandiford
[not found] ` <mailpost.1038314670.25092@news-sj1-1>
@ 2002-11-26 16:55 ` Andrew Cagney
[not found] ` <mailpost.1038358543.15485@news-sj1-1>
2003-01-05 7:57 ` cgd
2 siblings, 1 reply; 22+ messages in thread
From: Andrew Cagney @ 2002-11-26 16:55 UTC (permalink / raw)
To: Richard Sandiford, cgd; +Cc: gdb-patches
> :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
> {
> + /* There are no timing requirements in vr5500 code. */
> + if (MIPS_MACH (SD) == bfd_mach_mips5500)
> + return 1;
> if (history->mf.timestamp + 3 > time)
> {
> sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
Just this,
Add:
function:::int:check_mf_cycles:hilo_history *history, signed64 time,
const char *new
*vr5500
{
return 1;
}
and then tag the old function with the other CPU variants.
that way
if (MIPS_MACH (SD) == bfd_mach_mips5500)
is not needed and the compiler can (if configured with sufficient
inlining) eliminate the entire function call.
This post:
http://sources.redhat.com/ml/gdb-patches/2002-11/msg00512.html
> We have had very bad experiences with trying to make a single function
> serve two different ABI's in the past. (mips_push_arguments seems to
> have been cleaned up since I last looked; it was a real mess.) So
> while using things like 'REGISTER_SIZE' and
> 'S390_STACK_PARAMETER_ALIGNMENT' are clearly a good idea, for the sake
> of the other stuff I'd like to see a separate 's390x_push_arguments'
> function written that does things right for the s390x's ABI. The
> helper functions like `is_simple_arg' should be duplicated, rather
> than testing GDB_TARGET_IS_ESAME.
Gives the thrust of the rationale. Namely, its better to, from the
start, have separate independant functions and not confuse things by
adding more and more if(ISA/ABI) specific gunk. As JimB noted, the MIPS
is the not so shining example of how to do things (i.e., how things can
go wrong).
For the sim, the original gencode tried to be smart and combine isa
variants. Given the age of the code, the number of CPU variants, and
the number of developers making changes (the two are comparable and both
are large!), it ended to end up with a total mess. Someone trying to
add one ISA would [always, I'm pretty sure it was] broke the other ISAs
(only discovered months later) by either also adding instructions to
other ISAs or, worse, removing/changing existing instructions. Ulgh!
IGEN and MIPS.IGEN gave up.
Instead, the developer gets to spend a few minutes adding an ISA
selector to every relevant instruction. That's in the noise when
compared to the amount of time that needs to be spent auding the
instruction set looking for where the vendor has an instruction variant
that deviates from the official spec (how many mul/adds are there?). In
the case of a variant, the instruction can cloned, taged and changed
with the absolute certaintity that it won't break any other instruction,
because none of the other instructions / ISAs are affected.
So, while this might sux from an asthetic point of view, it definitly
doesn't sux from the point of view of being able to confidently, quickly
and reliably update the simulator.
(cgd, does this answer your question?)
Andrew
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
[not found] ` <mailpost.1038358543.15485@news-sj1-1>
@ 2002-11-26 17:48 ` cgd
2002-11-26 19:10 ` Andrew Cagney
0 siblings, 1 reply; 22+ messages in thread
From: cgd @ 2002-11-26 17:48 UTC (permalink / raw)
To: ac131313; +Cc: Richard Sandiford, gdb-patches
At Wed, 27 Nov 2002 00:55:43 +0000 (UTC), "Andrew Cagney" wrote:
> > :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
> > {
> > + /* There are no timing requirements in vr5500 code. */
> > + if (MIPS_MACH (SD) == bfd_mach_mips5500)
> > + return 1;
> > if (history->mf.timestamp + 3 > time)
> > {
> > sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
>
> Just this,
>
> Add:
>
> function:::int:check_mf_cycles:hilo_history *history, signed64 time,
> const char *new
> *vr5500
> {
> return 1;
> }
>
> and then tag the old function with the other CPU variants.
So, if you do this, then the old function will be tagged... well,
mipsIV at least, right?
And then given the way this patch invokes igen for multi-arch sims,
AFAIK _both_ this check_mf_cycles and the 'other' check_mf_cycles will
be included.
So, if you want to go this route, really, you have to add vr5500 to
every bloody mipsIV instruction.
> that way
> if (MIPS_MACH (SD) == bfd_mach_mips5500)
> is not needed and the compiler can (if configured with sufficient
> inlining) eliminate the entire function call.
FWIW, if configured with sufficient inlining and for a single arch,
even with the check it could do that i believe.
Like i said before, I don't think it's that important to squeeze the
last bit of speed out, for people building multi-arch sims.
> This post:
>
> http://sources.redhat.com/ml/gdb-patches/2002-11/msg00512.html
> > We have had very bad experiences with trying to make a single function
> > serve two different ABI's in the past. (mips_push_arguments seems to
> > have been cleaned up since I last looked; it was a real mess.) So
> > while using things like 'REGISTER_SIZE' and
> > 'S390_STACK_PARAMETER_ALIGNMENT' are clearly a good idea, for the sake
> > of the other stuff I'd like to see a separate 's390x_push_arguments'
> > function written that does things right for the s390x's ABI. The
> > helper functions like `is_simple_arg' should be duplicated, rather
> > than testing GDB_TARGET_IS_ESAME.
>
> Gives the thrust of the rationale. Namely, its better to, from the
> start, have separate independant functions and not confuse things by
> adding more and more if(ISA/ABI) specific gunk. As JimB noted, the MIPS
> is the not so shining example of how to do things (i.e., how things can
> go wrong).
Looked at another way, this means that you replace a single explicit
"if (ISA)" check in this case with ... dozens or hundreds of implicit
checks (the implied check being inclusion or not, for the given
architecture).
If what you really have is common code with 3 exceptions, i'd rather
see three exceptions.
> For the sim, the original gencode tried to be smart and combine isa
> variants. Given the age of the code, the number of CPU variants, and
> the number of developers making changes (the two are comparable and both
> are large!), it ended to end up with a total mess. Someone trying to
> add one ISA would [always, I'm pretty sure it was] broke the other ISAs
> (only discovered months later) by either also adding instructions to
> other ISAs or, worse, removing/changing existing instructions. Ulgh!
>
> IGEN and MIPS.IGEN gave up.
I agree that it's a potential problem, but to my mind there are two
solutions to the problem, one of which has to be applied to get
"quick, reliable" updates to the simulator:
* never, ever change the existing code. (The possible exception here
is "obvious" fixes, but, well, if you don't test them then you can
still screw them up.)
* more, and more complete testing, to find the brokenness.
What you're advocating, to my mind, boils down the former: duplicate
code then modify it, use the duplicated code or if you want to
duplicate again and modify again, etc.
I think that will lead to monstroustly bad maintainability.
(BTW, I don't actually think that the ABI comparison is a good one.)
> Instead, the developer gets to spend a few minutes adding an ISA
> selector to every relevant instruction. That's in the noise when
> compared to the amount of time that needs to be spent auding the
> instruction set looking for where the vendor has an instruction variant
> that deviates from the official spec (how many mul/adds are there?). In
> the case of a variant, the instruction can cloned, taged and changed
> with the absolute certaintity that it won't break any other instruction,
> because none of the other instructions / ISAs are affected.
Where "relevant" is like virtual: just delete it from the sentence,
and you keep the same meaning. 8-)
I agree with your argument for "standard ISA with instructions
removed" processors.
However, i don't see that there's ANY reason that if 17 different
processors add madd to mipsIII, each mipsIII instruction should have
to be tagged with all of those 17 different ISA names.
Certainly, I wouldn't want to be working in the resulting code base.
> So, while this might sux from an asthetic point of view, it definitly
> doesn't sux from the point of view of being able to confidently, quickly
> and reliably update the simulator.
I think the only way you can have that is to build it and test it and
build it more and test it more.
Otherwise, i can't see how you're not afraid of making any change to
existing code.
I'm willing to break some eggs to make an omelete, here; i've got
substantial work that i'd still like to see in the mips sim, and i'm
quite sure that in getting it in i'll break (more 8-) things.
If the goal here is to absolutely minimize potential code breakage,
and as a result of that a decision is made either to not substantially
enhance the code, or to produce IMO "nasty" unmaintainable
code... that doesn't seem like a positive thing, to me.
> (cgd, does this answer your question?)
Not really. 8-)
First of all i'm not sure which question you were trying to answer,
even (today's, i.e. "veto, anyone?" or a previous question).
Is your intent here to say that really, "the mips sim will/must be
done the way you outline above," or is it to provide a rationale for
why you think it should be done that way. (to my mind, it could be
either; you're a mips sim maintainer long before i got here.)
Based on what you've said above, I still don't agree that your
suggested way of doing this is the right one.
chris
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-11-26 17:48 ` cgd
@ 2002-11-26 19:10 ` Andrew Cagney
[not found] ` <mailpost.1038366650.19029@news-sj1-1>
0 siblings, 1 reply; 22+ messages in thread
From: Andrew Cagney @ 2002-11-26 19:10 UTC (permalink / raw)
To: cgd; +Cc: Richard Sandiford, gdb-patches
> Not really. 8-)
>
> First of all i'm not sure which question you were trying to answer,
> even (today's, i.e. "veto, anyone?" or a previous question).
>
> Is your intent here to say that really, "the mips sim will/must be
> done the way you outline above," or is it to provide a rationale for
> why you think it should be done that way. (to my mind, it could be
> either; you're a mips sim maintainer long before i got here.)
This is the way it has (ment to) been done for all MIPS ISA variants
since igen replaced gencode. You've proposed a change to that process
so I'm [trying to] explain the rationale behind the current status-quo :-)
Andrew
> Based on what you've said above, I still don't agree that your
> suggested way of doing this is the right one.
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
[not found] ` <mailpost.1038366650.19029@news-sj1-1>
@ 2002-12-03 9:17 ` cgd
2002-12-03 9:35 ` Andrew Cagney
0 siblings, 1 reply; 22+ messages in thread
From: cgd @ 2002-12-03 9:17 UTC (permalink / raw)
To: ac131313; +Cc: Richard Sandiford, gdb-patches
At Wed, 27 Nov 2002 03:10:50 +0000 (UTC), "Andrew Cagney" wrote:
> This is the way it has (ment to) been done for all MIPS ISA variants
> since igen replaced gencode. You've proposed a change to that process
> so I'm [trying to] explain the rationale behind the current status-quo :-)
Ahh. OK, I misinterpreted what you were trying to say.
So, all of that having been said, do you have strong objections to
proceeding in the "new way" as described here in previous messages?
(You have the right automatically reserved to tell me "I told you so"
if it turns out to be impractical. 8-)
chris
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-12-03 9:17 ` cgd
@ 2002-12-03 9:35 ` Andrew Cagney
0 siblings, 0 replies; 22+ messages in thread
From: Andrew Cagney @ 2002-12-03 9:35 UTC (permalink / raw)
To: cgd; +Cc: Richard Sandiford, gdb-patches
> At Wed, 27 Nov 2002 03:10:50 +0000 (UTC), "Andrew Cagney" wrote:
>
>> This is the way it has (ment to) been done for all MIPS ISA variants
>> since igen replaced gencode. You've proposed a change to that process
>> so I'm [trying to] explain the rationale behind the current status-quo :-)
>
>
> Ahh. OK, I misinterpreted what you were trying to say.
>
> So, all of that having been said, do you have strong objections to
> proceeding in the "new way" as described here in previous messages?
>
> (You have the right automatically reserved to tell me "I told you so"
> if it turns out to be impractical. 8-)
If the function is going to contain:
if (TARGET_ARCH (SD) == ...)
then I don't think it should be in the .igen file (i.e., put it
somewhere else as is done with the FP code (where I can't see it :-)).
The .igen files have a mechanism for differentiating between
architecures, so I don't think that file should be confused by using a
second mechanism. If igen ever gets finished (the C code is replaced by
a language parser) then the simpler that language is the better. Part
of that simplicity is avoiding dependencies on SD / sim-main.h like the
plague :-)
As for having to tag each individual entry in the .igen file with an
explicit CPU. Yes, that sux. However, I also believe that it has
significantly reduced the overall error rate (no more breaking one
target by editing another) and that benefit vastly outweighs the short
term pain.
Andrew
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2002-11-26 4:44 ` Richard Sandiford
[not found] ` <mailpost.1038314670.25092@news-sj1-1>
2002-11-26 16:55 ` Andrew Cagney
@ 2003-01-05 7:57 ` cgd
2003-01-05 11:51 ` Richard Sandiford
2 siblings, 1 reply; 22+ messages in thread
From: cgd @ 2003-01-05 7:57 UTC (permalink / raw)
To: Richard Sandiford; +Cc: gdb-patches
Richard,
At 26 Nov 2002 12:44:14 +0000, Richard Sandiford wrote:
> There doesn't seem to have been objection to your last mail, so I
> thought I'd have another stab at getting the stuff accepeted.
> Combined diff below.
I believe there are two relatively minor issues with this patch
remaining:
* Andrew wants to avoid explicit architecture checks in the mips.igen
file. That seems sensible enough, I guess. Without the code in
mips.igen:check_mf_cycles that he objects to, the vr5500 won't work
correctly but the rest of the new architectures being added should.
I've mentioned previously to you that i'd look into this. I've not
yet had much time yet, but hope to in the next week or two.
* I believe that there are still a couple of files not cleaned
properly by 'make distclean'.
Could you look into this?
I've checked in the rest (i.e., all but the change to
mips.igen:check_mf_cycles). The actual diff I applied is below.
cgd
--
2003-01-04 Richard Sandiford <rsandifo@redhat.com>
Andrew Cagney <ac131313@redhat.com>
Gavin Romig-Koch <gavin@redhat.com>
Graydon Hoare <graydon@redhat.com>
Aldy Hernandez <aldyh@redhat.com>
Dave Brolley <brolley@redhat.com>
Chris Demetriou <cgd@broadcom.com>
* configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
(sim_mach_default): New variable.
(mips64vr-*-*, mips64vrel-*-*): New configurations.
Add a new simulator generator, MULTI.
* configure: Regenerate.
* Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
(multi-run.o): New dependency.
(SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
(tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
(tmp-multi): Combine them.
(BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi.
(clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
(distclean-extra): New rule.
* sim-main.h: Include bfd.h.
(MIPS_MACH): New macro.
* mips.igen (vr4120, vr5400, vr5500): New models.
(clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
* vr.igen: Replace with new version.
Index: Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mips/Makefile.in,v
retrieving revision 1.7
diff -u -p -r1.7 Makefile.in
--- Makefile.in 14 Jun 2002 18:49:09 -0000 1.7
+++ Makefile.in 5 Jan 2003 07:15:03 -0000
@@ -33,6 +33,7 @@ SIM_M16_OBJ = \
itable.o \
m16run.o \
+SIM_MULTI_OBJ = itable.o @sim_multi_obj@
MIPS_EXTRA_OBJS = @mips_extra_objs@
MIPS_EXTRA_LIBS = @mips_extra_libs@
@@ -57,6 +58,7 @@ SIM_SUBTARGET=@SIM_SUBTARGET@
SIM_EXTRA_CFLAGS = $(SIM_SUBTARGET)
SIM_EXTRA_CLEAN = clean-extra
+SIM_EXTRA_DISTCLEAN = distclean-extra
SIM_EXTRA_ALL = $(SIM_@sim_gen@_ALL)
@@ -74,6 +76,8 @@ cp1.o: $(srcdir)/cp1.c config.h sim-main
mdmx.o: $(srcdir)/mdmx.c $(srcdir)/sim-main.h
+multi-run.o: multi-include.h tmp-mach-multi
+
../igen/igen:
cd ../igen && $(MAKE)
@@ -98,6 +102,7 @@ BUILT_SRC_FROM_GEN = \
SIM_IGEN_ALL = tmp-igen
SIM_M16_ALL = tmp-m16
+SIM_MULTI_ALL = tmp-multi
$(BUILT_SRC_FROM_GEN): $(SIM_@sim_gen@_ALL)
@@ -291,10 +296,99 @@ tmp-m16: $(IGEN_INSN) $(IGEN_DC) ../igen
touch tmp-m16
+BUILT_SRC_FROM_MULTI = @sim_multi_src@
+SIM_MULTI_IGEN_CONFIGS = @sim_multi_igen_configs@
+
+$(BUILT_SRC_FROM_MULTI): tmp-multi
+tmp-multi: tmp-mach-multi tmp-itable-multi tmp-run-multi targ-vals.h
+tmp-mach-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+ for t in $(SIM_MULTI_IGEN_CONFIGS); do \
+ p=`echo $${t} | sed -e 's/:.*//'` ; \
+ m=`echo $${t} | sed -e 's/.*:\(.*\):.*/\1/'` ; \
+ f=`echo $${t} | sed -e 's/.*://'` ; \
+ case $${p} in \
+ m16*) e="-B 16 -H 15 -o $(M16_DC) -F 16" ;; \
+ *) e="-B 32 -H 31 -o $(IGEN_DC) -F $${f}" ;; \
+ esac; \
+ ../igen/igen \
+ $(IGEN_TRACE) \
+ $${e} \
+ -I $(srcdir) \
+ -Werror \
+ -Wnodiscard \
+ -N 0 \
+ -M $${m} \
+ -G gen-direct-access \
+ -G gen-zero-r0 \
+ -i $(IGEN_INSN) \
+ -P $${p}_ \
+ -x \
+ -n $${p}_icache.h -hc tmp-icache.h \
+ -n $${p}_icache.c -c tmp-icache.c \
+ -n $${p}_semantics.h -hs tmp-semantics.h \
+ -n $${p}_semantics.c -s tmp-semantics.c \
+ -n $${p}_idecode.h -hd tmp-idecode.h \
+ -n $${p}_idecode.c -d tmp-idecode.c \
+ -n $${p}_model.h -hm tmp-model.h \
+ -n $${p}_model.c -m tmp-model.c \
+ -n $${p}_support.h -hf tmp-support.h \
+ -n $${p}_support.c -f tmp-support.c \
+ -n $${p}_engine.h -he tmp-engine.h \
+ -n $${p}_engine.c -e tmp-engine.c \
+ ; \
+ $(srcdir)/../../move-if-change tmp-icache.h $${p}_icache.h ; \
+ $(srcdir)/../../move-if-change tmp-icache.c $${p}_icache.c ; \
+ $(srcdir)/../../move-if-change tmp-idecode.h $${p}_idecode.h ; \
+ $(srcdir)/../../move-if-change tmp-idecode.c $${p}_idecode.c ; \
+ $(srcdir)/../../move-if-change tmp-semantics.h $${p}_semantics.h ; \
+ $(srcdir)/../../move-if-change tmp-semantics.c $${p}_semantics.c ; \
+ $(srcdir)/../../move-if-change tmp-model.h $${p}_model.h ; \
+ $(srcdir)/../../move-if-change tmp-model.c $${p}_model.c ; \
+ $(srcdir)/../../move-if-change tmp-support.h $${p}_support.h ; \
+ $(srcdir)/../../move-if-change tmp-support.c $${p}_support.c ; \
+ $(srcdir)/../../move-if-change tmp-engine.h $${p}_engine.h ; \
+ $(srcdir)/../../move-if-change tmp-engine.c $${p}_engine.c ; \
+ done
+ touch tmp-mach-multi
+tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC) ../igen/igen $(IGEN_INCLUDE)
+ ../igen/igen \
+ $(IGEN_TRACE) \
+ -I $(srcdir) \
+ -Werror \
+ -Wnodiscard \
+ -Wnowidth \
+ -N 0 \
+ @sim_multi_flags@ \
+ -G gen-direct-access \
+ -G gen-zero-r0 \
+ -i $(IGEN_INSN) \
+ -n itable.h -ht tmp-itable.h \
+ -n itable.c -t tmp-itable.c \
+ #
+ $(srcdir)/../../move-if-change tmp-itable.h itable.h
+ $(srcdir)/../../move-if-change tmp-itable.c itable.c
+ touch tmp-itable-multi
+tmp-run-multi: $(srcdir)/m16run.c
+ for t in $(SIM_MULTI_IGEN_CONFIGS); do \
+ case $${t} in \
+ *:*mips16*:*) \
+ m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
+ sed < $(srcdir)/m16run.c > tmp-run \
+ -e "s/^sim_/m16$${m}_/" \
+ -e "s/m16_/m16$${m}_/" \
+ -e "s/m32_/m32$${m}_/" ; \
+ $(srcdir)/../../move-if-change tmp-run m16$${m}_run.c ; \
+ esac \
+ done
+ touch tmp-run-multi
+
clean-extra:
rm -f $(BUILT_SRC_FROM_GEN)
rm -f $(BUILT_SRC_FROM_IGEN)
rm -f $(BUILT_SRC_FROM_M16)
+ rm -f $(BUILT_SRC_FROM_MULTI)
rm -f tmp-*
rm -f m16*.o m32*.o itable*.o
+distclean-extra:
+ rm -f multi-include.h multi-run.c
Index: configure.in
===================================================================
RCS file: /cvs/src/src/sim/mips/configure.in,v
retrieving revision 1.5
diff -u -p -r1.5 configure.in
--- configure.in 5 Jan 2003 06:13:51 -0000 1.5
+++ configure.in 5 Jan 2003 07:15:03 -0000
@@ -19,6 +19,7 @@ SIM_AC_OPTION_RESERVED_BITS(1)
# in question.
#
case "${target}" in
+ mips64vr*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1" ;;
mips*tx39*) SIM_SUBTARGET="-DSUBTARGET_R3900=1";;
mipsisa32*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
mipsisa64*-*-*) SIM_SUBTARGET="-DTARGET_ENABLE_FR=1";;
@@ -101,6 +102,8 @@ sim_igen_machine="-M mipsIV"
sim_m16_machine="-M mips16"
sim_igen_filter="32,64,f"
sim_m16_filter="16"
+sim_mach_default="mips8000"
+
case "${target}" in
mips*tx39*) sim_gen=IGEN
sim_igen_filter="32,f"
@@ -108,16 +111,29 @@ case "${target}" in
;;
mips64vr43*-*-*) sim_gen=IGEN
sim_igen_machine="-M mipsIV"
+ sim_mach_default="mips8000"
;;
mips64vr5*-*-*) sim_gen=IGEN
sim_igen_machine="-M vr5000"
+ sim_mach_default="mips5000"
;;
mips64vr41*) sim_gen=M16
sim_igen_machine="-M vr4100"
sim_m16_machine="-M vr4100"
sim_igen_filter="32,64,f"
sim_m16_filter="16"
+ sim_mach_default="mips4100"
;;
+ mips64vr-*-* | mips64vrel-*-*)
+ sim_gen=MULTI
+ sim_multi_configs="\
+ vr4100:mipsIII,mips16,vr4100:32,64:mips4100,mips4111\
+ vr4120:mipsIII,mips16,vr4120:32,64:mips4120\
+ vr5000:mipsIV:32,64,f:mips4300,mips5000\
+ vr5400:mipsIV,vr5400:32,64,f:mips5400\
+ vr5500:mipsIV,vr5500:32,64,f:mips5500"
+ sim_multi_default=mips5000
+ ;;
mips64*-*-*) sim_igen_filter="32,64,f"
sim_gen=IGEN
;;
@@ -128,30 +144,241 @@ case "${target}" in
mipsisa32*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips32"
sim_igen_filter="32,f"
+ sim_mach_default="mipsisa32"
;;
mipsisa64sb1*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64,sb1"
sim_igen_filter="32,64,f"
+ sim_mach_default="mips_sb1"
;;
mipsisa64*-*-*) sim_gen=IGEN
sim_igen_machine="-M mips64,mips3d"
sim_igen_filter="32,64,f"
+ sim_mach_default="mipsisa64"
;;
mips*lsi*) sim_gen=M16
sim_igen_machine="-M mipsIII,mips16"
sim_m16_machine="-M mips16,mipsIII"
sim_igen_filter="32,f"
sim_m16_filter="16"
+ sim_mach_default="mips4000"
;;
mips*-*-*) sim_gen=IGEN
sim_igen_filter="32,f"
;;
esac
+
+# The MULTI generator can combine several simulation engines into one.
+# executable. A configuration which uses the MULTI should set two
+# variables: ${sim_multi_configs} and ${sim_multi_default}.
+#
+# ${sim_multi_configs} is the list of engines to build. Each
+# space-separated entry has the form NAME:MACHINE:FILTER:BFDMACHS,
+# where:
+#
+# - NAME is a C-compatible prefix for the engine,
+# - MACHINE is a -M argument,
+# - FILTER is a -F argument, and
+# - BFDMACHS is a comma-separated list of bfd machines that the
+# simulator can run.
+#
+# Each entry will have a separate simulation engine whose prefix is
+# m32<NAME>. If the machine list includes "mips16", there will also
+# be a mips16 engine, prefix m16<NAME>. The mips16 engine will be
+# generated using the same machine list as the 32-bit version,
+# but the filter will be "16" instead of FILTER.
+#
+# The simulator compares the bfd mach against BFDMACHS to decide
+# which engine to use. Entries in BFDMACHS should be bfd_mach
+# values with "bfd_mach_" removed. ${sim_multi_default} says
+# which entry should be the default.
+if test ${sim_gen} = MULTI; then
+
+ # Simple sanity check.
+ if test -z "${sim_multi_configs}" || test -z "${sim_multi_default}"; then
+ AC_MSG_ERROR(Error in configure.in: MULTI simulator not set up correctly)
+ fi
+
+ # Start in a known state.
+ rm -f multi-include.h multi-run.c
+ sim_multi_flags=
+ sim_multi_src=
+ sim_multi_obj=multi-run.o
+ sim_multi_igen_configs=
+ sim_seen_default=no
+
+ cat << __EOF__ > multi-run.c
+/* Main entry point for MULTI simulators.
+ Copyright (C) 2003 Free Software Foundation, Inc.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ --
+
+ This file was generated by sim/mips/configure. */
+
+#include "sim-main.h"
+#include "multi-include.h"
+
+#define SD sd
+#define CPU cpu
+
+void
+sim_engine_run (SIM_DESC sd,
+ int next_cpu_nr,
+ int nr_cpus,
+ int signal) /* ignore */
+{
+ int mach;
+
+ if (STATE_ARCHITECTURE (sd) == NULL)
+ mach = bfd_mach_${sim_multi_default};
+ else
+ mach = STATE_ARCHITECTURE (SD)->mach;
+
+ switch (mach)
+ {
+__EOF__
+
+ for fc in ${sim_multi_configs}; do
+
+ # Split up the entry. ${c} contains the first three elements.
+ # Note: outer sqaure brackets are m4 quotes.
+ c=`echo ${fc} | sed ['s/:[^:]*$//']`
+ bfdmachs=`echo ${fc} | sed 's/.*://'`
+ name=`echo ${c} | sed 's/:.*//'`
+ machine=`echo ${c} | sed 's/.*:\(.*\):.*/\1/'`
+ filter=`echo ${c} | sed 's/.*://'`
+
+ # Build the following lists:
+ #
+ # sim_multi_flags: all -M and -F flags used by the simulator
+ # sim_multi_src: all makefile-generated source files
+ # sim_multi_obj: the objects for ${sim_multi_src}
+ # sim_multi_igen_configs: igen configuration strings.
+ #
+ # Each entry in ${sim_multi_igen_configs} is a prefix (m32
+ # or m16) followed by the NAME, MACHINE and FILTER part of
+ # the ${sim_multi_configs} entry.
+ sim_multi_flags="${sim_multi_flags} -F ${filter} -M ${machine}"
+
+ # Check whether mips16 handling is needed.
+ case ${c} in
+ *:*mips16*:*)
+ # Run igen twice, once for normal mode and once for mips16.
+ ws="m32 m16"
+
+ # The top-level function for the mips16 simulator is
+ # in a file m16${name}_run.c, generated by the
+ # tmp-run-multi Makefile rule.
+ sim_multi_src="${sim_multi_src} m16${name}_run.c"
+ sim_multi_obj="${sim_multi_obj} m16${name}_run.o"
+ sim_multi_flags="${sim_multi_flags} -F 16"
+ ;;
+ *)
+ ws=m32
+ ;;
+ esac
+
+ # Now add the list of igen-generated files to ${sim_multi_src}
+ # and ${sim_multi_obj}.
+ for w in ${ws}; do
+ for base in engine icache idecode model semantics support; do
+ sim_multi_src="${sim_multi_src} ${w}${name}_${base}.c"
+ sim_multi_src="${sim_multi_src} ${w}${name}_${base}.h"
+ sim_multi_obj="${sim_multi_obj} ${w}${name}_${base}.o"
+ done
+ sim_multi_igen_configs="${sim_multi_igen_configs} ${w}${c}"
+ done
+
+ # Add an include for the engine.h file. This file declares the
+ # top-level foo_engine_run() function.
+ echo "#include \"${w}${name}_engine.h\"" >> multi-include.h
+
+ # Add case statements for this engine to sim_engine_run().
+ for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
+ echo " case bfd_mach_${mach}:" >> multi-run.c
+ if test ${mach} = ${sim_multi_default}; then
+ echo " default:" >> multi-run.c
+ sim_seen_default=yes
+ fi
+ done
+ echo " ${w}${name}_engine_run (sd, next_cpu_nr, nr_cpus, signal);" \
+ >> multi-run.c
+ echo " break;" >> multi-run.c
+ done
+
+ # Check whether we added a 'default:' label.
+ if test ${sim_seen_default} = no; then
+ AC_MSG_ERROR(Error in configure.in: \${sim_multi_configs} doesn't have an entry for \${sim_multi_default})
+ fi
+
+ cat << __EOF__ >> multi-run.c
+ }
+}
+
+int
+mips_mach_multi (SIM_DESC sd)
+{
+ if (STATE_ARCHITECTURE (sd) == NULL)
+ return bfd_mach_${sim_multi_default};
+
+ switch (STATE_ARCHITECTURE (SD)->mach)
+ {
+__EOF__
+
+ # Add case statements for this engine to mips_mach_multi().
+ for fc in ${sim_multi_configs}; do
+
+ # Split up the entry. ${c} contains the first three elements.
+ # Note: outer sqaure brackets are m4 quotes.
+ c=`echo ${fc} | sed ['s/:[^:]*$//']`
+ bfdmachs=`echo ${fc} | sed 's/.*://'`
+
+ for mach in `echo ${bfdmachs} | sed 's/,/ /g'`; do
+ echo " case bfd_mach_${mach}:" >> multi-run.c
+ done
+ done
+
+ cat << __EOF__ >> multi-run.c
+ return (STATE_ARCHITECTURE (SD)->mach);
+ default:
+ return bfd_mach_${sim_multi_default};
+ }
+}
+__EOF__
+
+ SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_MULTI"
+else
+ # For clean-extra
+ sim_multi_src=doesnt-exist.c
+
+ if test x"${sim_mach_default}" = x""; then
+ AC_MSG_ERROR(Error in configure.in: \${sim_mach_default} not defined)
+ fi
+ SIM_SUBTARGET="$SIM_SUBTARGET -DMIPS_MACH_DEFAULT=bfd_mach_${sim_mach_default}"
+fi
sim_igen_flags="-F ${sim_igen_filter} ${sim_igen_machine} ${sim_igen_smp}"
sim_m16_flags=" -F ${sim_m16_filter} ${sim_m16_machine} ${sim_igen_smp}"
AC_SUBST(sim_igen_flags)
AC_SUBST(sim_m16_flags)
AC_SUBST(sim_gen)
+AC_SUBST(sim_multi_flags)
+AC_SUBST(sim_multi_igen_configs)
+AC_SUBST(sim_multi_src)
+AC_SUBST(sim_multi_obj)
#
Index: mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.50
diff -u -p -r1.50 mips.igen
--- mips.igen 31 Dec 2002 21:31:32 -0000 1.50
+++ mips.igen 5 Jan 2003 07:15:03 -0000
@@ -55,7 +55,10 @@
// (or which pre-date or use different encodings than the standard
// instructions) are (for the most part) in separate .igen files.
:model:::vr4100:mips4100: // vr.igen
+:model:::vr4120:mips4120:
:model:::vr5000:mips5000:
+:model:::vr5400:mips5400:
+:model:::vr5500:mips5500:
:model:::r3900:mips3900: // tx.igen
// MIPS Application Specific Extensions (ASEs)
@@ -978,6 +981,7 @@
"clo r<RD>, r<RS>"
*mips32:
*mips64:
+*vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
@@ -1002,6 +1006,7 @@
"clz r<RD>, r<RS>"
*mips32:
*mips64:
+*vr5500:
{
unsigned32 temp = GPR[RS];
unsigned32 i, mask;
@@ -1111,6 +1116,7 @@
011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
"dclo r<RD>, r<RS>"
*mips64:
+*vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
@@ -1134,6 +1140,7 @@
011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
"dclz r<RD>, r<RS>"
*mips64:
+*vr5500:
{
unsigned64 temp = GPR[RS];
unsigned32 i;
@@ -2157,6 +2164,7 @@
"madd r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2176,6 +2184,7 @@
"maddu r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2280,6 +2289,7 @@
"msub r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
signed64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2299,6 +2309,7 @@
"msubu r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
unsigned64 temp;
check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
@@ -2356,6 +2367,7 @@
"mul r<RD>, r<RS>, r<RT>"
*mips32:
*mips64:
+*vr5500:
{
signed64 prod;
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
Index: sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.h,v
retrieving revision 1.24
diff -u -p -r1.24 sim-main.h
--- sim-main.h 31 Dec 2002 21:31:32 -0000 1.24
+++ sim-main.h 5 Jan 2003 07:15:03 -0000
@@ -1,5 +1,5 @@
/* MIPS Simulator definition.
- Copyright (C) 1997, 1998 Free Software Foundation, Inc.
+ Copyright (C) 1997, 1998, 2003 Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of GDB, the GNU debugger.
@@ -41,7 +41,7 @@ mips_core_signal ((SD), (CPU), (CIA), (M
typedef address_word sim_cia;
#include "sim-base.h"
-
+#include "bfd.h"
/* Deprecated macros and types for manipulating 64bit values. Use
../common/sim-bits.h and ../common/sim-endian.h macros instead. */
@@ -946,6 +946,12 @@ void mips_cpu_exception_trigger(SIM_DESC
void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
+#ifdef MIPS_MACH_MULTI
+extern int mips_mach_multi(SIM_DESC sd);
+#define MIPS_MACH(SD) mips_mach_multi(SD)
+#else
+#define MIPS_MACH(SD) MIPS_MACH_DEFAULT
+#endif
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
#include "sim-main.c"
Index: vr.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/vr.igen,v
retrieving revision 1.1.1.1
diff -u -p -r1.1.1.1 vr.igen
--- vr.igen 16 Apr 1999 01:35:07 -0000 1.1.1.1
+++ vr.igen 5 Jan 2003 07:15:03 -0000
@@ -3,76 +3,321 @@
// NEC specific instructions
//
-// Integer Instructions
-// --------------------
-//
-// MulAcc is the Multiply Accumulator.
-// This register is mapped on the the HI and LO registers.
-// Upper 32 bits of MulAcc is mapped on to lower 32 bits of HI register.
-// Lower 32 bits of MulAcc is mapped on to lower 32 bits of LO register.
+:%s::::MFHI:int hi
+{
+ return hi ? "hi" : "";
+}
+:%s::::SAT:int s
+{
+ return s ? "s" : "";
+}
-:function:::unsigned64:MulAcc:
-*vr4100:
+:%s::::UNS:int u
{
- unsigned64 result = U8_4 (HI, LO);
- return result;
+ return u ? "u" : "";
}
-:function:::void:SET_MulAcc:unsigned64 value
-*vr4100:
+// Simulate the various kinds of multiply and multiply-accumulate instructions.
+// Perform an operation of the form:
+//
+// LHS (+/-) GPR[RS] * GPR[RT]
+//
+// and store it in the 64-bit accumulator. Optionally copy either LO or
+// HI into a general purpose register.
+//
+// - RD is the destination register of the LO or HI move
+// - RS are RT are the multiplication source registers
+// - ACCUMULATE_P is true if LHS should be the value of the 64-bit accumulator,
+// false if it should be 0.
+// - STORE_HI_P is true if HI should be stored in RD, false if LO should be.
+// - UNSIGNED_P is true if the operation should be unsigned.
+// - SATURATE_P is true if the result should be saturated to a 32-bit value.
+// - SUBTRACT_P is true if the right hand side should be subtraced from LHS,
+// false if it should be added.
+// - SHORT_P is true if RS and RT must be 16-bit numbers.
+// - DOUBLE_P is true if the 64-bit accumulator is in LO, false it is a
+// concatenation of the low 32 bits of HI and LO.
+:function:::void:do_vr_mul_op:int rd, int rs, int rt, int accumulate_p, int store_hi_p, int unsigned_p, int saturate_p, int subtract_p, int short_p, int double_p
{
- /* 64 bit specific */
- *AL4_8 (&HI) = VH4_8 (value);
- *AL4_8 (&LO) = VL4_8 (value);
+ unsigned64 lhs, x, y, xcut, ycut, product, result;
+
+ check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
+
+ lhs = (!accumulate_p ? 0 : double_p ? LO : U8_4 (HI, LO));
+ x = GPR[rs];
+ y = GPR[rt];
+
+ /* Work out the canonical form of X and Y from their significant bits. */
+ if (!short_p)
+ {
+ /* Normal sign-extension rule for 32-bit operands. */
+ xcut = EXTEND32 (x);
+ ycut = EXTEND32 (y);
+ }
+ else if (unsigned_p)
+ {
+ /* Operands must be zero-extended 16-bit numbers. */
+ xcut = x & 0xffff;
+ ycut = y & 0xffff;
+ }
+ else
+ {
+ /* Likewise but sign-extended. */
+ xcut = EXTEND16 (x);
+ ycut = EXTEND16 (y);
+ }
+ if (x != xcut || y != ycut)
+ sim_engine_abort (SD, CPU, CIA,
+ "invalid multiplication operand at 0x%08lx\n",
+ (long) CIA);
+
+ TRACE_ALU_INPUT2 (x, y);
+ product = (unsigned_p ? x * y : EXTEND32 (x) * EXTEND32 (y));
+ result = (subtract_p ? lhs - product : lhs + product);
+ if (saturate_p)
+ {
+ /* Saturate the result to 32 bits. An unsigned, unsaturated
+ result is zero-extended to 64 bits, but unsigned overflow
+ causes all 64 bits to be set. */
+ if (!unsigned_p && (unsigned64) EXTEND32 (result) != result)
+ result = ((signed64) result < 0 ? -0x7fffffff - 1 : 0x7fffffff);
+ else if (unsigned_p && (result >> 32) != 0)
+ result = (unsigned64) 0 - 1;
+ }
+ TRACE_ALU_RESULT (result);
+
+ if (double_p)
+ LO = result;
+ else
+ {
+ LO = EXTEND32 (result);
+ HI = EXTEND32 (VH4_8 (result));
+ }
+ if (rd != 0)
+ GPR[rd] = store_hi_p ? HI : LO;
}
-:function:::signed64:SignedMultiply:signed32 l, signed32 r
-*vr4100:
+// 32-bit rotate right of X by Y bits.
+:function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
+*vr5400:
+*vr5500:
{
- signed64 result = (signed64) l * (signed64) r;
+ unsigned64 result;
+
+ y &= 31;
+ TRACE_ALU_INPUT2 (x, y);
+ result = EXTEND32 (ROTR32 (x, y));
+ TRACE_ALU_RESULT (result);
return result;
}
-:function:::unsigned64:UnsignedMultiply:unsigned32 l, unsigned32 r
-*vr4100:
+// Likewise 64-bit
+:function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
+*vr5400:
+*vr5500:
{
- unsigned64 result = (unsigned64) l * (unsigned64) r;
+ unsigned64 result;
+
+ y &= 63;
+ TRACE_ALU_INPUT2 (x, y);
+ result = ROTR64 (x, y);
+ TRACE_ALU_RESULT (result);
return result;
}
-:function:::unsigned64:Low32Bits:unsigned64 value
+
+// VR4100 instructions.
+
+000000,5.RS,5.RT,00000,00000,101000::32::MADD16
+"madd16 r<RS>, r<RT>"
*vr4100:
{
- unsigned64 result = (signed64) (signed32) VL4_8 (value);
- return result;
+ do_vr_mul_op (SD_, 0, RS, RT,
+ 1 /* accumulate */,
+ 0 /* store in LO */,
+ 0 /* signed arithmetic */,
+ 0 /* don't saturate */,
+ 0 /* don't subtract */,
+ 1 /* short */,
+ 0 /* single */);
}
-:function:::unsigned64:High32Bits:unsigned64 value
+000000,5.RS,5.RT,00000,00000,101001::64::DMADD16
+"dmadd16 r<RS>, r<RT>"
*vr4100:
{
- unsigned64 result = (signed64) (signed32) VH4_8 (value);
- return result;
+ do_vr_mul_op (SD_, 0, RS, RT,
+ 1 /* accumulate */,
+ 0 /* store in LO */,
+ 0 /* signed arithmetic */,
+ 0 /* don't saturate */,
+ 0 /* don't subtract */,
+ 1 /* short */,
+ 1 /* double */);
}
-// Multiply, Accumulate
-000000,5.RS,5.RT,00000,00000,101000::64::MAC
-"mac r<RS>, r<RT>"
-*vr4100:
+// VR4120 and VR4130 instructions.
+
+000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101001::64::DMACC
+"dmacc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
+*vr4120:
{
- SET_MulAcc (SD_, MulAcc (SD_) + SignedMultiply (SD_, GPR[RS], GPR[RT]));
+ do_vr_mul_op (SD_, RD, RS, RT,
+ 1 /* accumulate */,
+ MFHI, UNS, SAT,
+ 0 /* don't subtract */,
+ SAT /* short */,
+ 1 /* double */);
}
+000000,5.RS,5.RT,5.RD,1.SAT,1.MFHI,00,1.UNS,101000::32::MACC_4120
+"macc%s<MFHI>%s<UNS>%s<SAT> r<RD>, r<RS>, r<RT>"
+*vr4120:
+{
+ do_vr_mul_op (SD_, RD, RS, RT,
+ 1 /* accumulate */,
+ MFHI, UNS, SAT,
+ 0 /* don't subtract */,
+ SAT /* short */,
+ 0 /* single */);
+}
-// D-Multiply, Accumulate
-000000,5.RS,5.RT,00000,00000,101001::64::DMAC
-"dmac r<RS>, r<RT>"
-*vr4100:
+
+// VR5400 and VR5500 instructions.
+
+000000,5.RS,5.RT,5.RD,0,1.MFHI,001,01100,1.UNS::32::MUL
+"mul%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
+*vr5400:
+*vr5500:
{
- LO = LO + SignedMultiply (SD_, GPR[RS], GPR[RT]);
+ do_vr_mul_op (SD_, RD, RS, RT,
+ 0 /* don't accumulate */,
+ MFHI, UNS,
+ 0 /* don't saturate */,
+ 0 /* don't subtract */,
+ 0 /* not short */,
+ 0 /* single */);
}
+000000,5.RS,5.RT,5.RD,0,1.MFHI,011,01100,1.UNS::32::MULS
+"muls%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
+*vr5400:
+*vr5500:
+{
+ do_vr_mul_op (SD_, RD, RS, RT,
+ 0 /* don't accumulate */,
+ MFHI, UNS,
+ 0 /* don't saturate */,
+ 1 /* subtract */,
+ 0 /* not short */,
+ 0 /* single */);
+}
+
+000000,5.RS,5.RT,5.RD,0,1.MFHI,101,01100,1.UNS::32::MACC_5xxx
+"macc%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
+*vr5400:
+*vr5500:
+{
+ do_vr_mul_op (SD_, RD, RS, RT,
+ 1 /* accumulate */,
+ MFHI, UNS,
+ 0 /* don't saturate */,
+ 0 /* don't subtract */,
+ 0 /* not short */,
+ 0 /* single */);
+}
+
+000000,5.RS,5.RT,5.RD,0,1.MFHI,111,01100,1.UNS::32::MSAC
+"msac%s<MFHI>%s<UNS> r<RD>, r<RS>, r<RT>"
+*vr5400:
+*vr5500:
+{
+ do_vr_mul_op (SD_, RD, RS, RT,
+ 1 /* accumulate */,
+ MFHI, UNS,
+ 0 /* don't saturate */,
+ 1 /* subtract */,
+ 0 /* not short */,
+ 0 /* single */);
+}
+
+000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
+"ror r<RD>, r<RT>, <SHIFT>"
+*vr5400:
+*vr5500:
+{
+ GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
+}
+
+000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
+"rorv r<RD>, r<RT>, r<RS>"
+*vr5400:
+*vr5500:
+{
+ GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
+}
+000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
+"dror r<RD>, r<RT>, <SHIFT>"
+*vr5400:
+*vr5500:
+{
+ GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
+}
+
+000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
+"dror32 r<RD>, r<RT>, <SHIFT>"
+*vr5400:
+*vr5500:
+{
+ GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
+}
+
+000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
+"drorv r<RD>, r<RT>, r<RS>"
+*vr5400:
+*vr5500:
+{
+ GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
+}
+
+010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64::LUXC1
+"luxc1 f<FD>, r<INDEX>(r<BASE>)"
+*vr5500:
+{
+ check_fpu (SD_);
+ COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD,
+ (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0));
+}
+
+010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64::SUXC1
+"suxc1 f<FS>, r<INDEX>(r<BASE>)"
+*vr5500:
+{
+ check_fpu (SD_);
+ do_store (SD_, AccessLength_DOUBLEWORD,
+ (GPR[BASE] + GPR[INDEX]) & ~MASK64 (2, 0), 0,
+ COP_SD (1, FS));
+}
+010000,1,19.*,100000:COP0:32::WAIT
+"wait"
+*vr5500:
+
+011100,00000,5.RT,5.DR,00000,111101:SPECIAL:64::MFDR
+"mfdr r<RT>, r<DR>"
+*vr5400:
+*vr5500:
+
+011100,00100,5.RT,5.DR,00000,111101:SPECIAL:64::MTDR
+"mtdr r<RT>, r<DR>"
+*vr5400:
+*vr5500:
+
+011100,00000,00000,00000,00000,111110:SPECIAL:64::DRET
+"dret"
+*vr5400:
+*vr5500:
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
2003-01-05 7:57 ` cgd
@ 2003-01-05 11:51 ` Richard Sandiford
[not found] ` <mailpost.1041767504.18587@news-sj1-1>
0 siblings, 1 reply; 22+ messages in thread
From: Richard Sandiford @ 2003-01-05 11:51 UTC (permalink / raw)
To: cgd; +Cc: gdb-patches
Thanks for applying the patch ;)
cgd@broadcom.com writes:
> I believe there are two relatively minor issues with this patch
> remaining:
>
> * Andrew wants to avoid explicit architecture checks in the mips.igen
> file. That seems sensible enough, I guess. Without the code in
> mips.igen:check_mf_cycles that he objects to, the vr5500 won't work
> correctly but the rest of the new architectures being added should.
>
> I've mentioned previously to you that i'd look into this. I've not
> yet had much time yet, but hope to in the next week or two.
OK. One way (I think I mentioned it privately, maybe it's what you
had in mind anyway) would be to add some sort of exclusion filter
to igen. As well as "*FOO" to include something for architecture
FOO there could be "!FOO" (or whatever) to exclude it.
Then we could have something like:
:function:::int:check_mt_hilo:hilo_history *history
...
*mipsIV:
...
!vr5500:
... version that calls check_mf_cycles ...
:function:::int:check_mt_hilo:hilo_history *history
*mips32:
*mips64:
*r3900:
*vr5500:
... version that doesn't ...
Would it be OK to change igen along these lines? I'll volunteer
to try it if so...
> * I believe that there are still a couple of files not cleaned
> properly by 'make distclean'.
>
> Could you look into this?
Heh, that was very sloppy of me, sorry. The files in question
(m16m32*_run.c) should never have been created in the first place.
The patch below gets rid of them and causes no change in the
executable (except for a timestamp). Please install if OK.
Richard
* Makefile.in (tmp-run-multi): Fix mips16 filter.
Index: sim/mips/Makefile.in
===================================================================
RCS file: /cvs/src/src/sim/mips/Makefile.in,v
retrieving revision 1.8
diff -u -d -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.8 Makefile.in
--- sim/mips/Makefile.in 5 Jan 2003 07:56:59 -0000 1.8
+++ sim/mips/Makefile.in 5 Jan 2003 11:28:14 -0000
@@ -371,7 +371,7 @@ tmp-itable-multi: $(IGEN_INSN) $(IGEN_DC
tmp-run-multi: $(srcdir)/m16run.c
for t in $(SIM_MULTI_IGEN_CONFIGS); do \
case $${t} in \
- *:*mips16*:*) \
+ m16*) \
m=`echo $${t} | sed -e 's/^m16//' -e 's/:.*//'`; \
sed < $(srcdir)/m16run.c > tmp-run \
-e "s/^sim_/m16$${m}_/" \
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: sim/mips patch: add support for more NEC VR targets
[not found] ` <mailpost.1041767504.18587@news-sj1-1>
@ 2003-01-06 7:18 ` cgd
0 siblings, 0 replies; 22+ messages in thread
From: cgd @ 2003-01-06 7:18 UTC (permalink / raw)
To: rsandifo; +Cc: gdb-patches
At Sun, 5 Jan 2003 11:51:44 +0000 (UTC), "Richard Sandiford" wrote:
> OK. One way (I think I mentioned it privately, maybe it's what you
> had in mind anyway) would be to add some sort of exclusion filter
> to igen. As well as "*FOO" to include something for architecture
> FOO there could be "!FOO" (or whatever) to exclude it.
quickly looking at the igen code, it doesn't look like that's an
approach that promises a pretty implementation...
> * Makefile.in (tmp-run-multi): Fix mips16 filter.
installed, thanks.
chris
^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2003-01-06 7:18 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2002-10-04 9:44 sim/mips patch: add support for more NEC VR targets Richard Sandiford
[not found] ` <mailpost.1033749908.1650@news-sj1-1>
2002-10-04 10:54 ` cgd
2002-10-09 7:14 ` Richard Sandiford
2002-10-22 15:27 ` cgd
2002-11-05 8:20 ` Richard Sandiford
2002-11-06 10:44 ` cgd
2002-11-06 14:46 ` cgd
2002-11-06 15:08 ` cgd
2002-11-26 4:44 ` Richard Sandiford
[not found] ` <mailpost.1038314670.25092@news-sj1-1>
2002-11-26 12:49 ` cgd
2002-11-26 16:55 ` Andrew Cagney
[not found] ` <mailpost.1038358543.15485@news-sj1-1>
2002-11-26 17:48 ` cgd
2002-11-26 19:10 ` Andrew Cagney
[not found] ` <mailpost.1038366650.19029@news-sj1-1>
2002-12-03 9:17 ` cgd
2002-12-03 9:35 ` Andrew Cagney
2003-01-05 7:57 ` cgd
2003-01-05 11:51 ` Richard Sandiford
[not found] ` <mailpost.1041767504.18587@news-sj1-1>
2003-01-06 7:18 ` cgd
2002-11-06 16:46 ` Andrew Cagney
2002-11-06 17:28 ` cgd
2002-11-06 17:40 ` Andrew Cagney
2002-11-07 11:08 ` cgd
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