* [rfa/mips] Second go at vr5500 hilo hazard fix
@ 2004-03-18 15:05 Richard Sandiford
2004-03-19 0:09 ` Richard Sandiford
[not found] ` <mailpost.1079622402.27828@news-sj1-1>
0 siblings, 2 replies; 19+ messages in thread
From: Richard Sandiford @ 2004-03-18 15:05 UTC (permalink / raw)
To: gdb-patches
Several months ago, I submitted a patch to add NEC VR support to sim/mips.
Most of it was accepted, but one controversial bit was the handling of hi/lo
hazards for the vr5500.
The vr5500 is currently treated as MIPS IV "plus a bit", i.e., it uses
all mips.igen entries marked "*mipsIV", plus some others that are
explicitly marked as "*vr5500". However, unlike some MIPS IV parts,
including the vr5400, the vr5500 has interlocks to work around the usual
mflo -> mtlo/mul/div hazard.
Various suggestions were made about how this could be handled, but I
think Andrew's position remained the same: we shouldn't try to treat the
vr5500 ISA as "MIPS IV plus a bit and minus a bit" (my words, not his).
He reckoned every vr5500 instruction should be marked as such.
The patch below does this. Tested on mips64vrel-elf. OK to install?
Richard
* configure.in (mips64vr-*-*, mips64vrel-*-*): Remove mipsIV from the
vr5500 entry in sim_multi_configs.
* configure: Regenerate.
* mips.igen: Explicitly mark all vr5500 instructions.
Index: sim/mips/configure.in
===================================================================
RCS file: /cvs/src/src/sim/mips/configure.in,v
retrieving revision 1.6
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.6 configure.in
*** sim/mips/configure.in 5 Jan 2003 07:56:59 -0000 1.6
--- sim/mips/configure.in 18 Mar 2004 14:49:48 -0000
*************** case "${target}" in
*** 131,137 ****
vr4120:mipsIII,mips16,vr4120:32,64:mips4120\
vr5000:mipsIV:32,64,f:mips4300,mips5000\
vr5400:mipsIV,vr5400:32,64,f:mips5400\
! vr5500:mipsIV,vr5500:32,64,f:mips5500"
sim_multi_default=mips5000
;;
mips64*-*-*) sim_igen_filter="32,64,f"
--- 131,137 ----
vr4120:mipsIII,mips16,vr4120:32,64:mips4120\
vr5000:mipsIV:32,64,f:mips4300,mips5000\
vr5400:mipsIV,vr5400:32,64,f:mips5400\
! vr5500:vr5500:32,64,f:mips5500"
sim_multi_default=mips5000
;;
mips64*-*-*) sim_igen_filter="32,64,f"
Index: sim/mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.55
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.55 mips.igen
*** sim/mips/mips.igen 20 Jan 2004 07:06:14 -0000 1.55
--- sim/mips/mips.igen 18 Mar 2004 14:49:48 -0000
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 134,139 ****
--- 134,140 ----
*mips32:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
return base + offset;
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 168,173 ****
--- 169,175 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* For historical simulator compatibility (until documentation is
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 206,211 ****
--- 208,214 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
}
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 289,294 ****
--- 292,298 ----
:function:::int:check_mt_hilo:hilo_history *history
*mips32:
*mips64:
+ *vr5500:
*r3900:
{
signed64 time = sim_events_time (SD);
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 313,318 ****
--- 317,323 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
signed64 time = sim_events_time (SD);
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 368,373 ****
--- 373,379 ----
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips64:
+ *vr5500:
*r3900:
{
/* FIXME: could record the fact that a stall occured if we want */
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 408,413 ****
--- 414,420 ----
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips64:
+ *vr5500:
{
signed64 time = sim_events_time (SD);
hi->op.timestamp = time;
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 430,435 ****
--- 437,443 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5500:
{
// The check should be similar to mips64 for any with PX/UX bit equivalents.
}
*************** 000000,5.RS,5.RT,5.RD,00000,100000:SPECI
*** 464,469 ****
--- 472,478 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
*************** 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 490,495 ****
--- 499,505 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
if (NotWordValue (GPR[RS]))
*************** 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 525,530 ****
--- 535,541 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_addiu (SD_, RS, RT, IMMEDIATE);
*************** 000000,5.RS,5.RT,5.RD,00000,100001:SPECI
*** 552,557 ****
--- 563,569 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_addu (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,100100:SPECI
*** 577,582 ****
--- 589,595 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_and (SD_, RS, RT, RD);
*************** 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 595,600 ****
--- 608,614 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
*************** 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BE
*** 615,620 ****
--- 629,635 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BE
*** 636,641 ****
--- 651,657 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS,00001,16.OFFSET:REGIMM:32::B
*** 660,665 ****
--- 676,682 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS!31,10001,16.OFFSET:REGIMM:32
*** 682,687 ****
--- 699,705 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS!31,10011,16.OFFSET:REGIMM:32
*** 706,711 ****
--- 724,730 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS,00011,16.OFFSET:REGIMM:32::B
*** 734,739 ****
--- 753,759 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000111,5.RS,00000,16.OFFSET:NORMAL:32::B
*** 758,763 ****
--- 778,784 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 010111,5.RS,00000,16.OFFSET:NORMAL:32::B
*** 779,784 ****
--- 800,806 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000110,5.RS,00000,16.OFFSET:NORMAL:32::B
*** 805,810 ****
--- 827,833 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 010110,5.RS,00000,16.OFFSET:NORMAL:32::B
*** 828,833 ****
--- 851,857 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS,00000,16.OFFSET:REGIMM:32::B
*** 852,857 ****
--- 876,882 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS!31,10000,16.OFFSET:REGIMM:32
*** 874,879 ****
--- 899,905 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS!31,10010,16.OFFSET:REGIMM:32
*** 900,905 ****
--- 926,932 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS,00010,16.OFFSET:REGIMM:32::B
*** 926,931 ****
--- 953,959 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BN
*** 952,957 ****
--- 980,986 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BN
*** 973,978 ****
--- 1002,1008 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000000,20.CODE,001101:SPECIAL:32::BREAK
*** 997,1002 ****
--- 1027,1033 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* Check for some break instruction which are reserved for use by the simulator. */
*************** 000000,5.RS,5.RT,5.RD,00000,101100:SPECI
*** 1085,1090 ****
--- 1116,1122 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
*************** 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64:
*** 1106,1111 ****
--- 1138,1144 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
*************** 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64:
*** 1134,1139 ****
--- 1167,1173 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_daddiu (SD_, RS, RT, IMMEDIATE);
*************** 000000,5.RS,5.RT,5.RD,00000,101101:SPECI
*** 1156,1161 ****
--- 1190,1196 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_daddu (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,0000000000,011110:SPECI
*** 1249,1254 ****
--- 1284,1290 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_ddiv (SD_, RS, RT);
*************** 000000,5.RS,5.RT,0000000000,011111:SPECI
*** 1289,1294 ****
--- 1325,1331 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_ddivu (SD_, RS, RT);
*************** 000000,5.RS,5.RT,0000000000,011010:SPECI
*** 1333,1338 ****
--- 1370,1376 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_div (SD_, RS, RT);
*************** 000000,5.RS,5.RT,0000000000,011011:SPECI
*** 1372,1377 ****
--- 1410,1416 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_divu (SD_, RS, RT);
*************** 000000,5.RS,5.RT,0000000000,011100:SPECI
*** 1451,1456 ****
--- 1490,1496 ----
*mipsV:
*mips64:
*vr4100:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dmult (SD_, RS, RT, 0);
*************** 000000,5.RS,5.RT,0000000000,011101:SPECI
*** 1479,1484 ****
--- 1519,1525 ----
*mipsV:
*mips64:
*vr4100:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dmultu (SD_, RS, RT, 0);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111000:SP
*** 1508,1513 ****
--- 1549,1555 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsll (SD_, RT, RD, SHIFT);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111100:SP
*** 1522,1527 ****
--- 1564,1570 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
*************** 000000,5.RS,5.RT,5.RD,00000,010100:SPECI
*** 1546,1551 ****
--- 1589,1595 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsllv (SD_, RS, RT, RD);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111011:SP
*** 1567,1572 ****
--- 1611,1617 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsra (SD_, RT, RD, SHIFT);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111111:SP
*** 1581,1586 ****
--- 1626,1632 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
*************** 000000,5.RS,5.RT,5.RD,00000,010111:SPECI
*** 1606,1611 ****
--- 1652,1658 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsrav (SD_, RS, RT, RD);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111010:SP
*** 1627,1632 ****
--- 1674,1680 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsrl (SD_, RT, RD, SHIFT);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111110:SP
*** 1641,1646 ****
--- 1689,1695 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
*************** 000000,5.RS,5.RT,5.RD,00000,010110:SPECI
*** 1668,1673 ****
--- 1717,1723 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsrlv (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,101110:SPECI
*** 1682,1687 ****
--- 1732,1738 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
*************** 000000,5.RS,5.RT,5.RD,00000,101111:SPECI
*** 1709,1714 ****
--- 1760,1766 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsubu (SD_, RS, RT, RD);
*************** 000010,26.INSTR_INDEX:NORMAL:32::J
*** 1726,1731 ****
--- 1778,1784 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* NOTE: The region used is that of the delay slot NIA and NOT the
*************** 000011,26.INSTR_INDEX:NORMAL:32::JAL
*** 1746,1751 ****
--- 1799,1805 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* NOTE: The region used is that of the delay slot and NOT the
*************** 000000,5.RS,00000,5.RD,00000,001001:SPEC
*** 1767,1772 ****
--- 1821,1827 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word temp = GPR[RS];
*************** 000000,5.RS,000000000000000,001000:SPECI
*** 1786,1791 ****
--- 1841,1847 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
DELAY_SLOT (GPR[RS]);
*************** 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 1913,1918 ****
--- 1969,1975 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
*************** 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 1930,1935 ****
--- 1987,1993 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
*************** 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 1944,1949 ****
--- 2002,2008 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
*************** 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM
*** 1960,1965 ****
--- 2019,2025 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
*************** 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 1976,1981 ****
--- 2036,2042 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 1990,1995 ****
--- 2051,2057 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2007,2012 ****
--- 2069,2075 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
*************** 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2024,2029 ****
--- 2087,2093 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
*************** 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2040,2045 ****
--- 2104,2110 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
*************** 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2081,2086 ****
--- 2146,2152 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
*************** 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32
*** 2119,2124 ****
--- 2185,2191 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
TRACE_ALU_INPUT1 (IMMEDIATE);
*************** 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2138,2143 ****
--- 2205,2211 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
*************** 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM
*** 2155,2160 ****
--- 2223,2229 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
*************** 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2172,2177 ****
--- 2241,2247 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
*************** 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2189,2194 ****
--- 2259,2265 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
*************** 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2203,2208 ****
--- 2274,2280 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
*************** 000000,0000000000,5.RD,00000,010000:SPEC
*** 2268,2273 ****
--- 2340,2346 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_mfhi (SD_, RD);
*************** 000000,0000000000,5.RD,00000,010010:SPEC
*** 2294,2299 ****
--- 2367,2373 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_mflo (SD_, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,001011:SPECI
*** 2308,2313 ****
--- 2382,2388 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
if (GPR[RT] != 0)
{
*************** 000000,5.RS,5.RT,5.RD,00000,001010:SPECI
*** 2325,2330 ****
--- 2400,2406 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
if (GPR[RT] == 0)
{
*************** 000000,5.RS,000000000000000,010001:SPECI
*** 2386,2391 ****
--- 2462,2468 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_mt_hilo (SD_, HIHISTORY);
*************** 000000,5.RS,000000000000000,010011:SPECI
*** 2405,2410 ****
--- 2482,2488 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_mt_hilo (SD_, LOHISTORY);
*************** 000000,5.RS,5.RT,0000000000,011000:SPECI
*** 2457,2462 ****
--- 2535,2541 ----
*mips32:
*mips64:
*vr4100:
+ *vr5500:
{
do_mult (SD_, RS, RT, 0);
}
*************** 000000,5.RS,5.RT,0000000000,011001:SPECI
*** 2498,2503 ****
--- 2577,2583 ----
*mips32:
*mips64:
*vr4100:
+ *vr5500:
{
do_multu (SD_, RS, RT, 0);
}
*************** 000000,5.RS,5.RT,5.RD,00000,100111:SPECI
*** 2530,2535 ****
--- 2610,2616 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_nor (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,100101:SPECI
*** 2554,2559 ****
--- 2635,2641 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_or (SD_, RS, RT, RD);
*************** 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 2579,2584 ****
--- 2661,2667 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_ori (SD_, RS, RT, IMMEDIATE);
*************** 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32
*** 2592,2597 ****
--- 2675,2681 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
*************** 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2708,2713 ****
--- 2792,2798 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2724,2729 ****
--- 2809,2815 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
unsigned32 instruction = instruction_0;
address_word base = GPR[BASE];
*************** 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2766,2771 ****
--- 2852,2858 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
*************** 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2804,2809 ****
--- 2891,2897 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM
*** 2820,2825 ****
--- 2908,2914 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
}
*************** 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2833,2838 ****
--- 2922,2928 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2847,2852 ****
--- 2937,2943 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2864,2869 ****
--- 2955,2961 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,000000:SP
*** 2888,2893 ****
--- 2980,2986 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* Skip shift for NOP, so that there won't be lots of extraneous
*************** 000000,5.RS,5.RT,5.RD,00000,000100:SPECI
*** 2930,2935 ****
--- 3023,3029 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_sllv (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,101010:SPECI
*** 2954,2959 ****
--- 3048,3054 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_slt (SD_, RS, RT, RD);
*************** 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 2978,2983 ****
--- 3073,3079 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_slti (SD_, RS, RT, IMMEDIATE);
*************** 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 3002,3007 ****
--- 3098,3104 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_sltiu (SD_, RS, RT, IMMEDIATE);
*************** 000000,5.RS,5.RT,5.RD,00000,101011:SPECI
*** 3027,3032 ****
--- 3124,3130 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_sltu (SD_, RS, RT, RD);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,000011:SP
*** 3054,3059 ****
--- 3152,3158 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_sra (SD_, RT, RD, SHIFT);
*************** 000000,5.RS,5.RT,5.RD,00000,000111:SPECI
*** 3083,3088 ****
--- 3182,3188 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_srav (SD_, RS, RT, RD);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,000010:SP
*** 3111,3116 ****
--- 3211,3217 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_srl (SD_, RT, RD, SHIFT);
*************** 000000,5.RS,5.RT,5.RD,00000,000110:SPECI
*** 3139,3144 ****
--- 3240,3246 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_srlv (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,100010:SPECI
*** 3156,3161 ****
--- 3258,3264 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
*************** 000000,5.RS,5.RT,5.RD,00000,100011:SPECI
*** 3190,3195 ****
--- 3293,3299 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_subu (SD_, RS, RT, RD);
*************** 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 3208,3213 ****
--- 3312,3318 ----
*vr4100:
*r3900:
*vr5000:
+ *vr5500:
{
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*************** 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM
*** 3224,3229 ****
--- 3329,3335 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
*************** 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 3241,3246 ****
--- 3347,3353 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 3258,3263 ****
--- 3365,3371 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 000000,000000000000000,5.STYPE,001111:SP
*** 3275,3280 ****
--- 3383,3389 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
SyncOperation (STYPE);
*************** 000000,20.CODE,001100:SPECIAL:32::SYSCAL
*** 3292,3297 ****
--- 3401,3407 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
SignalException (SystemCall, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:
*** 3308,3313 ****
--- 3418,3424 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32
*** 3324,3329 ****
--- 3435,3441 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:
*** 3340,3345 ****
--- 3452,3458 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32
*** 3356,3361 ****
--- 3469,3475 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32
*** 3372,3377 ****
--- 3486,3492 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:
*** 3388,3393 ****
--- 3503,3509 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:
*** 3404,3409 ****
--- 3520,3526 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32
*** 3420,3425 ****
--- 3537,3543 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32
*** 3436,3441 ****
--- 3554,3560 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:
*** 3452,3457 ****
--- 3571,3577 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:
*** 3468,3473 ****
--- 3588,3594 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32
*** 3484,3489 ****
--- 3605,3611 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,5.RD,00000,100110:SPECI
*** 3508,3513 ****
--- 3630,3636 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_xor (SD_, RS, RT, RD);
*************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 3532,3537 ****
--- 3655,3661 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_xori (SD_, RS, RT, IMMEDIATE);
*************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 3616,3621 ****
--- 3740,3746 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
if ((fmt != fmt_single) && (fmt != fmt_double))
*************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 3631,3636 ****
--- 3756,3762 ----
*mips32:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* None of these ISAs support Paired Single, so just fall back to
*************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 3664,3669 ****
--- 3790,3796 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
if (! COP_Usable (1))
*************** 010001,10,3.FMT,00000,5.FS,5.FD,000101:C
*** 3753,3758 ****
--- 3880,3886 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:CO
*** 3774,3779 ****
--- 3902,3908 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:CO
*** 3849,3854 ****
--- 3978,3984 ----
*mips64:
#*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.C
*** 3886,3891 ****
--- 4016,4022 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001010:C
*** 3904,3909 ****
--- 4035,4041 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001110:C
*** 3924,3929 ****
--- 4056,4062 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,00010,5.RT,5.FS,00000000000:COP1:
*** 3953,3958 ****
--- 4086,4092 ----
*mipsIV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,00110,5.RT,5.FS,00000000000:COP1:
*** 4000,4005 ****
--- 4134,4140 ----
*mipsIV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,10,3.FMT,00000,5.FS,5.FD,100001:C
*** 4037,4042 ****
--- 4172,4178 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,100101:C
*** 4056,4061 ****
--- 4192,4198 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT!6,00000,5.FS,5.FD,100000
*** 4093,4098 ****
--- 4230,4236 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT!6,00000,5.FS,5.FD,100100
*** 4137,4142 ****
--- 4275,4281 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:CO
*** 4159,4164 ****
--- 4298,4304 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,00001,5.RT,5.FS,00000000000:COP1:
*** 4192,4197 ****
--- 4332,4338 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,00101,5.RT,5.FS,00000000000:COP1:
*** 4232,4237 ****
--- 4373,4379 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001011:C
*** 4253,4258 ****
--- 4395,4401 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001111:C
*** 4273,4278 ****
--- 4416,4422 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::
*** 4301,4306 ****
--- 4445,4451 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010011,5.BASE,5.INDEX,5.0,5.FD,000001:CO
*** 4314,4319 ****
--- 4459,4465 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
*************** 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::
*** 4349,4354 ****
--- 4495,4501 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010011,5.BASE,5.INDEX,5.0,5.FD,000000:CO
*** 4362,4367 ****
--- 4509,4515 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
*************** 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP
*** 4376,4381 ****
--- 4524,4530 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010001,00000,5.RT,5.FS,00000000000:COP1:
*** 4407,4412 ****
--- 4556,4562 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,10,3.FMT,00000,5.FS,5.FD,000110:C
*** 4426,4431 ****
--- 4576,4582 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 000000,5.RS,3.CC,0,1.TF,5.RD,00000,00000
*** 4444,4449 ****
--- 4595,4601 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
if (GETFCC(CC) == TF)
*************** 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,01
*** 4460,4465 ****
--- 4612,4618 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:CO
*** 4489,4494 ****
--- 4642,4648 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
if (GPR[RT] != 0)
*************** 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:CO
*** 4512,4517 ****
--- 4666,4672 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
if (GPR[RT] == 0)
*************** 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP
*** 4527,4532 ****
--- 4682,4688 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010001,00100,5.RT,5.FS,00000000000:COP1:
*** 4559,4564 ****
--- 4715,4721 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:CO
*** 4577,4582 ****
--- 4734,4740 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,000111:C
*** 4597,4602 ****
--- 4755,4761 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP
*** 4612,4617 ****
--- 4771,4777 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP
*** 4628,4633 ****
--- 4788,4794 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010011,5.BASE,5.INDEX,5.HINT,00000,00111
*** 4668,4673 ****
--- 4829,4835 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
address_word index = GPR[INDEX];
*************** 010001,10,3.FMT,00000,5.FS,5.FD,010101:C
*** 4711,4716 ****
--- 4873,4879 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001000:C
*** 4727,4732 ****
--- 4890,4896 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001100:C
*** 4747,4752 ****
--- 4911,4917 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,010110:C
*** 4763,4768 ****
--- 4928,4934 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::
*** 4789,4794 ****
--- 4955,4961 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010011,5.BASE,5.INDEX,5.FS,00000001001:C
*** 4802,4807 ****
--- 4969,4975 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
*************** 010001,10,3.FMT,00000,5.FS,5.FD,000100:C
*** 4837,4842 ****
--- 5005,5011 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:CO
*** 4857,4862 ****
--- 5026,5032 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::
*** 4878,4883 ****
--- 5048,5054 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word base = GPR[BASE];
*************** 010011,5.BASE,5.INDEX,5.FS,00000,001000:
*** 4917,4922 ****
--- 5088,5094 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001001:C
*** 4959,4964 ****
--- 5131,5137 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001101:C
*** 4979,4984 ****
--- 5152,5158 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010000,01000,00000,16.OFFSET:COP0:32::BC
*** 5007,5012 ****
--- 5181,5187 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
*************** 010000,01000,00010,16.OFFSET:COP0:32::BC
*** 5028,5033 ****
--- 5203,5209 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
010000,01000,00001,16.OFFSET:COP0:32::BC0T
*************** 010000,01000,00001,16.OFFSET:COP0:32::BC
*** 5040,5045 ****
--- 5216,5222 ----
*mips32:
*mips64:
*vr4100:
+ *vr5500:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
*************** 010000,01000,00011,16.OFFSET:COP0:32::BC
*** 5053,5058 ****
--- 5230,5236 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
*************** 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::
*** 5064,5069 ****
--- 5242,5248 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word base = GPR[BASE];
*************** 010000,00001,5.RT,5.RD,00000000000:COP0:
*** 5084,5089 ****
--- 5263,5269 ----
*mipsIV:
*mipsV:
*mips64:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
*************** 010000,00101,5.RT,5.RD,00000000000:COP0:
*** 5096,5101 ****
--- 5276,5282 ----
*mipsIV:
*mipsV:
*mips64:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
*************** 010000,1,0000000000000000000,011000:COP0
*** 5111,5116 ****
--- 5292,5298 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if (SR & status_ERL)
{
*************** 010000,00000,5.RT,5.RD,00000,6.REGX:COP0
*** 5138,5143 ****
--- 5320,5326 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
TRACE_ALU_INPUT0 ();
*************** 010000,00100,5.RT,5.RD,00000,6.REGX:COP0
*** 5156,5161 ****
--- 5339,5345 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
DecodeCoproc (instruction_0);
*************** 010000,1,0000000000000000000,010000:COP0
*** 5171,5176 ****
--- 5355,5361 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
DecodeCoproc (instruction_0);
*************** 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16
*** 5187,5192 ****
--- 5372,5378 ----
*mips32:
*mips64:
*vr4100:
+ *vr5500:
*r3900:
{
DecodeCoproc (instruction_0);
*************** 010000,1,0000000000000000000,001000:COP0
*** 5205,5210 ****
--- 5391,5397 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
010000,1,0000000000000000000,000001:COP0:32::TLBR
*************** 010000,1,0000000000000000000,000001:COP0
*** 5218,5223 ****
--- 5405,5411 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
010000,1,0000000000000000000,000010:COP0:32::TLBWI
*************** 010000,1,0000000000000000000,000010:COP0
*** 5231,5236 ****
--- 5419,5425 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
010000,1,0000000000000000000,000110:COP0:32::TLBWR
*************** 010000,1,0000000000000000000,000110:COP0
*** 5244,5249 ****
--- 5433,5439 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
\f
:include:::m16.igen
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-19 0:09 ` cgd
@ 2004-03-18 17:57 ` cgd
2004-03-18 20:55 ` Richard Sandiford
2004-03-28 10:16 ` Richard Sandiford
2 siblings, 0 replies; 19+ messages in thread
From: cgd @ 2004-03-18 17:57 UTC (permalink / raw)
To: rsandifo; +Cc: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 2265 bytes --]
At Thu, 18 Mar 2004 15:06:42 +0000 (UTC), "Richard Sandiford" wrote:
> Various suggestions were made about how this could be handled, but I
> think Andrew's position remained the same: we shouldn't try to treat the
> vr5500 ISA as "MIPS IV plus a bit and minus a bit" (my words, not his).
> He reckoned every vr5500 instruction should be marked as such.
My reading is, unfortunately, is that it is a *correct* implementation
of the MIPS ISA.
At least according to the "Historical information" in the MIPS64 AFP
Volume II (Basic Instruction Set) -- I'm looking at revisions around
1.0 here -- the 3-cycle hi/lo hazards should only have been a problem
for MIPS I-III.
I.e., MIPS IV processors which *have* these hi/lo hazards are the
things broken... but as you note at least according to the 5400 docs,
it is MIPS IV and does have the hazard.
(I thought Andrew's biggest objection was stuffing bfd_* values into
mips.igen, but I may be wrong on that. It's been a while.)
> The patch below does this. Tested on mips64vrel-elf. OK to install?
Doing this doesn't seem satisfactory to me. It would open the door to
a very similar modification, for another handful of processors, which
would be really quite out of hand IMO.
Now that the mips sim 'multi' bits are in place (including good
default), and we have MIPS_MACH(SD) (thanks! 8-), it should be
possible to code a simple macro which checks for the appropriate bfd
machine, and decides whether interlocks are present.
I'd rather see an implementation that acts somewhat like the (rough,
uncompiled, not sanity-checked) patch below. Additional advice: make
sure the comment describing the new macros mentions the fact that they
should have cases only for certain ISAs' processors (mipsIV, mipsV).
The names were just a suggestion. there are probably better, shorter
ones, and I didn't try to reconcile them with any other code (e.g. the
code in headers where they might be defined 8-).
This type of change has the "right" properties, IMO:
* boils down to a no-op if not multi.
* doesn't impact ISAs with no hazard ambiguity if multi.
* shouldn't cause maint pain long term if everybody decides to
make the code right for their fave MIPS IV arch. 8-)
cgd
[-- Attachment #2: rough_haz.diff --]
[-- Type: text/x-patch, Size: 2977 bytes --]
Index: mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.55
diff -u -p -r1.55 mips.igen
--- mips.igen 20 Jan 2004 07:06:14 -0000 1.55
+++ mips.igen 18 Mar 2004 17:54:49 -0000
@@ -242,10 +242,15 @@
// enforced restrictions (2) and (3) for more ISAs and CPU types than
// necessary. Unfortunately, at least some MIPS IV and later parts'
// documentation describes them as having these hazards (e.g. vr5000),
-// so they can't be removed for at leats MIPS IV. MIPS V hasn't been
-// checked (since there are no known hardware implementations).
-//
+// so they can't be removed for at leats MIPS IV. (As of MIPS32 and MIPS64,
+// the hazards are definitely architected to not be required.)
+//
+// To accomodate implementations of particular ISAs which don't have the
+// hazards, for some ISAs we have a version of these helper functions which
+// calls a function to determine if the particular architecture has
+// a hazard.
+//
// check_mf_cycles:
//
// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
@@ -274,8 +279,6 @@
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
{
@@ -287,6 +290,18 @@
}
:function:::int:check_mt_hilo:hilo_history *history
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (MIPS_ARCH_HAS_MT_HILO_HAZARD (SD_)
+ || check_mf_cycles (SD_, history, time, "MT"));
+ history->mt.timestamp = time;
+ history->mt.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_mt_hilo:hilo_history *history
*mips32:
*mips64:
*r3900:
@@ -350,8 +365,6 @@
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
{
@@ -366,6 +379,21 @@
}
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_ARCH_HAS_MULT_HILO_HAZARD (SD_)
+ || (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP")));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips64:
*r3900:
@@ -389,8 +417,6 @@
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
*r3900:
@@ -398,6 +424,21 @@
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_ARCH_HAS_DIV_HILO_HAZARD (SD_)
+ || (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP")));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-19 0:09 ` cgd
2004-03-18 17:57 ` cgd
@ 2004-03-18 20:55 ` Richard Sandiford
2004-03-19 0:09 ` Richard Sandiford
` (2 more replies)
2004-03-28 10:16 ` Richard Sandiford
2 siblings, 3 replies; 19+ messages in thread
From: Richard Sandiford @ 2004-03-18 20:55 UTC (permalink / raw)
To: cgd; +Cc: gdb-patches
cgd@broadcom.com writes:
> Now that the mips sim 'multi' bits are in place (including good
> default), and we have MIPS_MACH(SD) (thanks! 8-), it should be
> possible to code a simple macro which checks for the appropriate bfd
> machine, and decides whether interlocks are present.
Well, I had a similar check in:
http://sources.redhat.com/ml/gdb-patches/2002-11/msg00642.html
OK, so it wasn't wrapped up in a nice macro, it just checked the
architecture directly:
+ /* There are no timing requirements in vr5500 code. */
+ if (MIPS_MACH (SD) == bfd_mach_mips5500)
+ return 1;
But that was exactly what Andrew objected to:
http://sources.redhat.com/ml/gdb-patches/2002-11/msg00668.html
Then there was:
http://sources.redhat.com/ml/gdb-patches/2002-12/msg00080.html
To quote:
As for having to tag each individual entry in the .igen file with an
explicit CPU. Yes, that sux. However, I also believe that it has
significantly reduced the overall error rate (no more breaking one
target by editing another) and that benefit vastly outweighs the short
term pain.
Richard
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
[not found] ` <mailpost.1079622402.27828@news-sj1-1>
@ 2004-03-19 0:09 ` cgd
2004-03-18 17:57 ` cgd
` (2 more replies)
0 siblings, 3 replies; 19+ messages in thread
From: cgd @ 2004-03-19 0:09 UTC (permalink / raw)
To: rsandifo; +Cc: gdb-patches
[-- Attachment #1: Type: text/plain, Size: 2265 bytes --]
At Thu, 18 Mar 2004 15:06:42 +0000 (UTC), "Richard Sandiford" wrote:
> Various suggestions were made about how this could be handled, but I
> think Andrew's position remained the same: we shouldn't try to treat the
> vr5500 ISA as "MIPS IV plus a bit and minus a bit" (my words, not his).
> He reckoned every vr5500 instruction should be marked as such.
My reading is, unfortunately, is that it is a *correct* implementation
of the MIPS ISA.
At least according to the "Historical information" in the MIPS64 AFP
Volume II (Basic Instruction Set) -- I'm looking at revisions around
1.0 here -- the 3-cycle hi/lo hazards should only have been a problem
for MIPS I-III.
I.e., MIPS IV processors which *have* these hi/lo hazards are the
things broken... but as you note at least according to the 5400 docs,
it is MIPS IV and does have the hazard.
(I thought Andrew's biggest objection was stuffing bfd_* values into
mips.igen, but I may be wrong on that. It's been a while.)
> The patch below does this. Tested on mips64vrel-elf. OK to install?
Doing this doesn't seem satisfactory to me. It would open the door to
a very similar modification, for another handful of processors, which
would be really quite out of hand IMO.
Now that the mips sim 'multi' bits are in place (including good
default), and we have MIPS_MACH(SD) (thanks! 8-), it should be
possible to code a simple macro which checks for the appropriate bfd
machine, and decides whether interlocks are present.
I'd rather see an implementation that acts somewhat like the (rough,
uncompiled, not sanity-checked) patch below. Additional advice: make
sure the comment describing the new macros mentions the fact that they
should have cases only for certain ISAs' processors (mipsIV, mipsV).
The names were just a suggestion. there are probably better, shorter
ones, and I didn't try to reconcile them with any other code (e.g. the
code in headers where they might be defined 8-).
This type of change has the "right" properties, IMO:
* boils down to a no-op if not multi.
* doesn't impact ISAs with no hazard ambiguity if multi.
* shouldn't cause maint pain long term if everybody decides to
make the code right for their fave MIPS IV arch. 8-)
cgd
[-- Attachment #2: rough_haz.diff --]
[-- Type: text/x-patch, Size: 2977 bytes --]
Index: mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.55
diff -u -p -r1.55 mips.igen
--- mips.igen 20 Jan 2004 07:06:14 -0000 1.55
+++ mips.igen 18 Mar 2004 17:54:49 -0000
@@ -242,10 +242,15 @@
// enforced restrictions (2) and (3) for more ISAs and CPU types than
// necessary. Unfortunately, at least some MIPS IV and later parts'
// documentation describes them as having these hazards (e.g. vr5000),
-// so they can't be removed for at leats MIPS IV. MIPS V hasn't been
-// checked (since there are no known hardware implementations).
-//
+// so they can't be removed for at leats MIPS IV. (As of MIPS32 and MIPS64,
+// the hazards are definitely architected to not be required.)
+//
+// To accomodate implementations of particular ISAs which don't have the
+// hazards, for some ISAs we have a version of these helper functions which
+// calls a function to determine if the particular architecture has
+// a hazard.
+//
// check_mf_cycles:
//
// Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
@@ -274,8 +279,6 @@
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
{
@@ -287,6 +290,18 @@
}
:function:::int:check_mt_hilo:hilo_history *history
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (MIPS_ARCH_HAS_MT_HILO_HAZARD (SD_)
+ || check_mf_cycles (SD_, history, time, "MT"));
+ history->mt.timestamp = time;
+ history->mt.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_mt_hilo:hilo_history *history
*mips32:
*mips64:
*r3900:
@@ -350,8 +365,6 @@
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
{
@@ -366,6 +379,21 @@
}
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_ARCH_HAS_MULT_HILO_HAZARD (SD_)
+ || (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP")));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips64:
*r3900:
@@ -389,8 +417,6 @@
*mipsI:
*mipsII:
*mipsIII:
-*mipsIV:
-*mipsV:
*vr4100:
*vr5000:
*r3900:
@@ -398,6 +424,21 @@
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+}
+
+:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
+*mipsIV:
+*mipsV:
+{
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_ARCH_HAS_DIV_HILO_HAZARD (SD_)
+ || (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP")));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-18 20:55 ` Richard Sandiford
@ 2004-03-19 0:09 ` Richard Sandiford
2004-03-19 15:19 ` Andrew Cagney
2004-03-25 7:15 ` cgd
2 siblings, 0 replies; 19+ messages in thread
From: Richard Sandiford @ 2004-03-19 0:09 UTC (permalink / raw)
To: cgd; +Cc: gdb-patches
cgd@broadcom.com writes:
> Now that the mips sim 'multi' bits are in place (including good
> default), and we have MIPS_MACH(SD) (thanks! 8-), it should be
> possible to code a simple macro which checks for the appropriate bfd
> machine, and decides whether interlocks are present.
Well, I had a similar check in:
http://sources.redhat.com/ml/gdb-patches/2002-11/msg00642.html
OK, so it wasn't wrapped up in a nice macro, it just checked the
architecture directly:
+ /* There are no timing requirements in vr5500 code. */
+ if (MIPS_MACH (SD) == bfd_mach_mips5500)
+ return 1;
But that was exactly what Andrew objected to:
http://sources.redhat.com/ml/gdb-patches/2002-11/msg00668.html
Then there was:
http://sources.redhat.com/ml/gdb-patches/2002-12/msg00080.html
To quote:
As for having to tag each individual entry in the .igen file with an
explicit CPU. Yes, that sux. However, I also believe that it has
significantly reduced the overall error rate (no more breaking one
target by editing another) and that benefit vastly outweighs the short
term pain.
Richard
^ permalink raw reply [flat|nested] 19+ messages in thread
* [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-18 15:05 [rfa/mips] Second go at vr5500 hilo hazard fix Richard Sandiford
@ 2004-03-19 0:09 ` Richard Sandiford
[not found] ` <mailpost.1079622402.27828@news-sj1-1>
1 sibling, 0 replies; 19+ messages in thread
From: Richard Sandiford @ 2004-03-19 0:09 UTC (permalink / raw)
To: gdb-patches
Several months ago, I submitted a patch to add NEC VR support to sim/mips.
Most of it was accepted, but one controversial bit was the handling of hi/lo
hazards for the vr5500.
The vr5500 is currently treated as MIPS IV "plus a bit", i.e., it uses
all mips.igen entries marked "*mipsIV", plus some others that are
explicitly marked as "*vr5500". However, unlike some MIPS IV parts,
including the vr5400, the vr5500 has interlocks to work around the usual
mflo -> mtlo/mul/div hazard.
Various suggestions were made about how this could be handled, but I
think Andrew's position remained the same: we shouldn't try to treat the
vr5500 ISA as "MIPS IV plus a bit and minus a bit" (my words, not his).
He reckoned every vr5500 instruction should be marked as such.
The patch below does this. Tested on mips64vrel-elf. OK to install?
Richard
* configure.in (mips64vr-*-*, mips64vrel-*-*): Remove mipsIV from the
vr5500 entry in sim_multi_configs.
* configure: Regenerate.
* mips.igen: Explicitly mark all vr5500 instructions.
Index: sim/mips/configure.in
===================================================================
RCS file: /cvs/src/src/sim/mips/configure.in,v
retrieving revision 1.6
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.6 configure.in
*** sim/mips/configure.in 5 Jan 2003 07:56:59 -0000 1.6
--- sim/mips/configure.in 18 Mar 2004 14:49:48 -0000
*************** case "${target}" in
*** 131,137 ****
vr4120:mipsIII,mips16,vr4120:32,64:mips4120\
vr5000:mipsIV:32,64,f:mips4300,mips5000\
vr5400:mipsIV,vr5400:32,64,f:mips5400\
! vr5500:mipsIV,vr5500:32,64,f:mips5500"
sim_multi_default=mips5000
;;
mips64*-*-*) sim_igen_filter="32,64,f"
--- 131,137 ----
vr4120:mipsIII,mips16,vr4120:32,64:mips4120\
vr5000:mipsIV:32,64,f:mips4300,mips5000\
vr5400:mipsIV,vr5400:32,64,f:mips5400\
! vr5500:vr5500:32,64,f:mips5500"
sim_multi_default=mips5000
;;
mips64*-*-*) sim_igen_filter="32,64,f"
Index: sim/mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.55
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.55 mips.igen
*** sim/mips/mips.igen 20 Jan 2004 07:06:14 -0000 1.55
--- sim/mips/mips.igen 18 Mar 2004 14:49:48 -0000
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 134,139 ****
--- 134,140 ----
*mips32:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
return base + offset;
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 168,173 ****
--- 169,175 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* For historical simulator compatibility (until documentation is
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 206,211 ****
--- 208,214 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
}
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 289,294 ****
--- 292,298 ----
:function:::int:check_mt_hilo:hilo_history *history
*mips32:
*mips64:
+ *vr5500:
*r3900:
{
signed64 time = sim_events_time (SD);
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 313,318 ****
--- 317,323 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
signed64 time = sim_events_time (SD);
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 368,373 ****
--- 373,379 ----
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips64:
+ *vr5500:
*r3900:
{
/* FIXME: could record the fact that a stall occured if we want */
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 408,413 ****
--- 414,420 ----
:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips64:
+ *vr5500:
{
signed64 time = sim_events_time (SD);
hi->op.timestamp = time;
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 430,435 ****
--- 437,443 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5500:
{
// The check should be similar to mips64 for any with PX/UX bit equivalents.
}
*************** 000000,5.RS,5.RT,5.RD,00000,100000:SPECI
*** 464,469 ****
--- 472,478 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
*************** 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 490,495 ****
--- 499,505 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
if (NotWordValue (GPR[RS]))
*************** 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 525,530 ****
--- 535,541 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_addiu (SD_, RS, RT, IMMEDIATE);
*************** 000000,5.RS,5.RT,5.RD,00000,100001:SPECI
*** 552,557 ****
--- 563,569 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_addu (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,100100:SPECI
*** 577,582 ****
--- 589,595 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_and (SD_, RS, RT, RD);
*************** 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 595,600 ****
--- 608,614 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
*************** 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BE
*** 615,620 ****
--- 629,635 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BE
*** 636,641 ****
--- 651,657 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS,00001,16.OFFSET:REGIMM:32::B
*** 660,665 ****
--- 676,682 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS!31,10001,16.OFFSET:REGIMM:32
*** 682,687 ****
--- 699,705 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS!31,10011,16.OFFSET:REGIMM:32
*** 706,711 ****
--- 724,730 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS,00011,16.OFFSET:REGIMM:32::B
*** 734,739 ****
--- 753,759 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000111,5.RS,00000,16.OFFSET:NORMAL:32::B
*** 758,763 ****
--- 778,784 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 010111,5.RS,00000,16.OFFSET:NORMAL:32::B
*** 779,784 ****
--- 800,806 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000110,5.RS,00000,16.OFFSET:NORMAL:32::B
*** 805,810 ****
--- 827,833 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 010110,5.RS,00000,16.OFFSET:NORMAL:32::B
*** 828,833 ****
--- 851,857 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS,00000,16.OFFSET:REGIMM:32::B
*** 852,857 ****
--- 876,882 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS!31,10000,16.OFFSET:REGIMM:32
*** 874,879 ****
--- 899,905 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS!31,10010,16.OFFSET:REGIMM:32
*** 900,905 ****
--- 926,932 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000001,5.RS,00010,16.OFFSET:REGIMM:32::B
*** 926,931 ****
--- 953,959 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BN
*** 952,957 ****
--- 980,986 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BN
*** 973,978 ****
--- 1002,1008 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word offset = EXTEND16 (OFFSET) << 2;
*************** 000000,20.CODE,001101:SPECIAL:32::BREAK
*** 997,1002 ****
--- 1027,1033 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* Check for some break instruction which are reserved for use by the simulator. */
*************** 000000,5.RS,5.RT,5.RD,00000,101100:SPECI
*** 1085,1090 ****
--- 1116,1122 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
*************** 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64:
*** 1106,1111 ****
--- 1138,1144 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
*************** 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64:
*** 1134,1139 ****
--- 1167,1173 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_daddiu (SD_, RS, RT, IMMEDIATE);
*************** 000000,5.RS,5.RT,5.RD,00000,101101:SPECI
*** 1156,1161 ****
--- 1190,1196 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_daddu (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,0000000000,011110:SPECI
*** 1249,1254 ****
--- 1284,1290 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_ddiv (SD_, RS, RT);
*************** 000000,5.RS,5.RT,0000000000,011111:SPECI
*** 1289,1294 ****
--- 1325,1331 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_ddivu (SD_, RS, RT);
*************** 000000,5.RS,5.RT,0000000000,011010:SPECI
*** 1333,1338 ****
--- 1370,1376 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_div (SD_, RS, RT);
*************** 000000,5.RS,5.RT,0000000000,011011:SPECI
*** 1372,1377 ****
--- 1410,1416 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_divu (SD_, RS, RT);
*************** 000000,5.RS,5.RT,0000000000,011100:SPECI
*** 1451,1456 ****
--- 1490,1496 ----
*mipsV:
*mips64:
*vr4100:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dmult (SD_, RS, RT, 0);
*************** 000000,5.RS,5.RT,0000000000,011101:SPECI
*** 1479,1484 ****
--- 1519,1525 ----
*mipsV:
*mips64:
*vr4100:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dmultu (SD_, RS, RT, 0);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111000:SP
*** 1508,1513 ****
--- 1549,1555 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsll (SD_, RT, RD, SHIFT);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111100:SP
*** 1522,1527 ****
--- 1564,1570 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
*************** 000000,5.RS,5.RT,5.RD,00000,010100:SPECI
*** 1546,1551 ****
--- 1589,1595 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsllv (SD_, RS, RT, RD);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111011:SP
*** 1567,1572 ****
--- 1611,1617 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsra (SD_, RT, RD, SHIFT);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111111:SP
*** 1581,1586 ****
--- 1626,1632 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
*************** 000000,5.RS,5.RT,5.RD,00000,010111:SPECI
*** 1606,1611 ****
--- 1652,1658 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsrav (SD_, RS, RT, RD);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111010:SP
*** 1627,1632 ****
--- 1674,1680 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsrl (SD_, RT, RD, SHIFT);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,111110:SP
*** 1641,1646 ****
--- 1689,1695 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
int s = 32 + SHIFT;
check_u64 (SD_, instruction_0);
*************** 000000,5.RS,5.RT,5.RD,00000,010110:SPECI
*** 1668,1673 ****
--- 1717,1723 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsrlv (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,101110:SPECI
*** 1682,1687 ****
--- 1732,1738 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
*************** 000000,5.RS,5.RT,5.RD,00000,101111:SPECI
*** 1709,1714 ****
--- 1760,1766 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_dsubu (SD_, RS, RT, RD);
*************** 000010,26.INSTR_INDEX:NORMAL:32::J
*** 1726,1731 ****
--- 1778,1784 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* NOTE: The region used is that of the delay slot NIA and NOT the
*************** 000011,26.INSTR_INDEX:NORMAL:32::JAL
*** 1746,1751 ****
--- 1799,1805 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* NOTE: The region used is that of the delay slot and NOT the
*************** 000000,5.RS,00000,5.RD,00000,001001:SPEC
*** 1767,1772 ****
--- 1821,1827 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word temp = GPR[RS];
*************** 000000,5.RS,000000000000000,001000:SPECI
*** 1786,1791 ****
--- 1841,1847 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
DELAY_SLOT (GPR[RS]);
*************** 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 1913,1918 ****
--- 1969,1975 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
*************** 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 1930,1935 ****
--- 1987,1993 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
*************** 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 1944,1949 ****
--- 2002,2008 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
*************** 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM
*** 1960,1965 ****
--- 2019,2025 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
*************** 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 1976,1981 ****
--- 2036,2042 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 1990,1995 ****
--- 2051,2057 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2007,2012 ****
--- 2069,2075 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
*************** 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2024,2029 ****
--- 2087,2093 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
*************** 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2040,2045 ****
--- 2104,2110 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
*************** 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2081,2086 ****
--- 2146,2152 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
*************** 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32
*** 2119,2124 ****
--- 2185,2191 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
TRACE_ALU_INPUT1 (IMMEDIATE);
*************** 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2138,2143 ****
--- 2205,2211 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
*************** 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM
*** 2155,2160 ****
--- 2223,2229 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
*************** 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2172,2177 ****
--- 2241,2247 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
*************** 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2189,2194 ****
--- 2259,2265 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
*************** 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2203,2208 ****
--- 2274,2280 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
*************** 000000,0000000000,5.RD,00000,010000:SPEC
*** 2268,2273 ****
--- 2340,2346 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_mfhi (SD_, RD);
*************** 000000,0000000000,5.RD,00000,010010:SPEC
*** 2294,2299 ****
--- 2367,2373 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_mflo (SD_, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,001011:SPECI
*** 2308,2313 ****
--- 2382,2388 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
if (GPR[RT] != 0)
{
*************** 000000,5.RS,5.RT,5.RD,00000,001010:SPECI
*** 2325,2330 ****
--- 2400,2406 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
if (GPR[RT] == 0)
{
*************** 000000,5.RS,000000000000000,010001:SPECI
*** 2386,2391 ****
--- 2462,2468 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_mt_hilo (SD_, HIHISTORY);
*************** 000000,5.RS,000000000000000,010011:SPECI
*** 2405,2410 ****
--- 2482,2488 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_mt_hilo (SD_, LOHISTORY);
*************** 000000,5.RS,5.RT,0000000000,011000:SPECI
*** 2457,2462 ****
--- 2535,2541 ----
*mips32:
*mips64:
*vr4100:
+ *vr5500:
{
do_mult (SD_, RS, RT, 0);
}
*************** 000000,5.RS,5.RT,0000000000,011001:SPECI
*** 2498,2503 ****
--- 2577,2583 ----
*mips32:
*mips64:
*vr4100:
+ *vr5500:
{
do_multu (SD_, RS, RT, 0);
}
*************** 000000,5.RS,5.RT,5.RD,00000,100111:SPECI
*** 2530,2535 ****
--- 2610,2616 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_nor (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,100101:SPECI
*** 2554,2559 ****
--- 2635,2641 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_or (SD_, RS, RT, RD);
*************** 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 2579,2584 ****
--- 2661,2667 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_ori (SD_, RS, RT, IMMEDIATE);
*************** 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32
*** 2592,2597 ****
--- 2675,2681 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
*************** 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2708,2713 ****
--- 2792,2798 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2724,2729 ****
--- 2809,2815 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
unsigned32 instruction = instruction_0;
address_word base = GPR[BASE];
*************** 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2766,2771 ****
--- 2852,2858 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
address_word offset = EXTEND16 (OFFSET);
*************** 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2804,2809 ****
--- 2891,2897 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM
*** 2820,2825 ****
--- 2908,2914 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
}
*************** 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2833,2838 ****
--- 2922,2928 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::
*** 2847,2852 ****
--- 2937,2943 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 2864,2869 ****
--- 2955,2961 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,000000:SP
*** 2888,2893 ****
--- 2980,2986 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* Skip shift for NOP, so that there won't be lots of extraneous
*************** 000000,5.RS,5.RT,5.RD,00000,000100:SPECI
*** 2930,2935 ****
--- 3023,3029 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_sllv (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,101010:SPECI
*** 2954,2959 ****
--- 3048,3054 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_slt (SD_, RS, RT, RD);
*************** 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 2978,2983 ****
--- 3073,3079 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_slti (SD_, RS, RT, IMMEDIATE);
*************** 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 3002,3007 ****
--- 3098,3104 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_sltiu (SD_, RS, RT, IMMEDIATE);
*************** 000000,5.RS,5.RT,5.RD,00000,101011:SPECI
*** 3027,3032 ****
--- 3124,3130 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_sltu (SD_, RS, RT, RD);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,000011:SP
*** 3054,3059 ****
--- 3152,3158 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_sra (SD_, RT, RD, SHIFT);
*************** 000000,5.RS,5.RT,5.RD,00000,000111:SPECI
*** 3083,3088 ****
--- 3182,3188 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_srav (SD_, RS, RT, RD);
*************** 000000,00000,5.RT,5.RD,5.SHIFT,000010:SP
*** 3111,3116 ****
--- 3211,3217 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_srl (SD_, RT, RD, SHIFT);
*************** 000000,5.RS,5.RT,5.RD,00000,000110:SPECI
*** 3139,3144 ****
--- 3240,3246 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_srlv (SD_, RS, RT, RD);
*************** 000000,5.RS,5.RT,5.RD,00000,100010:SPECI
*** 3156,3161 ****
--- 3258,3264 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
*************** 000000,5.RS,5.RT,5.RD,00000,100011:SPECI
*** 3190,3195 ****
--- 3293,3299 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_subu (SD_, RS, RT, RD);
*************** 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 3208,3213 ****
--- 3312,3318 ----
*vr4100:
*r3900:
*vr5000:
+ *vr5500:
{
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
}
*************** 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM
*** 3224,3229 ****
--- 3329,3335 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
*************** 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 3241,3246 ****
--- 3347,3353 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::
*** 3258,3263 ****
--- 3365,3371 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
*************** 000000,000000000000000,5.STYPE,001111:SP
*** 3275,3280 ****
--- 3383,3389 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
SyncOperation (STYPE);
*************** 000000,20.CODE,001100:SPECIAL:32::SYSCAL
*** 3292,3297 ****
--- 3401,3407 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
SignalException (SystemCall, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:
*** 3308,3313 ****
--- 3418,3424 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32
*** 3324,3329 ****
--- 3435,3441 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:
*** 3340,3345 ****
--- 3452,3458 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32
*** 3356,3361 ****
--- 3469,3475 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32
*** 3372,3377 ****
--- 3486,3492 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:
*** 3388,3393 ****
--- 3503,3509 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:
*** 3404,3409 ****
--- 3520,3526 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32
*** 3420,3425 ****
--- 3537,3543 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32
*** 3436,3441 ****
--- 3554,3560 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:
*** 3452,3457 ****
--- 3571,3577 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:
*** 3468,3473 ****
--- 3588,3594 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
SignalException (Trap, instruction_0);
*************** 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32
*** 3484,3489 ****
--- 3605,3611 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
SignalException (Trap, instruction_0);
*************** 000000,5.RS,5.RT,5.RD,00000,100110:SPECI
*** 3508,3513 ****
--- 3630,3636 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_xor (SD_, RS, RT, RD);
*************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 3532,3537 ****
--- 3655,3661 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
do_xori (SD_, RS, RT, IMMEDIATE);
*************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 3616,3621 ****
--- 3740,3746 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
if ((fmt != fmt_single) && (fmt != fmt_double))
*************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 3631,3636 ****
--- 3756,3762 ----
*mips32:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
/* None of these ISAs support Paired Single, so just fall back to
*************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32:
*** 3664,3669 ****
--- 3790,3796 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
if (! COP_Usable (1))
*************** 010001,10,3.FMT,00000,5.FS,5.FD,000101:C
*** 3753,3758 ****
--- 3880,3886 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:CO
*** 3774,3779 ****
--- 3902,3908 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:CO
*** 3849,3854 ****
--- 3978,3984 ----
*mips64:
#*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.C
*** 3886,3891 ****
--- 4016,4022 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001010:C
*** 3904,3909 ****
--- 4035,4041 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001110:C
*** 3924,3929 ****
--- 4056,4062 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,00010,5.RT,5.FS,00000000000:COP1:
*** 3953,3958 ****
--- 4086,4092 ----
*mipsIV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,00110,5.RT,5.FS,00000000000:COP1:
*** 4000,4005 ****
--- 4134,4140 ----
*mipsIV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,10,3.FMT,00000,5.FS,5.FD,100001:C
*** 4037,4042 ****
--- 4172,4178 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,100101:C
*** 4056,4061 ****
--- 4192,4198 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT!6,00000,5.FS,5.FD,100000
*** 4093,4098 ****
--- 4230,4236 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT!6,00000,5.FS,5.FD,100100
*** 4137,4142 ****
--- 4275,4281 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:CO
*** 4159,4164 ****
--- 4298,4304 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,00001,5.RT,5.FS,00000000000:COP1:
*** 4192,4197 ****
--- 4332,4338 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,00101,5.RT,5.FS,00000000000:COP1:
*** 4232,4237 ****
--- 4373,4379 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001011:C
*** 4253,4258 ****
--- 4395,4401 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001111:C
*** 4273,4278 ****
--- 4416,4422 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::
*** 4301,4306 ****
--- 4445,4451 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010011,5.BASE,5.INDEX,5.0,5.FD,000001:CO
*** 4314,4319 ****
--- 4459,4465 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
*************** 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::
*** 4349,4354 ****
--- 4495,4501 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010011,5.BASE,5.INDEX,5.0,5.FD,000000:CO
*** 4362,4367 ****
--- 4509,4515 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
*************** 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP
*** 4376,4381 ****
--- 4524,4530 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010001,00000,5.RT,5.FS,00000000000:COP1:
*** 4407,4412 ****
--- 4556,4562 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,10,3.FMT,00000,5.FS,5.FD,000110:C
*** 4426,4431 ****
--- 4576,4582 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 000000,5.RS,3.CC,0,1.TF,5.RD,00000,00000
*** 4444,4449 ****
--- 4595,4601 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
if (GETFCC(CC) == TF)
*************** 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,01
*** 4460,4465 ****
--- 4612,4618 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:CO
*** 4489,4494 ****
--- 4642,4648 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
if (GPR[RT] != 0)
*************** 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:CO
*** 4512,4517 ****
--- 4666,4672 ----
*mips32:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
if (GPR[RT] == 0)
*************** 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP
*** 4527,4532 ****
--- 4682,4688 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010001,00100,5.RT,5.FS,00000000000:COP1:
*** 4559,4564 ****
--- 4715,4721 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:CO
*** 4577,4582 ****
--- 4734,4740 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,000111:C
*** 4597,4602 ****
--- 4755,4761 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP
*** 4612,4617 ****
--- 4771,4777 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP
*** 4628,4633 ****
--- 4788,4794 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010011,5.BASE,5.INDEX,5.HINT,00000,00111
*** 4668,4673 ****
--- 4829,4835 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
address_word index = GPR[INDEX];
*************** 010001,10,3.FMT,00000,5.FS,5.FD,010101:C
*** 4711,4716 ****
--- 4873,4879 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001000:C
*** 4727,4732 ****
--- 4890,4896 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001100:C
*** 4747,4752 ****
--- 4911,4917 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,010110:C
*** 4763,4768 ****
--- 4928,4934 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
int fmt = FMT;
check_fpu (SD_);
*************** 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::
*** 4789,4794 ****
--- 4955,4961 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
check_fpu (SD_);
*************** 010011,5.BASE,5.INDEX,5.FS,00000001001:C
*** 4802,4807 ****
--- 4969,4975 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
check_fpu (SD_);
check_u64 (SD_, instruction_0);
*************** 010001,10,3.FMT,00000,5.FS,5.FD,000100:C
*** 4837,4842 ****
--- 5005,5011 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:CO
*** 4857,4862 ****
--- 5026,5032 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::
*** 4878,4883 ****
--- 5048,5054 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word base = GPR[BASE];
*************** 010011,5.BASE,5.INDEX,5.FS,00000,001000:
*** 4917,4922 ****
--- 5088,5094 ----
*mipsV:
*mips64:
*vr5000:
+ *vr5500:
{
address_word base = GPR[BASE];
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001001:C
*** 4959,4964 ****
--- 5131,5137 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010001,10,3.FMT,00000,5.FS,5.FD,001101:C
*** 4979,4984 ****
--- 5152,5158 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
int fmt = FMT;
*************** 010000,01000,00000,16.OFFSET:COP0:32::BC
*** 5007,5012 ****
--- 5181,5187 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
010000,01000,00000,16.OFFSET:COP0:32::BC0F
"bc0f <OFFSET>"
*************** 010000,01000,00010,16.OFFSET:COP0:32::BC
*** 5028,5033 ****
--- 5203,5209 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
010000,01000,00001,16.OFFSET:COP0:32::BC0T
*************** 010000,01000,00001,16.OFFSET:COP0:32::BC
*** 5040,5045 ****
--- 5216,5222 ----
*mips32:
*mips64:
*vr4100:
+ *vr5500:
010000,01000,00011,16.OFFSET:COP0:32::BC0TL
*************** 010000,01000,00011,16.OFFSET:COP0:32::BC
*** 5053,5058 ****
--- 5230,5236 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
*************** 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::
*** 5064,5069 ****
--- 5242,5248 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
address_word base = GPR[BASE];
*************** 010000,00001,5.RT,5.RD,00000000000:COP0:
*** 5084,5089 ****
--- 5263,5269 ----
*mipsIV:
*mipsV:
*mips64:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
*************** 010000,00101,5.RT,5.RD,00000000000:COP0:
*** 5096,5101 ****
--- 5276,5282 ----
*mipsIV:
*mipsV:
*mips64:
+ *vr5500:
{
check_u64 (SD_, instruction_0);
DecodeCoproc (instruction_0);
*************** 010000,1,0000000000000000000,011000:COP0
*** 5111,5116 ****
--- 5292,5298 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
{
if (SR & status_ERL)
{
*************** 010000,00000,5.RT,5.RD,00000,6.REGX:COP0
*** 5138,5143 ****
--- 5320,5326 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
TRACE_ALU_INPUT0 ();
*************** 010000,00100,5.RT,5.RD,00000,6.REGX:COP0
*** 5156,5161 ****
--- 5339,5345 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
DecodeCoproc (instruction_0);
*************** 010000,1,0000000000000000000,010000:COP0
*** 5171,5176 ****
--- 5355,5361 ----
*mipsV:
*vr4100:
*vr5000:
+ *vr5500:
*r3900:
{
DecodeCoproc (instruction_0);
*************** 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16
*** 5187,5192 ****
--- 5372,5378 ----
*mips32:
*mips64:
*vr4100:
+ *vr5500:
*r3900:
{
DecodeCoproc (instruction_0);
*************** 010000,1,0000000000000000000,001000:COP0
*** 5205,5210 ****
--- 5391,5397 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
010000,1,0000000000000000000,000001:COP0:32::TLBR
*************** 010000,1,0000000000000000000,000001:COP0
*** 5218,5223 ****
--- 5405,5411 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
010000,1,0000000000000000000,000010:COP0:32::TLBWI
*************** 010000,1,0000000000000000000,000010:COP0
*** 5231,5236 ****
--- 5419,5425 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
010000,1,0000000000000000000,000110:COP0:32::TLBWR
*************** 010000,1,0000000000000000000,000110:COP0
*** 5244,5249 ****
--- 5433,5439 ----
*mips64:
*vr4100:
*vr5000:
+ *vr5500:
\f
:include:::m16.igen
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-18 20:55 ` Richard Sandiford
2004-03-19 0:09 ` Richard Sandiford
@ 2004-03-19 15:19 ` Andrew Cagney
2004-03-24 7:59 ` Richard Sandiford
2004-03-25 7:15 ` cgd
2 siblings, 1 reply; 19+ messages in thread
From: Andrew Cagney @ 2004-03-19 15:19 UTC (permalink / raw)
To: Richard Sandiford, cgd; +Cc: gdb-patches
> cgd@broadcom.com writes:
>
>>> Now that the mips sim 'multi' bits are in place (including good
>>> default), and we have MIPS_MACH(SD) (thanks! 8-), it should be
>>> possible to code a simple macro which checks for the appropriate bfd
>>> machine, and decides whether interlocks are present.
>
>
> Well, I had a similar check in:
>
> http://sources.redhat.com/ml/gdb-patches/2002-11/msg00642.html
>
> OK, so it wasn't wrapped up in a nice macro, it just checked the
> architecture directly:
>
> + /* There are no timing requirements in vr5500 code. */
> + if (MIPS_MACH (SD) == bfd_mach_mips5500)
> + return 1;
>
> But that was exactly what Andrew objected to:
>
> http://sources.redhat.com/ml/gdb-patches/2002-11/msg00668.html
FYI, I think the comment still stands - I'm describing how IGEN is ment
to be used (and is what Richard's patch does).
(Richard thanks for pokeing at this),
Andrew
> Then there was:
>
> http://sources.redhat.com/ml/gdb-patches/2002-12/msg00080.html
>
> To quote:
>
> As for having to tag each individual entry in the .igen file with an
> explicit CPU. Yes, that sux. However, I also believe that it has
> significantly reduced the overall error rate (no more breaking one
> target by editing another) and that benefit vastly outweighs the short
> term pain.
>
> Richard
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-19 15:19 ` Andrew Cagney
@ 2004-03-24 7:59 ` Richard Sandiford
2004-03-24 15:59 ` cgd
0 siblings, 1 reply; 19+ messages in thread
From: Richard Sandiford @ 2004-03-24 7:59 UTC (permalink / raw)
To: Andrew Cagney; +Cc: cgd, gdb-patches
After leaving a bit of breathing room in case cgd or anyone else
wanted to object...
Andrew Cagney <cagney@gnu.org> writes:
>> cgd@broadcom.com writes:
>>>> Now that the mips sim 'multi' bits are in place (including good
>>>> default), and we have MIPS_MACH(SD) (thanks! 8-), it should be
>>>> possible to code a simple macro which checks for the appropriate bfd
>>>> machine, and decides whether interlocks are present.
>> Well, I had a similar check in:
>> http://sources.redhat.com/ml/gdb-patches/2002-11/msg00642.html
>> OK, so it wasn't wrapped up in a nice macro, it just checked the
>> architecture directly:
>> + /* There are no timing requirements in vr5500 code. */
>> + if (MIPS_MACH (SD) == bfd_mach_mips5500)
>> + return 1;
>> But that was exactly what Andrew objected to:
>> http://sources.redhat.com/ml/gdb-patches/2002-11/msg00668.html
>
> FYI, I think the comment still stands - I'm describing how IGEN is ment
> to be used (and is what Richard's patch does).
>
> (Richard thanks for pokeing at this),
> Andrew
Does this mean that the patch is approved?
Richard
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-24 7:59 ` Richard Sandiford
@ 2004-03-24 15:59 ` cgd
0 siblings, 0 replies; 19+ messages in thread
From: cgd @ 2004-03-24 15:59 UTC (permalink / raw)
To: Richard Sandiford; +Cc: Andrew Cagney, gdb-patches
At Wed, 24 Mar 2004 08:00:52 +0000, Richard Sandiford wrote:
> After leaving a bit of breathing room in case cgd or anyone else
> wanted to object...
I wrote most of a reply w/in hours of your second reply, then i
decided maybe i ought to put it down for a bit.
I'll send some more mail today. Sorry for the delay.
> Does this mean that the patch is approved?
No.
cgd
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-18 20:55 ` Richard Sandiford
2004-03-19 0:09 ` Richard Sandiford
2004-03-19 15:19 ` Andrew Cagney
@ 2004-03-25 7:15 ` cgd
2004-03-25 7:45 ` Richard Sandiford
2004-03-25 22:14 ` Andrew Cagney
2 siblings, 2 replies; 19+ messages in thread
From: cgd @ 2004-03-25 7:15 UTC (permalink / raw)
To: Richard Sandiford; +Cc: gdb-patches
[ chunks of reply re-ordered. also, sorry for the delay, i've been swamped. ]
At Thu, 18 Mar 2004 20:55:56 +0000, Richard Sandiford wrote:
> Well, I had a similar check in:
>
> http://sources.redhat.com/ml/gdb-patches/2002-11/msg00642.html
>
> OK, so it wasn't wrapped up in a nice macro, it just checked the
> architecture directly:
>
> + /* There are no timing requirements in vr5500 code. */
> + if (MIPS_MACH (SD) == bfd_mach_mips5500)
> + return 1;
Yes, I know. (You also did it in one place rather than three, i.e.,
didn't split it along the current check_* fn lines... though i don't
recall how much i changed them when I cleaned that code up a couple
(?) of months ago.)
> As for having to tag each individual entry in the .igen file with an
> explicit CPU. Yes, that sux. However, I also believe that it has
> significantly reduced the overall error rate (no more breaking one
> target by editing another) and that benefit vastly outweighs the short
> term pain.
I still take issue with the latter ("short term pain"), for such
additions have to stay in for the life of support for the arch in the
simulator, which *should* be quite long term.
> But that was exactly what Andrew objected to:
And he and I (strongly, IMO) disagreed at that time. (IIRC, I think I
mentioned at the time that the right solution to this is better
testing. I still think that's true.)
Of course, in August of last year, (unprompted by me!) he decided to
stop being MIPS co-maintainer. So, at this point, I'm the approval
authority, and I like my style of patch most. 8-)
I would like to see it augmented to include some test code (now that
there's a prelim test framework for mips, with what, 1 test? 8-), but
as long as you commit to actually doing that I'm OK with it waiting a
little bit.
If this is not an acceptable solution to Andrew (as a global
maintainer), then my back-off position is make MIPS IV follow the MIPS
architecture documentation, and make all "MIPS IV-ish" processors
which are documented to not act like MIPS' MIPS IV definition be "MIPS
III +". That is more technically correct from an architecture POV
than the current MIPS IV definition, unless somebody's got some MIPS
IV documentation that contradicts the current MIPS specs.
Note that I most decidedly do *not* think that is the right solution.
cgd
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-25 7:15 ` cgd
@ 2004-03-25 7:45 ` Richard Sandiford
[not found] ` <mailpost.1080200738.13330@news-sj1-1>
2004-03-25 22:14 ` Andrew Cagney
1 sibling, 1 reply; 19+ messages in thread
From: Richard Sandiford @ 2004-03-25 7:45 UTC (permalink / raw)
To: cgd; +Cc: gdb-patches, ac131313
cgd@broadcom.com writes:
> And he and I (strongly, IMO) disagreed at that time. (IIRC, I think I
> mentioned at the time that the right solution to this is better
> testing. I still think that's true.)
>
> Of course, in August of last year, (unprompted by me!) he decided to
> stop being MIPS co-maintainer. So, at this point, I'm the approval
> authority, and I like my style of patch most. 8-)
Well, so far I've done it your way, and had it rejected by Andrew, and
I've done it Andrew's way and had it rejected by you. ;) I'd like to
make sure there's now some agreement before going ahead and updating
the original MIPS_MACH version.
So, Andrew, is it OK with you to have a bfd_mach check in mips.igen?
As per previous discussion, we'd have something like:
if (MIPS_MACH (SD) == bfd_mach_mips5500)
...
Even if it's not how you'd recommend it be done, is it at least
something you can accept?
Richard
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
[not found] ` <mailpost.1080200738.13330@news-sj1-1>
@ 2004-03-25 18:53 ` cgd
0 siblings, 0 replies; 19+ messages in thread
From: cgd @ 2004-03-25 18:53 UTC (permalink / raw)
To: rsandifo; +Cc: gdb-patches, ac131313
At Thu, 25 Mar 2004 07:45:38 +0000 (UTC), "Richard Sandiford" wrote:
> So, Andrew, is it OK with you to have a bfd_mach check in mips.igen?
> As per previous discussion, we'd have something like:
>
> if (MIPS_MACH (SD) == bfd_mach_mips5500)
> ...
That is explicitly *not* what i want. I want it hidden under macros,
so that there are no obvious uses of bfd_mach* in mips.igen itself.
Given that we already have plenty of calls out to macros, some of
which may already have an architecture-related check buried way inside
(well, i don't think most do right not, but they could), IMO there's
no reason it couldn't be done in this case.
cgd
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-25 7:15 ` cgd
2004-03-25 7:45 ` Richard Sandiford
@ 2004-03-25 22:14 ` Andrew Cagney
2004-03-26 0:01 ` cgd
1 sibling, 1 reply; 19+ messages in thread
From: Andrew Cagney @ 2004-03-25 22:14 UTC (permalink / raw)
To: cgd; +Cc: Richard Sandiford, gdb-patches
>>> As for having to tag each individual entry in the .igen file with an
>>> explicit CPU. Yes, that sux. However, I also believe that it has
>>> significantly reduced the overall error rate (no more breaking one
>>> target by editing another) and that benefit vastly outweighs the short
>>> term pain.
>
>
> I still take issue with the latter ("short term pain"), for such
> additions have to stay in for the life of support for the arch in the
> simulator, which *should* be quite long term.
Look at it this way, if the igen mechanism is used, gcc is able to
eliminate everything :-)
If there's another way of achieving the same effect, I'm interested.
>>> But that was exactly what Andrew objected to:
>
>
> And he and I (strongly, IMO) disagreed at that time. (IIRC, I think I
> mentioned at the time that the right solution to this is better
> testing. I still think that's true.)
>
> Of course, in August of last year, (unprompted by me!) he decided to
> stop being MIPS co-maintainer. So, at this point, I'm the approval
> authority, and I like my style of patch most. 8-)
>
> I would like to see it augmented to include some test code (now that
> there's a prelim test framework for mips, with what, 1 test? 8-), but
> as long as you commit to actually doing that I'm OK with it waiting a
> little bit.
Your call.
Andrew
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-25 22:14 ` Andrew Cagney
@ 2004-03-26 0:01 ` cgd
2004-03-26 0:28 ` Andrew Cagney
0 siblings, 1 reply; 19+ messages in thread
From: cgd @ 2004-03-26 0:01 UTC (permalink / raw)
To: Andrew Cagney; +Cc: Richard Sandiford, gdb-patches
At Thu, 25 Mar 2004 17:14:18 -0500, Andrew Cagney wrote:
> Look at it this way, if the igen mechanism is used, gcc is able to
> eliminate everything :-)
In the case of a single-architecture sim (i.e., not 'multi', then
yes), GCC will automatically eliminate the test.
In the case of a multiple-architecture sim, it won't. But (a) at
least in my mind, i'm not worried about absolute maximal performance
from that configuration (if you want max performance, build a single
arch sim), and (b) until somebody quantifies the difference, I'll
claim that i don't believe it'll be a measurable difference. 8-)
cgd
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-26 0:01 ` cgd
@ 2004-03-26 0:28 ` Andrew Cagney
[not found] ` <mailpost.1080260907.10999@news-sj1-1>
0 siblings, 1 reply; 19+ messages in thread
From: Andrew Cagney @ 2004-03-26 0:28 UTC (permalink / raw)
To: cgd; +Cc: Richard Sandiford, gdb-patches
> At Thu, 25 Mar 2004 17:14:18 -0500, Andrew Cagney wrote:
>
>>> Look at it this way, if the igen mechanism is used, gcc is able to
>>> eliminate everything :-)
>
>
> In the case of a single-architecture sim (i.e., not 'multi', then
> yes), GCC will automatically eliminate the test.
>
> In the case of a multiple-architecture sim, it won't.
It still does (or at least can), trust me :-)
> But (a) at
> least in my mind, i'm not worried about absolute maximal performance
> from that configuration (if you want max performance, build a single
> arch sim), and (b) until somebody quantifies the difference, I'll
> claim that i don't believe it'll be a measurable difference. 8-)
But yes, you won't measure the difference.
Andrew
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
[not found] ` <mailpost.1080260907.10999@news-sj1-1>
@ 2004-03-26 2:19 ` cgd
0 siblings, 0 replies; 19+ messages in thread
From: cgd @ 2004-03-26 2:19 UTC (permalink / raw)
To: cagney; +Cc: Richard Sandiford, gdb-patches
At Fri, 26 Mar 2004 00:28:27 +0000 (UTC), "Andrew Cagney" wrote:
> > At Thu, 25 Mar 2004 17:14:18 -0500, Andrew Cagney wrote:
> >
> >>> Look at it this way, if the igen mechanism is used, gcc is able to
> >>> eliminate everything :-)
> > In the case of a single-architecture sim (i.e., not 'multi', then
> > yes), GCC will automatically eliminate the test.
> > In the case of a multiple-architecture sim, it won't.
>
> It still does (or at least can), trust me :-)
err, sorry, i think i misquoted you. What I meant to quote was:
> If there's another way of achieving the same effect, I'm interested.
I know that doing multi-arch checking entirely with different machine
attributes will eliminate the diff.
(actually, in that case, it's still "mostly," now that i think about
it. in multiple-MIPS-arch-capable sims, it still moves moves the arch
check up into sim_engine_run.)
cgd
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
2004-03-19 0:09 ` cgd
2004-03-18 17:57 ` cgd
2004-03-18 20:55 ` Richard Sandiford
@ 2004-03-28 10:16 ` Richard Sandiford
[not found] ` <mailpost.1080469040.8967@news-sj1-1>
2 siblings, 1 reply; 19+ messages in thread
From: Richard Sandiford @ 2004-03-28 10:16 UTC (permalink / raw)
To: cgd; +Cc: gdb-patches
cgd@broadcom.com writes:
> At Thu, 18 Mar 2004 15:06:42 +0000 (UTC), "Richard Sandiford" wrote:
>> Various suggestions were made about how this could be handled, but I
>> think Andrew's position remained the same: we shouldn't try to treat the
>> vr5500 ISA as "MIPS IV plus a bit and minus a bit" (my words, not his).
>> He reckoned every vr5500 instruction should be marked as such.
>
> My reading is, unfortunately, is that it is a *correct* implementation
> of the MIPS ISA.
>
> At least according to the "Historical information" in the MIPS64 AFP
> Volume II (Basic Instruction Set) -- I'm looking at revisions around
> 1.0 here -- the 3-cycle hi/lo hazards should only have been a problem
> for MIPS I-III.
>
> I.e., MIPS IV processors which *have* these hi/lo hazards are the
> things broken... but as you note at least according to the 5400 docs,
> it is MIPS IV and does have the hazard.
Hmm. I have something that claims to be the "MIPS IV Instruction Set",
Revision 3.2, dated September 1995, (C) MIPS Technologies. It _does_
document the hazards. Not quite sure where I got hold of it though...
If that's anything to go by, MIPS IV parts with these hazards might not
necessarily be broken. There seems to be enough ambiguity that the code
should just say it's ambiguous rather than call out one side as being wrong.
> I'd rather see an implementation that acts somewhat like the (rough,
> uncompiled, not sanity-checked) patch below. Additional advice: make
> sure the comment describing the new macros mentions the fact that they
> should have cases only for certain ISAs' processors (mipsIV, mipsV).
OK, this patch worked with a couple of minor mods: it needed s/SD_/SD/
in the macro calls, and there was some inverted logic in the check_mt_hilo
hunk. Not bad for an untested patch. ;)
> The names were just a suggestion. there are probably better, shorter
> ones, and I didn't try to reconcile them with any other code (e.g. the
> code in headers where they might be defined 8-).
I kept the same style of names, but with "MIPS_MACH_..." instead of
"MIPS_ARCH_...", for consistency with the existing MIPS_MACH macro.
As per request, I've added some test cases to the testsuite.
This involved splitting the existing model lists into two: those that
are supported directly, and those that can be modelled approximately
because they are "subsets" of directly-supported models. E.g.
mipsisa32-elf can simulate most mips1 code, but mips1 has the hazards
and mips32 doesn't.
Tested with the gcc testsute on mips64vrel-elf The VR5500 tests no longer
suffer from bogus hazard complaints. Also run through the sim testsuite
on mipsisa64-elf, mipsisa32-elf, mips64-elf, mips-elf and mips64vrel-elf.
OK to install?
Richard
2004-??-?? Chris Demetriou <cgd@broadcom.com>
Richard Sandiford <rsandifo@redhat.com>
sim/mips/
* sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
(MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
* mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
separate implementations for mipsIV and mipsV. Use new macros to
determine whether the restrictions apply.
sim/testsuite/
* sim/mips/hilo-hazard-[123].s: New files.
* sim/mips/basic.exp (run_hilo_test): New procedure.
(models): Only list models that are included in the configuration.
(submodels): New variable, set to submodels of the above.
(mips64vr-*-elf, mips64vrel-*-elf): New configuration stanza.
Run hilo-hazard-[123].s.
Index: sim/mips/sim-main.h
===================================================================
RCS file: /cvs/src/src/sim/mips/sim-main.h,v
retrieving revision 1.25
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.25 sim-main.h
*** sim/mips/sim-main.h 5 Jan 2003 07:56:59 -0000 1.25
--- sim/mips/sim-main.h 28 Mar 2004 09:33:12 -0000
*************** #define MIPS_MACH(SD) mips_mach_multi(SD
*** 953,958 ****
--- 953,970 ----
#define MIPS_MACH(SD) MIPS_MACH_DEFAULT
#endif
+ /* Macros for determining whether a MIPS IV or MIPS V part is subject
+ to the hi/lo restrictions described in mips.igen. */
+
+ #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
+ (MIPS_MACH (SD) != bfd_mach_mips5500)
+
+ #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
+ (MIPS_MACH (SD) != bfd_mach_mips5500)
+
+ #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
+ (MIPS_MACH (SD) != bfd_mach_mips5500)
+
#if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
#include "sim-main.c"
#endif
Index: sim/mips/mips.igen
===================================================================
RCS file: /cvs/src/src/sim/mips/mips.igen,v
retrieving revision 1.55
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.55 mips.igen
*** sim/mips/mips.igen 20 Jan 2004 07:06:14 -0000 1.55
--- sim/mips/mips.igen 28 Mar 2004 09:33:12 -0000
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 238,250 ****
// On the r3900, restriction (2) is not present, and restriction (3) is not
// present for multiplication.
//
! // For now this code is paranoid. Historically the simulator
! // enforced restrictions (2) and (3) for more ISAs and CPU types than
! // necessary. Unfortunately, at least some MIPS IV and later parts'
! // documentation describes them as having these hazards (e.g. vr5000),
! // so they can't be removed for at leats MIPS IV. MIPS V hasn't been
! // checked (since there are no known hardware implementations).
! //
// check_mf_cycles:
//
--- 238,252 ----
// On the r3900, restriction (2) is not present, and restriction (3) is not
// present for multiplication.
//
! // Unfortunately, there seems to be some confusion about whether the last
! // two restrictions should apply to "MIPS IV" as well. One edition of
! // the MIPS IV ISA says they do, but references in later ISA documents
! // suggest they don't.
! //
! // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
! // these restrictions, while others, like the VR5500, don't. To accomodate
! // such differences, the MIPS IV and MIPS V version of these helper functions
! // use auxillary routines to determine whether the restriction applies.
// check_mf_cycles:
//
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 274,281 ****
*mipsI:
*mipsII:
*mipsIII:
- *mipsIV:
- *mipsV:
*vr4100:
*vr5000:
{
--- 276,281 ----
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 287,292 ****
--- 287,304 ----
}
:function:::int:check_mt_hilo:hilo_history *history
+ *mipsIV:
+ *mipsV:
+ {
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
+ || check_mf_cycles (SD_, history, time, "MT"));
+ history->mt.timestamp = time;
+ history->mt.cia = CIA;
+ return ok;
+ }
+
+ :function:::int:check_mt_hilo:hilo_history *history
*mips32:
*mips64:
*r3900:
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 350,357 ****
*mipsI:
*mipsII:
*mipsIII:
- *mipsIV:
- *mipsV:
*vr4100:
*vr5000:
{
--- 362,367 ----
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 366,371 ****
--- 376,396 ----
}
:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+ *mipsIV:
+ *mipsV:
+ {
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
+ || (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP")));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+ }
+
+ :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
*mips32:
*mips64:
*r3900:
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 389,396 ****
*mipsI:
*mipsII:
*mipsIII:
- *mipsIV:
- *mipsV:
*vr4100:
*vr5000:
*r3900:
--- 414,419 ----
*************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3
*** 398,403 ****
--- 421,441 ----
signed64 time = sim_events_time (SD);
int ok = (check_mf_cycles (SD_, hi, time, "OP")
&& check_mf_cycles (SD_, lo, time, "OP"));
+ hi->op.timestamp = time;
+ lo->op.timestamp = time;
+ hi->op.cia = CIA;
+ lo->op.cia = CIA;
+ return ok;
+ }
+
+ :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
+ *mipsIV:
+ *mipsV:
+ {
+ signed64 time = sim_events_time (SD);
+ int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
+ || (check_mf_cycles (SD_, hi, time, "OP")
+ && check_mf_cycles (SD_, lo, time, "OP")));
hi->op.timestamp = time;
lo->op.timestamp = time;
hi->op.cia = CIA;
Index: sim/testsuite/sim/mips/basic.exp
===================================================================
RCS file: /cvs/src/src/sim/testsuite/sim/mips/basic.exp,v
retrieving revision 1.1
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.1 basic.exp
*** sim/testsuite/sim/mips/basic.exp 26 Jan 2004 08:12:44 -0000 1.1
--- sim/testsuite/sim/mips/basic.exp 28 Mar 2004 09:33:12 -0000
***************
*** 6,26 ****
# than the compiler) can't necessarily find.
unset_currtarget_info ldscript
# Only test mips*-elf (e.g., no mips-linux), and only test if the target
# board really is a simulator (sim tests don't work on real HW).
if {[istarget mips*-elf] && [board_info target exists is_simulator]} {
if {[istarget mipsisa64*-elf]} {
! set models "mips1 mips2 mips3 mips4 mips32 mips64"
} elseif {[istarget mipsisa32*-elf]} {
! set models "mips1 mips2 mips32"
} elseif {[istarget mips64*-elf]} {
! set models "mips1 mips2 mips3"
} else {
# fall back to just testing mips1 code.
set models "mips1"
}
set cpu_option -march
! run_sim_test sanity.s $models
}
--- 6,65 ----
# than the compiler) can't necessarily find.
unset_currtarget_info ldscript
+ # Do "run_sim_test TESTFILE MODELS" for each combination of the
+ # mf{lo,hi} -> mult/div/mt{lo,hi} hazard described in mips.igen.
+ # Insert NOPS nops after the mflo or mfhi.
+ proc run_hilo_test {testfile models nops} {
+ foreach reg {lo hi} {
+ foreach insn "{mult\t\$4,\$4} {div\t\$0,\$4,\$4} {mt$reg\t\$4}" {
+ set contents ""
+ append contents "\t.macro hilo\n"
+ append contents "\tmf$reg\t\$4\n"
+ append contents "\t.rept\t$nops\n"
+ append contents "\tnop\n"
+ append contents "\t.endr\n"
+ append contents "\t$insn\n"
+ append contents "\t.endm"
+
+ verbose -log "HILO test:\n$contents"
+ set file [open hilo-hazard.inc w]
+ puts $file $contents
+ close $file
+
+ run_sim_test $testfile $models
+ }
+ }
+ }
+
+
# Only test mips*-elf (e.g., no mips-linux), and only test if the target
# board really is a simulator (sim tests don't work on real HW).
if {[istarget mips*-elf] && [board_info target exists is_simulator]} {
if {[istarget mipsisa64*-elf]} {
! set models "mips32 mips64"
! set submodels "mips1 mips2 mips3 mips4"
} elseif {[istarget mipsisa32*-elf]} {
! set models "mips32"
! set submodels "mips1 mips2"
! } elseif {[istarget mips64vr-*-elf] || [istarget mips64vrel-*-elf]} {
! set models "vr4100 vr4111 vr4120 vr5000 vr5400 vr5500"
! set submodels "mips1 mips2 mips3 mips4"
} elseif {[istarget mips64*-elf]} {
! set models "mips3"
! set submodels "mips1 mips2"
} else {
# fall back to just testing mips1 code.
set models "mips1"
+ set submodels ""
}
+ append submodels " " $models
set cpu_option -march
! run_sim_test sanity.s $submodels
! foreach nops {0 1} {
! run_hilo_test hilo-hazard-1.s $models $nops
! run_hilo_test hilo-hazard-2.s $models $nops
! }
! run_hilo_test hilo-hazard-3.s $models 2
}
*** /dev/null Tue Jun 17 23:06:41 2003
--- sim/testsuite/sim/mips/hilo-hazard-1.s Sat Mar 27 20:56:32 2004
***************
*** 0 ****
--- 1,19 ----
+ # Test for architectures with mf{hi,lo} -> mult/div/mt{hi,lo} hazards.
+ #
+ # mach: mips1 mips2 mips3 mips4 vr4100 vr4111 vr4120 vr5000 vr5400
+ # as: -mabi=eabi
+ # ld: -N -Ttext=0x80010000
+ # output: HILO: * too close to MF at *\\n\\nprogram stopped*\\n
+ # xerror:
+
+ .include "hilo-hazard.inc"
+ .include "testutils.inc"
+
+ setup
+
+ .set noreorder
+ .ent DIAG
+ DIAG:
+ hilo
+ pass
+ .end DIAG
*** /dev/null Tue Jun 17 23:06:41 2003
--- sim/testsuite/sim/mips/hilo-hazard-2.s Sat Mar 27 20:56:41 2004
***************
*** 0 ****
--- 1,18 ----
+ # Test for architectures without mf{hi,lo} -> mult/div/mt{hi,lo} hazards.
+ #
+ # mach: vr5500 mips32 mips64
+ # as: -mabi=eabi
+ # ld: -N -Ttext=0x80010000
+ # output: pass\\n
+
+ .include "hilo-hazard.inc"
+ .include "testutils.inc"
+
+ setup
+
+ .set noreorder
+ .ent DIAG
+ DIAG:
+ hilo
+ pass
+ .end DIAG
*** /dev/null Tue Jun 17 23:06:41 2003
--- sim/testsuite/sim/mips/hilo-hazard-3.s Sat Mar 27 20:56:59 2004
***************
*** 0 ****
--- 1,18 ----
+ # Test for mf{hi,lo} -> mult/div/mt{hi,lo} with 2 nops inbetween.
+ #
+ # mach: all
+ # as: -mabi=eabi
+ # ld: -N -Ttext=0x80010000
+ # output: pass\\n
+
+ .include "hilo-hazard.inc"
+ .include "testutils.inc"
+
+ setup
+
+ .set noreorder
+ .ent DIAG
+ DIAG:
+ hilo
+ pass
+ .end DIAG
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
[not found] ` <mailpost.1080469040.8967@news-sj1-1>
@ 2004-03-29 19:38 ` cgd
2004-04-10 6:59 ` cgd
1 sibling, 0 replies; 19+ messages in thread
From: cgd @ 2004-03-29 19:38 UTC (permalink / raw)
To: rsandifo; +Cc: gdb-patches
At Sun, 28 Mar 2004 10:17:20 +0000 (UTC), "Richard Sandiford" wrote:
> OK, this patch worked with a couple of minor mods: it needed s/SD_/SD/
> in the macro calls, and there was some inverted logic in the check_mt_hilo
> hunk. Not bad for an untested patch. ;)
Some have said in the past that my logic is twisted^Winverted... 8-)
> OK to install?
Yes.
The new testsuite bits are a bit ... odd, but then, I yet don't know
what the "right way" to do the MIPS sim testsuite code is. I don't
get the feeling that listing all the arches all over is the best
thing, but then, any testsuite at all is better than nothing. If you
think of a better way to do the sim testsuite for MIPS, by all means,
I'm open to something.
chris
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [rfa/mips] Second go at vr5500 hilo hazard fix
[not found] ` <mailpost.1080469040.8967@news-sj1-1>
2004-03-29 19:38 ` cgd
@ 2004-04-10 6:59 ` cgd
1 sibling, 0 replies; 19+ messages in thread
From: cgd @ 2004-04-10 6:59 UTC (permalink / raw)
To: rsandifo; +Cc: gdb-patches
At Sun, 28 Mar 2004 10:17:20 +0000 (UTC), "Richard Sandiford" wrote:
> sim/testsuite/
> * sim/mips/hilo-hazard-[123].s: New files.
> * sim/mips/basic.exp (run_hilo_test): New procedure.
> (models): Only list models that are included in the configuration.
> (submodels): New variable, set to submodels of the above.
> (mips64vr-*-elf, mips64vrel-*-elf): New configuration stanza.
> Run hilo-hazard-[123].s.
i just noticed that this went into sim/testsuite/ChangeLog, rather than
sim/testsuite/sim/mips/ChangeLog.
I've moved it. (FYI for next time.)
chris
^ permalink raw reply [flat|nested] 19+ messages in thread
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2004-03-18 15:05 [rfa/mips] Second go at vr5500 hilo hazard fix Richard Sandiford
2004-03-19 0:09 ` Richard Sandiford
[not found] ` <mailpost.1079622402.27828@news-sj1-1>
2004-03-19 0:09 ` cgd
2004-03-18 17:57 ` cgd
2004-03-18 20:55 ` Richard Sandiford
2004-03-19 0:09 ` Richard Sandiford
2004-03-19 15:19 ` Andrew Cagney
2004-03-24 7:59 ` Richard Sandiford
2004-03-24 15:59 ` cgd
2004-03-25 7:15 ` cgd
2004-03-25 7:45 ` Richard Sandiford
[not found] ` <mailpost.1080200738.13330@news-sj1-1>
2004-03-25 18:53 ` cgd
2004-03-25 22:14 ` Andrew Cagney
2004-03-26 0:01 ` cgd
2004-03-26 0:28 ` Andrew Cagney
[not found] ` <mailpost.1080260907.10999@news-sj1-1>
2004-03-26 2:19 ` cgd
2004-03-28 10:16 ` Richard Sandiford
[not found] ` <mailpost.1080469040.8967@news-sj1-1>
2004-03-29 19:38 ` cgd
2004-04-10 6:59 ` cgd
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