From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18359 invoked by alias); 18 Mar 2004 15:05:41 -0000 Mailing-List: contact gdb-patches-help@sources.redhat.com; run by ezmlm Precedence: bulk List-Subscribe: List-Archive: List-Post: List-Help: , Sender: gdb-patches-owner@sources.redhat.com Received: (qmail 18204 invoked from network); 18 Mar 2004 15:05:34 -0000 Received: from unknown (HELO mx1.redhat.com) (66.187.233.31) by sources.redhat.com with SMTP; 18 Mar 2004 15:05:34 -0000 Received: from int-mx2.corp.redhat.com (nat-pool-rdu-dmz.redhat.com [172.16.52.200] (may be forged)) by mx1.redhat.com (8.12.10/8.12.10) with ESMTP id i2IF5V4b001333 for ; Thu, 18 Mar 2004 10:05:32 -0500 Received: from localhost (vpn50-45.rdu.redhat.com [172.16.50.45]) by int-mx2.corp.redhat.com (8.11.6/8.11.6) with ESMTP id i2IF5SM27251 for ; Thu, 18 Mar 2004 10:05:29 -0500 Received: from rsandifo by localhost with local (Exim 3.35 #1) id 1B3z6B-0004vu-00 for gdb-patches@sources.redhat.com; Thu, 18 Mar 2004 15:06:19 +0000 To: gdb-patches@sources.redhat.com Subject: [rfa/mips] Second go at vr5500 hilo hazard fix From: Richard Sandiford Date: Fri, 19 Mar 2004 00:09:00 -0000 Message-ID: <87oequw5xw.fsf@redhat.com> User-Agent: Gnus/5.1006 (Gnus v5.10.6) Emacs/21.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-RedHat-Spam-Score: 0 X-SW-Source: 2004-03/txt/msg00422.txt.bz2 Message-ID: <20040319000900.5uoKtCsWF72E5qQZsKEJg05djpIZWpgv47upigFqgKY@z> Several months ago, I submitted a patch to add NEC VR support to sim/mips. Most of it was accepted, but one controversial bit was the handling of hi/lo hazards for the vr5500. The vr5500 is currently treated as MIPS IV "plus a bit", i.e., it uses all mips.igen entries marked "*mipsIV", plus some others that are explicitly marked as "*vr5500". However, unlike some MIPS IV parts, including the vr5400, the vr5500 has interlocks to work around the usual mflo -> mtlo/mul/div hazard. Various suggestions were made about how this could be handled, but I think Andrew's position remained the same: we shouldn't try to treat the vr5500 ISA as "MIPS IV plus a bit and minus a bit" (my words, not his). He reckoned every vr5500 instruction should be marked as such. The patch below does this. Tested on mips64vrel-elf. OK to install? Richard * configure.in (mips64vr-*-*, mips64vrel-*-*): Remove mipsIV from the vr5500 entry in sim_multi_configs. * configure: Regenerate. * mips.igen: Explicitly mark all vr5500 instructions. Index: sim/mips/configure.in =================================================================== RCS file: /cvs/src/src/sim/mips/configure.in,v retrieving revision 1.6 diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.6 configure.in *** sim/mips/configure.in 5 Jan 2003 07:56:59 -0000 1.6 --- sim/mips/configure.in 18 Mar 2004 14:49:48 -0000 *************** case "${target}" in *** 131,137 **** vr4120:mipsIII,mips16,vr4120:32,64:mips4120\ vr5000:mipsIV:32,64,f:mips4300,mips5000\ vr5400:mipsIV,vr5400:32,64,f:mips5400\ ! vr5500:mipsIV,vr5500:32,64,f:mips5500" sim_multi_default=mips5000 ;; mips64*-*-*) sim_igen_filter="32,64,f" --- 131,137 ---- vr4120:mipsIII,mips16,vr4120:32,64:mips4120\ vr5000:mipsIV:32,64,f:mips4300,mips5000\ vr5400:mipsIV,vr5400:32,64,f:mips5400\ ! vr5500:vr5500:32,64,f:mips5500" sim_multi_default=mips5000 ;; mips64*-*-*) sim_igen_filter="32,64,f" Index: sim/mips/mips.igen =================================================================== RCS file: /cvs/src/src/sim/mips/mips.igen,v retrieving revision 1.55 diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.55 mips.igen *** sim/mips/mips.igen 20 Jan 2004 07:06:14 -0000 1.55 --- sim/mips/mips.igen 18 Mar 2004 14:49:48 -0000 *************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3 *** 134,139 **** --- 134,140 ---- *mips32: *vr4100: *vr5000: + *vr5500: *r3900: { return base + offset; *************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3 *** 168,173 **** --- 169,175 ---- *mipsV: *vr4100: *vr5000: + *vr5500: *r3900: { /* For historical simulator compatibility (until documentation is *************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3 *** 206,211 **** --- 208,214 ---- *mipsV: *vr4100: *vr5000: + *vr5500: *r3900: { } *************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3 *** 289,294 **** --- 292,298 ---- :function:::int:check_mt_hilo:hilo_history *history *mips32: *mips64: + *vr5500: *r3900: { signed64 time = sim_events_time (SD); *************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3 *** 313,318 **** --- 317,323 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { signed64 time = sim_events_time (SD); *************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3 *** 368,373 **** --- 373,379 ---- :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo *mips32: *mips64: + *vr5500: *r3900: { /* FIXME: could record the fact that a stall occured if we want */ *************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3 *** 408,413 **** --- 414,420 ---- :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo *mips32: *mips64: + *vr5500: { signed64 time = sim_events_time (SD); hi->op.timestamp = time; *************** 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:3 *** 430,435 **** --- 437,443 ---- *mipsV: *vr4100: *vr5000: + *vr5500: { // The check should be similar to mips64 for any with PX/UX bit equivalents. } *************** 000000,5.RS,5.RT,5.RD,00000,100000:SPECI *** 464,469 **** --- 472,478 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) *************** 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32: *** 490,495 **** --- 499,505 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { if (NotWordValue (GPR[RS])) *************** 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32: *** 525,530 **** --- 535,541 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_addiu (SD_, RS, RT, IMMEDIATE); *************** 000000,5.RS,5.RT,5.RD,00000,100001:SPECI *** 552,557 **** --- 563,569 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_addu (SD_, RS, RT, RD); *************** 000000,5.RS,5.RT,5.RD,00000,100100:SPECI *** 577,582 **** --- 589,595 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_and (SD_, RS, RT, RD); *************** 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32: *** 595,600 **** --- 608,614 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE); *************** 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BE *** 615,620 **** --- 629,635 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BE *** 636,641 **** --- 651,657 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000001,5.RS,00001,16.OFFSET:REGIMM:32::B *** 660,665 **** --- 676,682 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000001,5.RS!31,10001,16.OFFSET:REGIMM:32 *** 682,687 **** --- 699,705 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000001,5.RS!31,10011,16.OFFSET:REGIMM:32 *** 706,711 **** --- 724,730 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000001,5.RS,00011,16.OFFSET:REGIMM:32::B *** 734,739 **** --- 753,759 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000111,5.RS,00000,16.OFFSET:NORMAL:32::B *** 758,763 **** --- 778,784 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 010111,5.RS,00000,16.OFFSET:NORMAL:32::B *** 779,784 **** --- 800,806 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000110,5.RS,00000,16.OFFSET:NORMAL:32::B *** 805,810 **** --- 827,833 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 010110,5.RS,00000,16.OFFSET:NORMAL:32::B *** 828,833 **** --- 851,857 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000001,5.RS,00000,16.OFFSET:REGIMM:32::B *** 852,857 **** --- 876,882 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000001,5.RS!31,10000,16.OFFSET:REGIMM:32 *** 874,879 **** --- 899,905 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000001,5.RS!31,10010,16.OFFSET:REGIMM:32 *** 900,905 **** --- 926,932 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000001,5.RS,00010,16.OFFSET:REGIMM:32::B *** 926,931 **** --- 953,959 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BN *** 952,957 **** --- 980,986 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BN *** 973,978 **** --- 1002,1008 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word offset = EXTEND16 (OFFSET) << 2; *************** 000000,20.CODE,001101:SPECIAL:32::BREAK *** 997,1002 **** --- 1027,1033 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { /* Check for some break instruction which are reserved for use by the simulator. */ *************** 000000,5.RS,5.RT,5.RD,00000,101100:SPECI *** 1085,1090 **** --- 1116,1122 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); *************** 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64: *** 1106,1111 **** --- 1138,1144 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE)); *************** 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64: *** 1134,1139 **** --- 1167,1173 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_daddiu (SD_, RS, RT, IMMEDIATE); *************** 000000,5.RS,5.RT,5.RD,00000,101101:SPECI *** 1156,1161 **** --- 1190,1196 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_daddu (SD_, RS, RT, RD); *************** 000000,5.RS,5.RT,0000000000,011110:SPECI *** 1249,1254 **** --- 1284,1290 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_ddiv (SD_, RS, RT); *************** 000000,5.RS,5.RT,0000000000,011111:SPECI *** 1289,1294 **** --- 1325,1331 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_ddivu (SD_, RS, RT); *************** 000000,5.RS,5.RT,0000000000,011010:SPECI *** 1333,1338 **** --- 1370,1376 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_div (SD_, RS, RT); *************** 000000,5.RS,5.RT,0000000000,011011:SPECI *** 1372,1377 **** --- 1410,1416 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_divu (SD_, RS, RT); *************** 000000,5.RS,5.RT,0000000000,011100:SPECI *** 1451,1456 **** --- 1490,1496 ---- *mipsV: *mips64: *vr4100: + *vr5500: { check_u64 (SD_, instruction_0); do_dmult (SD_, RS, RT, 0); *************** 000000,5.RS,5.RT,0000000000,011101:SPECI *** 1479,1484 **** --- 1519,1525 ---- *mipsV: *mips64: *vr4100: + *vr5500: { check_u64 (SD_, instruction_0); do_dmultu (SD_, RS, RT, 0); *************** 000000,00000,5.RT,5.RD,5.SHIFT,111000:SP *** 1508,1513 **** --- 1549,1555 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_dsll (SD_, RT, RD, SHIFT); *************** 000000,00000,5.RT,5.RD,5.SHIFT,111100:SP *** 1522,1527 **** --- 1564,1570 ---- *mips64: *vr4100: *vr5000: + *vr5500: { int s = 32 + SHIFT; check_u64 (SD_, instruction_0); *************** 000000,5.RS,5.RT,5.RD,00000,010100:SPECI *** 1546,1551 **** --- 1589,1595 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_dsllv (SD_, RS, RT, RD); *************** 000000,00000,5.RT,5.RD,5.SHIFT,111011:SP *** 1567,1572 **** --- 1611,1617 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_dsra (SD_, RT, RD, SHIFT); *************** 000000,00000,5.RT,5.RD,5.SHIFT,111111:SP *** 1581,1586 **** --- 1626,1632 ---- *mips64: *vr4100: *vr5000: + *vr5500: { int s = 32 + SHIFT; check_u64 (SD_, instruction_0); *************** 000000,5.RS,5.RT,5.RD,00000,010111:SPECI *** 1606,1611 **** --- 1652,1658 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_dsrav (SD_, RS, RT, RD); *************** 000000,00000,5.RT,5.RD,5.SHIFT,111010:SP *** 1627,1632 **** --- 1674,1680 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_dsrl (SD_, RT, RD, SHIFT); *************** 000000,00000,5.RT,5.RD,5.SHIFT,111110:SP *** 1641,1646 **** --- 1689,1695 ---- *mips64: *vr4100: *vr5000: + *vr5500: { int s = 32 + SHIFT; check_u64 (SD_, instruction_0); *************** 000000,5.RS,5.RT,5.RD,00000,010110:SPECI *** 1668,1673 **** --- 1717,1723 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_dsrlv (SD_, RS, RT, RD); *************** 000000,5.RS,5.RT,5.RD,00000,101110:SPECI *** 1682,1687 **** --- 1732,1738 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]); *************** 000000,5.RS,5.RT,5.RD,00000,101111:SPECI *** 1709,1714 **** --- 1760,1766 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_dsubu (SD_, RS, RT, RD); *************** 000010,26.INSTR_INDEX:NORMAL:32::J *** 1726,1731 **** --- 1778,1784 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { /* NOTE: The region used is that of the delay slot NIA and NOT the *************** 000011,26.INSTR_INDEX:NORMAL:32::JAL *** 1746,1751 **** --- 1799,1805 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { /* NOTE: The region used is that of the delay slot and NOT the *************** 000000,5.RS,00000,5.RD,00000,001001:SPEC *** 1767,1772 **** --- 1821,1827 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word temp = GPR[RS]; *************** 000000,5.RS,000000000000000,001000:SPECI *** 1786,1791 **** --- 1841,1847 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { DELAY_SLOT (GPR[RS]); *************** 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 1913,1918 **** --- 1969,1975 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET))); *************** 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 1930,1935 **** --- 1987,1993 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)); *************** 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64:: *** 1944,1949 **** --- 2002,2008 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); *************** 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM *** 1960,1965 **** --- 2019,2025 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET))); *************** 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64:: *** 1976,1981 **** --- 2036,2042 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); *************** 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64:: *** 1990,1995 **** --- 2051,2057 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); *************** 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 2007,2012 **** --- 2069,2075 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET))); *************** 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 2024,2029 **** --- 2087,2093 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)); *************** 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 2040,2045 **** --- 2104,2110 ---- *mips64: *vr4100: *vr5000: + *vr5500: { address_word base = GPR[BASE]; address_word offset = EXTEND16 (OFFSET); *************** 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64:: *** 2081,2086 **** --- 2146,2152 ---- *mips64: *vr4100: *vr5000: + *vr5500: { address_word base = GPR[BASE]; address_word offset = EXTEND16 (OFFSET); *************** 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32 *** 2119,2124 **** --- 2185,2191 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { TRACE_ALU_INPUT1 (IMMEDIATE); *************** 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 2138,2143 **** --- 2205,2211 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); *************** 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM *** 2155,2160 **** --- 2223,2229 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET))); *************** 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 2172,2177 **** --- 2241,2247 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); *************** 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 2189,2194 **** --- 2259,2265 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT])); *************** 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64:: *** 2203,2208 **** --- 2274,2280 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)); *************** 000000,0000000000,5.RD,00000,010000:SPEC *** 2268,2273 **** --- 2340,2346 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_mfhi (SD_, RD); *************** 000000,0000000000,5.RD,00000,010010:SPEC *** 2294,2299 **** --- 2367,2373 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_mflo (SD_, RD); *************** 000000,5.RS,5.RT,5.RD,00000,001011:SPECI *** 2308,2313 **** --- 2382,2388 ---- *mips32: *mips64: *vr5000: + *vr5500: { if (GPR[RT] != 0) { *************** 000000,5.RS,5.RT,5.RD,00000,001010:SPECI *** 2325,2330 **** --- 2400,2406 ---- *mips32: *mips64: *vr5000: + *vr5500: { if (GPR[RT] == 0) { *************** 000000,5.RS,000000000000000,010001:SPECI *** 2386,2391 **** --- 2462,2468 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { check_mt_hilo (SD_, HIHISTORY); *************** 000000,5.RS,000000000000000,010011:SPECI *** 2405,2410 **** --- 2482,2488 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { check_mt_hilo (SD_, LOHISTORY); *************** 000000,5.RS,5.RT,0000000000,011000:SPECI *** 2457,2462 **** --- 2535,2541 ---- *mips32: *mips64: *vr4100: + *vr5500: { do_mult (SD_, RS, RT, 0); } *************** 000000,5.RS,5.RT,0000000000,011001:SPECI *** 2498,2503 **** --- 2577,2583 ---- *mips32: *mips64: *vr4100: + *vr5500: { do_multu (SD_, RS, RT, 0); } *************** 000000,5.RS,5.RT,5.RD,00000,100111:SPECI *** 2530,2535 **** --- 2610,2616 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_nor (SD_, RS, RT, RD); *************** 000000,5.RS,5.RT,5.RD,00000,100101:SPECI *** 2554,2559 **** --- 2635,2641 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_or (SD_, RS, RT, RD); *************** 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32: *** 2579,2584 **** --- 2661,2667 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_ori (SD_, RS, RT, IMMEDIATE); *************** 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32 *** 2592,2597 **** --- 2675,2681 ---- *mips32: *mips64: *vr5000: + *vr5500: { address_word base = GPR[BASE]; address_word offset = EXTEND16 (OFFSET); *************** 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 2708,2713 **** --- 2792,2798 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); *************** 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 2724,2729 **** --- 2809,2815 ---- *mips64: *vr4100: *vr5000: + *vr5500: { unsigned32 instruction = instruction_0; address_word base = GPR[BASE]; *************** 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64:: *** 2766,2771 **** --- 2852,2858 ---- *mips64: *vr4100: *vr5000: + *vr5500: { address_word base = GPR[BASE]; address_word offset = EXTEND16 (OFFSET); *************** 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64:: *** 2804,2809 **** --- 2891,2897 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); *************** 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM *** 2820,2825 **** --- 2908,2914 ---- *mips64: *vr4100: *vr5000: + *vr5500: { do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT)); } *************** 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64:: *** 2833,2838 **** --- 2922,2928 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); *************** 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64:: *** 2847,2852 **** --- 2937,2943 ---- *mips64: *vr4100: *vr5000: + *vr5500: { check_u64 (SD_, instruction_0); do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); *************** 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 2864,2869 **** --- 2955,2961 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); *************** 000000,00000,5.RT,5.RD,5.SHIFT,000000:SP *** 2888,2893 **** --- 2980,2986 ---- *mipsV: *vr4100: *vr5000: + *vr5500: *r3900: { /* Skip shift for NOP, so that there won't be lots of extraneous *************** 000000,5.RS,5.RT,5.RD,00000,000100:SPECI *** 2930,2935 **** --- 3023,3029 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_sllv (SD_, RS, RT, RD); *************** 000000,5.RS,5.RT,5.RD,00000,101010:SPECI *** 2954,2959 **** --- 3048,3054 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_slt (SD_, RS, RT, RD); *************** 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32: *** 2978,2983 **** --- 3073,3079 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_slti (SD_, RS, RT, IMMEDIATE); *************** 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32: *** 3002,3007 **** --- 3098,3104 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_sltiu (SD_, RS, RT, IMMEDIATE); *************** 000000,5.RS,5.RT,5.RD,00000,101011:SPECI *** 3027,3032 **** --- 3124,3130 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_sltu (SD_, RS, RT, RD); *************** 000000,00000,5.RT,5.RD,5.SHIFT,000011:SP *** 3054,3059 **** --- 3152,3158 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_sra (SD_, RT, RD, SHIFT); *************** 000000,5.RS,5.RT,5.RD,00000,000111:SPECI *** 3083,3088 **** --- 3182,3188 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_srav (SD_, RS, RT, RD); *************** 000000,00000,5.RT,5.RD,5.SHIFT,000010:SP *** 3111,3116 **** --- 3211,3217 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_srl (SD_, RT, RD, SHIFT); *************** 000000,5.RS,5.RT,5.RD,00000,000110:SPECI *** 3139,3144 **** --- 3240,3246 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_srlv (SD_, RS, RT, RD); *************** 000000,5.RS,5.RT,5.RD,00000,100010:SPECI *** 3156,3161 **** --- 3258,3264 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT])) *************** 000000,5.RS,5.RT,5.RD,00000,100011:SPECI *** 3190,3195 **** --- 3293,3299 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_subu (SD_, RS, RT, RD); *************** 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 3208,3213 **** --- 3312,3318 ---- *vr4100: *r3900: *vr5000: + *vr5500: { do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); } *************** 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORM *** 3224,3229 **** --- 3329,3335 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT)); *************** 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 3241,3246 **** --- 3347,3353 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); *************** 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32:: *** 3258,3263 **** --- 3365,3371 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]); *************** 000000,000000000000000,5.STYPE,001111:SP *** 3275,3280 **** --- 3383,3389 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { SyncOperation (STYPE); *************** 000000,20.CODE,001100:SPECIAL:32::SYSCAL *** 3292,3297 **** --- 3401,3407 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { SignalException (SystemCall, instruction_0); *************** 000000,5.RS,5.RT,10.CODE,110100:SPECIAL: *** 3308,3313 **** --- 3418,3424 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((signed_word) GPR[RS] == (signed_word) GPR[RT]) SignalException (Trap, instruction_0); *************** 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32 *** 3324,3329 **** --- 3435,3441 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE)) SignalException (Trap, instruction_0); *************** 000000,5.RS,5.RT,10.CODE,110000:SPECIAL: *** 3340,3345 **** --- 3452,3458 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((signed_word) GPR[RS] >= (signed_word) GPR[RT]) SignalException (Trap, instruction_0); *************** 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32 *** 3356,3361 **** --- 3469,3475 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE)) SignalException (Trap, instruction_0); *************** 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32 *** 3372,3377 **** --- 3486,3492 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE)) SignalException (Trap, instruction_0); *************** 000000,5.RS,5.RT,10.CODE,110001:SPECIAL: *** 3388,3393 **** --- 3503,3509 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT]) SignalException (Trap, instruction_0); *************** 000000,5.RS,5.RT,10.CODE,110010:SPECIAL: *** 3404,3409 **** --- 3520,3526 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((signed_word) GPR[RS] < (signed_word) GPR[RT]) SignalException (Trap, instruction_0); *************** 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32 *** 3420,3425 **** --- 3537,3543 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE)) SignalException (Trap, instruction_0); *************** 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32 *** 3436,3441 **** --- 3554,3560 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE)) SignalException (Trap, instruction_0); *************** 000000,5.RS,5.RT,10.CODE,110011:SPECIAL: *** 3452,3457 **** --- 3571,3577 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT]) SignalException (Trap, instruction_0); *************** 000000,5.RS,5.RT,10.CODE,110110:SPECIAL: *** 3468,3473 **** --- 3588,3594 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((signed_word) GPR[RS] != (signed_word) GPR[RT]) SignalException (Trap, instruction_0); *************** 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32 *** 3484,3489 **** --- 3605,3611 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE)) SignalException (Trap, instruction_0); *************** 000000,5.RS,5.RT,5.RD,00000,100110:SPECI *** 3508,3513 **** --- 3630,3636 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_xor (SD_, RS, RT, RD); *************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32: *** 3532,3537 **** --- 3655,3661 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { do_xori (SD_, RS, RT, IMMEDIATE); *************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32: *** 3616,3621 **** --- 3740,3746 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { if ((fmt != fmt_single) && (fmt != fmt_double)) *************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32: *** 3631,3636 **** --- 3756,3762 ---- *mips32: *vr4100: *vr5000: + *vr5500: *r3900: { /* None of these ISAs support Paired Single, so just fall back to *************** 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32: *** 3664,3669 **** --- 3790,3796 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { if (! COP_Usable (1)) *************** 010001,10,3.FMT,00000,5.FS,5.FD,000101:C *** 3753,3758 **** --- 3880,3886 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:CO *** 3774,3779 **** --- 3902,3908 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:CO *** 3849,3854 **** --- 3978,3984 ---- *mips64: #*vr4100: *vr5000: + *vr5500: *r3900: { check_fpu (SD_); *************** 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.C *** 3886,3891 **** --- 4016,4022 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,00000,5.FS,5.FD,001010:C *** 3904,3909 **** --- 4035,4041 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,00000,5.FS,5.FD,001110:C *** 3924,3929 **** --- 4056,4062 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,00010,5.RT,5.FS,00000000000:COP1: *** 3953,3958 **** --- 4086,4092 ---- *mipsIV: *vr4100: *vr5000: + *vr5500: *r3900: { check_fpu (SD_); *************** 010001,00110,5.RT,5.FS,00000000000:COP1: *** 4000,4005 **** --- 4134,4140 ---- *mipsIV: *vr4100: *vr5000: + *vr5500: *r3900: { check_fpu (SD_); *************** 010001,10,3.FMT,00000,5.FS,5.FD,100001:C *** 4037,4042 **** --- 4172,4178 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,00000,5.FS,5.FD,100101:C *** 4056,4061 **** --- 4192,4198 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT!6,00000,5.FS,5.FD,100000 *** 4093,4098 **** --- 4230,4236 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT!6,00000,5.FS,5.FD,100100 *** 4137,4142 **** --- 4275,4281 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:CO *** 4159,4164 **** --- 4298,4304 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,00001,5.RT,5.FS,00000000000:COP1: *** 4192,4197 **** --- 4332,4338 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { check_fpu (SD_); *************** 010001,00101,5.RT,5.FS,00000000000:COP1: *** 4232,4237 **** --- 4373,4379 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { check_fpu (SD_); *************** 010001,10,3.FMT,00000,5.FS,5.FD,001011:C *** 4253,4258 **** --- 4395,4401 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,00000,5.FS,5.FD,001111:C *** 4273,4278 **** --- 4416,4422 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f:: *** 4301,4306 **** --- 4445,4451 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { check_fpu (SD_); *************** 010011,5.BASE,5.INDEX,5.0,5.FD,000001:CO *** 4314,4319 **** --- 4459,4465 ---- *mipsV: *mips64: *vr5000: + *vr5500: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f:: *** 4349,4354 **** --- 4495,4501 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { check_fpu (SD_); *************** 010011,5.BASE,5.INDEX,5.0,5.FD,000000:CO *** 4362,4367 **** --- 4509,4515 ---- *mipsV: *mips64: *vr5000: + *vr5500: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP *** 4376,4381 **** --- 4524,4530 ---- *mipsV: *mips64: *vr5000: + *vr5500: { int fmt = FMT; check_fpu (SD_); *************** 010001,00000,5.RT,5.FS,00000000000:COP1: *** 4407,4412 **** --- 4556,4562 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { check_fpu (SD_); *************** 010001,10,3.FMT,00000,5.FS,5.FD,000110:C *** 4426,4431 **** --- 4576,4582 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 000000,5.RS,3.CC,0,1.TF,5.RD,00000,00000 *** 4444,4449 **** --- 4595,4601 ---- *mips32: *mips64: *vr5000: + *vr5500: { check_fpu (SD_); if (GETFCC(CC) == TF) *************** 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,01 *** 4460,4465 **** --- 4612,4618 ---- *mips32: *mips64: *vr5000: + *vr5500: { int fmt = FMT; check_fpu (SD_); *************** 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:CO *** 4489,4494 **** --- 4642,4648 ---- *mips32: *mips64: *vr5000: + *vr5500: { check_fpu (SD_); if (GPR[RT] != 0) *************** 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:CO *** 4512,4517 **** --- 4666,4672 ---- *mips32: *mips64: *vr5000: + *vr5500: { check_fpu (SD_); if (GPR[RT] == 0) *************** 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP *** 4527,4532 **** --- 4682,4688 ---- *mipsV: *mips64: *vr5000: + *vr5500: { int fmt = FMT; check_fpu (SD_); *************** 010001,00100,5.RT,5.FS,00000000000:COP1: *** 4559,4564 **** --- 4715,4721 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { check_fpu (SD_); *************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:CO *** 4577,4582 **** --- 4734,4740 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,00000,5.FS,5.FD,000111:C *** 4597,4602 **** --- 4755,4761 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP *** 4612,4617 **** --- 4771,4777 ---- *mipsV: *mips64: *vr5000: + *vr5500: { int fmt = FMT; check_fpu (SD_); *************** 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP *** 4628,4633 **** --- 4788,4794 ---- *mipsV: *mips64: *vr5000: + *vr5500: { int fmt = FMT; check_fpu (SD_); *************** 010011,5.BASE,5.INDEX,5.HINT,00000,00111 *** 4668,4673 **** --- 4829,4835 ---- *mipsV: *mips64: *vr5000: + *vr5500: { address_word base = GPR[BASE]; address_word index = GPR[INDEX]; *************** 010001,10,3.FMT,00000,5.FS,5.FD,010101:C *** 4711,4716 **** --- 4873,4879 ---- *mipsV: *mips64: *vr5000: + *vr5500: { int fmt = FMT; check_fpu (SD_); *************** 010001,10,3.FMT,00000,5.FS,5.FD,001000:C *** 4727,4732 **** --- 4890,4896 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,00000,5.FS,5.FD,001100:C *** 4747,4752 **** --- 4911,4917 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,00000,5.FS,5.FD,010110:C *** 4763,4768 **** --- 4928,4934 ---- *mipsV: *mips64: *vr5000: + *vr5500: { int fmt = FMT; check_fpu (SD_); *************** 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f:: *** 4789,4794 **** --- 4955,4961 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { check_fpu (SD_); *************** 010011,5.BASE,5.INDEX,5.FS,00000001001:C *** 4802,4807 **** --- 4969,4975 ---- *mipsV: *mips64: *vr5000: + *vr5500: { check_fpu (SD_); check_u64 (SD_, instruction_0); *************** 010001,10,3.FMT,00000,5.FS,5.FD,000100:C *** 4837,4842 **** --- 5005,5011 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:CO *** 4857,4862 **** --- 5026,5032 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f:: *** 4878,4883 **** --- 5048,5054 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word base = GPR[BASE]; *************** 010011,5.BASE,5.INDEX,5.FS,00000,001000: *** 4917,4922 **** --- 5088,5094 ---- *mipsV: *mips64: *vr5000: + *vr5500: { address_word base = GPR[BASE]; *************** 010001,10,3.FMT,00000,5.FS,5.FD,001001:C *** 4959,4964 **** --- 5131,5137 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010001,10,3.FMT,00000,5.FS,5.FD,001101:C *** 4979,4984 **** --- 5152,5158 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { int fmt = FMT; *************** 010000,01000,00000,16.OFFSET:COP0:32::BC *** 5007,5012 **** --- 5181,5187 ---- *mips64: *vr4100: *vr5000: + *vr5500: 010000,01000,00000,16.OFFSET:COP0:32::BC0F "bc0f " *************** 010000,01000,00010,16.OFFSET:COP0:32::BC *** 5028,5033 **** --- 5203,5209 ---- *mips64: *vr4100: *vr5000: + *vr5500: 010000,01000,00001,16.OFFSET:COP0:32::BC0T *************** 010000,01000,00001,16.OFFSET:COP0:32::BC *** 5040,5045 **** --- 5216,5222 ---- *mips32: *mips64: *vr4100: + *vr5500: 010000,01000,00011,16.OFFSET:COP0:32::BC0TL *************** 010000,01000,00011,16.OFFSET:COP0:32::BC *** 5053,5058 **** --- 5230,5236 ---- *mips64: *vr4100: *vr5000: + *vr5500: 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE *************** 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32:: *** 5064,5069 **** --- 5242,5248 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { address_word base = GPR[BASE]; *************** 010000,00001,5.RT,5.RD,00000000000:COP0: *** 5084,5089 **** --- 5263,5269 ---- *mipsIV: *mipsV: *mips64: + *vr5500: { check_u64 (SD_, instruction_0); DecodeCoproc (instruction_0); *************** 010000,00101,5.RT,5.RD,00000000000:COP0: *** 5096,5101 **** --- 5276,5282 ---- *mipsIV: *mipsV: *mips64: + *vr5500: { check_u64 (SD_, instruction_0); DecodeCoproc (instruction_0); *************** 010000,1,0000000000000000000,011000:COP0 *** 5111,5116 **** --- 5292,5298 ---- *mips64: *vr4100: *vr5000: + *vr5500: { if (SR & status_ERL) { *************** 010000,00000,5.RT,5.RD,00000,6.REGX:COP0 *** 5138,5143 **** --- 5320,5326 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { TRACE_ALU_INPUT0 (); *************** 010000,00100,5.RT,5.RD,00000,6.REGX:COP0 *** 5156,5161 **** --- 5339,5345 ---- *mips64: *vr4100: *vr5000: + *vr5500: *r3900: { DecodeCoproc (instruction_0); *************** 010000,1,0000000000000000000,010000:COP0 *** 5171,5176 **** --- 5355,5361 ---- *mipsV: *vr4100: *vr5000: + *vr5500: *r3900: { DecodeCoproc (instruction_0); *************** 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16 *** 5187,5192 **** --- 5372,5378 ---- *mips32: *mips64: *vr4100: + *vr5500: *r3900: { DecodeCoproc (instruction_0); *************** 010000,1,0000000000000000000,001000:COP0 *** 5205,5210 **** --- 5391,5397 ---- *mips64: *vr4100: *vr5000: + *vr5500: 010000,1,0000000000000000000,000001:COP0:32::TLBR *************** 010000,1,0000000000000000000,000001:COP0 *** 5218,5223 **** --- 5405,5411 ---- *mips64: *vr4100: *vr5000: + *vr5500: 010000,1,0000000000000000000,000010:COP0:32::TLBWI *************** 010000,1,0000000000000000000,000010:COP0 *** 5231,5236 **** --- 5419,5425 ---- *mips64: *vr4100: *vr5000: + *vr5500: 010000,1,0000000000000000000,000110:COP0:32::TLBWR *************** 010000,1,0000000000000000000,000110:COP0 *** 5244,5249 **** --- 5433,5439 ---- *mips64: *vr4100: *vr5000: + *vr5500: :include:::m16.igen