From: pbonzini@redhat.com (Paolo Bonzini)
Subject: [ltt-dev] [URCU PATCH] cmm: provide lightweight rmb/wmb on PPC
Date: Tue, 20 Sep 2011 09:12:48 +0200 [thread overview]
Message-ID: <1316502769-576-1-git-send-email-pbonzini@redhat.com> (raw)
lwsync orders loads with respect to other loads, and stores with respect
to other stores. eieio instead only orders stores. Use them to
implement rmb/wmb/smp_wmb.
---
urcu/arch/ppc.h | 9 ++++++++-
1 files changed, 8 insertions(+), 1 deletions(-)
diff --git a/urcu/arch/ppc.h b/urcu/arch/ppc.h
index a03d688..3a6c702 100644
--- a/urcu/arch/ppc.h
+++ b/urcu/arch/ppc.h
@@ -32,7 +32,14 @@ extern "C" {
/* Include size of POWER5+ L3 cache lines: 256 bytes */
#define CAA_CACHE_LINE_SIZE 256
-#define cmm_mb() asm volatile("sync":::"memory")
+#define cmm_mb() asm volatile("sync":::"memory")
+#define cmm_rmb() asm volatile("lwsync":::"memory")
+#define cmm_wmb() asm volatile("lwsync":::"memory")
+
+/* eieio is good for a write memory barrier, assuming we don't
+ * need to order cacheable and non-cacheable stores with respect
+ * to each other. */
+#define cmm_smp_wmb() asm volatile("eieio":::"memory")
#define mftbl() \
({ \
--
1.7.6
next reply other threads:[~2011-09-20 7:12 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-09-20 7:12 Paolo Bonzini [this message]
2011-09-20 16:31 ` Mathieu Desnoyers
2011-09-20 16:39 ` Paolo Bonzini
2011-09-20 16:51 ` Mathieu Desnoyers
2011-09-21 7:20 ` Paolo Bonzini
2011-09-21 23:43 ` Paul E. McKenney
2011-09-21 23:42 ` Paul E. McKenney
2011-09-22 8:42 ` [ltt-dev] [PATCH v2] cmm: provide lightweight smp_rmb/smp_wmb " Paolo Bonzini
2011-09-22 9:10 ` Mathieu Desnoyers
2011-09-22 14:49 ` Paul E. McKenney
2011-09-22 14:57 ` Mathieu Desnoyers
2011-09-22 15:26 ` Paul E. McKenney
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